2 * ATI Frame Buffer Device Driver Core
4 * Copyright (C) 1997-2001 Geert Uytterhoeven
5 * Copyright (C) 1998 Bernd Harries
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
8 * This driver supports the following ATI graphics chips:
11 * To do: add support for
12 * - ATI Rage128 (from aty128fb.c)
13 * - ATI Radeon (from radeonfb.c)
15 * This driver is partly based on the PowerMac console driver:
17 * Copyright (C) 1996 Paul Mackerras
19 * and on the PowerMac ATI/mach64 display driver:
21 * Copyright (C) 1997 Michael AK Tesch
23 * with work by Jon Howell
25 * Anthony Tong <atong@uiuc.edu>
27 * This file is subject to the terms and conditions of the GNU General Public
28 * License. See the file COPYING in the main directory of this archive for
31 * Many thanks to Nitya from ATI devrel for support and patience !
34 /******************************************************************************
38 - cursor support on all cards and all ramdacs.
39 - cursor parameters controlable via ioctl()s.
40 - guess PLL and MCLK based on the original PLL register values initialized
41 by the BIOS or Open Firmware (if they are initialized).
43 (Anyone to help with this?)
45 ******************************************************************************/
48 #include <linux/config.h>
49 #include <linux/module.h>
50 #include <linux/kernel.h>
51 #include <linux/errno.h>
52 #include <linux/string.h>
54 #include <linux/slab.h>
55 #include <linux/vmalloc.h>
56 #include <linux/delay.h>
57 #include <linux/selection.h>
58 #include <linux/console.h>
60 #include <linux/init.h>
61 #include <linux/pci.h>
62 #include <linux/vt_kern.h>
66 #include <asm/uaccess.h>
68 #include <video/mach64.h>
73 #include "../macmodes.h"
81 #include <linux/adb.h>
82 #include <linux/pmu.h>
84 #ifdef CONFIG_BOOTX_TEXT
85 #include <asm/btext.h>
87 #ifdef CONFIG_PMAC_BACKLIGHT
88 #include <asm/backlight.h>
97 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
98 /* - must be large enough to catch all GUI-Regs */
99 /* - must be aligned to a PAGE boundary */
100 #define GUI_RESERVE (1 * PAGE_SIZE)
103 /* FIXME: remove the FAIL definition */
104 #define FAIL(x) do { printk(x "\n"); return -EINVAL; } while (0)
108 * The Hardware parameters for each card
111 struct aty_cmap_regs {
119 struct pci_mmap_map {
123 unsigned long prot_flag;
124 unsigned long prot_mask;
127 static struct fb_fix_screeninfo atyfb_fix __initdata = {
129 .type = FB_TYPE_PACKED_PIXELS,
130 .visual = FB_VISUAL_PSEUDOCOLOR,
136 * Frame buffer device API
139 static int atyfb_open(struct fb_info *info, int user);
140 static int atyfb_release(struct fb_info *info, int user);
141 static int atyfb_check_var(struct fb_var_screeninfo *var,
142 struct fb_info *info);
143 static int atyfb_set_par(struct fb_info *info);
144 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
145 u_int transp, struct fb_info *info);
146 static int atyfb_pan_display(struct fb_var_screeninfo *var,
147 struct fb_info *info);
148 static int atyfb_blank(int blank, struct fb_info *info);
149 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
150 u_long arg, struct fb_info *info);
151 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
152 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
153 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
155 static int atyfb_mmap(struct fb_info *info, struct file *file,
156 struct vm_area_struct *vma);
158 static int atyfb_sync(struct fb_info *info);
164 static int aty_init(struct fb_info *info, const char *name);
166 static int store_video_par(char *videopar, unsigned char m64_num);
169 static void aty_set_crtc(const struct atyfb_par *par,
170 const struct crtc *crtc);
171 static int aty_var_to_crtc(const struct fb_info *info,
172 const struct fb_var_screeninfo *var,
174 static int aty_crtc_to_var(const struct crtc *crtc,
175 struct fb_var_screeninfo *var);
176 static void set_off_pitch(struct atyfb_par *par,
177 const struct fb_info *info);
179 static int read_aty_sense(const struct atyfb_par *par);
184 * Interface used by the world
187 int atyfb_init(void);
189 int atyfb_setup(char *);
192 static struct fb_ops atyfb_ops = {
193 .owner = THIS_MODULE,
194 .fb_open = atyfb_open,
195 .fb_release = atyfb_release,
196 .fb_check_var = atyfb_check_var,
197 .fb_set_par = atyfb_set_par,
198 .fb_setcolreg = atyfb_setcolreg,
199 .fb_pan_display = atyfb_pan_display,
200 .fb_blank = atyfb_blank,
201 .fb_ioctl = atyfb_ioctl,
202 .fb_fillrect = atyfb_fillrect,
203 .fb_copyarea = atyfb_copyarea,
204 .fb_imageblit = atyfb_imageblit,
205 .fb_cursor = soft_cursor,
207 .fb_mmap = atyfb_mmap,
209 .fb_sync = atyfb_sync,
212 static char curblink __initdata = 1;
213 static char noaccel __initdata = 0;
214 static u32 default_vram __initdata = 0;
215 static int default_pll __initdata = 0;
216 static int default_mclk __initdata = 0;
219 static char *mode_option __initdata = NULL;
223 static int default_vmode __initdata = VMODE_CHOOSE;
224 static int default_cmode __initdata = CMODE_CHOOSE;
228 static unsigned int mach64_count __initdata = 0;
229 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
230 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
231 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
234 #ifdef CONFIG_FB_ATY_GX
235 static char m64n_gx[] __initdata = "mach64GX (ATI888GX00)";
236 static char m64n_cx[] __initdata = "mach64CX (ATI888CX00)";
237 #endif /* CONFIG_FB_ATY_GX */
238 #ifdef CONFIG_FB_ATY_CT
239 static char m64n_ct[] __initdata = "mach64CT (ATI264CT)";
240 static char m64n_et[] __initdata = "mach64ET (ATI264ET)";
241 static char m64n_vta3[] __initdata = "mach64VTA3 (ATI264VT)";
242 static char m64n_vta4[] __initdata = "mach64VTA4 (ATI264VT)";
243 static char m64n_vtb[] __initdata = "mach64VTB (ATI264VTB)";
244 static char m64n_vt4[] __initdata = "mach64VT4 (ATI264VT4)";
245 static char m64n_gt[] __initdata = "3D RAGE (GT)";
246 static char m64n_gtb[] __initdata = "3D RAGE II+ (GTB)";
247 static char m64n_iic_p[] __initdata = "3D RAGE IIC (PCI)";
248 static char m64n_iic_a[] __initdata = "3D RAGE IIC (AGP)";
249 static char m64n_lt[] __initdata = "3D RAGE LT";
250 static char m64n_ltg[] __initdata = "3D RAGE LT-G";
251 static char m64n_gtc_ba[] __initdata = "3D RAGE PRO (BGA, AGP)";
252 static char m64n_gtc_ba1[] __initdata = "3D RAGE PRO (BGA, AGP, 1x only)";
253 static char m64n_gtc_bp[] __initdata = "3D RAGE PRO (BGA, PCI)";
254 static char m64n_gtc_pp[] __initdata = "3D RAGE PRO (PQFP, PCI)";
255 static char m64n_gtc_ppl[] __initdata =
256 "3D RAGE PRO (PQFP, PCI, limited 3D)";
257 static char m64n_xl[] __initdata = "3D RAGE (XL)";
258 static char m64n_ltp_a[] __initdata = "3D RAGE LT PRO (AGP)";
259 static char m64n_ltp_p[] __initdata = "3D RAGE LT PRO (PCI)";
260 static char m64n_mob_p[] __initdata = "3D RAGE Mobility (PCI)";
261 static char m64n_mob_a[] __initdata = "3D RAGE Mobility (AGP)";
262 #endif /* CONFIG_FB_ATY_CT */
265 u16 pci_id, chip_type;
266 u8 rev_mask, rev_val;
270 } aty_chips[] __initdata = {
271 #ifdef CONFIG_FB_ATY_GX
274 0x4758, 0x00d7, 0x00, 0x00, m64n_gx, 135, 50, M64F_GX}, {
275 0x4358, 0x0057, 0x00, 0x00, m64n_cx, 135, 50, M64F_GX},
276 #endif /* CONFIG_FB_ATY_GX */
277 #ifdef CONFIG_FB_ATY_CT
280 0x4354, 0x4354, 0x00, 0x00, m64n_ct, 135, 60,
281 M64F_CT | M64F_INTEGRATED | M64F_CT_BUS |
283 0x4554, 0x4554, 0x00, 0x00, m64n_et, 135, 60,
284 M64F_CT | M64F_INTEGRATED | M64F_CT_BUS |
288 0x5654, 0x5654, 0xc7, 0x00, m64n_vta3, 170, 67,
289 M64F_VT | M64F_INTEGRATED | M64F_VT_BUS |
290 M64F_MAGIC_FIFO | M64F_FIFO_24}, {
291 0x5654, 0x5654, 0xc7, 0x40, m64n_vta4, 200, 67,
292 M64F_VT | M64F_INTEGRATED | M64F_VT_BUS |
293 M64F_MAGIC_FIFO | M64F_FIFO_24 | M64F_MAGIC_POSTDIV}, {
294 0x5654, 0x5654, 0x00, 0x00, m64n_vtb, 200, 67,
295 M64F_VT | M64F_INTEGRATED | M64F_VT_BUS |
296 M64F_GTB_DSP | M64F_FIFO_24}, {
297 0x5655, 0x5655, 0x00, 0x00, m64n_vtb, 200, 67,
298 M64F_VT | M64F_INTEGRATED | M64F_VT_BUS |
299 M64F_GTB_DSP | M64F_FIFO_24 | M64F_SDRAM_MAGIC_PLL}, {
300 0x5656, 0x5656, 0x00, 0x00, m64n_vt4, 230, 83,
301 M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP},
302 /* Mach64 GT (3D RAGE) */
304 0x4754, 0x4754, 0x07, 0x00, m64n_gt, 135, 63,
305 M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO |
306 M64F_FIFO_24 | M64F_EXTRA_BRIGHT}, {
307 0x4754, 0x4754, 0x07, 0x01, m64n_gt, 170, 67,
308 M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP |
309 M64F_FIFO_24 | M64F_SDRAM_MAGIC_PLL |
310 M64F_EXTRA_BRIGHT}, {
311 0x4754, 0x4754, 0x07, 0x02, m64n_gt, 200, 67,
312 M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP |
313 M64F_FIFO_24 | M64F_SDRAM_MAGIC_PLL |
314 M64F_EXTRA_BRIGHT}, {
315 0x4755, 0x4755, 0x00, 0x00, m64n_gtb, 200, 67,
316 M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP |
317 M64F_FIFO_24 | M64F_SDRAM_MAGIC_PLL |
318 M64F_EXTRA_BRIGHT}, {
319 0x4756, 0x4756, 0x00, 0x00, m64n_iic_p, 230, 83,
320 M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP |
321 M64F_FIFO_24 | M64F_SDRAM_MAGIC_PLL |
322 M64F_EXTRA_BRIGHT}, {
323 0x4757, 0x4757, 0x00, 0x00, m64n_iic_a, 230, 83,
324 M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP |
325 M64F_FIFO_24 | M64F_SDRAM_MAGIC_PLL |
326 M64F_EXTRA_BRIGHT}, {
327 0x475a, 0x475a, 0x00, 0x00, m64n_iic_a, 230, 83,
328 M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP |
329 M64F_FIFO_24 | M64F_SDRAM_MAGIC_PLL |
333 0x4c54, 0x4c54, 0x00, 0x00, m64n_lt, 135, 63,
334 M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP}, {
335 0x4c47, 0x4c47, 0x00, 0x00, m64n_ltg, 230, 63,
336 M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP |
337 M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT |
338 M64F_LT_SLEEP | M64F_G3_PB_1024x768},
339 /* Mach64 GTC (3D RAGE PRO) */
341 0x4742, 0x4742, 0x00, 0x00, m64n_gtc_ba, 230, 100,
342 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
343 M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL |
344 M64F_EXTRA_BRIGHT}, {
345 0x4744, 0x4744, 0x00, 0x00, m64n_gtc_ba1, 230, 100,
346 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
347 M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL |
348 M64F_EXTRA_BRIGHT}, {
349 0x4749, 0x4749, 0x00, 0x00, m64n_gtc_bp, 230, 100,
350 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
351 M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL |
352 M64F_EXTRA_BRIGHT | M64F_MAGIC_VRAM_SIZE}, {
353 0x4750, 0x4750, 0x00, 0x00, m64n_gtc_pp, 230, 100,
354 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
355 M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL |
356 M64F_EXTRA_BRIGHT}, {
357 0x4751, 0x4751, 0x00, 0x00, m64n_gtc_ppl, 230, 100,
358 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
359 M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL |
363 0x4752, 0x4752, 0x00, 0x00, m64n_xl, 230, 100,
364 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
365 M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL |
366 M64F_EXTRA_BRIGHT | M64F_XL_DLL},
369 0x4c42, 0x4c42, 0x00, 0x00, m64n_ltp_a, 230, 100,
370 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
372 0x4c44, 0x4c44, 0x00, 0x00, m64n_ltp_p, 230, 100,
373 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
375 0x4c49, 0x4c49, 0x00, 0x00, m64n_ltp_p, 230, 100,
376 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
377 M64F_GTB_DSP | M64F_EXTRA_BRIGHT |
378 M64F_G3_PB_1_1 | M64F_G3_PB_1024x768}, {
379 0x4c50, 0x4c50, 0x00, 0x00, m64n_ltp_p, 230, 100,
380 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
382 /* 3D RAGE Mobility */
384 0x4c4d, 0x4c4d, 0x00, 0x00, m64n_mob_p, 230, 50,
385 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
386 M64F_GTB_DSP | M64F_MOBIL_BUS}, {
387 0x4c4e, 0x4c4e, 0x00, 0x00, m64n_mob_a, 230, 50,
388 M64F_GT | M64F_INTEGRATED | M64F_RESET_3D |
389 M64F_GTB_DSP | M64F_MOBIL_BUS},
390 #endif /* CONFIG_FB_ATY_CT */
393 static char ram_dram[] __initdata = "DRAM";
394 #ifdef CONFIG_FB_ATY_GX
395 static char ram_vram[] __initdata = "VRAM";
396 #endif /* CONFIG_FB_ATY_GX */
397 #ifdef CONFIG_FB_ATY_CT
398 static char ram_edo[] __initdata = "EDO";
399 static char ram_sdram[] __initdata = "SDRAM";
400 static char ram_sgram[] __initdata = "SGRAM";
401 static char ram_wram[] __initdata = "WRAM";
402 static char ram_off[] __initdata = "OFF";
403 #endif /* CONFIG_FB_ATY_CT */
404 static char ram_resv[] __initdata = "RESV";
406 static u32 pseudo_palette[17];
408 #ifdef CONFIG_FB_ATY_GX
409 static char *aty_gx_ram[8] __initdata = {
410 ram_dram, ram_vram, ram_vram, ram_dram,
411 ram_dram, ram_vram, ram_vram, ram_resv
413 #endif /* CONFIG_FB_ATY_GX */
415 #ifdef CONFIG_FB_ATY_CT
416 static char *aty_ct_ram[8] __initdata = {
417 ram_off, ram_dram, ram_edo, ram_edo,
418 ram_sdram, ram_sgram, ram_wram, ram_resv
420 #endif /* CONFIG_FB_ATY_CT */
423 #if defined(CONFIG_PPC)
426 * Apple monitor sense
429 static int __init read_aty_sense(const struct atyfb_par *par)
433 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
435 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
437 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
438 sense = ((i & 0x3000) >> 3) | (i & 0x100);
440 /* drive each sense line low in turn and collect the other 2 */
441 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
443 i = aty_ld_le32(GP_IO, par);
444 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
445 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
448 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
450 i = aty_ld_le32(GP_IO, par);
451 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
452 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
455 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
457 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
458 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
462 #endif /* defined(CONFIG_PPC) */
464 #if defined(CONFIG_PMAC_PBOOK) || defined(CONFIG_PMAC_BACKLIGHT)
465 static void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
469 /* write addr byte */
470 temp = aty_ld_le32(LCD_INDEX, par);
471 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
472 /* write the register value */
473 aty_st_le32(LCD_DATA, val, par);
476 static u32 aty_ld_lcd(int index, const struct atyfb_par *par)
480 /* write addr byte */
481 temp = aty_ld_le32(LCD_INDEX, par);
482 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
483 /* read the register value */
484 return aty_ld_le32(LCD_DATA, par);
486 #endif /* CONFIG_PMAC_PBOOK || CONFIG_PMAC_BACKLIGHT */
488 /* ------------------------------------------------------------------------- */
494 static void aty_set_crtc(const struct atyfb_par *par,
495 const struct crtc *crtc)
497 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
498 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
499 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
500 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
501 aty_st_le32(CRTC_VLINE_CRNT_VLINE, 0, par);
502 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
503 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
506 static int aty_var_to_crtc(const struct fb_info *info,
507 const struct fb_var_screeninfo *var,
510 struct atyfb_par *par = (struct atyfb_par *) info->par;
511 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
512 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
513 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
515 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
516 u32 pix_width, dp_pix_width, dp_chain_mask;
521 vxres = var->xres_virtual;
522 vyres = var->yres_virtual;
523 xoffset = var->xoffset;
524 yoffset = var->yoffset;
525 bpp = var->bits_per_pixel;
526 left = var->left_margin;
527 right = var->right_margin;
528 upper = var->upper_margin;
529 lower = var->lower_margin;
530 hslen = var->hsync_len;
531 vslen = var->vsync_len;
535 /* convert (and round up) and validate */
536 xres = (xres + 7) & ~7;
537 xoffset = (xoffset + 7) & ~7;
538 vxres = (vxres + 7) & ~7;
539 if (vxres < xres + xoffset)
540 vxres = xres + xoffset;
541 h_disp = xres / 8 - 1;
543 FAIL("h_disp too large");
544 h_sync_strt = h_disp + (right / 8);
545 if (h_sync_strt > 0x1ff)
546 FAIL("h_sync_start too large");
547 h_sync_dly = right & 7;
548 h_sync_wid = (hslen + 7) / 8;
549 if (h_sync_wid > 0x1f)
550 FAIL("h_sync_wid too large");
551 h_total = h_sync_strt + h_sync_wid + (h_sync_dly + left + 7) / 8;
553 FAIL("h_total too large");
554 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
556 if (vyres < yres + yoffset)
557 vyres = yres + yoffset;
560 FAIL("v_disp too large");
561 v_sync_strt = v_disp + lower;
562 if (v_sync_strt > 0x7ff)
563 FAIL("v_sync_strt too large");
565 if (v_sync_wid > 0x1f)
566 FAIL("v_sync_wid too large");
567 v_total = v_sync_strt + v_sync_wid + upper;
569 FAIL("v_total too large");
570 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
572 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
576 pix_width = CRTC_PIX_WIDTH_8BPP;
578 HOST_8BPP | SRC_8BPP | DST_8BPP |
579 BYTE_ORDER_LSB_TO_MSB;
580 dp_chain_mask = 0x8080;
581 } else if (bpp <= 16) {
583 pix_width = CRTC_PIX_WIDTH_15BPP;
584 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
585 BYTE_ORDER_LSB_TO_MSB;
586 dp_chain_mask = 0x4210;
587 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
589 pix_width = CRTC_PIX_WIDTH_24BPP;
591 HOST_8BPP | SRC_8BPP | DST_8BPP |
592 BYTE_ORDER_LSB_TO_MSB;
593 dp_chain_mask = 0x8080;
594 } else if (bpp <= 32) {
596 pix_width = CRTC_PIX_WIDTH_32BPP;
597 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
598 BYTE_ORDER_LSB_TO_MSB;
599 dp_chain_mask = 0x8080;
603 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
604 FAIL("not enough video RAM");
606 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
607 FAIL("invalid vmode");
612 crtc->h_tot_disp = h_total | (h_disp << 16);
613 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly << 8) |
614 ((h_sync_strt & 0x100) << 4) | (h_sync_wid << 16) |
616 crtc->v_tot_disp = v_total | (v_disp << 16);
617 crtc->v_sync_strt_wid =
618 v_sync_strt | (v_sync_wid << 16) | (v_sync_pol << 21);
620 ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
622 pix_width | c_sync | CRTC_EXT_DISP_EN | CRTC_ENABLE;
623 if (M64_HAS(MAGIC_FIFO)) {
625 /* FIXME: magic FIFO values */
627 aty_ld_le32(CRTC_GEN_CNTL, par) & 0x000e0000;
629 crtc->dp_pix_width = dp_pix_width;
630 crtc->dp_chain_mask = dp_chain_mask;
636 static int aty_crtc_to_var(const struct crtc *crtc,
637 struct fb_var_screeninfo *var)
639 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
640 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
642 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
646 h_total = crtc->h_tot_disp & 0x1ff;
647 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
648 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) |
649 ((crtc->h_sync_strt_wid >> 4) & 0x100);
650 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
651 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
652 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
653 v_total = crtc->v_tot_disp & 0x7ff;
654 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
655 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
656 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
657 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
658 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
659 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
662 xres = (h_disp + 1) * 8;
664 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
665 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
666 hslen = h_sync_wid * 8;
667 upper = v_total - v_sync_strt - v_sync_wid;
668 lower = v_sync_strt - v_disp;
670 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
671 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
672 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
676 case CRTC_PIX_WIDTH_4BPP:
680 var->green.offset = 0;
681 var->green.length = 8;
682 var->blue.offset = 0;
683 var->blue.length = 8;
684 var->transp.offset = 0;
685 var->transp.length = 0;
688 case CRTC_PIX_WIDTH_8BPP:
692 var->green.offset = 0;
693 var->green.length = 8;
694 var->blue.offset = 0;
695 var->blue.length = 8;
696 var->transp.offset = 0;
697 var->transp.length = 0;
699 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
701 var->red.offset = 10;
703 var->green.offset = 5;
704 var->green.length = 5;
705 var->blue.offset = 0;
706 var->blue.length = 5;
707 var->transp.offset = 0;
708 var->transp.length = 0;
711 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
713 var->red.offset = 11;
715 var->green.offset = 5;
716 var->green.length = 6;
717 var->blue.offset = 0;
718 var->blue.length = 5;
719 var->transp.offset = 0;
720 var->transp.length = 0;
723 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
725 var->red.offset = 16;
727 var->green.offset = 8;
728 var->green.length = 8;
729 var->blue.offset = 0;
730 var->blue.length = 8;
731 var->transp.offset = 0;
732 var->transp.length = 0;
734 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
736 var->red.offset = 16;
738 var->green.offset = 8;
739 var->green.length = 8;
740 var->blue.offset = 0;
741 var->blue.length = 8;
742 var->transp.offset = 24;
743 var->transp.length = 8;
746 FAIL("Invalid pixel width");
752 var->xres_virtual = crtc->vxres;
753 var->yres_virtual = crtc->vyres;
754 var->bits_per_pixel = bpp;
755 var->left_margin = left;
756 var->right_margin = right;
757 var->upper_margin = upper;
758 var->lower_margin = lower;
759 var->hsync_len = hslen;
760 var->vsync_len = vslen;
762 var->vmode = FB_VMODE_NONINTERLACED;
767 /* ------------------------------------------------------------------------- */
769 static int atyfb_set_par(struct fb_info *info)
771 struct atyfb_par *par = (struct atyfb_par *) info->par;
772 struct fb_var_screeninfo *var = &info->var;
777 if ((err = aty_var_to_crtc(info, var, &par->crtc)) ||
778 (err = par->pll_ops->var_to_pll(info, var->pixclock,
779 var->bits_per_pixel, &par->pll)))
782 par->accel_flags = var->accel_flags; /* hack */
784 if (par->blitter_may_be_busy)
786 tmp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
787 aty_set_crtc(par, &par->crtc);
788 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par);
789 /* better call aty_StrobeClock ?? */
790 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, CLOCK_STROBE, par);
792 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel,
794 par->pll_ops->set_pll(info, &par->pll);
796 if (!M64_HAS(INTEGRATED)) {
797 /* Don't forget MEM_CNTL */
798 i = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
799 switch (var->bits_per_pixel) {
810 aty_st_le32(MEM_CNTL, i, par);
812 i = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
813 if (!M64_HAS(MAGIC_POSTDIV))
814 i |= par->mem_refresh_rate << 20;
815 switch (var->bits_per_pixel) {
827 if (M64_HAS(CT_BUS)) {
828 aty_st_le32(DAC_CNTL, 0x87010184, par);
829 aty_st_le32(BUS_CNTL, 0x680000f9, par);
830 } else if (M64_HAS(VT_BUS)) {
831 aty_st_le32(DAC_CNTL, 0x87010184, par);
832 aty_st_le32(BUS_CNTL, 0x680000f9, par);
833 } else if (M64_HAS(MOBIL_BUS)) {
834 aty_st_le32(DAC_CNTL, 0x80010102, par);
835 aty_st_le32(BUS_CNTL, 0x7b33a040, par);
838 aty_st_le32(DAC_CNTL, 0x86010102, par);
839 aty_st_le32(BUS_CNTL, 0x7b23a040, par);
840 aty_st_le32(EXT_MEM_CNTL,
841 aty_ld_le32(EXT_MEM_CNTL,
842 par) | 0x5000001, par);
844 aty_st_le32(MEM_CNTL, i, par);
846 aty_st_8(DAC_MASK, 0xff, par);
848 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
849 info->fix.visual = var->bits_per_pixel <= 8 ?
850 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
852 /* Initialize the graphics engine */
853 if (par->accel_flags & FB_ACCELF_TEXT)
854 aty_init_engine(par, info);
856 #ifdef CONFIG_BOOTX_TEXT
857 btext_update_display(info->fix.smem_start,
858 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
859 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
861 par->crtc.vxres * var->bits_per_pixel / 8);
862 #endif /* CONFIG_BOOTX_TEXT */
866 static int atyfb_check_var(struct fb_var_screeninfo *var,
867 struct fb_info *info)
869 struct atyfb_par *par = (struct atyfb_par *) info->par;
874 if ((err = aty_var_to_crtc(info, var, &crtc)) ||
875 (err = par->pll_ops->var_to_pll(info, var->pixclock,
876 var->bits_per_pixel, &pll)))
879 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
880 if (!fbmon_valid_timings(var->pixclock, htotal, vtotal, info))
883 aty_crtc_to_var(&crtc, var);
884 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
888 static void set_off_pitch(struct atyfb_par *par,
889 const struct fb_info *info)
891 u32 xoffset = info->var.xoffset;
892 u32 yoffset = info->var.yoffset;
893 u32 vxres = par->crtc.vxres;
894 u32 bpp = info->var.bits_per_pixel;
896 par->crtc.off_pitch =
897 ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
898 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
903 * Open/Release the frame buffer device
906 static int atyfb_open(struct fb_info *info, int user)
909 struct atyfb_par *par = (struct atyfb_par *) info->par;
919 struct fb_var_screeninfo default_var = {
920 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
921 640, 480, 640, 480, 0, 0, 8, 0,
922 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
923 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
924 0, FB_VMODE_NONINTERLACED
927 static int atyfb_release(struct fb_info *info, int user)
930 struct atyfb_par *par = (struct atyfb_par *) info->par;
937 int was_mmaped = par->mmaped;
942 struct fb_var_screeninfo var;
944 /* Now reset the default display config, we have no
945 * idea what the program(s) which mmap'd the chip did
946 * to the configuration, nor whether it restored it
951 var.accel_flags &= ~FB_ACCELF_TEXT;
953 var.accel_flags |= FB_ACCELF_TEXT;
954 if (var.yres == var.yres_virtual) {
956 (info->fix.smem_len -
960 var.bits_per_pixel) /
962 if (var.yres_virtual < var.yres)
974 * Pan or Wrap the Display
976 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
979 static int atyfb_pan_display(struct fb_var_screeninfo *var,
980 struct fb_info *info)
982 struct atyfb_par *par = (struct atyfb_par *) info->par;
983 u32 xres, yres, xoffset, yoffset;
985 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
986 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
987 xoffset = (var->xoffset + 7) & ~7;
988 yoffset = var->yoffset;
989 if (xoffset + xres > par->crtc.vxres
990 || yoffset + yres > par->crtc.vyres)
992 info->var.xoffset = xoffset;
993 info->var.yoffset = yoffset;
994 set_off_pitch(par, info);
999 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1000 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1006 u8 mclk_post_div; /* 1,2,3,4,8 */
1008 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1009 u32 dsp_xclks_per_row; /* 0-16383 */
1010 u32 dsp_loop_latency; /* 0-15 */
1011 u32 dsp_precision; /* 0-7 */
1012 u32 dsp_on; /* 0-2047 */
1013 u32 dsp_off; /* 0-2047 */
1016 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1017 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1020 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1021 u_long arg, struct fb_info *info)
1023 #if defined(__sparc__) || (defined(DEBUG) && defined(CONFIG_FB_ATY_CT))
1024 struct atyfb_par *par = (struct atyfb_par *) info->par;
1025 #endif /* __sparc__ || DEBUG */
1027 struct fbtype fbtyp;
1033 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1034 fbtyp.fb_width = par->crtc.vxres;
1035 fbtyp.fb_height = par->crtc.vyres;
1036 fbtyp.fb_depth = info->var.bits_per_pixel;
1037 fbtyp.fb_cmsize = info->cmap.len;
1038 fbtyp.fb_size = info->fix.smem_len;
1040 ((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1043 #endif /* __sparc__ */
1044 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1046 if (M64_HAS(INTEGRATED)) {
1048 union aty_pll *pll = par->pll;
1049 u32 dsp_config = pll->ct.dsp_config;
1050 u32 dsp_on_off = pll->ct.dsp_on_off;
1051 clk.ref_clk_per = par->ref_clk_per;
1052 clk.pll_ref_div = pll->ct.pll_ref_div;
1053 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1054 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1055 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1056 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1057 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1058 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1059 clk.dsp_precision = (dsp_config >> 20) & 7;
1060 clk.dsp_on = dsp_on_off & 0x7ff;
1061 clk.dsp_off = (dsp_on_off >> 16) & 0x7ff;
1063 ((struct atyclk *) arg, &clk, sizeof(clk)))
1069 if (M64_HAS(INTEGRATED)) {
1071 union aty_pll *pll = par->pll;
1073 (&clk, (struct atyclk *) arg, sizeof(clk)))
1075 par->ref_clk_per = clk.ref_clk_per;
1076 pll->ct.pll_ref_div = clk.pll_ref_div;
1077 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1078 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1079 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1080 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1081 pll->ct.dsp_config =
1083 dsp_xclks_per_row & 0x3fff) | ((clk.
1086 | ((clk.dsp_precision & 7) << 20);
1087 pll->ct.dsp_on_off =
1089 dsp_on & 0x7ff) | ((clk.
1090 dsp_off & 0x7ff) << 16);
1091 aty_calc_pll_ct(info, &pll->ct);
1092 aty_set_pll_ct(info, pll);
1097 if (get_user(par->features, (u32 *) arg))
1101 if (put_user(par->features, (u32 *) arg))
1104 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1111 static int atyfb_sync(struct fb_info *info)
1113 struct atyfb_par *par = (struct atyfb_par *) info->par;
1115 if (par->blitter_may_be_busy)
1121 static int atyfb_mmap(struct fb_info *info, struct file *file,
1122 struct vm_area_struct *vma)
1124 struct atyfb_par *par = (struct atyfb_par *) info->par;
1125 unsigned int size, page, map_size = 0;
1126 unsigned long map_offset = 0;
1133 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1136 off = vma->vm_pgoff << PAGE_SHIFT;
1137 size = vma->vm_end - vma->vm_start;
1139 /* To stop the swapper from even considering these pages. */
1140 vma->vm_flags |= (VM_SHM | VM_LOCKED);
1142 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1143 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1144 off += 0x8000000000000000UL;
1146 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1148 /* Each page, see which map applies */
1149 for (page = 0; page < size;) {
1151 for (i = 0; par->mmap_map[i].size; i++) {
1152 unsigned long start = par->mmap_map[i].voff;
1153 unsigned long end = start + par->mmap_map[i].size;
1154 unsigned long offset = off + page;
1161 map_size = par->mmap_map[i].size - (offset - start);
1163 par->mmap_map[i].poff + (offset - start);
1170 if (page + map_size > size)
1171 map_size = size - page;
1173 pgprot_val(vma->vm_page_prot) &=
1174 ~(par->mmap_map[i].prot_mask);
1175 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1177 if (remap_page_range(vma, vma->vm_start + page, map_offset,
1178 map_size, vma->vm_page_prot))
1187 vma->vm_flags |= VM_IO;
1201 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1205 for (i = 0; i < 256; i++) {
1206 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1207 if (M64_HAS(EXTRA_BRIGHT))
1209 aty_st_8(DAC_CNTL, tmp, par);
1210 aty_st_8(DAC_MASK, 0xff, par);
1212 writeb(i, &par->aty_cmap_regs->rindex);
1213 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1214 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1215 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1216 writeb(i, &par->aty_cmap_regs->windex);
1217 writeb(atyfb_save.r[1 - enter][i],
1218 &par->aty_cmap_regs->lut);
1219 writeb(atyfb_save.g[1 - enter][i],
1220 &par->aty_cmap_regs->lut);
1221 writeb(atyfb_save.b[1 - enter][i],
1222 &par->aty_cmap_regs->lut);
1226 static void atyfb_palette(int enter)
1228 struct atyfb_par *par;
1229 struct fb_info *info;
1232 for (i = 0; i < FB_MAX; i++) {
1233 info = registered_fb[i];
1234 if (info && info->fbops == &atyfb_ops) {
1235 par = (struct atyfb_par *) info->par;
1237 atyfb_save_palette(par, enter);
1239 atyfb_save.yoffset = info->var.yoffset;
1240 info->var.yoffset = 0;
1241 set_off_pitch(par, info);
1243 info->var.yoffset = atyfb_save.yoffset;
1244 set_off_pitch(par, info);
1250 #endif /* __sparc__ */
1254 #ifdef CONFIG_PMAC_PBOOK
1256 static struct fb_info *first_display = NULL;
1258 /* Power management routines. Those are used for PowerBook sleep.
1260 * It appears that Rage LT and Rage LT Pro have different power
1261 * management registers. There's is some confusion about which
1262 * chipID is a Rage LT or LT pro :(
1264 static int aty_power_mgmt_LT(int sleep, struct atyfb_par *par)
1269 pm = aty_ld_le32(POWER_MANAGEMENT_LG, par);
1270 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1271 aty_st_le32(POWER_MANAGEMENT_LG, pm, par);
1272 pm = aty_ld_le32(POWER_MANAGEMENT_LG, par);
1278 aty_st_le32(POWER_MANAGEMENT_LG, pm, par);
1279 pm = aty_ld_le32(POWER_MANAGEMENT_LG, par);
1281 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1283 aty_st_le32(POWER_MANAGEMENT_LG, pm, par);
1284 pm = aty_ld_le32(POWER_MANAGEMENT_LG, par);
1287 aty_st_le32(POWER_MANAGEMENT_LG, pm, par);
1289 pm = aty_ld_le32(POWER_MANAGEMENT_LG, par);
1291 if ((--timeout) == 0)
1293 } while ((pm & PWR_MGT_STATUS_MASK) !=
1294 PWR_MGT_STATUS_SUSPEND);
1298 aty_st_le32(POWER_MANAGEMENT_LG, pm, par);
1299 pm = aty_ld_le32(POWER_MANAGEMENT_LG, par);
1301 pm |= (PWR_BLON | AUTO_PWR_UP);
1303 aty_st_le32(POWER_MANAGEMENT_LG, pm, par);
1304 pm = aty_ld_le32(POWER_MANAGEMENT_LG, par);
1307 aty_st_le32(POWER_MANAGEMENT_LG, pm, par);
1309 pm = aty_ld_le32(POWER_MANAGEMENT_LG, par);
1311 if ((--timeout) == 0)
1313 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
1317 return timeout ? PBOOK_SLEEP_OK : PBOOK_SLEEP_REFUSE;
1320 static int aty_power_mgmt_LTPro(int sleep, struct atyfb_par *par)
1325 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1326 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1327 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1328 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1334 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1335 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1337 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1339 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1340 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1343 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1345 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1347 if ((--timeout) == 0)
1349 } while ((pm & PWR_MGT_STATUS_MASK) !=
1350 PWR_MGT_STATUS_SUSPEND);
1354 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1355 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1358 pm |= (PWR_BLON | AUTO_PWR_UP);
1359 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1360 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1363 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1365 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1367 if ((--timeout) == 0)
1369 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
1372 return timeout ? PBOOK_SLEEP_OK : PBOOK_SLEEP_REFUSE;
1375 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1377 return M64_HAS(LT_SLEEP) ? aty_power_mgmt_LT(sleep, par)
1378 : aty_power_mgmt_LTPro(sleep, par);
1382 * Save the contents of the frame buffer when we go to sleep,
1383 * and restore it when we wake up again.
1385 static int aty_sleep_notify(struct pmu_sleep_notifier *self, int when)
1387 struct fb_info *info;
1388 struct atyfb_par *par;
1391 result = PBOOK_SLEEP_OK;
1393 for (info = first_display; info != NULL; info = par->next) {
1396 par = (struct atyfb_par *) info->par;
1397 nb = info->var.yres * info->fix.line_length;
1400 case PBOOK_SLEEP_REQUEST:
1401 par->save_framebuffer = vmalloc(nb);
1402 if (par->save_framebuffer == NULL)
1403 return PBOOK_SLEEP_REFUSE;
1405 case PBOOK_SLEEP_REJECT:
1406 if (par->save_framebuffer) {
1407 vfree(par->save_framebuffer);
1408 par->save_framebuffer = NULL;
1411 case PBOOK_SLEEP_NOW:
1412 if (par->blitter_may_be_busy)
1414 /* Stop accel engine (stop bus mastering) */
1415 if (par->accel_flags & FB_ACCELF_TEXT)
1416 aty_reset_engine(par);
1418 /* Backup fb content */
1419 if (par->save_framebuffer)
1420 memcpy_fromio(par->save_framebuffer,
1421 (void *) info->screen_base, nb);
1423 /* Blank display and LCD */
1424 atyfb_blank(VESA_POWERDOWN + 1, info);
1426 /* Set chip to "suspend" mode */
1427 result = aty_power_mgmt(1, par);
1431 result = aty_power_mgmt(0, par);
1433 /* Restore fb content */
1434 if (par->save_framebuffer) {
1435 memcpy_toio((void *) info->screen_base,
1436 par->save_framebuffer, nb);
1437 vfree(par->save_framebuffer);
1438 par->save_framebuffer = NULL;
1440 /* Restore display */
1441 atyfb_set_par(info);
1442 atyfb_blank(0, info);
1449 static struct pmu_sleep_notifier aty_sleep_notifier = {
1450 aty_sleep_notify, SLEEP_LEVEL_VIDEO,
1452 #endif /* CONFIG_PMAC_PBOOK */
1454 #ifdef CONFIG_PMAC_BACKLIGHT
1457 * LCD backlight control
1460 static int backlight_conv[] = {
1461 0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
1462 0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
1465 static int aty_set_backlight_enable(int on, int level, void *data)
1467 struct fb_info *info = (struct fb_info *) data;
1468 struct atyfb_par *par = (struct atyfb_par *) info->par;
1469 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
1471 reg |= (BLMOD_EN | BIASMOD_EN);
1472 if (on && level > BACKLIGHT_OFF) {
1473 reg &= ~BIAS_MOD_LEVEL_MASK;
1474 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
1476 reg &= ~BIAS_MOD_LEVEL_MASK;
1477 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
1479 aty_st_lcd(LCD_MISC_CNTL, reg, par);
1483 static int aty_set_backlight_level(int level, void *data)
1485 return aty_set_backlight_enable(1, level, data);
1488 static struct backlight_controller aty_backlight_controller = {
1489 aty_set_backlight_enable,
1490 aty_set_backlight_level
1492 #endif /* CONFIG_PMAC_BACKLIGHT */
1500 static struct fb_info *fb_list = NULL;
1502 static int __init aty_init(struct fb_info *info, const char *name)
1504 struct atyfb_par *par = (struct atyfb_par *) info->par;
1505 const char *chipname = NULL, *ramname = NULL, *xtal;
1506 int j, pll, mclk, gtb_memsize;
1507 struct fb_var_screeninfo var;
1511 #if defined(CONFIG_PPC)
1516 par->aty_cmap_regs =
1517 (struct aty_cmap_regs *) (par->ati_regbase + 0xc0);
1518 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
1519 type = chip_id & CFG_CHIP_TYPE;
1520 rev = (chip_id & CFG_CHIP_REV) >> 24;
1521 for (j = 0; j < (sizeof(aty_chips) / sizeof(*aty_chips)); j++)
1522 if (type == aty_chips[j].chip_type &&
1523 (rev & aty_chips[j].rev_mask) ==
1524 aty_chips[j].rev_val) {
1525 chipname = aty_chips[j].name;
1526 pll = aty_chips[j].pll;
1527 mclk = aty_chips[j].mclk;
1528 par->features = aty_chips[j].features;
1531 printk("atyfb: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
1535 printk("atyfb: %s [0x%04x rev 0x%02x] ", chipname, type, rev);
1536 #ifdef CONFIG_FB_ATY_GX
1537 if (!M64_HAS(INTEGRATED)) {
1539 u8 dac_type, dac_subtype, clk_type;
1540 stat0 = aty_ld_le32(CONFIG_STAT0, par);
1541 par->bus_type = (stat0 >> 0) & 0x07;
1542 par->ram_type = (stat0 >> 3) & 0x07;
1543 ramname = aty_gx_ram[par->ram_type];
1544 /* FIXME: clockchip/RAMDAC probing? */
1545 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
1547 clk_type = CLK_ATI18818_1;
1548 dac_type = (stat0 >> 9) & 0x07;
1549 if (dac_type == 0x07)
1550 dac_subtype = DAC_ATT20C408;
1553 (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) |
1556 dac_type = DAC_IBMRGB514;
1557 dac_subtype = DAC_IBMRGB514;
1558 clk_type = CLK_IBMRGB514;
1560 switch (dac_subtype) {
1562 par->dac_ops = &aty_dac_ibm514;
1564 case DAC_ATI68860_B:
1565 case DAC_ATI68860_C:
1566 par->dac_ops = &aty_dac_ati68860b;
1570 par->dac_ops = &aty_dac_att21c498;
1574 (" atyfb_set_par: DAC type not implemented yet!\n");
1575 par->dac_ops = &aty_dac_unsupported;
1579 case CLK_ATI18818_1:
1580 par->pll_ops = &aty_pll_ati18818_1;
1583 par->pll_ops = &aty_pll_stg1703;
1586 par->pll_ops = &aty_pll_ch8398;
1589 par->pll_ops = &aty_pll_att20c408;
1592 par->pll_ops = &aty_pll_ibm514;
1596 (" atyfb_set_par: CLK type not implemented yet!");
1597 par->pll_ops = &aty_pll_unsupported;
1601 #endif /* CONFIG_FB_ATY_GX */
1602 #ifdef CONFIG_FB_ATY_CT
1603 if (M64_HAS(INTEGRATED)) {
1604 par->bus_type = PCI;
1605 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
1606 ramname = aty_ct_ram[par->ram_type];
1607 par->dac_ops = &aty_dac_ct;
1608 par->pll_ops = &aty_pll_ct;
1609 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
1610 if (mclk == 67 && par->ram_type < SDRAM)
1613 #endif /* CONFIG_FB_ATY_CT */
1615 par->ref_clk_per = 1000000000000ULL / 14318180;
1617 if (M64_HAS(GTB_DSP)
1618 && (pll_ref_div = aty_ld_pll(PLL_REF_DIV, par))) {
1620 diff1 = 510 * 14 / pll_ref_div - pll;
1621 diff2 = 510 * 29 / pll_ref_div - pll;
1626 if (diff2 < diff1) {
1627 par->ref_clk_per = 1000000000000ULL / 29498928;
1632 i = aty_ld_le32(MEM_CNTL, par);
1633 gtb_memsize = M64_HAS(GTB_DSP);
1635 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
1637 info->fix.smem_len = 0x80000;
1640 info->fix.smem_len = 0x100000;
1642 case MEM_SIZE_2M_GTB:
1643 info->fix.smem_len = 0x200000;
1645 case MEM_SIZE_4M_GTB:
1646 info->fix.smem_len = 0x400000;
1648 case MEM_SIZE_6M_GTB:
1649 info->fix.smem_len = 0x600000;
1651 case MEM_SIZE_8M_GTB:
1652 info->fix.smem_len = 0x800000;
1655 info->fix.smem_len = 0x80000;
1657 switch (i & MEM_SIZE_ALIAS) {
1659 info->fix.smem_len = 0x80000;
1662 info->fix.smem_len = 0x100000;
1665 info->fix.smem_len = 0x200000;
1668 info->fix.smem_len = 0x400000;
1671 info->fix.smem_len = 0x600000;
1674 info->fix.smem_len = 0x800000;
1677 info->fix.smem_len = 0x80000;
1680 if (M64_HAS(MAGIC_VRAM_SIZE)) {
1681 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
1682 info->fix.smem_len += 0x400000;
1686 info->fix.smem_len = default_vram * 1024;
1687 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
1688 if (info->fix.smem_len <= 0x80000)
1690 else if (info->fix.smem_len <= 0x100000)
1692 else if (info->fix.smem_len <= 0x200000)
1693 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
1694 else if (info->fix.smem_len <= 0x400000)
1695 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
1696 else if (info->fix.smem_len <= 0x600000)
1697 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
1699 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
1700 aty_st_le32(MEM_CNTL, i, par);
1704 * Reg Block 0 (CT-compatible block) is at mmio_start
1705 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
1708 info->fix.mmio_len = 0x400;
1709 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
1710 } else if (M64_HAS(CT)) {
1711 info->fix.mmio_len = 0x400;
1712 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
1713 } else if (M64_HAS(VT)) {
1714 info->fix.mmio_start = -0x400;
1715 info->fix.mmio_len = 0x800;
1716 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
1717 } else { /* if (M64_HAS(GT)) */
1719 info->fix.mmio_start = -0x400;
1720 info->fix.mmio_len = 0x800;
1721 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
1727 mclk = default_mclk;
1729 printk("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK\n",
1730 info->fix.smem_len ==
1731 0x80000 ? 512 : (info->fix.smem_len >> 20),
1732 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname,
1736 par->mem_refresh_rate = 0; /* 000 = 10 Mhz - 43 Mhz */
1738 par->mem_refresh_rate = 1; /* 001 = 44 Mhz - 49 Mhz */
1740 par->mem_refresh_rate = 2; /* 010 = 50 Mhz - 54 Mhz */
1742 par->mem_refresh_rate = 3; /* 011 = 55 Mhz - 65 Mhz */
1744 par->mem_refresh_rate = 4; /* 100 = 66 Mhz - 74 Mhz */
1746 par->mem_refresh_rate = 5; /* 101 = 75 Mhz - 79 Mhz */
1747 else if (mclk < 100)
1748 par->mem_refresh_rate = 6; /* 110 = 80 Mhz - 100 Mhz */
1750 par->mem_refresh_rate = 7; /* 111 = 100 Mhz and above */
1751 par->pll_per = 1000000 / pll;
1752 par->mclk_per = 1000000 / mclk;
1755 if (M64_HAS(INTEGRATED)) {
1758 ("BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
1759 "DSP_CONFIG DSP_ON_OFF\n"
1760 "%08x %08x %08x %08x %08x %08x %08x\n"
1761 "PLL", aty_ld_le32(BUS_CNTL, par),
1762 aty_ld_le32(DAC_CNTL, par), aty_ld_le32(MEM_CNTL,
1764 aty_ld_le32(EXT_MEM_CNTL, par),
1765 aty_ld_le32(CRTC_GEN_CNTL, par),
1766 aty_ld_le32(DSP_CONFIG, par), aty_ld_le32(DSP_ON_OFF,
1768 for (i = 0; i < 16; i++)
1769 printk(" %02x", aty_ld_pll(i, par));
1775 * Last page of 8 MB (4 MB on ISA) aperture is MMIO
1776 * FIXME: we should use the auxiliary aperture instead so we can access
1777 * the full 8 MB of video RAM on 8 MB boards
1779 if (info->fix.smem_len == 0x800000 ||
1780 (par->bus_type == ISA
1781 && info->fix.smem_len == 0x400000))
1782 info->fix.smem_len -= GUI_RESERVE;
1784 /* Clear the video memory */
1785 fb_memset((void *) info->screen_base, 0,
1786 info->fix.smem_len);
1788 info->fbops = &atyfb_ops;
1789 info->pseudo_palette = pseudo_palette;
1790 info->flags = FBINFO_FLAG_DEFAULT;
1792 #ifdef CONFIG_PMAC_BACKLIGHT
1793 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
1794 /* these bits let the 101 powerbook wake up from sleep -- paulus */
1795 aty_st_lcd(POWER_MANAGEMENT,
1796 aty_ld_lcd(POWER_MANAGEMENT, par)
1797 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
1799 if (M64_HAS(MOBIL_BUS))
1800 register_backlight_controller(&aty_backlight_controller,
1802 #endif /* CONFIG_PMAC_BACKLIGHT */
1807 memset(&var, 0, sizeof(var));
1809 if (_machine == _MACH_Pmac) {
1811 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
1812 * applies to all Mac video cards
1816 (&var, info, mode_option, 8))
1819 if (default_vmode == VMODE_CHOOSE) {
1820 if (M64_HAS(G3_PB_1024x768))
1821 /* G3 PowerBook with 1024x768 LCD */
1822 default_vmode = VMODE_1024_768_60;
1823 else if (machine_is_compatible("iMac"))
1824 default_vmode = VMODE_1024_768_75;
1825 else if (machine_is_compatible
1827 /* iBook with 800x600 LCD */
1828 default_vmode = VMODE_800_600_60;
1830 default_vmode = VMODE_640_480_67;
1831 sense = read_aty_sense(par);
1833 "atyfb: monitor sense=%x, mode %d\n",
1835 mac_map_monitor_sense(sense));
1837 if (default_vmode <= 0
1838 || default_vmode > VMODE_MAX)
1839 default_vmode = VMODE_640_480_60;
1840 if (default_cmode < CMODE_8
1841 || default_cmode > CMODE_32)
1842 default_cmode = CMODE_8;
1843 if (mac_vmode_to_var
1844 (default_vmode, default_cmode, &var))
1849 (&var, info, mode_option, NULL, 0, NULL, 8))
1851 #else /* !CONFIG_PPC */
1855 (&var, info, mode_option, NULL, 0, NULL, 8))
1861 (&var, info, mode_option, NULL, 0, NULL, 8))
1863 #endif /* !__sparc__ */
1864 #endif /* !CONFIG_PPC */
1865 #endif /* !MODULE */
1867 var.accel_flags &= ~FB_ACCELF_TEXT;
1869 var.accel_flags |= FB_ACCELF_TEXT;
1871 if (var.yres == var.yres_virtual) {
1872 u32 vram = (info->fix.smem_len - (PAGE_SIZE << 2));
1874 ((vram * 8) / var.bits_per_pixel) / var.xres_virtual;
1875 if (var.yres_virtual < var.yres)
1876 var.yres_virtual = var.yres;
1879 if (atyfb_check_var(&var, info)) {
1880 printk("atyfb: can't set default video mode\n");
1884 atyfb_save_palette(par, 0);
1887 #ifdef CONFIG_FB_ATY_CT
1888 if (curblink && M64_HAS(INTEGRATED))
1889 par->cursor = aty_init_cursor(info);
1890 #endif /* CONFIG_FB_ATY_CT */
1893 fb_alloc_cmap(&info->cmap, 256, 0);
1895 if (register_framebuffer(info) < 0)
1900 printk("fb%d: %s frame buffer device on %s\n",
1901 info->node, info->fix.id, name);
1905 int __init atyfb_init(void)
1907 #if defined(CONFIG_PCI)
1908 unsigned long addr, res_start, res_size;
1909 struct atyfb_par *default_par;
1910 struct pci_dev *pdev = NULL;
1911 struct fb_info *info;
1914 extern void (*prom_palette) (int);
1915 extern int con_is_present(void);
1916 struct pcidev_cookie *pcp;
1921 /* Do not attach when we have a serial console. */
1922 if (!con_is_present())
1929 pci_find_device(PCI_VENDOR_ID_ATI, PCI_ANY_ID, pdev))) {
1930 if ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
1931 struct resource *rp;
1934 sizeof(aty_chips) / sizeof(*aty_chips) - 1;
1936 if (pdev->device == aty_chips[i].pci_id)
1941 rp = &pdev->resource[0];
1942 if (rp->flags & IORESOURCE_IO)
1943 rp = &pdev->resource[1];
1948 res_start = rp->start;
1949 res_size = rp->end - rp->start + 1;
1950 if (!request_mem_region
1951 (res_start, res_size, "atyfb"))
1955 kmalloc(sizeof(struct fb_info), GFP_ATOMIC);
1958 ("atyfb_init: can't alloc fb_info\n");
1961 memset(info, 0, sizeof(struct fb_info));
1964 kmalloc(sizeof(struct atyfb_par), GFP_ATOMIC);
1967 ("atyfb_init: can't alloc atyfb_par\n");
1971 memset(default_par, 0, sizeof(struct atyfb_par));
1973 info->fix = atyfb_fix;
1974 info->par = default_par;
1978 * Map memory-mapped registers.
1980 default_par->ati_regbase = addr + 0x7ffc00UL;
1981 info->fix.mmio_start = addr + 0x7ffc00UL;
1984 * Map in big-endian aperture.
1986 info->screen_base = (char *) (addr + 0x800000UL);
1987 info->fix.smem_start = addr + 0x800000UL;
1990 * Figure mmap addresses from PCI config space.
1991 * Split Framebuffer in big- and little-endian halfs.
1993 for (i = 0; i < 6 && pdev->resource[i].start; i++)
1997 default_par->mmap_map =
1998 kmalloc(j * sizeof(*default_par->mmap_map),
2000 if (!default_par->mmap_map) {
2002 ("atyfb_init: can't alloc mmap_map\n");
2005 release_mem_region(res_start, res_size);
2008 memset(default_par->mmap_map, 0,
2009 j * sizeof(*default_par->mmap_map));
2012 i < 6 && pdev->resource[i].start; i++) {
2013 struct resource *rp = &pdev->resource[i];
2015 PCI_BASE_ADDRESS_0 + (i << 2);
2021 io = (rp->flags & IORESOURCE_IO);
2023 size = rp->end - base + 1;
2025 pci_read_config_dword(pdev, breg, &pbase);
2031 * Map the framebuffer a second time, this time without
2032 * the braindead _PAGE_IE setting. This is used by the
2033 * fixed Xserver, but we need to maintain the old mapping
2034 * to stay compatible with older ones...
2037 default_par->mmap_map[j].voff =
2039 0x10000000) & PAGE_MASK;
2040 default_par->mmap_map[j].poff =
2042 default_par->mmap_map[j].size =
2044 ~PAGE_MASK) & PAGE_MASK;
2045 default_par->mmap_map[j].prot_mask =
2047 default_par->mmap_map[j].prot_flag =
2053 * Here comes the old framebuffer mapping with _PAGE_IE
2054 * set for the big endian half of the framebuffer...
2057 default_par->mmap_map[j].voff =
2058 (pbase + 0x800000) & PAGE_MASK;
2059 default_par->mmap_map[j].poff =
2060 (base + 0x800000) & PAGE_MASK;
2061 default_par->mmap_map[j].size = 0x800000;
2062 default_par->mmap_map[j].prot_mask =
2064 default_par->mmap_map[j].prot_flag =
2070 default_par->mmap_map[j].voff = pbase & PAGE_MASK;
2071 default_par->mmap_map[j].poff = base & PAGE_MASK;
2072 default_par->mmap_map[j].size =
2073 (size + ~PAGE_MASK) & PAGE_MASK;
2074 default_par->mmap_map[j].prot_mask = _PAGE_CACHE;
2075 default_par->mmap_map[j].prot_flag = _PAGE_E;
2079 if (pdev->device != XL_CHIP_ID) {
2081 * Fix PROMs idea of MEM_CNTL settings...
2083 mem = aty_ld_le32(MEM_CNTL, default_par);
2084 chip_id = aty_ld_le32(CONFIG_CHIP_ID, default_par);
2085 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID)
2086 && !((chip_id >> 24) & 1)) {
2087 switch (mem & 0x0f) {
2089 mem = (mem & ~(0x0f)) | 2;
2092 mem = (mem & ~(0x0f)) | 3;
2095 mem = (mem & ~(0x0f)) | 4;
2098 mem = (mem & ~(0x0f)) | 5;
2103 if ((aty_ld_le32(CONFIG_STAT0, default_par) & 7) >= SDRAM)
2104 mem &= ~(0x00700000);
2106 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
2107 aty_st_le32(MEM_CNTL, mem, default_par);
2111 * If this is the console device, we will set default video
2112 * settings to what the PROM left us with.
2114 node = prom_getchild(prom_root_node);
2115 node = prom_searchsiblings(node, "aliases");
2118 prom_getproperty(node, "screen", prop,
2122 node = prom_finddevice(prop);
2128 pcp = pdev->sysdata;
2129 if (node == pcp->prom_node) {
2131 struct fb_var_screeninfo *var =
2133 unsigned int N, P, Q, M, T, R;
2134 u32 v_total, h_total;
2140 prom_getintdefault(node, "width",
2143 prom_getintdefault(node, "height",
2145 var->bits_per_pixel =
2146 prom_getintdefault(node, "depth", 8);
2147 var->xoffset = var->yoffset = 0;
2149 aty_ld_le32(CRTC_H_TOTAL_DISP, default_par);
2150 crtc.h_sync_strt_wid =
2151 aty_ld_le32(CRTC_H_SYNC_STRT_WID,
2154 aty_ld_le32(CRTC_V_TOTAL_DISP, default_par);
2155 crtc.v_sync_strt_wid =
2156 aty_ld_le32(CRTC_V_SYNC_STRT_WID,
2159 aty_ld_le32(CRTC_GEN_CNTL, default_par);
2160 aty_crtc_to_var(&crtc, var);
2162 h_total = var->xres + var->right_margin +
2163 var->hsync_len + var->left_margin;
2164 v_total = var->yres + var->lower_margin +
2165 var->vsync_len + var->upper_margin;
2168 * Read the PLL to figure actual Refresh Rate.
2170 clock_cntl = aty_ld_8(CLOCK_CNTL, default_par);
2171 /* printk("atyfb: CLOCK_CNTL: %02x\n", clock_cntl); */
2172 for (i = 0; i < 16; i++)
2173 pll_regs[i] = aty_ld_pll(i, default_par);
2176 * PLL Reference Divider M:
2181 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
2183 N = pll_regs[7 + (clock_cntl & 3)];
2186 * PLL Post Divider P (Dependant on CLOCK_CNTL):
2188 P = 1 << (pll_regs[6] >>
2189 ((clock_cntl & 3) << 1));
2203 * where R is XTALIN (= 14318 or 29498 kHz).
2205 if (pdev->device == XL_CHIP_ID)
2212 default_var.pixclock = 1000000000 / T;
2214 #else /* __sparc__ */
2216 info->fix.mmio_start = 0x7ff000 + addr;
2217 default_par->ati_regbase = (unsigned long)
2218 ioremap(info->fix.mmio_start, 0x1000);
2220 if (!default_par->ati_regbase) {
2222 kfree(default_par->mmap_map);
2226 release_mem_region(res_start, res_size);
2230 info->fix.mmio_start += 0xc00;
2231 default_par->ati_regbase += 0xc00;
2234 * Enable memory-space accesses using config-space
2237 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
2238 if (!(tmp & PCI_COMMAND_MEMORY)) {
2239 tmp |= PCI_COMMAND_MEMORY;
2240 pci_write_config_word(pdev, PCI_COMMAND,
2244 /* Use the big-endian aperture */
2248 /* Map in frame buffer */
2249 info->fix.smem_start = addr;
2251 (char *) ioremap(addr, 0x800000);
2253 if (!info->screen_base) {
2255 kfree(default_par->mmap_map);
2259 release_mem_region(res_start, res_size);
2262 #endif /* __sparc__ */
2264 if (!aty_init(info, "PCI")) {
2266 if (default_par->mmap_map)
2267 kfree(default_par->mmap_map);
2271 release_mem_region(res_start, res_size);
2276 prom_palette = atyfb_palette;
2279 * Add /dev/fb mmap values.
2281 default_par->mmap_map[0].voff = 0x8000000000000000UL;
2282 default_par->mmap_map[0].poff =
2283 (unsigned long) info->screen_base & PAGE_MASK;
2284 default_par->mmap_map[0].size =
2286 default_par->mmap_map[0].prot_mask = _PAGE_CACHE;
2287 default_par->mmap_map[0].prot_flag = _PAGE_E;
2288 default_par->mmap_map[1].voff =
2289 default_par->mmap_map[0].voff +
2291 default_par->mmap_map[1].poff =
2292 default_par->ati_regbase & PAGE_MASK;
2293 default_par->mmap_map[1].size = PAGE_SIZE;
2294 default_par->mmap_map[1].prot_mask = _PAGE_CACHE;
2295 default_par->mmap_map[1].prot_flag = _PAGE_E;
2296 #endif /* __sparc__ */
2298 #ifdef CONFIG_PMAC_PBOOK
2299 if (first_display == NULL)
2300 pmu_register_sleep_notifier(&aty_sleep_notifier);
2301 default_par->next = first_display;
2306 #elif defined(CONFIG_ATARI)
2307 struct atyfb_par *default_par;
2308 struct fb_info *info;
2312 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
2313 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
2314 !phys_guiregbase[m64_num]) {
2316 (" phys_*[%d] parameters not set => returning early. \n",
2321 info = kmalloc(sizeof(struct fb_info), GFP_ATOMIC);
2323 printk("atyfb_init: can't alloc fb_info\n");
2326 memset(info, 0, sizeof(struct fb_info));
2328 default_par = kmalloc(sizeof(struct atyfb_par), GFP_ATOMIC);
2331 ("atyfb_init: can't alloc atyfb_par\n");
2335 memset(default_par, 0, sizeof(struct atyfb_par));
2337 info->fix = atyfb_fix;
2338 info->par = default_par;
2341 * Map the video memory (physical address given) to somewhere in the
2342 * kernel address space.
2344 info->screen_base = ioremap(phys_vmembase[m64_num],
2345 phys_size[m64_num]);
2346 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
2347 default_par->ati_regbase = (unsigned long)ioremap(phys_guiregbase[m64_num],
2348 0x10000) + 0xFC00ul;
2349 info->fix.mmio_start = default_par->ati_regbase; /* Fake! */
2351 aty_st_le32(CLOCK_CNTL, 0x12345678, default_par);
2352 clock_r = aty_ld_le32(CLOCK_CNTL, default_par);
2354 switch (clock_r & 0x003F) {
2356 default_par->clk_wr_offset = 3; /* */
2359 default_par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
2362 default_par->clk_wr_offset = 1; /* */
2365 default_par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
2369 if (!aty_init(info, "ISA bus")) {
2372 /* This is insufficient! kernel_map has added two large chunks!! */
2376 #endif /* CONFIG_ATARI */
2381 int __init atyfb_setup(char *options)
2385 if (!options || !*options)
2388 while ((this_opt = strsep(&options, ",")) != NULL) {
2389 if (!strncmp(this_opt, "noblink", 7)) {
2391 } else if (!strncmp(this_opt, "noaccel", 7)) {
2393 } else if (!strncmp(this_opt, "vram:", 5))
2395 simple_strtoul(this_opt + 5, NULL, 0);
2396 else if (!strncmp(this_opt, "pll:", 4))
2398 simple_strtoul(this_opt + 4, NULL, 0);
2399 else if (!strncmp(this_opt, "mclk:", 5))
2401 simple_strtoul(this_opt + 5, NULL, 0);
2403 else if (!strncmp(this_opt, "vmode:", 6)) {
2404 unsigned int vmode =
2405 simple_strtoul(this_opt + 6, NULL, 0);
2406 if (vmode > 0 && vmode <= VMODE_MAX)
2407 default_vmode = vmode;
2408 } else if (!strncmp(this_opt, "cmode:", 6)) {
2409 unsigned int cmode =
2410 simple_strtoul(this_opt + 6, NULL, 0);
2414 default_cmode = CMODE_8;
2418 default_cmode = CMODE_16;
2422 default_cmode = CMODE_32;
2429 * Why do we need this silly Mach64 argument?
2430 * We are already here because of mach64= so its redundant.
2432 else if (MACH_IS_ATARI
2433 && (!strncmp(this_opt, "Mach64:", 7))) {
2434 static unsigned char m64_num;
2435 static char mach64_str[80];
2436 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
2437 if (!store_video_par(mach64_str, m64_num)) {
2439 mach64_count = m64_num;
2444 mode_option = this_opt;
2448 #endif /* !MODULE */
2451 static int __init store_video_par(char *video_str, unsigned char m64_num)
2454 unsigned long vmembase, size, guiregbase;
2456 printk("store_video_par() '%s' \n", video_str);
2458 if (!(p = strsep(&video_str, ";")) || !*p)
2459 goto mach64_invalid;
2460 vmembase = simple_strtoul(p, NULL, 0);
2461 if (!(p = strsep(&video_str, ";")) || !*p)
2462 goto mach64_invalid;
2463 size = simple_strtoul(p, NULL, 0);
2464 if (!(p = strsep(&video_str, ";")) || !*p)
2465 goto mach64_invalid;
2466 guiregbase = simple_strtoul(p, NULL, 0);
2468 phys_vmembase[m64_num] = vmembase;
2469 phys_size[m64_num] = size;
2470 phys_guiregbase[m64_num] = guiregbase;
2471 printk(" stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2476 phys_vmembase[m64_num] = 0;
2479 #endif /* CONFIG_ATARI */
2482 #ifdef CONFIG_FB_ATY_CT
2484 if (par->cursor && (info->currcon >= 0))
2485 atyfb_cursor(&fb_display[par->currcon], CM_ERASE,
2486 par->cursor->pos.x, par->cursor->pos.y);
2487 #endif * CONFIG_FB_ATY_CT *
2489 #ifdef CONFIG_FB_ATY_CT
2490 * Install hw cursor *
2492 aty_set_cursor_color(info);
2493 aty_set_cursor_shape(info);
2495 #endif * CONFIG_FB_ATY_CT */
2498 * Blank the display.
2501 static int atyfb_blank(int blank, struct fb_info *info)
2503 struct atyfb_par *par = (struct atyfb_par *) info->par;
2506 #ifdef CONFIG_PMAC_BACKLIGHT
2507 if ((_machine == _MACH_Pmac) && blank)
2508 set_backlight_enable(0);
2509 #endif /* CONFIG_PMAC_BACKLIGHT */
2511 gen_cntl = aty_ld_8(CRTC_GEN_CNTL, par);
2513 switch (blank - 1) {
2514 case VESA_NO_BLANKING:
2517 case VESA_VSYNC_SUSPEND:
2520 case VESA_HSYNC_SUSPEND:
2523 case VESA_POWERDOWN:
2527 gen_cntl &= ~(0x4c);
2528 aty_st_8(CRTC_GEN_CNTL, gen_cntl, par);
2530 #ifdef CONFIG_PMAC_BACKLIGHT
2531 if ((_machine == _MACH_Pmac) && !blank)
2532 set_backlight_enable(1);
2533 #endif /* CONFIG_PMAC_BACKLIGHT */
2538 * Set a single color register. The values supplied are already
2539 * rounded down to the hardware's capabilities (according to the
2540 * entries in the var structure). Return != 0 for invalid regno.
2543 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2544 u_int transp, struct fb_info *info)
2546 struct atyfb_par *par = (struct atyfb_par *) info->par;
2548 u32 *pal = info->pseudo_palette;
2555 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2556 if (M64_HAS(EXTRA_BRIGHT))
2557 i |= 0x2; /*DAC_CNTL|0x2 turns off the extra brightness for gt */
2558 aty_st_8(DAC_CNTL, i, par);
2559 aty_st_8(DAC_MASK, 0xff, par);
2560 scale = (M64_HAS(INTEGRATED) && info->var.bits_per_pixel == 16) ? 3 : 0;
2562 out_8(&par->aty_cmap_regs->windex, regno << scale);
2563 out_8(&par->aty_cmap_regs->lut, red);
2564 out_8(&par->aty_cmap_regs->lut, green);
2565 out_8(&par->aty_cmap_regs->lut, blue);
2567 writeb(regno << scale, &par->aty_cmap_regs->windex);
2568 writeb(red, &par->aty_cmap_regs->lut);
2569 writeb(green, &par->aty_cmap_regs->lut);
2570 writeb(blue, &par->aty_cmap_regs->lut);
2573 switch (info->var.bits_per_pixel) {
2575 pal[regno] = (regno << 10) | (regno << 5) | regno;
2578 pal[regno] = (regno << 16) | (regno << 8) | regno;
2581 i = (regno << 8) | regno;
2582 pal[regno] = (i << 16) | i;
2589 int __init init_module(void)
2592 return fb_list ? 0 : -ENXIO;
2595 void cleanup_module(void)
2597 struct fb_info *info = fb_list;
2598 struct atyfb_par *par = (struct atyfb_par *) info->par;
2599 unregister_framebuffer(info);
2602 if (par->ati_regbase)
2603 iounmap((void *) par->ati_regbase);
2604 if (info->screen_base)
2605 iounmap((void *) info->screen_base);
2607 if (par->cursor && par->cursor->ram)
2608 iounmap(par->cursor->ram);
2615 kfree(par->mmap_map);
2621 MODULE_LICENSE("GPL");