2 * drivers/video/radeonfb.c
3 * framebuffer driver for ATI Radeon chipset video boards
5 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
6 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 * Special thanks to ATI DevRel team for their hardware donations.
12 * ...Insert GPL boilerplate here...
14 * Significant portions of this driver apdated from XFree86 Radeon
15 * driver which has the following copyright notice:
17 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
18 * VA Linux Systems Inc., Fremont, California.
20 * All Rights Reserved.
22 * Permission is hereby granted, free of charge, to any person obtaining
23 * a copy of this software and associated documentation files (the
24 * "Software"), to deal in the Software without restriction, including
25 * without limitation on the rights to use, copy, modify, merge,
26 * publish, distribute, sublicense, and/or sell copies of the Software,
27 * and to permit persons to whom the Software is furnished to do so,
28 * subject to the following conditions:
30 * The above copyright notice and this permission notice (including the
31 * next paragraph) shall be included in all copies or substantial
32 * portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
38 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
40 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
41 * DEALINGS IN THE SOFTWARE.
43 * XFree86 driver authors:
45 * Kevin E. Martin <martin@xfree86.org>
46 * Rickard E. Faith <faith@valinux.com>
47 * Alan Hourihane <alanh@fairlite.demon.co.uk>
52 #define RADEON_VERSION "0.2.0"
54 #include <linux/config.h>
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/errno.h>
59 #include <linux/string.h>
61 #include <linux/tty.h>
62 #include <linux/slab.h>
63 #include <linux/delay.h>
65 #include <linux/ioport.h>
66 #include <linux/init.h>
67 #include <linux/pci.h>
68 #include <linux/vmalloc.h>
69 #include <linux/device.h>
70 #include <linux/i2c.h>
73 #include <asm/uaccess.h>
78 #include <asm/pci-bridge.h>
79 #include "../macmodes.h"
81 #ifdef CONFIG_PMAC_BACKLIGHT
82 #include <asm/backlight.h>
85 #ifdef CONFIG_BOOTX_TEXT
86 #include <asm/btext.h>
89 #endif /* CONFIG_PPC_OF */
95 #include <video/radeon.h>
96 #include <linux/radeonfb.h>
98 #include "../edid.h" // MOVE THAT TO include/video
100 #include "radeonfb.h"
102 #define MAX_MAPPED_VRAM (2048*2048*4)
103 #define MIN_MAPPED_VRAM (1024*768*1)
105 #define CHIP_DEF(id, family, flags) \
106 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
108 static struct pci_device_id radeonfb_pci_table[] = {
110 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
111 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
113 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
114 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
115 /* Radeon IGP320M (U1) */
116 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
117 /* Radeon IGP320 (A3) */
118 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
119 /* IGP330M/340M/350M (U2) */
120 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
121 /* IGP330/340/350 (A4) */
122 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
123 /* Mobility 7000 IGP */
124 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
126 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
128 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
129 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
131 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
133 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
135 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
137 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
138 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
141 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
143 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
148 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
149 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
150 /* Mobility 9100 IGP (U3) */
151 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
153 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
154 /* Mobility 9200 (M9+) */
155 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
156 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
158 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
159 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
160 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
161 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
165 /* 9600TX / FireGL Z1 */
166 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
167 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
168 /* 9700/9500/Pro/FireGL X1 */
169 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
170 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
172 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
173 /* Mobility M10/M11 */
174 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
175 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
176 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
182 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
183 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
184 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
187 /* 9800/Pro/FileGL X2 */
188 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
196 /* Original Radeon/7200 */
197 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
198 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
199 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
200 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
203 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
212 /* these common regs are cleared before mode setting so they do not
213 * interfere with anything
215 static reg_val common_regs[] = {
217 { OVR_WID_LEFT_RIGHT, 0 },
218 { OVR_WID_TOP_BOTTOM, 0 },
219 { OV0_SCALE_CNTL, 0 },
224 { CAP0_TRIG_CNTL, 0 },
225 { CAP1_TRIG_CNTL, 0 },
232 static char *mode_option;
233 static char *monitor_layout;
234 static int noaccel = 0;
235 static int nomodeset = 0;
236 static int ignore_edid = 0;
237 static int mirror = 0;
238 static int panel_yres = 0;
239 static int force_dfp = 0;
240 static int force_measure_pll = 0;
242 static int nomtrr = 0;
252 #ifdef CONFIG_PMAC_BACKLIGHT
253 static int radeon_set_backlight_enable(int on, int level, void *data);
254 static int radeon_set_backlight_level(int level, void *data);
255 static struct backlight_controller radeon_backlight_controller = {
256 radeon_set_backlight_enable,
257 radeon_set_backlight_level
259 #endif /* CONFIG_PMAC_BACKLIGHT */
261 #endif /* CONFIG_PPC_OF */
263 static void __devexit radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
265 // leave it disabled and unassigned
266 struct resource *r = &dev->resource[PCI_ROM_RESOURCE];
268 if (!rinfo->bios_seg)
270 iounmap(rinfo->bios_seg);
272 /* Release the ROM resource if we used it in the first place */
273 if (r->parent && r->flags & PCI_ROM_ADDRESS_ENABLE) {
275 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
279 /* This will disable and set address to unassigned */
280 pci_write_config_dword(dev, dev->rom_base_reg, 0);
283 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
290 /* If this is a primary card, there is a shadow copy of the
291 * ROM somewhere in the first meg. We will just ignore the copy
292 * and use the ROM directly.
295 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
297 temp = INREG(MPP_TB_CONFIG);
300 OUTREG(MPP_TB_CONFIG, temp);
301 temp = INREG(MPP_TB_CONFIG);
303 /* no need to search for the ROM, just ask the card where it is. */
304 r = &dev->resource[PCI_ROM_RESOURCE];
306 /* assign the ROM an address if it doesn't have one */
307 if (r->parent == NULL)
308 pci_assign_resource(dev, PCI_ROM_RESOURCE);
310 /* enable if needed */
311 if (!(r->flags & PCI_ROM_ADDRESS_ENABLE)) {
312 pci_write_config_dword(dev, dev->rom_base_reg,
313 r->start | PCI_ROM_ADDRESS_ENABLE);
314 r->flags |= PCI_ROM_ADDRESS_ENABLE;
317 rom = ioremap(r->start, r->end - r->start + 1);
319 printk(KERN_ERR "radeonfb: ROM failed to map\n");
323 rinfo->bios_seg = rom;
325 /* Very simple test to make sure it appeared */
326 if (BIOS_IN16(0) != 0xaa55) {
327 printk(KERN_ERR "radeonfb: Invalid ROM signature %x should be 0xaa55\n",
331 /* Look for the PCI data to check the ROM type */
332 dptr = BIOS_IN16(0x18);
334 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
335 * for now, until I've verified this works everywhere. The goal here is more
336 * to phase out Open Firmware images.
338 * Currently, we only look at the first PCI data, we could iteratre and deal with
339 * them all, and we should use fb_bios_start relative to start of image and not
340 * relative start of ROM, but so far, I never found a dual-image ATI card
343 * u32 signature; + 0x00
346 * u16 reserved_1; + 0x08
348 * u8 drevision; + 0x0c
349 * u8 class_hi; + 0x0d
350 * u16 class_lo; + 0x0e
352 * u16 irevision; + 0x12
354 * u8 indicator; + 0x15
355 * u16 reserved_2; + 0x16
358 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
359 printk(KERN_WARNING "radeonfb: PCI DATA signature in ROM incorrect: %08x\n",
363 rom_type = BIOS_IN8(dptr + 0x14);
366 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
369 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
372 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
375 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
379 /* Locate the flat panel infos, do some sanity checking !!! */
380 rinfo->fp_bios_start = BIOS_IN16(0x48);
384 rinfo->bios_seg = NULL;
385 radeon_unmap_ROM(rinfo, dev);
390 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
392 /* I simplified this code as we used to miss the signatures in
393 * a lot of case. It's now closer to XFree, we just don't check
394 * for signatures at all... Something better will have to be done
395 * if we end up having conflicts
398 void __iomem *rom_base = NULL;
400 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
401 rom_base = ioremap(segstart, 0x10000);
402 if (rom_base == NULL)
404 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
409 if (rom_base == NULL)
412 /* Locate the flat panel infos, do some sanity checking !!! */
413 rinfo->bios_seg = rom_base;
414 rinfo->fp_bios_start = BIOS_IN16(0x48);
422 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
423 * tree. Hopefully, ATI OF driver is kind enough to fill these
425 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
427 struct device_node *dp;
430 dp = pci_device_to_OF_node(rinfo->pdev);
432 printk(KERN_WARNING "radeonfb: Cannot match card to OF node !\n");
435 val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);
437 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
441 rinfo->pll.ref_clk = (*val) / 10;
443 val = (u32 *) get_property(dp, "ATY,SCLK", NULL);
445 rinfo->pll.sclk = (*val) / 10;
447 val = (u32 *) get_property(dp, "ATY,MCLK", NULL);
449 rinfo->pll.mclk = (*val) / 10;
453 #endif /* CONFIG_PPC_OF */
456 * Read PLL infos from chip registers
458 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
460 unsigned char ppll_div_sel;
462 unsigned sclk, mclk, tmp, ref_div;
463 int hTotal, vTotal, num, denom, m, n;
464 unsigned long long hz, vclk;
466 struct timeval start_tv, stop_tv;
467 long total_secs, total_usecs;
470 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
474 /* Flush PCI buffers ? */
475 tmp = INREG(DEVICE_ID);
479 for(i=0; i<1000000; i++)
480 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
483 do_gettimeofday(&start_tv);
485 for(i=0; i<1000000; i++)
486 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
489 for(i=0; i<1000000; i++)
490 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
493 do_gettimeofday(&stop_tv);
497 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
500 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
501 total_usecs += total_secs * 1000000;
503 total_usecs = -total_usecs;
504 hz = 1000000/total_usecs;
506 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
507 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
508 vclk = (long long)hTotal * (long long)vTotal * hz;
510 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
517 n = ((INPLL(X_MPLL_REF_FB_DIV) >> 16) & 0xff);
518 m = (INPLL(X_MPLL_REF_FB_DIV) & 0xff);
523 n = ((INPLL(X_MPLL_REF_FB_DIV) >> 8) & 0xff);
524 m = (INPLL(X_MPLL_REF_FB_DIV) & 0xff);
530 OUTREG8(CLOCK_CNTL_INDEX, 1);
531 ppll_div_sel = INREG8(CLOCK_CNTL_DATA + 1) & 0x3;
533 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
534 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
539 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
561 do_div(vclk, 1000 * num);
564 if ((xtal > 26900) && (xtal < 27100))
566 else if ((xtal > 14200) && (xtal < 14400))
568 else if ((xtal > 29400) && (xtal < 29600))
571 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
575 tmp = INPLL(X_MPLL_REF_FB_DIV);
576 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
578 Ns = (tmp & 0xff0000) >> 16;
579 Nm = (tmp & 0xff00) >> 8;
581 sclk = round_div((2 * Ns * xtal), (2 * M));
582 mclk = round_div((2 * Nm * xtal), (2 * M));
584 /* we're done, hopefully these are sane values */
585 rinfo->pll.ref_clk = xtal;
586 rinfo->pll.ref_div = ref_div;
587 rinfo->pll.sclk = sclk;
588 rinfo->pll.mclk = mclk;
594 * Retreive PLL infos by different means (BIOS, Open Firmware, register probing...)
596 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
600 * Retreive PLL infos from Open Firmware first
602 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
603 printk(KERN_INFO "radeonfb: Retreived PLL infos from Open Firmware\n");
604 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
605 /* FIXME: Max clock may be higher on newer chips */
606 rinfo->pll.ppll_min = 12000;
607 rinfo->pll.ppll_max = 35000;
610 #endif /* CONFIG_PPC_OF */
613 * Check out if we have an X86 which gave us some PLL informations
614 * and if yes, retreive them
616 if (!force_measure_pll && rinfo->bios_seg) {
617 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
619 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
620 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
621 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
622 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
623 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
624 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
626 printk(KERN_INFO "radeonfb: Retreived PLL infos from BIOS\n");
631 * We didn't get PLL parameters from either OF or BIOS, we try to
634 if (radeon_probe_pll_params(rinfo) == 0) {
635 printk(KERN_INFO "radeonfb: Retreived PLL infos from registers\n");
636 /* FIXME: Max clock may be higher on newer chips */
637 rinfo->pll.ppll_min = 12000;
638 rinfo->pll.ppll_max = 35000;
643 * Neither of the above worked, we have a few default values, though
644 * that's mostly incomplete
646 switch (rinfo->chipset) {
647 case PCI_DEVICE_ID_ATI_RADEON_QW:
648 case PCI_DEVICE_ID_ATI_RADEON_QX:
649 rinfo->pll.ppll_max = 35000;
650 rinfo->pll.ppll_min = 12000;
651 rinfo->pll.mclk = 23000;
652 rinfo->pll.sclk = 23000;
653 rinfo->pll.ref_clk = 2700;
655 case PCI_DEVICE_ID_ATI_RADEON_QL:
656 case PCI_DEVICE_ID_ATI_RADEON_QN:
657 case PCI_DEVICE_ID_ATI_RADEON_QO:
658 case PCI_DEVICE_ID_ATI_RADEON_Ql:
659 case PCI_DEVICE_ID_ATI_RADEON_BB:
660 rinfo->pll.ppll_max = 35000;
661 rinfo->pll.ppll_min = 12000;
662 rinfo->pll.mclk = 27500;
663 rinfo->pll.sclk = 27500;
664 rinfo->pll.ref_clk = 2700;
666 case PCI_DEVICE_ID_ATI_RADEON_Id:
667 case PCI_DEVICE_ID_ATI_RADEON_Ie:
668 case PCI_DEVICE_ID_ATI_RADEON_If:
669 case PCI_DEVICE_ID_ATI_RADEON_Ig:
670 rinfo->pll.ppll_max = 35000;
671 rinfo->pll.ppll_min = 12000;
672 rinfo->pll.mclk = 25000;
673 rinfo->pll.sclk = 25000;
674 rinfo->pll.ref_clk = 2700;
676 case PCI_DEVICE_ID_ATI_RADEON_ND:
677 case PCI_DEVICE_ID_ATI_RADEON_NE:
678 case PCI_DEVICE_ID_ATI_RADEON_NF:
679 case PCI_DEVICE_ID_ATI_RADEON_NG:
680 rinfo->pll.ppll_max = 40000;
681 rinfo->pll.ppll_min = 20000;
682 rinfo->pll.mclk = 27000;
683 rinfo->pll.sclk = 27000;
684 rinfo->pll.ref_clk = 2700;
686 case PCI_DEVICE_ID_ATI_RADEON_QD:
687 case PCI_DEVICE_ID_ATI_RADEON_QE:
688 case PCI_DEVICE_ID_ATI_RADEON_QF:
689 case PCI_DEVICE_ID_ATI_RADEON_QG:
691 rinfo->pll.ppll_max = 35000;
692 rinfo->pll.ppll_min = 12000;
693 rinfo->pll.mclk = 16600;
694 rinfo->pll.sclk = 16600;
695 rinfo->pll.ref_clk = 2700;
698 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
700 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
704 * Some methods fail to retreive SCLK and MCLK values, we apply default
705 * settings in this case (200Mhz). If that really happne often, we could
706 * fetch from registers instead...
708 if (rinfo->pll.mclk == 0)
709 rinfo->pll.mclk = 20000;
710 if (rinfo->pll.sclk == 0)
711 rinfo->pll.sclk = 20000;
713 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
714 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
716 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
717 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
720 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
722 struct radeonfb_info *rinfo = info->par;
723 struct fb_var_screeninfo v;
727 if (radeon_match_mode(rinfo, &v, var))
730 switch (v.bits_per_pixel) {
732 v.bits_per_pixel = 8;
735 v.bits_per_pixel = 16;
738 #if 0 /* Doesn't seem to work */
739 v.bits_per_pixel = 24;
744 v.bits_per_pixel = 32;
750 switch (var_to_depth(&v)) {
753 v.red.offset = v.green.offset = v.blue.offset = 0;
754 v.red.length = v.green.length = v.blue.length = 8;
755 v.transp.offset = v.transp.length = 0;
763 v.red.length = v.green.length = v.blue.length = 5;
764 v.transp.offset = v.transp.length = 0;
775 v.transp.offset = v.transp.length = 0;
783 v.red.length = v.blue.length = v.green.length = 8;
784 v.transp.offset = v.transp.length = 0;
792 v.red.length = v.blue.length = v.green.length = 8;
793 v.transp.offset = 24;
797 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
798 var->xres, var->yres, var->bits_per_pixel);
802 if (v.yres_virtual < v.yres)
803 v.yres_virtual = v.yres;
804 if (v.xres_virtual < v.xres)
805 v.xres_virtual = v.xres;
808 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
809 * with some panels, though I don't quite like this solution
811 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
812 v.xres_virtual = v.xres_virtual & ~7ul;
814 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
816 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
819 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
822 if (v.xres_virtual < v.xres)
823 v.xres = v.xres_virtual;
830 if (v.xoffset > v.xres_virtual - v.xres)
831 v.xoffset = v.xres_virtual - v.xres - 1;
833 if (v.yoffset > v.yres_virtual - v.yres)
834 v.yoffset = v.yres_virtual - v.yres - 1;
836 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
837 v.transp.offset = v.transp.length =
838 v.transp.msb_right = 0;
840 memcpy(var, &v, sizeof(v));
846 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
847 struct fb_info *info)
849 struct radeonfb_info *rinfo = info->par;
851 if ((var->xoffset + var->xres > var->xres_virtual)
852 || (var->yoffset + var->yres > var->yres_virtual))
859 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
860 * var->bits_per_pixel / 8) & ~7);
865 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
866 unsigned long arg, struct fb_info *info)
868 struct radeonfb_info *rinfo = info->par;
875 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
876 * and do something better using 2nd CRTC instead of just hackish
877 * routing to second output
879 case FBIO_RADEON_SET_MIRROR:
880 if (!rinfo->is_mobility)
883 rc = get_user(value, (__u32 __user *)arg);
890 tmp = INREG(LVDS_GEN_CNTL);
892 tmp |= (LVDS_ON | LVDS_BLON);
894 tmp = INREG(LVDS_GEN_CNTL);
896 tmp &= ~(LVDS_ON | LVDS_BLON);
899 OUTREG(LVDS_GEN_CNTL, tmp);
902 tmp = INREG(CRTC_EXT_CNTL);
907 tmp = INREG(CRTC_EXT_CNTL);
913 OUTREG(CRTC_EXT_CNTL, tmp);
916 case FBIO_RADEON_GET_MIRROR:
917 if (!rinfo->is_mobility)
920 tmp = INREG(LVDS_GEN_CNTL);
921 if ((LVDS_ON | LVDS_BLON) & tmp)
924 tmp = INREG(CRTC_EXT_CNTL);
925 if (CRTC_CRT_ON & tmp)
928 return put_user(value, (__u32 __user *)arg);
937 static int radeon_screen_blank (struct radeonfb_info *rinfo, int blank)
939 u32 val = INREG(CRTC_EXT_CNTL);
942 if (rinfo->mon1_type == MT_LCD)
943 val2 = INREG(LVDS_GEN_CNTL) & ~LVDS_DISPLAY_DIS;
946 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
950 case VESA_NO_BLANKING:
952 case VESA_VSYNC_SUSPEND:
953 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
955 case VESA_HSYNC_SUSPEND:
956 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
959 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
961 val2 |= (LVDS_DISPLAY_DIS);
966 switch (rinfo->mon1_type) {
968 OUTREG(LVDS_GEN_CNTL, val2);
972 OUTREG(CRTC_EXT_CNTL, val);
979 int radeonfb_blank (int blank, struct fb_info *info)
981 struct radeonfb_info *rinfo = info->par;
986 #ifdef CONFIG_PMAC_BACKLIGHT
987 if (rinfo->mon1_type == MT_LCD && _machine == _MACH_Pmac && blank)
988 set_backlight_enable(0);
991 radeon_screen_blank(rinfo, blank);
993 #ifdef CONFIG_PMAC_BACKLIGHT
994 if (rinfo->mon1_type == MT_LCD && _machine == _MACH_Pmac && !blank)
995 set_backlight_enable(1);
1001 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1002 unsigned blue, unsigned transp, struct fb_info *info)
1004 struct radeonfb_info *rinfo = info->par;
1014 rinfo->palette[regno].red = red;
1015 rinfo->palette[regno].green = green;
1016 rinfo->palette[regno].blue = blue;
1021 if (!rinfo->asleep) {
1022 u32 dac_cntl2, vclk_cntl = 0;
1024 radeon_fifo_wait(9);
1025 if (rinfo->is_mobility) {
1026 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1027 OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1030 /* Make sure we are on first palette */
1031 if (rinfo->has_CRTC2) {
1032 dac_cntl2 = INREG(DAC_CNTL2);
1033 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1034 OUTREG(DAC_CNTL2, dac_cntl2);
1037 if (rinfo->bpp == 16) {
1040 if (rinfo->depth == 16 && regno > 63)
1042 if (rinfo->depth == 15 && regno > 31)
1045 /* For 565, the green component is mixed one order below */
1046 if (rinfo->depth == 16) {
1047 OUTREG(PALETTE_INDEX, pindex>>1);
1048 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1049 (green << 8) | (rinfo->palette[regno>>1].blue));
1050 green = rinfo->palette[regno<<1].green;
1054 if (rinfo->depth != 16 || regno < 32) {
1055 OUTREG(PALETTE_INDEX, pindex);
1056 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1058 if (rinfo->is_mobility)
1059 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1062 u32 *pal = info->pseudo_palette;
1063 switch (rinfo->depth) {
1065 pal[regno] = (regno << 10) | (regno << 5) | regno;
1068 pal[regno] = (regno << 11) | (regno << 5) | regno;
1071 pal[regno] = (regno << 16) | (regno << 8) | regno;
1074 i = (regno << 8) | regno;
1075 pal[regno] = (i << 16) | i;
1083 static void radeon_save_state (struct radeonfb_info *rinfo, struct radeon_regs *save)
1086 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1087 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1088 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1089 save->dac_cntl = INREG(DAC_CNTL);
1090 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1091 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1092 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1093 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1094 save->crtc_pitch = INREG(CRTC_PITCH);
1095 save->surface_cntl = INREG(SURFACE_CNTL);
1098 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1099 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1100 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1101 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1102 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1103 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1104 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1105 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1106 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1107 save->tmds_crc = INREG(TMDS_CRC); save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1108 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1112 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1116 radeon_fifo_wait(20);
1118 /* Workaround from XFree */
1119 if (rinfo->is_mobility) {
1120 /* A temporal workaround for the occational blanking on certain laptop panels.
1121 This appears to related to the PLL divider registers (fail to lock?).
1122 It occurs even when all dividers are the same with their old settings.
1123 In this case we really don't need to fiddle with PLL registers.
1124 By doing this we can avoid the blanking problem with some panels.
1126 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1127 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1128 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1129 /* We still have to force a switch to PPLL div 3 thanks to
1130 * an XFree86 driver bug which will switch it away in some cases
1131 * even when using UseFDev */
1132 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, ~PPLL_DIV_SEL_MASK);
1137 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1138 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1140 /* Reset PPLL & enable atomic update */
1142 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1143 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1145 /* Switch to PPLL div 3 */
1146 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, ~PPLL_DIV_SEL_MASK);
1148 /* Set PPLL ref. div */
1149 if (rinfo->family == CHIP_FAMILY_R300 ||
1150 rinfo->family == CHIP_FAMILY_RS300 ||
1151 rinfo->family == CHIP_FAMILY_R350 ||
1152 rinfo->family == CHIP_FAMILY_RV350) {
1153 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1154 /* When restoring console mode, use saved PPLL_REF_DIV
1157 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1159 /* R300 uses ref_div_acc field as real ref divider */
1160 OUTPLLP(PPLL_REF_DIV,
1161 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1162 ~R300_PPLL_REF_DIV_ACC_MASK);
1165 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1167 /* Set PPLL divider 3 & post divider*/
1168 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1169 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1172 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1174 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1176 /* Wait read update complete */
1177 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1178 the cause yet, but this workaround will mask the problem for now.
1179 Other chips usually will pass at the very first test, so the
1180 workaround shouldn't have any effect on them. */
1181 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1184 OUTPLL(HTOTAL_CNTL, 0);
1186 /* Clear reset & atomic update */
1187 OUTPLLP(PPLL_CNTL, 0,
1188 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1190 /* We may want some locking ... oh well */
1193 /* Switch back VCLK source to PPLL */
1194 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1198 * Timer function for delayed LVDS panel power up/down
1200 static void radeon_lvds_timer_func(unsigned long data)
1202 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1204 radeon_fifo_wait(3);
1206 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1207 if (rinfo->pending_pixclks_cntl) {
1208 OUTPLL(PIXCLKS_CNTL, rinfo->pending_pixclks_cntl);
1209 rinfo->pending_pixclks_cntl = 0;
1214 * Apply a video mode. This will apply the whole register set, including
1215 * the PLL registers, to the card
1217 static void radeon_write_mode (struct radeonfb_info *rinfo,
1218 struct radeon_regs *mode)
1221 int primary_mon = PRIMARY_MONITOR(rinfo);
1226 del_timer_sync(&rinfo->lvds_timer);
1228 radeon_screen_blank(rinfo, VESA_POWERDOWN);
1230 radeon_fifo_wait(31);
1231 for (i=0; i<10; i++)
1232 OUTREG(common_regs[i].reg, common_regs[i].val);
1234 /* Apply surface registers */
1235 for (i=0; i<8; i++) {
1236 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1237 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1238 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1241 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1242 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1243 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1244 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1245 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1246 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1247 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1248 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1249 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1250 OUTREG(CRTC_OFFSET, 0);
1251 OUTREG(CRTC_OFFSET_CNTL, 0);
1252 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1253 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1255 radeon_write_pll_regs(rinfo, mode);
1257 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1258 radeon_fifo_wait(10);
1259 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1260 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1261 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1262 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1263 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1264 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1265 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1266 OUTREG(TMDS_CRC, mode->tmds_crc);
1267 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1269 if (primary_mon == MT_LCD) {
1270 unsigned int tmp = INREG(LVDS_GEN_CNTL);
1272 /* HACK: The backlight control code may have modified init_state.lvds_gen_cntl,
1273 * so we update ourselves
1275 mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
1276 mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
1278 if ((tmp & (LVDS_ON | LVDS_BLON)) ==
1279 (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
1280 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
1282 rinfo->pending_pixclks_cntl = INPLL(PIXCLKS_CNTL);
1283 if (rinfo->is_mobility || rinfo->is_IGP)
1284 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1285 if (!(tmp & (LVDS_ON | LVDS_BLON)))
1286 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl | LVDS_BLON);
1287 rinfo->pending_lvds_gen_cntl = mode->lvds_gen_cntl;
1288 mod_timer(&rinfo->lvds_timer,
1289 jiffies + MS_TO_HZ(rinfo->panel_info.pwr_delay));
1294 RTRACE("lvds_gen_cntl: %08x\n", INREG(LVDS_GEN_CNTL));
1296 radeon_screen_blank(rinfo, VESA_NO_BLANKING);
1298 radeon_fifo_wait(2);
1299 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1305 * Calculate the PLL values for a given mode
1307 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1325 int fb_div, pll_output_freq = 0;
1328 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1329 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1330 * recent than an r(v)100...
1333 /* XXX I had reports of flicker happening with the cinema display
1334 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1335 * this case. This could just be a bandwidth calculation issue, I
1336 * haven't implemented the bandwidth code yet, but in the meantime,
1337 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1338 * I haven't seen a case were were absolutely needed an odd PLL
1339 * divider. I'll find a better fix once I have more infos on the
1340 * real cause of the problem.
1342 while (rinfo->has_CRTC2) {
1343 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1344 u32 disp_output_cntl;
1347 /* FP2 path not enabled */
1348 if ((fp2_gen_cntl & FP2_ON) == 0)
1350 /* Not all chip revs have the same format for this register,
1351 * extract the source selection
1353 if (rinfo->family == CHIP_FAMILY_R200 ||
1354 rinfo->family == CHIP_FAMILY_R300 ||
1355 rinfo->family == CHIP_FAMILY_R350 ||
1356 rinfo->family == CHIP_FAMILY_RV350) {
1357 source = (fp2_gen_cntl >> 10) & 0x3;
1358 /* sourced from transform unit, check for transform unit
1362 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1363 source = (disp_output_cntl >> 12) & 0x3;
1366 source = (fp2_gen_cntl >> 13) & 0x1;
1367 /* sourced from CRTC2 -> exit */
1371 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1378 if (freq > rinfo->pll.ppll_max)
1379 freq = rinfo->pll.ppll_max;
1380 if (freq*12 < rinfo->pll.ppll_min)
1381 freq = rinfo->pll.ppll_min / 12;
1383 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1384 pll_output_freq = post_div->divider * freq;
1385 /* If we output to the DVO port (external TMDS), we don't allow an
1386 * odd PLL divider as those aren't supported on this path
1388 if (uses_dvo && (post_div->divider & 1))
1390 if (pll_output_freq >= rinfo->pll.ppll_min &&
1391 pll_output_freq <= rinfo->pll.ppll_max)
1395 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1396 rinfo->pll.ref_clk);
1397 regs->ppll_ref_div = rinfo->pll.ref_div;
1398 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1400 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1401 RTRACE("fb_div = 0x%x\n", fb_div);
1402 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1405 int radeonfb_set_par(struct fb_info *info)
1407 struct radeonfb_info *rinfo = info->par;
1408 struct fb_var_screeninfo *mode = &info->var;
1409 struct radeon_regs *newmode;
1410 int hTotal, vTotal, hSyncStart, hSyncEnd,
1411 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1412 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1413 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1414 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1418 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1419 int primary_mon = PRIMARY_MONITOR(rinfo);
1420 int depth = var_to_depth(mode);
1422 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1426 /* We always want engine to be idle on a mode switch, even
1427 * if we won't actually change the mode
1429 radeon_engine_idle();
1431 hSyncStart = mode->xres + mode->right_margin;
1432 hSyncEnd = hSyncStart + mode->hsync_len;
1433 hTotal = hSyncEnd + mode->left_margin;
1435 vSyncStart = mode->yres + mode->lower_margin;
1436 vSyncEnd = vSyncStart + mode->vsync_len;
1437 vTotal = vSyncEnd + mode->upper_margin;
1438 pixClock = mode->pixclock;
1441 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1442 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1444 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1445 if (rinfo->panel_info.xres < mode->xres)
1446 mode->xres = rinfo->panel_info.xres;
1447 if (rinfo->panel_info.yres < mode->yres)
1448 mode->yres = rinfo->panel_info.yres;
1450 hTotal = mode->xres + rinfo->panel_info.hblank;
1451 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1452 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1454 vTotal = mode->yres + rinfo->panel_info.vblank;
1455 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1456 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1458 h_sync_pol = !rinfo->panel_info.hAct_high;
1459 v_sync_pol = !rinfo->panel_info.vAct_high;
1461 pixClock = 100000000 / rinfo->panel_info.clock;
1463 if (rinfo->panel_info.use_bios_dividers) {
1465 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1466 (rinfo->panel_info.post_divider << 16);
1467 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1470 dotClock = 1000000000 / pixClock;
1471 freq = dotClock / 10; /* x100 */
1473 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1474 hSyncStart, hSyncEnd, hTotal);
1475 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1476 vSyncStart, vSyncEnd, vTotal);
1478 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1479 vsync_wid = vSyncEnd - vSyncStart;
1482 else if (hsync_wid > 0x3f) /* max */
1487 else if (vsync_wid > 0x1f) /* max */
1490 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1491 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1493 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1495 format = radeon_get_dstbpp(depth);
1496 bytpp = mode->bits_per_pixel >> 3;
1498 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1499 hsync_fudge = hsync_fudge_fp[format-1];
1501 hsync_fudge = hsync_adj_tab[format-1];
1503 hsync_start = hSyncStart - 8 + hsync_fudge;
1505 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1508 /* Clear auto-center etc... */
1509 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1510 newmode->crtc_more_cntl &= 0xfffffff0;
1512 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1513 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1515 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1517 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1520 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1524 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1527 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1528 (((mode->xres / 8) - 1) << 16));
1530 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1531 (hsync_wid << 16) | (h_sync_pol << 23));
1533 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1534 ((mode->yres - 1) << 16);
1536 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1537 (vsync_wid << 16) | (v_sync_pol << 23));
1539 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1540 /* We first calculate the engine pitch */
1541 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1544 /* Then, re-multiply it to get the CRTC pitch */
1545 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1547 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1549 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1552 * It looks like recent chips have a problem with SURFACE_CNTL,
1553 * setting SURF_TRANSLATION_DIS completely disables the
1554 * swapper as well, so we leave it unset now.
1556 newmode->surface_cntl = 0;
1558 #if defined(__BIG_ENDIAN)
1560 /* Setup swapping on both apertures, though we currently
1561 * only use aperture 0, enabling swapper on aperture 1
1564 switch (mode->bits_per_pixel) {
1566 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1567 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1571 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1572 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1577 /* Clear surface registers */
1578 for (i=0; i<8; i++) {
1579 newmode->surf_lower_bound[i] = 0;
1580 newmode->surf_upper_bound[i] = 0x1f;
1581 newmode->surf_info[i] = 0;
1584 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1585 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1586 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1587 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1589 rinfo->bpp = mode->bits_per_pixel;
1590 rinfo->depth = depth;
1592 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1593 RTRACE("freq = %lu\n", (unsigned long)freq);
1596 radeon_calc_pll_regs(rinfo, newmode, freq);
1598 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1600 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1601 unsigned int hRatio, vRatio;
1603 if (mode->xres > rinfo->panel_info.xres)
1604 mode->xres = rinfo->panel_info.xres;
1605 if (mode->yres > rinfo->panel_info.yres)
1606 mode->yres = rinfo->panel_info.yres;
1608 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1609 << HORZ_PANEL_SHIFT);
1610 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1611 << VERT_PANEL_SHIFT);
1613 if (mode->xres != rinfo->panel_info.xres) {
1614 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1615 rinfo->panel_info.xres);
1616 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1617 (newmode->fp_horz_stretch &
1618 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1619 HORZ_AUTO_RATIO_INC)));
1620 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1621 HORZ_STRETCH_ENABLE);
1623 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1625 if (mode->yres != rinfo->panel_info.yres) {
1626 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1627 rinfo->panel_info.yres);
1628 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1629 (newmode->fp_vert_stretch &
1630 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1631 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1632 VERT_STRETCH_ENABLE);
1634 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1636 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1638 FP_RMX_HVSYNC_CONTROL_EN |
1643 FP_CRTC_USE_SHADOW_VEND |
1646 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1647 FP_CRTC_DONT_SHADOW_HEND);
1649 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1650 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1651 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1652 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1654 if (primary_mon == MT_LCD) {
1655 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1656 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1659 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1660 newmode->tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | TMDS_ICHCSEL) &
1662 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1663 if ((rinfo->family == CHIP_FAMILY_R300) ||
1664 (rinfo->family == CHIP_FAMILY_R350) ||
1665 (rinfo->family == CHIP_FAMILY_RV350) ||
1666 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1667 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1669 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1670 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1673 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1674 (((mode->xres / 8) - 1) << 16));
1675 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1676 ((mode->yres - 1) << 16);
1677 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1678 (hsync_wid << 16) | (h_sync_pol << 23));
1679 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1680 (vsync_wid << 16) | (v_sync_pol << 23));
1684 if (!rinfo->asleep) {
1685 radeon_write_mode (rinfo, newmode);
1686 /* (re)initialize the engine */
1687 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1688 radeonfb_engine_init (rinfo);
1691 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1692 info->fix.line_length = rinfo->pitch*64;
1694 info->fix.line_length = mode->xres_virtual
1695 * ((mode->bits_per_pixel + 1) / 8);
1696 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1697 : FB_VISUAL_DIRECTCOLOR;
1699 #ifdef CONFIG_BOOTX_TEXT
1700 /* Update debug text engine */
1701 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1702 rinfo->depth, info->fix.line_length);
1710 static struct fb_ops radeonfb_ops = {
1711 .owner = THIS_MODULE,
1712 .fb_check_var = radeonfb_check_var,
1713 .fb_set_par = radeonfb_set_par,
1714 .fb_setcolreg = radeonfb_setcolreg,
1715 .fb_pan_display = radeonfb_pan_display,
1716 .fb_blank = radeonfb_blank,
1717 .fb_ioctl = radeonfb_ioctl,
1718 .fb_sync = radeonfb_sync,
1719 .fb_fillrect = radeonfb_fillrect,
1720 .fb_copyarea = radeonfb_copyarea,
1721 .fb_imageblit = radeonfb_imageblit,
1722 .fb_cursor = soft_cursor,
1726 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1728 struct fb_info *info = rinfo->info;
1732 info->pseudo_palette = rinfo->pseudo_palette;
1733 info->flags = FBINFO_DEFAULT
1734 | FBINFO_HWACCEL_COPYAREA
1735 | FBINFO_HWACCEL_FILLRECT
1736 | FBINFO_HWACCEL_XPAN
1737 | FBINFO_HWACCEL_YPAN;
1738 info->fbops = &radeonfb_ops;
1739 info->screen_base = rinfo->fb_base;
1740 info->screen_size = rinfo->mapped_vram;
1741 /* Fill fix common fields */
1742 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1743 info->fix.smem_start = rinfo->fb_base_phys;
1744 info->fix.smem_len = rinfo->video_ram;
1745 info->fix.type = FB_TYPE_PACKED_PIXELS;
1746 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1747 info->fix.xpanstep = 8;
1748 info->fix.ypanstep = 1;
1749 info->fix.ywrapstep = 0;
1750 info->fix.type_aux = 0;
1751 info->fix.mmio_start = rinfo->mmio_base_phys;
1752 info->fix.mmio_len = RADEON_REGSIZE;
1754 fb_alloc_cmap(&info->cmap, 256, 0);
1757 info->flags |= FBINFO_HWACCEL_DISABLED;
1763 #ifdef CONFIG_PMAC_BACKLIGHT
1765 /* TODO: Dbl check these tables, we don't go up to full ON backlight
1766 * in these, possibly because we noticed MacOS doesn't, but I'd prefer
1767 * having some more official numbers from ATI
1769 static int backlight_conv_m6[] = {
1770 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
1771 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
1773 static int backlight_conv_m7[] = {
1774 0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
1775 0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
1778 #define BACKLIGHT_LVDS_OFF
1779 #undef BACKLIGHT_DAC_OFF
1781 /* We turn off the LCD completely instead of just dimming the backlight.
1782 * This provides some greater power saving and the display is useless
1783 * without backlight anyway.
1785 static int radeon_set_backlight_enable(int on, int level, void *data)
1787 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1788 unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1789 unsigned long tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
1792 if (rinfo->mon1_type != MT_LCD)
1795 /* Pardon me for that hack... maybe some day we can figure
1796 * out in what direction backlight should work on a given
1799 if ((rinfo->family == CHIP_FAMILY_RV200 ||
1800 rinfo->family == CHIP_FAMILY_RV250 ||
1801 rinfo->family == CHIP_FAMILY_RV280 ||
1802 rinfo->family == CHIP_FAMILY_RV350) &&
1803 !machine_is_compatible("PowerBook4,3") &&
1804 !machine_is_compatible("PowerBook6,3") &&
1805 !machine_is_compatible("PowerBook6,5"))
1806 conv_table = backlight_conv_m7;
1808 conv_table = backlight_conv_m6;
1810 del_timer_sync(&rinfo->lvds_timer);
1812 lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
1813 radeon_fifo_wait(3);
1814 if (on && (level > BACKLIGHT_OFF)) {
1815 lvds_gen_cntl |= LVDS_DIGON;
1816 if (!(lvds_gen_cntl & LVDS_ON)) {
1817 lvds_gen_cntl &= ~LVDS_BLON;
1818 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1819 (void)INREG(LVDS_GEN_CNTL);
1820 mdelay(rinfo->panel_info.pwr_delay);/* OUCH !!! FIXME */
1821 lvds_gen_cntl |= LVDS_BLON;
1822 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1824 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1825 lvds_gen_cntl |= (conv_table[level] <<
1826 LVDS_BL_MOD_LEVEL_SHIFT);
1827 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
1828 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
1830 /* Asic bug, when turning off LVDS_ON, we have to make sure
1831 RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1833 if (rinfo->is_mobility || rinfo->is_IGP)
1834 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1835 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1836 lvds_gen_cntl |= (conv_table[0] <<
1837 LVDS_BL_MOD_LEVEL_SHIFT);
1838 lvds_gen_cntl |= LVDS_DISPLAY_DIS | LVDS_BLON;
1839 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1840 mdelay(rinfo->panel_info.pwr_delay);/* OUCH !!! FIXME */
1841 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
1844 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1845 if (rinfo->is_mobility || rinfo->is_IGP)
1846 OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
1847 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1848 rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
1854 static int radeon_set_backlight_level(int level, void *data)
1856 return radeon_set_backlight_enable(1, level, data);
1858 #endif /* CONFIG_PMAC_BACKLIGHT */
1862 * This reconfigure the card's internal memory map. In theory, we'd like
1863 * to setup the card's memory at the same address as it's PCI bus address,
1864 * and the AGP aperture right after that so that system RAM on 32 bits
1865 * machines at least, is directly accessible. However, doing so would
1866 * conflict with the current XFree drivers...
1867 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1868 * on the proper way to set this up and duplicate this here. In the meantime,
1869 * I put the card's memory at 0 in card space and AGP at some random high
1870 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1872 #ifdef CONFIG_PPC_OF
1873 #undef SET_MC_FB_FROM_APERTURE
1874 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1876 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1877 u32 save_crtc_ext_cntl;
1878 u32 aper_base, aper_size;
1881 /* First, we disable display to avoid interfering */
1882 if (rinfo->has_CRTC2) {
1883 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1884 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1886 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1887 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1889 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1890 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1893 aper_base = INREG(CONFIG_APER_0_BASE);
1894 aper_size = INREG(CONFIG_APER_SIZE);
1896 #ifdef SET_MC_FB_FROM_APERTURE
1897 /* Set framebuffer to be at the same address as set in PCI BAR */
1898 OUTREG(MC_FB_LOCATION,
1899 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1900 rinfo->fb_local_base = aper_base;
1902 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1903 rinfo->fb_local_base = 0;
1905 agp_base = aper_base + aper_size;
1906 if (agp_base & 0xf0000000)
1907 agp_base = (aper_base | 0x0fffffff) + 1;
1909 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1910 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1911 * always the case on PPCs afaik.
1913 #ifdef SET_MC_FB_FROM_APERTURE
1914 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1916 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1919 /* Fixup the display base addresses & engine offsets while we
1922 #ifdef SET_MC_FB_FROM_APERTURE
1923 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1924 if (rinfo->has_CRTC2)
1925 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1927 OUTREG(DISPLAY_BASE_ADDR, 0);
1928 if (rinfo->has_CRTC2)
1929 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1933 /* Restore display settings */
1934 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1935 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1936 if (rinfo->has_CRTC2)
1937 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1939 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1941 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1942 0xffff0000 | (agp_base >> 16));
1944 #endif /* CONFIG_PPC_OF */
1951 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
1953 if (off > EDID_LENGTH)
1956 if (off + count > EDID_LENGTH)
1957 count = EDID_LENGTH - off;
1959 memcpy(buf, edid + off, count);
1965 static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
1967 struct device *dev = container_of(kobj, struct device, kobj);
1968 struct pci_dev *pdev = to_pci_dev(dev);
1969 struct fb_info *info = pci_get_drvdata(pdev);
1970 struct radeonfb_info *rinfo = info->par;
1972 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
1976 static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
1978 struct device *dev = container_of(kobj, struct device, kobj);
1979 struct pci_dev *pdev = to_pci_dev(dev);
1980 struct fb_info *info = pci_get_drvdata(pdev);
1981 struct radeonfb_info *rinfo = info->par;
1983 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
1986 static struct bin_attribute edid1_attr = {
1989 .owner = THIS_MODULE,
1992 .size = EDID_LENGTH,
1993 .read = radeon_show_edid1,
1996 static struct bin_attribute edid2_attr = {
1999 .owner = THIS_MODULE,
2002 .size = EDID_LENGTH,
2003 .read = radeon_show_edid2,
2007 static int radeonfb_pci_register (struct pci_dev *pdev,
2008 const struct pci_device_id *ent)
2010 struct fb_info *info;
2011 struct radeonfb_info *rinfo;
2015 RTRACE("radeonfb_pci_register BEGIN\n");
2017 /* Enable device in PCI config */
2018 ret = pci_enable_device(pdev);
2020 printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
2024 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2026 printk (KERN_ERR "radeonfb: could not allocate memory\n");
2034 spin_lock_init(&rinfo->reg_lock);
2035 init_timer(&rinfo->lvds_timer);
2036 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2037 rinfo->lvds_timer.data = (unsigned long)rinfo;
2039 strcpy(rinfo->name, "ATI Radeon XX ");
2040 rinfo->name[11] = ent->device >> 8;
2041 rinfo->name[12] = ent->device & 0xFF;
2042 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2043 rinfo->chipset = pdev->device;
2044 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2045 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2046 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2048 /* Set base addrs */
2049 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2050 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2052 /* request the mem regions */
2053 ret = pci_request_regions(pdev, "radeonfb");
2055 printk( KERN_ERR "radeonfb: cannot reserve PCI regions."
2056 " Someone already got them?\n");
2057 goto err_release_fb;
2060 /* map the regions */
2061 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2062 if (!rinfo->mmio_base) {
2063 printk(KERN_ERR "radeonfb: cannot map MMIO\n");
2065 goto err_release_pci;
2068 /* On PPC, the firmware sets up a memory mapping that tends
2069 * to cause lockups when enabling the engine. We reconfigure
2070 * the card internal memory mappings properly
2072 #ifdef CONFIG_PPC_OF
2073 fixup_memory_mappings(rinfo);
2075 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2076 #endif /* CONFIG_PPC_OF */
2078 /* framebuffer size */
2079 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2080 (rinfo->family == CHIP_FAMILY_RS200) ||
2081 (rinfo->family == CHIP_FAMILY_RS300)) {
2082 u32 tom = INREG(NB_TOM);
2083 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2085 radeon_fifo_wait(6);
2086 OUTREG(MC_FB_LOCATION, tom);
2087 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2088 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2089 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2091 /* This is supposed to fix the crtc2 noise problem. */
2092 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2094 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2095 (rinfo->family == CHIP_FAMILY_RS200)) {
2096 /* This is to workaround the asic bug for RMX, some versions
2097 of BIOS dosen't have this register initialized correctly.
2099 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2100 ~CRTC_H_CUTOFF_ACTIVE_EN);
2103 tmp = INREG(CONFIG_MEMSIZE);
2106 /* mem size is bits [28:0], mask off the rest */
2107 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2110 tmp = INREG(MEM_SDRAM_MODE_REG);
2111 switch ((MEM_CFG_TYPE & tmp) >> 30) {
2113 /* SDR SGRAM (2:1) */
2114 strcpy(rinfo->ram_type, "SDR SGRAM");
2117 rinfo->ram.trcd = 1;
2121 rinfo->ram.loop_latency = 16;
2122 rinfo->ram.rloop = 16;
2126 strcpy(rinfo->ram_type, "DDR SGRAM");
2129 rinfo->ram.trcd = 3;
2133 rinfo->ram.tr2w = 1;
2134 rinfo->ram.loop_latency = 16;
2135 rinfo->ram.rloop = 16;
2138 /* 64-bit SDR SGRAM */
2139 strcpy(rinfo->ram_type, "SDR SGRAM 64");
2142 rinfo->ram.trcd = 3;
2146 rinfo->ram.tr2w = 1;
2147 rinfo->ram.loop_latency = 17;
2148 rinfo->ram.rloop = 17;
2153 * Hack to get around some busted production M6's
2156 if (rinfo->video_ram == 0) {
2157 switch (pdev->device) {
2158 case PCI_CHIP_RADEON_LY:
2159 case PCI_CHIP_RADEON_LZ:
2160 rinfo->video_ram = 8192 * 1024;
2167 RTRACE("radeonfb: probed %s %ldk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
2169 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2172 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2173 rinfo->mapped_vram);
2174 } while ( rinfo->fb_base == 0 &&
2175 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2178 memset_io(rinfo->fb_base, 0, rinfo->mapped_vram);
2180 printk (KERN_ERR "radeonfb: cannot map FB\n");
2185 RTRACE("radeonfb: mapped %ldk videoram\n", rinfo->mapped_vram/1024);
2188 * Check for required workaround for PLL accesses
2190 rinfo->R300_cg_workaround = (rinfo->family == CHIP_FAMILY_R300 &&
2191 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2192 == CFG_ATI_REV_A11);
2195 * Map the BIOS ROM if any and retreive PLL parameters from
2196 * the BIOS. We skip that on mobility chips as the real panel
2197 * values we need aren't in the ROM but in the BIOS image in
2198 * memory. This is definitely not the best meacnism though,
2199 * we really need the arch code to tell us which is the "primary"
2200 * video adapter to use the memory image (or better, the arch
2201 * should provide us a copy of the BIOS image to shield us from
2202 * archs who would store that elsewhere and/or could initialize
2203 * more than one adapter during boot).
2205 if (!rinfo->is_mobility)
2206 radeon_map_ROM(rinfo, pdev);
2209 * On x86, the primary display on laptop may have it's BIOS
2210 * ROM elsewhere, try to locate it at the legacy memory hole.
2211 * We probably need to make sure this is the primary display,
2212 * but that is difficult without some arch support.
2215 if (rinfo->bios_seg == NULL)
2216 radeon_find_mem_vbios(rinfo);
2219 /* If both above failed, try the BIOS ROM again for mobility
2222 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2223 radeon_map_ROM(rinfo, pdev);
2225 /* Get informations about the board's PLL */
2226 radeon_get_pllinfo(rinfo);
2228 #ifdef CONFIG_FB_RADEON_I2C
2229 /* Register I2C bus */
2230 radeon_create_i2c_busses(rinfo);
2233 /* set all the vital stuff */
2234 radeon_set_fbinfo (rinfo);
2236 /* Probe screen types */
2237 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2239 /* Build mode list, check out panel native model */
2240 radeon_check_modes(rinfo, mode_option);
2242 /* Register some sysfs stuff (should be done better) */
2243 if (rinfo->mon1_EDID)
2244 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2245 if (rinfo->mon2_EDID)
2246 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2248 /* save current mode regs before we switch into the new one
2249 * so we can restore this upon __exit
2251 radeon_save_state (rinfo, &rinfo->init_state);
2253 pci_set_drvdata(pdev, info);
2255 /* Enable PM on mobility chips */
2256 if (rinfo->is_mobility) {
2257 /* Find PM registers in config space */
2258 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
2259 /* Enable dynamic PM of chip clocks */
2260 radeon_pm_enable_dynamic_mode(rinfo);
2261 printk("radeonfb: Power Management enabled for Mobility chipsets\n");
2264 ret = register_framebuffer(info);
2266 printk (KERN_ERR "radeonfb: could not register framebuffer\n");
2271 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2273 MTRR_TYPE_WRCOMB, 1);
2276 #ifdef CONFIG_PMAC_BACKLIGHT
2277 if (rinfo->mon1_type == MT_LCD) {
2278 register_backlight_controller(&radeon_backlight_controller,
2280 register_backlight_controller(&radeon_backlight_controller,
2285 printk ("radeonfb: %s %s %ld MB\n", rinfo->name, rinfo->ram_type,
2286 (rinfo->video_ram/(1024*1024)));
2288 if (rinfo->bios_seg)
2289 radeon_unmap_ROM(rinfo, pdev);
2290 RTRACE("radeonfb_pci_register END\n");
2294 iounmap(rinfo->fb_base);
2296 if (rinfo->mon1_EDID)
2297 kfree(rinfo->mon1_EDID);
2298 if (rinfo->mon2_EDID)
2299 kfree(rinfo->mon2_EDID);
2300 if (rinfo->mon1_modedb)
2301 fb_destroy_modedb(rinfo->mon1_modedb);
2302 fb_dealloc_cmap(&info->cmap);
2303 #ifdef CONFIG_FB_RADEON_I2C
2304 radeon_delete_i2c_busses(rinfo);
2306 if (rinfo->bios_seg)
2307 radeon_unmap_ROM(rinfo, pdev);
2308 iounmap(rinfo->mmio_base);
2310 pci_release_regions(pdev);
2312 framebuffer_release(info);
2314 pci_disable_device(pdev);
2321 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2323 struct fb_info *info = pci_get_drvdata(pdev);
2324 struct radeonfb_info *rinfo = info->par;
2329 /* restore original state
2331 * Doesn't quite work yet, possibly because of the PPC hacking
2332 * I do on startup, disable for now. --BenH
2334 radeon_write_mode (rinfo, &rinfo->init_state);
2336 del_timer_sync(&rinfo->lvds_timer);
2339 if (rinfo->mtrr_hdl >= 0)
2340 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2343 unregister_framebuffer(info);
2345 iounmap(rinfo->mmio_base);
2346 iounmap(rinfo->fb_base);
2348 pci_release_regions(pdev);
2350 if (rinfo->mon1_EDID)
2351 kfree(rinfo->mon1_EDID);
2352 if (rinfo->mon2_EDID)
2353 kfree(rinfo->mon2_EDID);
2354 if (rinfo->mon1_modedb)
2355 fb_destroy_modedb(rinfo->mon1_modedb);
2356 #ifdef CONFIG_FB_RADEON_I2C
2357 radeon_delete_i2c_busses(rinfo);
2359 fb_dealloc_cmap(&info->cmap);
2360 framebuffer_release(info);
2361 pci_disable_device(pdev);
2365 static struct pci_driver radeonfb_driver = {
2367 .id_table = radeonfb_pci_table,
2368 .probe = radeonfb_pci_register,
2369 .remove = __devexit_p(radeonfb_pci_unregister),
2371 .suspend = radeonfb_pci_suspend,
2372 .resume = radeonfb_pci_resume,
2373 #endif /* CONFIG_PM */
2376 int __init radeonfb_setup (char *options);
2378 int __init radeonfb_init (void)
2381 char *option = NULL;
2383 if (fb_get_options("radeonfb", &option))
2385 radeonfb_setup(option);
2387 return pci_module_init (&radeonfb_driver);
2391 void __exit radeonfb_exit (void)
2393 pci_unregister_driver (&radeonfb_driver);
2396 int __init radeonfb_setup (char *options)
2400 if (!options || !*options)
2403 while ((this_opt = strsep (&options, ",")) != NULL) {
2407 if (!strncmp(this_opt, "noaccel", 7)) {
2409 } else if (!strncmp(this_opt, "mirror", 6)) {
2411 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2413 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2414 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2416 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2419 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2421 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2422 force_measure_pll = 1;
2423 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2426 mode_option = this_opt;
2431 module_init(radeonfb_init);
2434 module_exit(radeonfb_exit);
2437 MODULE_AUTHOR("Ani Joshi");
2438 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2439 MODULE_LICENSE("GPL");
2440 module_param(noaccel, bool, 0);
2441 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2442 module_param(nomodeset, bool, 0);
2443 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2444 module_param(mirror, bool, 0);
2445 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2446 module_param(force_dfp, bool, 0);
2447 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2448 module_param(ignore_edid, bool, 0);
2449 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2450 module_param(monitor_layout, charp, 0);
2451 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2452 module_param(force_measure_pll, bool, 0);
2453 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2455 module_param(nomtrr, bool, 0);
2456 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2458 module_param(panel_yres, int, 0);
2459 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2460 module_param(mode_option, charp, 0);
2461 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");