drivers/video/aty/radeon_base.c

   1 /*
   2  *      drivers/video/radeonfb.c
   3  *      framebuffer driver for ATI Radeon chipset video boards
   4  *
   5  *      Copyright 2003  Ben. Herrenschmidt <benh@kernel.crashing.org>
   6  *      Copyright 2000  Ani Joshi <ajoshi@kernel.crashing.org>
   7  *
   8  *      i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
   9  *
  10  *      Special thanks to ATI DevRel team for their hardware donations.
  11  *
  12  *      ...Insert GPL boilerplate here...
  13  *
  14  *      Significant portions of this driver apdated from XFree86 Radeon
  15  *      driver which has the following copyright notice:
  16  *
  17  *      Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  18  *                     VA Linux Systems Inc., Fremont, California.
  19  *
  20  *      All Rights Reserved.
  21  *
  22  *      Permission is hereby granted, free of charge, to any person obtaining
  23  *      a copy of this software and associated documentation files (the
  24  *      "Software"), to deal in the Software without restriction, including
  25  *      without limitation on the rights to use, copy, modify, merge,
  26  *      publish, distribute, sublicense, and/or sell copies of the Software,
  27  *      and to permit persons to whom the Software is furnished to do so,
  28  *      subject to the following conditions:
  29  *
  30  *      The above copyright notice and this permission notice (including the
  31  *      next paragraph) shall be included in all copies or substantial
  32  *      portions of the Software.
  33  *
  34  *      THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *      EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  36  *      MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *      NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
  38  *      THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *      WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  40  *      OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  41  *      DEALINGS IN THE SOFTWARE.
  42  *
  43  *      XFree86 driver authors:
  44  *
  45  *         Kevin E. Martin <martin@xfree86.org>
  46  *         Rickard E. Faith <faith@valinux.com>
  47  *         Alan Hourihane <alanh@fairlite.demon.co.uk>
  48  *
  49  */
  50
  51
  52 #define RADEON_VERSION  "0.2.0"
  53
  54 #include <linux/config.h>
  55 #include <linux/module.h>
  56 #include <linux/moduleparam.h>
  57 #include <linux/kernel.h>
  58 #include <linux/errno.h>
  59 #include <linux/string.h>
  60 #include <linux/mm.h>
  61 #include <linux/tty.h>
  62 #include <linux/slab.h>
  63 #include <linux/delay.h>
  64 #include <linux/fb.h>
  65 #include <linux/ioport.h>
  66 #include <linux/init.h>
  67 #include <linux/pci.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/device.h>
  70 #include <linux/i2c.h>
  71
  72 #include <asm/io.h>
  73 #include <asm/uaccess.h>
  74
  75 #ifdef CONFIG_PPC_OF
  76
  77 #include <asm/prom.h>
  78 #include <asm/pci-bridge.h>
  79 #include "../macmodes.h"
  80
  81 #ifdef CONFIG_PMAC_BACKLIGHT
  82 #include <asm/backlight.h>
  83 #endif
  84
  85 #ifdef CONFIG_BOOTX_TEXT
  86 #include <asm/btext.h>
  87 #endif
  88
  89 #endif /* CONFIG_PPC_OF */
  90
  91 #ifdef CONFIG_MTRR
  92 #include <asm/mtrr.h>
  93 #endif
  94
  95 #include <video/radeon.h>
  96 #include <linux/radeonfb.h>
  97
  98 #include "../edid.h" // MOVE THAT TO include/video
  99 #include "ati_ids.h"
 100 #include "radeonfb.h"
 101
 102 #define MAX_MAPPED_VRAM (2048*2048*4)
 103 #define MIN_MAPPED_VRAM (1024*768*1)
 104
 105 #define CHIP_DEF(id, family, flags)                                     \
 106         { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
 107
 108 static struct pci_device_id radeonfb_pci_table[] = {
 109         /* Mobility M6 */
 110         CHIP_DEF(PCI_CHIP_RADEON_LY,    RV100,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 111         CHIP_DEF(PCI_CHIP_RADEON_LZ,    RV100,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 112         /* Radeon VE/7000 */
 113         CHIP_DEF(PCI_CHIP_RV100_QY,     RV100,  CHIP_HAS_CRTC2),
 114         CHIP_DEF(PCI_CHIP_RV100_QZ,     RV100,  CHIP_HAS_CRTC2),
 115         /* Radeon IGP320M (U1) */
 116         CHIP_DEF(PCI_CHIP_RS100_4336,   RS100,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 117         /* Radeon IGP320 (A3) */
 118         CHIP_DEF(PCI_CHIP_RS100_4136,   RS100,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 119         /* IGP330M/340M/350M (U2) */
 120         CHIP_DEF(PCI_CHIP_RS200_4337,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 121         /* IGP330/340/350 (A4) */
 122         CHIP_DEF(PCI_CHIP_RS200_4137,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 123         /* Mobility 7000 IGP */
 124         CHIP_DEF(PCI_CHIP_RS250_4437,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 125         /* 7000 IGP (A4+) */
 126         CHIP_DEF(PCI_CHIP_RS250_4237,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 127         /* 8500 AIW */
 128         CHIP_DEF(PCI_CHIP_R200_BB,      R200,   CHIP_HAS_CRTC2),
 129         CHIP_DEF(PCI_CHIP_R200_BC,      R200,   CHIP_HAS_CRTC2),
 130         /* 8700/8800 */
 131         CHIP_DEF(PCI_CHIP_R200_QH,      R200,   CHIP_HAS_CRTC2),
 132         /* 8500 */
 133         CHIP_DEF(PCI_CHIP_R200_QL,      R200,   CHIP_HAS_CRTC2),
 134         /* 9100 */
 135         CHIP_DEF(PCI_CHIP_R200_QM,      R200,   CHIP_HAS_CRTC2),
 136         /* Mobility M7 */
 137         CHIP_DEF(PCI_CHIP_RADEON_LW,    RV200,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 138         CHIP_DEF(PCI_CHIP_RADEON_LX,    RV200,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 139         /* 7500 */
 140         CHIP_DEF(PCI_CHIP_RV200_QW,     RV200,  CHIP_HAS_CRTC2),
 141         CHIP_DEF(PCI_CHIP_RV200_QX,     RV200,  CHIP_HAS_CRTC2),
 142         /* Mobility M9 */
 143         CHIP_DEF(PCI_CHIP_RV250_Ld,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 144         CHIP_DEF(PCI_CHIP_RV250_Le,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 145         CHIP_DEF(PCI_CHIP_RV250_Lf,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 146         CHIP_DEF(PCI_CHIP_RV250_Lg,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 147         /* 9000/Pro */
 148         CHIP_DEF(PCI_CHIP_RV250_If,     RV250,  CHIP_HAS_CRTC2),
 149         CHIP_DEF(PCI_CHIP_RV250_Ig,     RV250,  CHIP_HAS_CRTC2),
 150         /* Mobility 9100 IGP (U3) */
 151         CHIP_DEF(PCI_CHIP_RS300_5835,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 152         /* 9100 IGP (A5) */
 153         CHIP_DEF(PCI_CHIP_RS300_5834,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 154         /* Mobility 9200 (M9+) */
 155         CHIP_DEF(PCI_CHIP_RV280_5C61,   RV280,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 156         CHIP_DEF(PCI_CHIP_RV280_5C63,   RV280,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 157         /* 9200 */
 158         CHIP_DEF(PCI_CHIP_RV280_5960,   RV280,  CHIP_HAS_CRTC2),
 159         CHIP_DEF(PCI_CHIP_RV280_5961,   RV280,  CHIP_HAS_CRTC2),
 160         CHIP_DEF(PCI_CHIP_RV280_5962,   RV280,  CHIP_HAS_CRTC2),
 161         CHIP_DEF(PCI_CHIP_RV280_5964,   RV280,  CHIP_HAS_CRTC2),
 162         /* 9500 */
 163         CHIP_DEF(PCI_CHIP_R300_AD,      R300,   CHIP_HAS_CRTC2),
 164         CHIP_DEF(PCI_CHIP_R300_AE,      R300,   CHIP_HAS_CRTC2),
 165         /* 9600TX / FireGL Z1 */
 166         CHIP_DEF(PCI_CHIP_R300_AF,      R300,   CHIP_HAS_CRTC2),
 167         CHIP_DEF(PCI_CHIP_R300_AG,      R300,   CHIP_HAS_CRTC2),
 168         /* 9700/9500/Pro/FireGL X1 */
 169         CHIP_DEF(PCI_CHIP_R300_ND,      R300,   CHIP_HAS_CRTC2),
 170         CHIP_DEF(PCI_CHIP_R300_NE,      R300,   CHIP_HAS_CRTC2),
 171         CHIP_DEF(PCI_CHIP_R300_NF,      R300,   CHIP_HAS_CRTC2),
 172         CHIP_DEF(PCI_CHIP_R300_NG,      R300,   CHIP_HAS_CRTC2),
 173         /* Mobility M10/M11 */
 174         CHIP_DEF(PCI_CHIP_RV350_NP,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 175         CHIP_DEF(PCI_CHIP_RV350_NQ,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 176         CHIP_DEF(PCI_CHIP_RV350_NR,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 177         CHIP_DEF(PCI_CHIP_RV350_NS,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 178         CHIP_DEF(PCI_CHIP_RV350_NT,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 179         CHIP_DEF(PCI_CHIP_RV350_NV,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 180         /* 9600/FireGL T2 */
 181         CHIP_DEF(PCI_CHIP_RV350_AP,     RV350,  CHIP_HAS_CRTC2),
 182         CHIP_DEF(PCI_CHIP_RV350_AQ,     RV350,  CHIP_HAS_CRTC2),
 183         CHIP_DEF(PCI_CHIP_RV360_AR,     RV350,  CHIP_HAS_CRTC2),
 184         CHIP_DEF(PCI_CHIP_RV350_AS,     RV350,  CHIP_HAS_CRTC2),
 185         CHIP_DEF(PCI_CHIP_RV350_AT,     RV350,  CHIP_HAS_CRTC2),
 186         CHIP_DEF(PCI_CHIP_RV350_AV,     RV350,  CHIP_HAS_CRTC2),
 187         /* 9800/Pro/FileGL X2 */
 188         CHIP_DEF(PCI_CHIP_R350_AH,      R350,   CHIP_HAS_CRTC2),
 189         CHIP_DEF(PCI_CHIP_R350_AI,      R350,   CHIP_HAS_CRTC2),
 190         CHIP_DEF(PCI_CHIP_R350_AJ,      R350,   CHIP_HAS_CRTC2),
 191         CHIP_DEF(PCI_CHIP_R350_AK,      R350,   CHIP_HAS_CRTC2),
 192         CHIP_DEF(PCI_CHIP_R350_NH,      R350,   CHIP_HAS_CRTC2),
 193         CHIP_DEF(PCI_CHIP_R350_NI,      R350,   CHIP_HAS_CRTC2),
 194         CHIP_DEF(PCI_CHIP_R360_NJ,      R350,   CHIP_HAS_CRTC2),
 195         CHIP_DEF(PCI_CHIP_R350_NK,      R350,   CHIP_HAS_CRTC2),
 196         /* Original Radeon/7200 */
 197         CHIP_DEF(PCI_CHIP_RADEON_QD,    RADEON, 0),
 198         CHIP_DEF(PCI_CHIP_RADEON_QE,    RADEON, 0),
 199         CHIP_DEF(PCI_CHIP_RADEON_QF,    RADEON, 0),
 200         CHIP_DEF(PCI_CHIP_RADEON_QG,    RADEON, 0),
 201         { 0, }
 202 };
 203 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
 204
 205
 206 typedef struct {
 207         u16 reg;
 208         u32 val;
 209 } reg_val;
 210
 211
 212 /* these common regs are cleared before mode setting so they do not
 213  * interfere with anything
 214  */
 215 static reg_val common_regs[] = {
 216         { OVR_CLR, 0 },
 217         { OVR_WID_LEFT_RIGHT, 0 },
 218         { OVR_WID_TOP_BOTTOM, 0 },
 219         { OV0_SCALE_CNTL, 0 },
 220         { SUBPIC_CNTL, 0 },
 221         { VIPH_CONTROL, 0 },
 222         { I2C_CNTL_1, 0 },
 223         { GEN_INT_CNTL, 0 },
 224         { CAP0_TRIG_CNTL, 0 },
 225         { CAP1_TRIG_CNTL, 0 },
 226 };
 227
 228 /*
 229  * globals
 230  */
 231
 232 static char *mode_option;
 233 static char *monitor_layout;
 234 static int noaccel = 0;
 235 static int nomodeset = 0;
 236 static int ignore_edid = 0;
 237 static int mirror = 0;
 238 static int panel_yres = 0;
 239 static int force_dfp = 0;
 240 static int force_measure_pll = 0;
 241 #ifdef CONFIG_MTRR
 242 static int nomtrr = 0;
 243 #endif
 244
 245 int radeonfb_noaccel = 0;
 246
 247 /*
 248  * prototypes
 249  */
 250
 251
 252 #ifdef CONFIG_PPC_OF
 253
 254 #ifdef CONFIG_PMAC_BACKLIGHT
 255 static int radeon_set_backlight_enable(int on, int level, void *data);
 256 static int radeon_set_backlight_level(int level, void *data);
 257 static struct backlight_controller radeon_backlight_controller = {
 258         radeon_set_backlight_enable,
 259         radeon_set_backlight_level
 260 };
 261 #endif /* CONFIG_PMAC_BACKLIGHT */
 262
 263 #endif /* CONFIG_PPC_OF */
 264
 265 static void __devexit radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
 266 {
 267         // leave it disabled and unassigned
 268         struct resource *r = &dev->resource[PCI_ROM_RESOURCE];
 269
 270         if (!rinfo->bios_seg)
 271                 return;
 272         iounmap(rinfo->bios_seg);
 273
 274         /* Release the ROM resource if we used it in the first place */
 275         if (r->parent && r->flags & PCI_ROM_ADDRESS_ENABLE) {
 276                 release_resource(r);
 277                 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
 278                 r->end -= r->start;
 279                 r->start = 0;
 280         }
 281         /* This will disable and set address to unassigned */
 282         pci_write_config_dword(dev, dev->rom_base_reg, 0);
 283 }
 284
 285 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
 286 {
 287         void *rom;
 288         struct resource *r;
 289         u16 dptr;
 290         u8 rom_type;
 291
 292         /* If this is a primary card, there is a shadow copy of the
 293          * ROM somewhere in the first meg. We will just ignore the copy
 294          * and use the ROM directly.
 295          */
 296
 297         /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
 298         unsigned int temp;
 299         temp = INREG(MPP_TB_CONFIG);
 300         temp &= 0x00ffffffu;
 301         temp |= 0x04 << 24;
 302         OUTREG(MPP_TB_CONFIG, temp);
 303         temp = INREG(MPP_TB_CONFIG);
 304
 305         /* no need to search for the ROM, just ask the card where it is. */
 306         r = &dev->resource[PCI_ROM_RESOURCE];
 307
 308         /* assign the ROM an address if it doesn't have one */
 309         if (r->parent == NULL)
 310                 pci_assign_resource(dev, PCI_ROM_RESOURCE);
 311
 312         /* enable if needed */
 313         if (!(r->flags & PCI_ROM_ADDRESS_ENABLE)) {
 314                 pci_write_config_dword(dev, dev->rom_base_reg,
 315                                        r->start | PCI_ROM_ADDRESS_ENABLE);
 316                 r->flags |= PCI_ROM_ADDRESS_ENABLE;
 317         }
 318
 319         rom = ioremap(r->start, r->end - r->start + 1);
 320         if (!rom) {
 321                 printk(KERN_ERR "radeonfb: ROM failed to map\n");
 322                 return -ENOMEM;
 323         }
 324
 325         rinfo->bios_seg = rom;
 326
 327         /* Very simple test to make sure it appeared */
 328         if (BIOS_IN16(0) != 0xaa55) {
 329                 printk(KERN_ERR "radeonfb: Invalid ROM signature %x should be 0xaa55\n",
 330                        BIOS_IN16(0));
 331                 goto failed;
 332         }
 333         /* Look for the PCI data to check the ROM type */
 334         dptr = BIOS_IN16(0x18);
 335
 336         /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
 337          * for now, until I've verified this works everywhere. The goal here is more
 338          * to phase out Open Firmware images.
 339          *
 340          * Currently, we only look at the first PCI data, we could iteratre and deal with
 341          * them all, and we should use fb_bios_start relative to start of image and not
 342          * relative start of ROM, but so far, I never found a dual-image ATI card
 343          *
 344          * typedef struct {
 345          *      u32     signature;      + 0x00
 346          *      u16     vendor;         + 0x04
 347          *      u16     device;         + 0x06
 348          *      u16     reserved_1;     + 0x08
 349          *      u16     dlen;           + 0x0a
 350          *      u8      drevision;      + 0x0c
 351          *      u8      class_hi;       + 0x0d
 352          *      u16     class_lo;       + 0x0e
 353          *      u16     ilen;           + 0x10
 354          *      u16     irevision;      + 0x12
 355          *      u8      type;           + 0x14
 356          *      u8      indicator;      + 0x15
 357          *      u16     reserved_2;     + 0x16
 358          * } pci_data_t;
 359          */
 360         if (BIOS_IN32(dptr) !=  (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
 361                 printk(KERN_WARNING "radeonfb: PCI DATA signature in ROM incorrect: %08x\n",
 362                        BIOS_IN32(dptr));
 363                 goto anyway;
 364         }
 365         rom_type = BIOS_IN8(dptr + 0x14);
 366         switch(rom_type) {
 367         case 0:
 368                 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
 369                 break;
 370         case 1:
 371                 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
 372                 goto failed;
 373         case 2:
 374                 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
 375                 goto failed;
 376         default:
 377                 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
 378                 goto failed;
 379         }
 380  anyway:
 381         /* Locate the flat panel infos, do some sanity checking !!! */
 382         rinfo->fp_bios_start = BIOS_IN16(0x48);
 383         return 0;
 384
 385  failed:
 386         rinfo->bios_seg = NULL;
 387         radeon_unmap_ROM(rinfo, dev);
 388         return -ENXIO;
 389 }
 390
 391 #ifdef __i386__
 392 static int  __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
 393 {
 394         /* I simplified this code as we used to miss the signatures in
 395          * a lot of case. It's now closer to XFree, we just don't check
 396          * for signatures at all... Something better will have to be done
 397          * if we end up having conflicts
 398          */
 399         u32  segstart;
 400         unsigned char *rom_base = NULL;
 401
 402         for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
 403                 rom_base = (char *)ioremap(segstart, 0x10000);
 404                 if (rom_base == NULL)
 405                         return -ENOMEM;
 406                 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
 407                         break;
 408                 iounmap(rom_base);
 409                 rom_base = NULL;
 410         }
 411         if (rom_base == NULL)
 412                 return -ENXIO;
 413
 414         /* Locate the flat panel infos, do some sanity checking !!! */
 415         rinfo->bios_seg = rom_base;
 416         rinfo->fp_bios_start = BIOS_IN16(0x48);
 417
 418         return 0;
 419 }
 420 #endif /* __i386__ */
 421
 422 #ifdef CONFIG_PPC_OF
 423 /*
 424  * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
 425  * tree. Hopefully, ATI OF driver is kind enough to fill these
 426  */
 427 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
 428 {
 429         struct device_node *dp;
 430         u32 *val;
 431
 432         dp = pci_device_to_OF_node(rinfo->pdev);
 433         if (dp == NULL) {
 434                 printk(KERN_WARNING "radeonfb: Cannot match card to OF node !\n");
 435                 return -ENODEV;
 436         }
 437         val = (u32 *) get_property(dp, "ATY,RefCLK", 0);
 438         if (!val || !*val) {
 439                 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
 440                 return -EINVAL;
 441         }
 442
 443         rinfo->pll.ref_clk = (*val) / 10;
 444
 445         val = (u32 *) get_property(dp, "ATY,SCLK", 0);
 446         if (val && *val)
 447                 rinfo->pll.sclk = (*val) / 10;
 448
 449         val = (u32 *) get_property(dp, "ATY,MCLK", 0);
 450         if (val && *val)
 451                 rinfo->pll.mclk = (*val) / 10;
 452
 453         return 0;
 454 }
 455 #endif /* CONFIG_PPC_OF */
 456
 457 /*
 458  * Read PLL infos from chip registers
 459  */
 460 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
 461 {
 462         unsigned char ppll_div_sel;
 463         unsigned Ns, Nm, M;
 464         unsigned sclk, mclk, tmp, ref_div;
 465         int hTotal, vTotal, num, denom, m, n;
 466         unsigned long long hz, vclk;
 467         long xtal;
 468         struct timeval start_tv, stop_tv;
 469         long total_secs, total_usecs;
 470         int i;
 471
 472         /* Ugh, we cut interrupts, bad bad bad, but we want some precision
 473          * here, so... --BenH
 474          */
 475
 476         /* Flush PCI buffers ? */
 477         tmp = INREG(DEVICE_ID);
 478
 479         local_irq_disable();
 480
 481         for(i=0; i<1000000; i++)
 482                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
 483                         break;
 484
 485         do_gettimeofday(&start_tv);
 486
 487         for(i=0; i<1000000; i++)
 488                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
 489                         break;
 490
 491         for(i=0; i<1000000; i++)
 492                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
 493                         break;
 494
 495         do_gettimeofday(&stop_tv);
 496
 497         local_irq_enable();
 498
 499         total_secs = stop_tv.tv_sec - start_tv.tv_sec;
 500         if (total_secs > 10)
 501                 return -1;
 502         total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
 503         total_usecs += total_secs * 1000000;
 504         if (total_usecs < 0)
 505                 total_usecs = -total_usecs;
 506         hz = 1000000/total_usecs;
 507
 508         hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
 509         vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
 510         vclk = (long long)hTotal * (long long)vTotal * hz;
 511
 512         switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
 513         case 0:
 514         default:
 515                 num = 1;
 516                 denom = 1;
 517                 break;
 518         case 1:
 519                 n = ((INPLL(X_MPLL_REF_FB_DIV) >> 16) & 0xff);
 520                 m = (INPLL(X_MPLL_REF_FB_DIV) & 0xff);
 521                 num = 2*n;
 522                 denom = 2*m;
 523                 break;
 524         case 2:
 525                 n = ((INPLL(X_MPLL_REF_FB_DIV) >> 8) & 0xff);
 526                 m = (INPLL(X_MPLL_REF_FB_DIV) & 0xff);
 527                 num = 2*n;
 528                 denom = 2*m;
 529         break;
 530         }
 531
 532         OUTREG8(CLOCK_CNTL_INDEX, 1);
 533         ppll_div_sel = INREG8(CLOCK_CNTL_DATA + 1) & 0x3;
 534
 535         n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
 536         m = (INPLL(PPLL_REF_DIV) & 0x3ff);
 537
 538         num *= n;
 539         denom *= m;
 540
 541         switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
 542         case 1:
 543                 denom *= 2;
 544                 break;
 545         case 2:
 546                 denom *= 4;
 547                 break;
 548         case 3:
 549                 denom *= 8;
 550                 break;
 551         case 4:
 552                 denom *= 3;
 553                 break;
 554         case 6:
 555                 denom *= 6;
 556                 break;
 557         case 7:
 558                 denom *= 12;
 559                 break;
 560         }
 561
 562         vclk *= denom;
 563         do_div(vclk, 1000 * num);
 564         xtal = vclk;
 565
 566         if ((xtal > 26900) && (xtal < 27100))
 567                 xtal = 2700;
 568         else if ((xtal > 14200) && (xtal < 14400))
 569                 xtal = 1432;
 570         else if ((xtal > 29400) && (xtal < 29600))
 571                 xtal = 2950;
 572         else {
 573                 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
 574                 return -1;
 575         }
 576
 577         tmp = INPLL(X_MPLL_REF_FB_DIV);
 578         ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 579
 580         Ns = (tmp & 0xff0000) >> 16;
 581         Nm = (tmp & 0xff00) >> 8;
 582         M = (tmp & 0xff);
 583         sclk = round_div((2 * Ns * xtal), (2 * M));
 584         mclk = round_div((2 * Nm * xtal), (2 * M));
 585
 586         /* we're done, hopefully these are sane values */
 587         rinfo->pll.ref_clk = xtal;
 588         rinfo->pll.ref_div = ref_div;
 589         rinfo->pll.sclk = sclk;
 590         rinfo->pll.mclk = mclk;
 591
 592         return 0;
 593 }
 594
 595 /*
 596  * Retreive PLL infos by different means (BIOS, Open Firmware, register probing...)
 597  */
 598 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
 599 {
 600 #ifdef CONFIG_PPC_OF
 601         /*
 602          * Retreive PLL infos from Open Firmware first
 603          */
 604         if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
 605                 printk(KERN_INFO "radeonfb: Retreived PLL infos from Open Firmware\n");
 606                 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 607                 /* FIXME: Max clock may be higher on newer chips */
 608                 rinfo->pll.ppll_min = 12000;
 609                 rinfo->pll.ppll_max = 35000;
 610                 goto found;
 611         }
 612 #endif /* CONFIG_PPC_OF */
 613
 614         /*
 615          * Check out if we have an X86 which gave us some PLL informations
 616          * and if yes, retreive them
 617          */
 618         if (!force_measure_pll && rinfo->bios_seg) {
 619                 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
 620
 621                 rinfo->pll.sclk         = BIOS_IN16(pll_info_block + 0x08);
 622                 rinfo->pll.mclk         = BIOS_IN16(pll_info_block + 0x0a);
 623                 rinfo->pll.ref_clk      = BIOS_IN16(pll_info_block + 0x0e);
 624                 rinfo->pll.ref_div      = BIOS_IN16(pll_info_block + 0x10);
 625                 rinfo->pll.ppll_min     = BIOS_IN32(pll_info_block + 0x12);
 626                 rinfo->pll.ppll_max     = BIOS_IN32(pll_info_block + 0x16);
 627
 628                 printk(KERN_INFO "radeonfb: Retreived PLL infos from BIOS\n");
 629                 goto found;
 630         }
 631
 632         /*
 633          * We didn't get PLL parameters from either OF or BIOS, we try to
 634          * probe them
 635          */
 636         if (radeon_probe_pll_params(rinfo) == 0) {
 637                 printk(KERN_INFO "radeonfb: Retreived PLL infos from registers\n");
 638                 /* FIXME: Max clock may be higher on newer chips */
 639                 rinfo->pll.ppll_min = 12000;
 640                 rinfo->pll.ppll_max = 35000;
 641                 goto found;
 642         }
 643
 644         /*
 645          * Neither of the above worked, we have a few default values, though
 646          * that's mostly incomplete
 647          */
 648         switch (rinfo->chipset) {
 649         case PCI_DEVICE_ID_ATI_RADEON_QW:
 650         case PCI_DEVICE_ID_ATI_RADEON_QX:
 651                 rinfo->pll.ppll_max = 35000;
 652                 rinfo->pll.ppll_min = 12000;
 653                 rinfo->pll.mclk = 23000;
 654                 rinfo->pll.sclk = 23000;
 655                 rinfo->pll.ref_clk = 2700;
 656                 break;
 657         case PCI_DEVICE_ID_ATI_RADEON_QL:
 658         case PCI_DEVICE_ID_ATI_RADEON_QN:
 659         case PCI_DEVICE_ID_ATI_RADEON_QO:
 660         case PCI_DEVICE_ID_ATI_RADEON_Ql:
 661         case PCI_DEVICE_ID_ATI_RADEON_BB:
 662                 rinfo->pll.ppll_max = 35000;
 663                 rinfo->pll.ppll_min = 12000;
 664                 rinfo->pll.mclk = 27500;
 665                 rinfo->pll.sclk = 27500;
 666                 rinfo->pll.ref_clk = 2700;
 667                 break;
 668         case PCI_DEVICE_ID_ATI_RADEON_Id:
 669         case PCI_DEVICE_ID_ATI_RADEON_Ie:
 670         case PCI_DEVICE_ID_ATI_RADEON_If:
 671         case PCI_DEVICE_ID_ATI_RADEON_Ig:
 672                 rinfo->pll.ppll_max = 35000;
 673                 rinfo->pll.ppll_min = 12000;
 674                 rinfo->pll.mclk = 25000;
 675                 rinfo->pll.sclk = 25000;
 676                 rinfo->pll.ref_clk = 2700;
 677                 break;
 678         case PCI_DEVICE_ID_ATI_RADEON_ND:
 679         case PCI_DEVICE_ID_ATI_RADEON_NE:
 680         case PCI_DEVICE_ID_ATI_RADEON_NF:
 681         case PCI_DEVICE_ID_ATI_RADEON_NG:
 682                 rinfo->pll.ppll_max = 40000;
 683                 rinfo->pll.ppll_min = 20000;
 684                 rinfo->pll.mclk = 27000;
 685                 rinfo->pll.sclk = 27000;
 686                 rinfo->pll.ref_clk = 2700;
 687                 break;
 688         case PCI_DEVICE_ID_ATI_RADEON_QD:
 689         case PCI_DEVICE_ID_ATI_RADEON_QE:
 690         case PCI_DEVICE_ID_ATI_RADEON_QF:
 691         case PCI_DEVICE_ID_ATI_RADEON_QG:
 692         default:
 693                 rinfo->pll.ppll_max = 35000;
 694                 rinfo->pll.ppll_min = 12000;
 695                 rinfo->pll.mclk = 16600;
 696                 rinfo->pll.sclk = 16600;
 697                 rinfo->pll.ref_clk = 2700;
 698                 break;
 699         }
 700         rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 701
 702         printk(KERN_INFO "radeonfb: Used default PLL infos\n");
 703
 704 found:
 705         /*
 706          * Some methods fail to retreive SCLK and MCLK values, we apply default
 707          * settings in this case (200Mhz). If that really happne often, we could
 708          * fetch from registers instead...
 709          */
 710         if (rinfo->pll.mclk == 0)
 711                 rinfo->pll.mclk = 20000;
 712         if (rinfo->pll.sclk == 0)
 713                 rinfo->pll.sclk = 20000;
 714
 715         printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
 716                rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
 717                rinfo->pll.ref_div,
 718                rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
 719                rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
 720 }
 721
 722 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
 723 {
 724         struct radeonfb_info *rinfo = info->par;
 725         struct fb_var_screeninfo v;
 726         int nom, den;
 727         unsigned int pitch;
 728
 729         if (radeon_match_mode(rinfo, &v, var))
 730                 return -EINVAL;
 731
 732         switch (v.bits_per_pixel) {
 733                 case 0 ... 8:
 734                         v.bits_per_pixel = 8;
 735                         break;
 736                 case 9 ... 16:
 737                         v.bits_per_pixel = 16;
 738                         break;
 739                 case 17 ... 24:
 740 #if 0 /* Doesn't seem to work */
 741                         v.bits_per_pixel = 24;
 742                         break;
 743 #endif
 744                         return -EINVAL;
 745                 case 25 ... 32:
 746                         v.bits_per_pixel = 32;
 747                         break;
 748                 default:
 749                         return -EINVAL;
 750         }
 751
 752         switch (var_to_depth(&v)) {
 753                 case 8:
 754                         nom = den = 1;
 755                         v.red.offset = v.green.offset = v.blue.offset = 0;
 756                         v.red.length = v.green.length = v.blue.length = 8;
 757                         v.transp.offset = v.transp.length = 0;
 758                         break;
 759                 case 15:
 760                         nom = 2;
 761                         den = 1;
 762                         v.red.offset = 10;
 763                         v.green.offset = 5;
 764                         v.blue.offset = 0;
 765                         v.red.length = v.green.length = v.blue.length = 5;
 766                         v.transp.offset = v.transp.length = 0;
 767                         break;
 768                 case 16:
 769                         nom = 2;
 770                         den = 1;
 771                         v.red.offset = 11;
 772                         v.green.offset = 5;
 773                         v.blue.offset = 0;
 774                         v.red.length = 5;
 775                         v.green.length = 6;
 776                         v.blue.length = 5;
 777                         v.transp.offset = v.transp.length = 0;
 778                         break;
 779                 case 24:
 780                         nom = 4;
 781                         den = 1;
 782                         v.red.offset = 16;
 783                         v.green.offset = 8;
 784                         v.blue.offset = 0;
 785                         v.red.length = v.blue.length = v.green.length = 8;
 786                         v.transp.offset = v.transp.length = 0;
 787                         break;
 788                 case 32:
 789                         nom = 4;
 790                         den = 1;
 791                         v.red.offset = 16;
 792                         v.green.offset = 8;
 793                         v.blue.offset = 0;
 794                         v.red.length = v.blue.length = v.green.length = 8;
 795                         v.transp.offset = 24;
 796                         v.transp.length = 8;
 797                         break;
 798                 default:
 799                         printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
 800                                 var->xres, var->yres, var->bits_per_pixel);
 801                         return -EINVAL;
 802         }
 803
 804         if (v.yres_virtual < v.yres)
 805                 v.yres_virtual = v.yres;
 806         if (v.xres_virtual < v.xres)
 807                 v.xres_virtual = v.xres;
 808
 809
 810         /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
 811          * with some panels, though I don't quite like this solution
 812          */
 813         if (radeon_accel_disabled()) {
 814                 v.xres_virtual = v.xres_virtual & ~7ul;
 815                 v.accel_flags = 0;
 816         } else {
 817                 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
 818                                 & ~(0x3f)) >> 6;
 819                 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
 820         }
 821
 822         if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
 823                 return -EINVAL;
 824
 825         if (v.xres_virtual < v.xres)
 826                 v.xres = v.xres_virtual;
 827
 828         if (v.xoffset < 0)
 829                 v.xoffset = 0;
 830         if (v.yoffset < 0)
 831                 v.yoffset = 0;
 832
 833         if (v.xoffset > v.xres_virtual - v.xres)
 834                 v.xoffset = v.xres_virtual - v.xres - 1;
 835
 836         if (v.yoffset > v.yres_virtual - v.yres)
 837                 v.yoffset = v.yres_virtual - v.yres - 1;
 838
 839         v.red.msb_right = v.green.msb_right = v.blue.msb_right =
 840                           v.transp.offset = v.transp.length =
 841                           v.transp.msb_right = 0;
 842
 843         memcpy(var, &v, sizeof(v));
 844
 845         return 0;
 846 }
 847
 848
 849 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
 850                                  struct fb_info *info)
 851 {
 852         struct radeonfb_info *rinfo = info->par;
 853
 854         if ((var->xoffset + var->xres > var->xres_virtual)
 855             || (var->yoffset + var->yres > var->yres_virtual))
 856                return -EINVAL;
 857
 858         if (rinfo->asleep)
 859                 return 0;
 860
 861         radeon_fifo_wait(2);
 862         OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
 863                              * var->bits_per_pixel / 8) & ~7);
 864         return 0;
 865 }
 866
 867
 868 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
 869                            unsigned long arg, struct fb_info *info)
 870 {
 871         struct radeonfb_info *rinfo = info->par;
 872         unsigned int tmp;
 873         u32 value = 0;
 874         int rc;
 875
 876         switch (cmd) {
 877                 /*
 878                  * TODO:  set mirror accordingly for non-Mobility chipsets with 2 CRTC's
 879                  *        and do something better using 2nd CRTC instead of just hackish
 880                  *        routing to second output
 881                  */
 882                 case FBIO_RADEON_SET_MIRROR:
 883                         if (!rinfo->is_mobility)
 884                                 return -EINVAL;
 885
 886                         rc = get_user(value, (__u32 __user *)arg);
 887
 888                         if (rc)
 889                                 return rc;
 890
 891                         radeon_fifo_wait(2);
 892                         if (value & 0x01) {
 893                                 tmp = INREG(LVDS_GEN_CNTL);
 894
 895                                 tmp |= (LVDS_ON | LVDS_BLON);
 896                         } else {
 897                                 tmp = INREG(LVDS_GEN_CNTL);
 898
 899                                 tmp &= ~(LVDS_ON | LVDS_BLON);
 900                         }
 901
 902                         OUTREG(LVDS_GEN_CNTL, tmp);
 903
 904                         if (value & 0x02) {
 905                                 tmp = INREG(CRTC_EXT_CNTL);
 906                                 tmp |= CRTC_CRT_ON;
 907
 908                                 mirror = 1;
 909                         } else {
 910                                 tmp = INREG(CRTC_EXT_CNTL);
 911                                 tmp &= ~CRTC_CRT_ON;
 912
 913                                 mirror = 0;
 914                         }
 915
 916                         OUTREG(CRTC_EXT_CNTL, tmp);
 917
 918                         break;
 919                 case FBIO_RADEON_GET_MIRROR:
 920                         if (!rinfo->is_mobility)
 921                                 return -EINVAL;
 922
 923                         tmp = INREG(LVDS_GEN_CNTL);
 924                         if ((LVDS_ON | LVDS_BLON) & tmp)
 925                                 value |= 0x01;
 926
 927                         tmp = INREG(CRTC_EXT_CNTL);
 928                         if (CRTC_CRT_ON & tmp)
 929                                 value |= 0x02;
 930
 931                         return put_user(value, (__u32 __user *)arg);
 932                 default:
 933                         return -EINVAL;
 934         }
 935
 936         return -EINVAL;
 937 }
 938
 939
 940 static int radeon_screen_blank (struct radeonfb_info *rinfo, int blank)
 941 {
 942         u32 val = INREG(CRTC_EXT_CNTL);
 943         u32 val2 = 0;
 944
 945         if (rinfo->mon1_type == MT_LCD)
 946                 val2 = INREG(LVDS_GEN_CNTL) & ~LVDS_DISPLAY_DIS;
 947
 948         /* reset it */
 949         val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
 950                  CRTC_VSYNC_DIS);
 951
 952         switch (blank) {
 953                 case VESA_NO_BLANKING:
 954                         break;
 955                 case VESA_VSYNC_SUSPEND:
 956                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
 957                         break;
 958                 case VESA_HSYNC_SUSPEND:
 959                         val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
 960                         break;
 961                 case VESA_POWERDOWN:
 962                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
 963                                 CRTC_HSYNC_DIS);
 964                         val2 |= (LVDS_DISPLAY_DIS);
 965                         break;
 966         }
 967
 968         radeon_fifo_wait(1);
 969         switch (rinfo->mon1_type) {
 970                 case MT_LCD:
 971                         OUTREG(LVDS_GEN_CNTL, val2);
 972                         break;
 973                 case MT_CRT:
 974                 default:
 975                         OUTREG(CRTC_EXT_CNTL, val);
 976                         break;
 977         }
 978
 979         return 0;
 980 }
 981
 982 int radeonfb_blank (int blank, struct fb_info *info)
 983 {
 984         struct radeonfb_info *rinfo = info->par;
 985
 986         if (rinfo->asleep)
 987                 return 0;
 988
 989 #ifdef CONFIG_PMAC_BACKLIGHT
 990         if (rinfo->mon1_type == MT_LCD && _machine == _MACH_Pmac && blank)
 991                 set_backlight_enable(0);
 992 #endif
 993
 994         radeon_screen_blank(rinfo, blank);
 995
 996 #ifdef CONFIG_PMAC_BACKLIGHT
 997         if (rinfo->mon1_type == MT_LCD && _machine == _MACH_Pmac && !blank)
 998                 set_backlight_enable(1);
 999 #endif
1000
1001         return 0;
1002 }
1003
1004 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1005                              unsigned blue, unsigned transp, struct fb_info *info)
1006 {
1007         struct radeonfb_info *rinfo = info->par;
1008         u32 pindex;
1009         unsigned int i;
1010
1011         if (regno > 255)
1012                 return 1;
1013
1014         red >>= 8;
1015         green >>= 8;
1016         blue >>= 8;
1017         rinfo->palette[regno].red = red;
1018         rinfo->palette[regno].green = green;
1019         rinfo->palette[regno].blue = blue;
1020
1021         /* default */
1022         pindex = regno;
1023
1024         if (!rinfo->asleep) {
1025                 u32 dac_cntl2, vclk_cntl = 0;
1026
1027                 radeon_fifo_wait(9);
1028                 if (rinfo->is_mobility) {
1029                         vclk_cntl = INPLL(VCLK_ECP_CNTL);
1030                         OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1031                 }
1032
1033                 /* Make sure we are on first palette */
1034                 if (rinfo->has_CRTC2) {
1035                         dac_cntl2 = INREG(DAC_CNTL2);
1036                         dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1037                         OUTREG(DAC_CNTL2, dac_cntl2);
1038                 }
1039
1040                 if (rinfo->bpp == 16) {
1041                         pindex = regno * 8;
1042
1043                         if (rinfo->depth == 16 && regno > 63)
1044                                 return 1;
1045                         if (rinfo->depth == 15 && regno > 31)
1046                                 return 1;
1047
1048                         /* For 565, the green component is mixed one order below */
1049                         if (rinfo->depth == 16) {
1050                                 OUTREG(PALETTE_INDEX, pindex>>1);
1051                                 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1052                                         (green << 8) | (rinfo->palette[regno>>1].blue));
1053                                 green = rinfo->palette[regno<<1].green;
1054                         }
1055                 }
1056
1057                 if (rinfo->depth != 16 || regno < 32) {
1058                         OUTREG(PALETTE_INDEX, pindex);
1059                         OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1060                 }
1061                 if (rinfo->is_mobility)
1062                         OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1063         }
1064         if (regno < 16) {
1065                 u32 *pal = info->pseudo_palette;
1066                 switch (rinfo->depth) {
1067                 case 15:
1068                         pal[regno] = (regno << 10) | (regno << 5) | regno;
1069                         break;
1070                 case 16:
1071                         pal[regno] = (regno << 11) | (regno << 5) | regno;
1072                         break;
1073                 case 24:
1074                         pal[regno] = (regno << 16) | (regno << 8) | regno;
1075                         break;
1076                 case 32:
1077                         i = (regno << 8) | regno;
1078                         pal[regno] = (i << 16) | i;
1079                         break;
1080                 }
1081         }
1082         return 0;
1083 }
1084
1085
1086 static void radeon_save_state (struct radeonfb_info *rinfo, struct radeon_regs *save)
1087 {
1088         /* CRTC regs */
1089         save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1090         save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1091         save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1092         save->dac_cntl = INREG(DAC_CNTL);
1093         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1094         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1095         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1096         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1097         save->crtc_pitch = INREG(CRTC_PITCH);
1098         save->surface_cntl = INREG(SURFACE_CNTL);
1099
1100         /* FP regs */
1101         save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1102         save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1103         save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1104         save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1105         save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1106         save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1107         save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1108         save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1109         save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1110         save->tmds_crc = INREG(TMDS_CRC);       save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1111         save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1112 }
1113
1114
1115 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1116 {
1117         int i;
1118
1119         radeon_fifo_wait(20);
1120
1121         /* Workaround from XFree */
1122         if (rinfo->is_mobility) {
1123                 /* A temporal workaround for the occational blanking on certain laptop panels.
1124                    This appears to related to the PLL divider registers (fail to lock?).
1125                    It occurs even when all dividers are the same with their old settings.
1126                    In this case we really don't need to fiddle with PLL registers.
1127                    By doing this we can avoid the blanking problem with some panels.
1128                 */
1129                 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1130                     (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1131                                           (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1132                         /* We still have to force a switch to PPLL div 3 thanks to
1133                          * an XFree86 driver bug which will switch it away in some cases
1134                          * even when using UseFDev */
1135                         OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, ~PPLL_DIV_SEL_MASK);
1136                         return;
1137                 }
1138         }
1139
1140         /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1141         OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1142
1143         /* Reset PPLL & enable atomic update */
1144         OUTPLLP(PPLL_CNTL,
1145                 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1146                 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1147
1148         /* Switch to PPLL div 3 */
1149         OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, ~PPLL_DIV_SEL_MASK);
1150
1151         /* Set PPLL ref. div */
1152         if (rinfo->family == CHIP_FAMILY_R300 ||
1153             rinfo->family == CHIP_FAMILY_RS300 ||
1154             rinfo->family == CHIP_FAMILY_R350 ||
1155             rinfo->family == CHIP_FAMILY_RV350) {
1156                 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1157                         /* When restoring console mode, use saved PPLL_REF_DIV
1158                          * setting.
1159                          */
1160                         OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1161                 } else {
1162                         /* R300 uses ref_div_acc field as real ref divider */
1163                         OUTPLLP(PPLL_REF_DIV,
1164                                 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1165                                 ~R300_PPLL_REF_DIV_ACC_MASK);
1166                 }
1167         } else
1168                 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1169
1170         /* Set PPLL divider 3 & post divider*/
1171         OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1172         OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1173
1174         /* Write update */
1175         while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1176                 ;
1177         OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1178
1179         /* Wait read update complete */
1180         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
1181            the cause yet, but this workaround will mask the problem for now.
1182            Other chips usually will pass at the very first test, so the
1183            workaround shouldn't have any effect on them. */
1184         for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1185                 ;
1186
1187         OUTPLL(HTOTAL_CNTL, 0);
1188
1189         /* Clear reset & atomic update */
1190         OUTPLLP(PPLL_CNTL, 0,
1191                 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1192
1193         /* We may want some locking ... oh well */
1194         msleep(5);
1195
1196         /* Switch back VCLK source to PPLL */
1197         OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1198 }
1199
1200 /*
1201  * Timer function for delayed LVDS panel power up/down
1202  */
1203 static void radeon_lvds_timer_func(unsigned long data)
1204 {
1205         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1206
1207         radeon_fifo_wait(3);
1208
1209         OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1210         if (rinfo->pending_pixclks_cntl) {
1211                 OUTPLL(PIXCLKS_CNTL, rinfo->pending_pixclks_cntl);
1212                 rinfo->pending_pixclks_cntl = 0;
1213         }
1214 }
1215
1216 /*
1217  * Apply a video mode. This will apply the whole register set, including
1218  * the PLL registers, to the card
1219  */
1220 static void radeon_write_mode (struct radeonfb_info *rinfo,
1221                                struct radeon_regs *mode)
1222 {
1223         int i;
1224         int primary_mon = PRIMARY_MONITOR(rinfo);
1225
1226         if (nomodeset)
1227                 return;
1228
1229         del_timer_sync(&rinfo->lvds_timer);
1230
1231         radeon_screen_blank(rinfo, VESA_POWERDOWN);
1232
1233         radeon_fifo_wait(31);
1234         for (i=0; i<10; i++)
1235                 OUTREG(common_regs[i].reg, common_regs[i].val);
1236
1237         /* Apply surface registers */
1238         for (i=0; i<8; i++) {
1239                 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1240                 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1241                 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1242         }
1243
1244         OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1245         OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1246                 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1247         OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1248         OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1249         OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1250         OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1251         OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1252         OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1253         OUTREG(CRTC_OFFSET, 0);
1254         OUTREG(CRTC_OFFSET_CNTL, 0);
1255         OUTREG(CRTC_PITCH, mode->crtc_pitch);
1256         OUTREG(SURFACE_CNTL, mode->surface_cntl);
1257
1258         radeon_write_pll_regs(rinfo, mode);
1259
1260         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1261                 radeon_fifo_wait(10);
1262                 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1263                 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1264                 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1265                 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1266                 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1267                 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1268                 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1269                 OUTREG(TMDS_CRC, mode->tmds_crc);
1270                 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1271
1272                 if (primary_mon == MT_LCD) {
1273                         unsigned int tmp = INREG(LVDS_GEN_CNTL);
1274
1275                         /* HACK: The backlight control code may have modified init_state.lvds_gen_cntl,
1276                          * so we update ourselves
1277                          */
1278                         mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
1279                         mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
1280
1281                         if ((tmp & (LVDS_ON | LVDS_BLON)) ==
1282                             (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
1283                                 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
1284                         } else {
1285                                 rinfo->pending_pixclks_cntl = INPLL(PIXCLKS_CNTL);
1286                                 if (rinfo->is_mobility || rinfo->is_IGP)
1287                                         OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1288                                 if (!(tmp & (LVDS_ON | LVDS_BLON)))
1289                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl | LVDS_BLON);
1290                                 rinfo->pending_lvds_gen_cntl = mode->lvds_gen_cntl;
1291                                 mod_timer(&rinfo->lvds_timer,
1292                                           jiffies + MS_TO_HZ(rinfo->panel_info.pwr_delay));
1293                         }
1294                 }
1295         }
1296
1297         RTRACE("lvds_gen_cntl: %08x\n", INREG(LVDS_GEN_CNTL));
1298
1299         radeon_screen_blank(rinfo, VESA_NO_BLANKING);
1300
1301         radeon_fifo_wait(2);
1302         OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1303
1304         return;
1305 }
1306
1307 /*
1308  * Calculate the PLL values for a given mode
1309  */
1310 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1311                                  unsigned long freq)
1312 {
1313         const struct {
1314                 int divider;
1315                 int bitvalue;
1316         } *post_div,
1317           post_divs[] = {
1318                 { 1,  0 },
1319                 { 2,  1 },
1320                 { 4,  2 },
1321                 { 8,  3 },
1322                 { 3,  4 },
1323                 { 16, 5 },
1324                 { 6,  6 },
1325                 { 12, 7 },
1326                 { 0,  0 },
1327         };
1328         int fb_div, pll_output_freq = 0;
1329         int uses_dvo = 0;
1330
1331         /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1332          * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1333          * recent than an r(v)100...
1334          */
1335 #if 0
1336         /* XXX I had reports of flicker happening with the cinema display
1337          * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1338          * this case. This could just be a bandwidth calculation issue, I
1339          * haven't implemented the bandwidth code yet, but in the meantime,
1340          * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1341          * I haven't seen a case were were absolutely needed an odd PLL
1342          * divider. I'll find a better fix once I have more infos on the
1343          * real cause of the problem.
1344          */
1345         while (rinfo->has_CRTC2) {
1346                 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1347                 u32 disp_output_cntl;
1348                 int source;
1349
1350                 /* FP2 path not enabled */
1351                 if ((fp2_gen_cntl & FP2_ON) == 0)
1352                         break;
1353                 /* Not all chip revs have the same format for this register,
1354                  * extract the source selection
1355                  */
1356                 if (rinfo->family == CHIP_FAMILY_R200 ||
1357                     rinfo->family == CHIP_FAMILY_R300 ||
1358                     rinfo->family == CHIP_FAMILY_R350 ||
1359                     rinfo->family == CHIP_FAMILY_RV350) {
1360                         source = (fp2_gen_cntl >> 10) & 0x3;
1361                         /* sourced from transform unit, check for transform unit
1362                          * own source
1363                          */
1364                         if (source == 3) {
1365                                 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1366                                 source = (disp_output_cntl >> 12) & 0x3;
1367                         }
1368                 } else
1369                         source = (fp2_gen_cntl >> 13) & 0x1;
1370                 /* sourced from CRTC2 -> exit */
1371                 if (source == 1)
1372                         break;
1373
1374                 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1375                 uses_dvo = 1;
1376                 break;
1377         }
1378 #else
1379         uses_dvo = 1;
1380 #endif
1381         if (freq > rinfo->pll.ppll_max)
1382                 freq = rinfo->pll.ppll_max;
1383         if (freq*12 < rinfo->pll.ppll_min)
1384                 freq = rinfo->pll.ppll_min / 12;
1385
1386         for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1387                 pll_output_freq = post_div->divider * freq;
1388                 /* If we output to the DVO port (external TMDS), we don't allow an
1389                  * odd PLL divider as those aren't supported on this path
1390                  */
1391                 if (uses_dvo && (post_div->divider & 1))
1392                         continue;
1393                 if (pll_output_freq >= rinfo->pll.ppll_min  &&
1394                     pll_output_freq <= rinfo->pll.ppll_max)
1395                         break;
1396         }
1397
1398         fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1399                                   rinfo->pll.ref_clk);
1400         regs->ppll_ref_div = rinfo->pll.ref_div;
1401         regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1402
1403         RTRACE("post div = 0x%x\n", post_div->bitvalue);
1404         RTRACE("fb_div = 0x%x\n", fb_div);
1405         RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1406 }
1407
1408 int radeonfb_set_par(struct fb_info *info)
1409 {
1410         struct radeonfb_info *rinfo = info->par;
1411         struct fb_var_screeninfo *mode = &info->var;
1412         struct radeon_regs *newmode;
1413         int hTotal, vTotal, hSyncStart, hSyncEnd,
1414             hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1415         u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1416         u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1417         u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1418         int i, freq;
1419         int format = 0;
1420         int nopllcalc = 0;
1421         int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1422         int primary_mon = PRIMARY_MONITOR(rinfo);
1423         int depth = var_to_depth(mode);
1424
1425         newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1426         if (!newmode)
1427                 return -ENOMEM;
1428
1429         /* We always want engine to be idle on a mode switch, even
1430          * if we won't actually change the mode
1431          */
1432         radeon_engine_idle();
1433
1434         hSyncStart = mode->xres + mode->right_margin;
1435         hSyncEnd = hSyncStart + mode->hsync_len;
1436         hTotal = hSyncEnd + mode->left_margin;
1437
1438         vSyncStart = mode->yres + mode->lower_margin;
1439         vSyncEnd = vSyncStart + mode->vsync_len;
1440         vTotal = vSyncEnd + mode->upper_margin;
1441         pixClock = mode->pixclock;
1442
1443         sync = mode->sync;
1444         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1445         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1446
1447         if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1448                 if (rinfo->panel_info.xres < mode->xres)
1449                         mode->xres = rinfo->panel_info.xres;
1450                 if (rinfo->panel_info.yres < mode->yres)
1451                         mode->yres = rinfo->panel_info.yres;
1452
1453                 hTotal = mode->xres + rinfo->panel_info.hblank;
1454                 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1455                 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1456
1457                 vTotal = mode->yres + rinfo->panel_info.vblank;
1458                 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1459                 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1460
1461                 h_sync_pol = !rinfo->panel_info.hAct_high;
1462                 v_sync_pol = !rinfo->panel_info.vAct_high;
1463
1464                 pixClock = 100000000 / rinfo->panel_info.clock;
1465
1466                 if (rinfo->panel_info.use_bios_dividers) {
1467                         nopllcalc = 1;
1468                         newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1469                                 (rinfo->panel_info.post_divider << 16);
1470                         newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1471                 }
1472         }
1473         dotClock = 1000000000 / pixClock;
1474         freq = dotClock / 10; /* x100 */
1475
1476         RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1477                 hSyncStart, hSyncEnd, hTotal);
1478         RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1479                 vSyncStart, vSyncEnd, vTotal);
1480
1481         hsync_wid = (hSyncEnd - hSyncStart) / 8;
1482         vsync_wid = vSyncEnd - vSyncStart;
1483         if (hsync_wid == 0)
1484                 hsync_wid = 1;
1485         else if (hsync_wid > 0x3f)      /* max */
1486                 hsync_wid = 0x3f;
1487
1488         if (vsync_wid == 0)
1489                 vsync_wid = 1;
1490         else if (vsync_wid > 0x1f)      /* max */
1491                 vsync_wid = 0x1f;
1492
1493         hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1494         vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1495
1496         cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1497
1498         format = radeon_get_dstbpp(depth);
1499         bytpp = mode->bits_per_pixel >> 3;
1500
1501         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1502                 hsync_fudge = hsync_fudge_fp[format-1];
1503         else
1504                 hsync_fudge = hsync_adj_tab[format-1];
1505
1506         hsync_start = hSyncStart - 8 + hsync_fudge;
1507
1508         newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1509                                 (format << 8);
1510
1511         /* Clear auto-center etc... */
1512         newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1513         newmode->crtc_more_cntl &= 0xfffffff0;
1514
1515         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1516                 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1517                 if (mirror)
1518                         newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1519
1520                 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1521                                            CRTC_INTERLACE_EN);
1522         } else {
1523                 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1524                                         CRTC_CRT_ON;
1525         }
1526
1527         newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1528                            DAC_8BIT_EN;
1529
1530         newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1531                                      (((mode->xres / 8) - 1) << 16));
1532
1533         newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1534                                         (hsync_wid << 16) | (h_sync_pol << 23));
1535
1536         newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1537                                     ((mode->yres - 1) << 16);
1538
1539         newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1540                                          (vsync_wid << 16) | (v_sync_pol  << 23));
1541
1542         if (!radeon_accel_disabled()) {
1543                 /* We first calculate the engine pitch */
1544                 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1545                                 & ~(0x3f)) >> 6;
1546
1547                 /* Then, re-multiply it to get the CRTC pitch */
1548                 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1549         } else
1550                 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1551
1552         newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1553
1554         /*
1555          * It looks like recent chips have a problem with SURFACE_CNTL,
1556          * setting SURF_TRANSLATION_DIS completely disables the
1557          * swapper as well, so we leave it unset now.
1558          */
1559         newmode->surface_cntl = 0;
1560
1561 #if defined(__BIG_ENDIAN)
1562
1563         /* Setup swapping on both apertures, though we currently
1564          * only use aperture 0, enabling swapper on aperture 1
1565          * won't harm
1566          */
1567         switch (mode->bits_per_pixel) {
1568                 case 16:
1569                         newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1570                         newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1571                         break;
1572                 case 24:
1573                 case 32:
1574                         newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1575                         newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1576                         break;
1577         }
1578 #endif
1579
1580         /* Clear surface registers */
1581         for (i=0; i<8; i++) {
1582                 newmode->surf_lower_bound[i] = 0;
1583                 newmode->surf_upper_bound[i] = 0x1f;
1584                 newmode->surf_info[i] = 0;
1585         }
1586
1587         RTRACE("h_total_disp = 0x%x\t   hsync_strt_wid = 0x%x\n",
1588                 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1589         RTRACE("v_total_disp = 0x%x\t   vsync_strt_wid = 0x%x\n",
1590                 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1591
1592         rinfo->bpp = mode->bits_per_pixel;
1593         rinfo->depth = depth;
1594
1595         RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1596         RTRACE("freq = %lu\n", (unsigned long)freq);
1597
1598         if (!nopllcalc)
1599                 radeon_calc_pll_regs(rinfo, newmode, freq);
1600
1601         newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1602
1603         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1604                 unsigned int hRatio, vRatio;
1605
1606                 if (mode->xres > rinfo->panel_info.xres)
1607                         mode->xres = rinfo->panel_info.xres;
1608                 if (mode->yres > rinfo->panel_info.yres)
1609                         mode->yres = rinfo->panel_info.yres;
1610
1611                 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1612                                            << HORZ_PANEL_SHIFT);
1613                 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1614                                            << VERT_PANEL_SHIFT);
1615
1616                 if (mode->xres != rinfo->panel_info.xres) {
1617                         hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1618                                            rinfo->panel_info.xres);
1619                         newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1620                                                    (newmode->fp_horz_stretch &
1621                                                     (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1622                                                      HORZ_AUTO_RATIO_INC)));
1623                         newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1624                                                     HORZ_STRETCH_ENABLE);
1625                 }
1626                 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1627
1628                 if (mode->yres != rinfo->panel_info.yres) {
1629                         vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1630                                            rinfo->panel_info.yres);
1631                         newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1632                                                    (newmode->fp_vert_stretch &
1633                                                    (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1634                         newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1635                                                     VERT_STRETCH_ENABLE);
1636                 }
1637                 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1638
1639                 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1640                                        ~(FP_SEL_CRTC2 |
1641                                          FP_RMX_HVSYNC_CONTROL_EN |
1642                                          FP_DFP_SYNC_SEL |
1643                                          FP_CRT_SYNC_SEL |
1644                                          FP_CRTC_LOCK_8DOT |
1645                                          FP_USE_SHADOW_EN |
1646                                          FP_CRTC_USE_SHADOW_VEND |
1647                                          FP_CRT_SYNC_ALT));
1648
1649                 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1650                                         FP_CRTC_DONT_SHADOW_HEND);
1651
1652                 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1653                 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1654                 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1655                 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1656
1657                 if (primary_mon == MT_LCD) {
1658                         newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1659                         newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1660                 } else {
1661                         /* DFP */
1662                         newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1663                         newmode->tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | TMDS_ICHCSEL) &
1664                                                          ~(TMDS_PLLRST);
1665                         /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1666                         if ((rinfo->family == CHIP_FAMILY_R300) ||
1667                             (rinfo->family == CHIP_FAMILY_R350) ||
1668                             (rinfo->family == CHIP_FAMILY_RV350) ||
1669                             (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1670                                 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1671                         else
1672                                 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1673                         newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1674                 }
1675
1676                 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1677                                 (((mode->xres / 8) - 1) << 16));
1678                 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1679                                 ((mode->yres - 1) << 16);
1680                 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1681                                 (hsync_wid << 16) | (h_sync_pol << 23));
1682                 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1683                                 (vsync_wid << 16) | (v_sync_pol  << 23));
1684         }
1685
1686         /* do it! */
1687         if (!rinfo->asleep) {
1688                 radeon_write_mode (rinfo, newmode);
1689                 /* (re)initialize the engine */
1690                 if (!radeon_accel_disabled())
1691                         radeonfb_engine_init (rinfo);
1692
1693         }
1694         /* Update fix */
1695         if (!radeon_accel_disabled())
1696                 info->fix.line_length = rinfo->pitch*64;
1697         else
1698                 info->fix.line_length = mode->xres_virtual
1699                         * ((mode->bits_per_pixel + 1) / 8);
1700         info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1701                 : FB_VISUAL_DIRECTCOLOR;
1702
1703 #ifdef CONFIG_BOOTX_TEXT
1704         /* Update debug text engine */
1705         btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1706                              rinfo->depth, info->fix.line_length);
1707 #endif
1708
1709         kfree(newmode);
1710         return 0;
1711 }
1712
1713
1714
1715 static ssize_t radeonfb_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
1716 {
1717         unsigned long p = *ppos;
1718         struct inode *inode = file->f_dentry->d_inode;
1719         int fbidx = iminor(inode);
1720         struct fb_info *info = registered_fb[fbidx];
1721         struct radeonfb_info *rinfo = info->par;
1722
1723         if (p >= rinfo->mapped_vram)
1724             return 0;
1725         if (count >= rinfo->mapped_vram)
1726             count = rinfo->mapped_vram;
1727         if (count + p > rinfo->mapped_vram)
1728                 count = rinfo->mapped_vram - p;
1729         radeonfb_sync(info);
1730         if (count) {
1731             char *base_addr;
1732
1733             base_addr = info->screen_base;
1734             count -= copy_to_user(buf, base_addr+p, count);
1735             if (!count)
1736                 return -EFAULT;
1737             *ppos += count;
1738         }
1739         return count;
1740 }
1741
1742 static ssize_t radeonfb_write(struct file *file, const char __user *buf, size_t count,
1743                               loff_t *ppos)
1744 {
1745         unsigned long p = *ppos;
1746         struct inode *inode = file->f_dentry->d_inode;
1747         int fbidx = iminor(inode);
1748         struct fb_info *info = registered_fb[fbidx];
1749         struct radeonfb_info *rinfo = info->par;
1750         int err;
1751
1752         if (p > rinfo->mapped_vram)
1753             return -ENOSPC;
1754         if (count >= rinfo->mapped_vram)
1755             count = rinfo->mapped_vram;
1756         err = 0;
1757         if (count + p > rinfo->mapped_vram) {
1758             count = rinfo->mapped_vram - p;
1759             err = -ENOSPC;
1760         }
1761         radeonfb_sync(info);
1762         if (count) {
1763             char *base_addr;
1764
1765             base_addr = info->screen_base;
1766             count -= copy_from_user(base_addr+p, buf, count);
1767             *ppos += count;
1768             err = -EFAULT;
1769         }
1770         if (count)
1771                 return count;
1772         return err;
1773 }
1774
1775
1776 static struct fb_ops radeonfb_ops = {
1777         .owner                  = THIS_MODULE,
1778         .fb_check_var           = radeonfb_check_var,
1779         .fb_set_par             = radeonfb_set_par,
1780         .fb_setcolreg           = radeonfb_setcolreg,
1781         .fb_pan_display         = radeonfb_pan_display,
1782         .fb_blank               = radeonfb_blank,
1783         .fb_ioctl               = radeonfb_ioctl,
1784         .fb_sync                = radeonfb_sync,
1785         .fb_fillrect            = radeonfb_fillrect,
1786         .fb_copyarea            = radeonfb_copyarea,
1787         .fb_imageblit           = radeonfb_imageblit,
1788         .fb_read                = radeonfb_read,
1789         .fb_write               = radeonfb_write,
1790         .fb_cursor              = soft_cursor,
1791 };
1792
1793
1794 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1795 {
1796         struct fb_info *info = rinfo->info;
1797
1798         info->currcon = -1;
1799         info->par = rinfo;
1800         info->pseudo_palette = rinfo->pseudo_palette;
1801         info->flags = FBINFO_FLAG_DEFAULT;
1802         info->fbops = &radeonfb_ops;
1803         info->screen_base = (char *)rinfo->fb_base;
1804
1805         /* Fill fix common fields */
1806         strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1807         info->fix.smem_start = rinfo->fb_base_phys;
1808         info->fix.smem_len = rinfo->video_ram;
1809         info->fix.type = FB_TYPE_PACKED_PIXELS;
1810         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1811         info->fix.xpanstep = 8;
1812         info->fix.ypanstep = 1;
1813         info->fix.ywrapstep = 0;
1814         info->fix.type_aux = 0;
1815         info->fix.mmio_start = rinfo->mmio_base_phys;
1816         info->fix.mmio_len = RADEON_REGSIZE;
1817         if (radeon_accel_disabled())
1818                 info->fix.accel = FB_ACCEL_NONE;
1819         else
1820                 info->fix.accel = FB_ACCEL_ATI_RADEON;
1821
1822         fb_alloc_cmap(&info->cmap, 256, 0);
1823
1824         if (radeon_accel_disabled())
1825                 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1826         else
1827                 info->var.accel_flags |= FB_ACCELF_TEXT;
1828
1829         return 0;
1830 }
1831
1832
1833 #ifdef CONFIG_PMAC_BACKLIGHT
1834
1835 /* TODO: Dbl check these tables, we don't go up to full ON backlight
1836  * in these, possibly because we noticed MacOS doesn't, but I'd prefer
1837  * having some more official numbers from ATI
1838  */
1839 static int backlight_conv_m6[] = {
1840         0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
1841         0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
1842 };
1843 static int backlight_conv_m7[] = {
1844         0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
1845         0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
1846 };
1847
1848 #define BACKLIGHT_LVDS_OFF
1849 #undef BACKLIGHT_DAC_OFF
1850
1851 /* We turn off the LCD completely instead of just dimming the backlight.
1852  * This provides some greater power saving and the display is useless
1853  * without backlight anyway.
1854  */
1855 static int radeon_set_backlight_enable(int on, int level, void *data)
1856 {
1857         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1858         unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1859         unsigned long tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
1860         int* conv_table;
1861
1862         if (rinfo->mon1_type != MT_LCD)
1863                 return 0;
1864
1865         /* Pardon me for that hack... maybe some day we can figure
1866          * out in what direction backlight should work on a given
1867          * panel ?
1868          */
1869         if ((rinfo->family == CHIP_FAMILY_RV200 ||
1870              rinfo->family == CHIP_FAMILY_RV250 ||
1871              rinfo->family == CHIP_FAMILY_RV280 ||
1872              rinfo->family == CHIP_FAMILY_RV350) &&
1873             !machine_is_compatible("PowerBook4,3") &&
1874             !machine_is_compatible("PowerBook6,3") &&
1875             !machine_is_compatible("PowerBook6,5"))
1876                 conv_table = backlight_conv_m7;
1877         else
1878                 conv_table = backlight_conv_m6;
1879
1880         del_timer_sync(&rinfo->lvds_timer);
1881
1882         lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
1883         radeon_fifo_wait(3);
1884         if (on && (level > BACKLIGHT_OFF)) {
1885                 lvds_gen_cntl |= LVDS_DIGON;
1886                 if (!(lvds_gen_cntl & LVDS_ON)) {
1887                         lvds_gen_cntl &= ~LVDS_BLON;
1888                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1889                         (void)INREG(LVDS_GEN_CNTL);
1890                         mdelay(rinfo->panel_info.pwr_delay);/* OUCH !!! FIXME */
1891                         lvds_gen_cntl |= LVDS_BLON;
1892                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1893                 }
1894                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1895                 lvds_gen_cntl |= (conv_table[level] <<
1896                                   LVDS_BL_MOD_LEVEL_SHIFT);
1897                 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
1898                 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
1899         } else {
1900                 /* Asic bug, when turning off LVDS_ON, we have to make sure
1901                    RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1902                 */
1903                 if (rinfo->is_mobility || rinfo->is_IGP)
1904                         OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1905                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1906                 lvds_gen_cntl |= (conv_table[0] <<
1907                                   LVDS_BL_MOD_LEVEL_SHIFT);
1908                 lvds_gen_cntl |= LVDS_DISPLAY_DIS | LVDS_BLON;
1909                 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1910                 mdelay(rinfo->panel_info.pwr_delay);/* OUCH !!! FIXME */
1911                 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
1912         }
1913
1914         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1915         if (rinfo->is_mobility || rinfo->is_IGP)
1916                 OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
1917         rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1918         rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
1919
1920         return 0;
1921 }
1922
1923
1924 static int radeon_set_backlight_level(int level, void *data)
1925 {
1926         return radeon_set_backlight_enable(1, level, data);
1927 }
1928 #endif /* CONFIG_PMAC_BACKLIGHT */
1929
1930
1931 /*
1932  * This reconfigure the card's internal memory map. In theory, we'd like
1933  * to setup the card's memory at the same address as it's PCI bus address,
1934  * and the AGP aperture right after that so that system RAM on 32 bits
1935  * machines at least, is directly accessible. However, doing so would
1936  * conflict with the current XFree drivers...
1937  * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1938  * on the proper way to set this up and duplicate this here. In the meantime,
1939  * I put the card's memory at 0 in card space and AGP at some random high
1940  * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1941  */
1942 #ifdef CONFIG_PPC_OF
1943 #undef SET_MC_FB_FROM_APERTURE
1944 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1945 {
1946         u32 save_crtc_gen_cntl, save_crtc2_gen_cntl;
1947         u32 save_crtc_ext_cntl;
1948         u32 aper_base, aper_size;
1949         u32 agp_base;
1950
1951         /* First, we disable display to avoid interfering */
1952         if (rinfo->has_CRTC2) {
1953                 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1954                 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1955         }
1956         save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1957         save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1958
1959         OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1960         OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1961         mdelay(100);
1962
1963         aper_base = INREG(CONFIG_APER_0_BASE);
1964         aper_size = INREG(CONFIG_APER_SIZE);
1965
1966 #ifdef SET_MC_FB_FROM_APERTURE
1967         /* Set framebuffer to be at the same address as set in PCI BAR */
1968         OUTREG(MC_FB_LOCATION,
1969                 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1970         rinfo->fb_local_base = aper_base;
1971 #else
1972         OUTREG(MC_FB_LOCATION, 0x7fff0000);
1973         rinfo->fb_local_base = 0;
1974 #endif
1975         agp_base = aper_base + aper_size;
1976         if (agp_base & 0xf0000000)
1977                 agp_base = (aper_base | 0x0fffffff) + 1;
1978
1979         /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1980          * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1981          * always the case on PPCs afaik.
1982          */
1983 #ifdef SET_MC_FB_FROM_APERTURE
1984         OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1985 #else
1986         OUTREG(MC_AGP_LOCATION, 0xffffe000);
1987 #endif
1988
1989         /* Fixup the display base addresses & engine offsets while we
1990          * are at it as well
1991          */
1992 #ifdef SET_MC_FB_FROM_APERTURE
1993         OUTREG(DISPLAY_BASE_ADDR, aper_base);
1994         if (rinfo->has_CRTC2)
1995                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1996 #else
1997         OUTREG(DISPLAY_BASE_ADDR, 0);
1998         if (rinfo->has_CRTC2)
1999                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
2000 #endif
2001         mdelay(100);
2002
2003         /* Restore display settings */
2004         OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
2005         OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
2006         if (rinfo->has_CRTC2)
2007                 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
2008
2009         RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
2010                 aper_base,
2011                 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2012                 0xffff0000 | (agp_base >> 16));
2013 }
2014 #endif /* CONFIG_PPC_OF */
2015
2016
2017 /*
2018  * Sysfs
2019  */
2020
2021 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2022 {
2023         if (off > EDID_LENGTH)
2024                 return 0;
2025
2026         if (off + count > EDID_LENGTH)
2027                 count = EDID_LENGTH - off;
2028
2029         memcpy(buf, edid + off, count);
2030
2031         return count;
2032 }
2033
2034
2035 static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2036 {
2037         struct device *dev = container_of(kobj, struct device, kobj);
2038         struct pci_dev *pdev = to_pci_dev(dev);
2039         struct fb_info *info = pci_get_drvdata(pdev);
2040         struct radeonfb_info *rinfo = info->par;
2041
2042         return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2043 }
2044
2045
2046 static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2047 {
2048         struct device *dev = container_of(kobj, struct device, kobj);
2049         struct pci_dev *pdev = to_pci_dev(dev);
2050         struct fb_info *info = pci_get_drvdata(pdev);
2051         struct radeonfb_info *rinfo = info->par;
2052
2053         return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2054 }
2055
2056 static struct bin_attribute edid1_attr = {
2057         .attr   = {
2058                 .name   = "edid1",
2059                 .owner  = THIS_MODULE,
2060                 .mode   = 0444,
2061         },
2062         .size   = EDID_LENGTH,
2063         .read   = radeon_show_edid1,
2064 };
2065
2066 static struct bin_attribute edid2_attr = {
2067         .attr   = {
2068                 .name   = "edid2",
2069                 .owner  = THIS_MODULE,
2070                 .mode   = 0444,
2071         },
2072         .size   = EDID_LENGTH,
2073         .read   = radeon_show_edid2,
2074 };
2075
2076
2077 static int radeonfb_pci_register (struct pci_dev *pdev,
2078                                   const struct pci_device_id *ent)
2079 {
2080         struct fb_info *info;
2081         struct radeonfb_info *rinfo;
2082         u32 tmp;
2083
2084         RTRACE("radeonfb_pci_register BEGIN\n");
2085
2086         /* Enable device in PCI config */
2087         if (pci_enable_device(pdev) != 0) {
2088                 printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
2089                 return -ENODEV;
2090         }
2091
2092         info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2093         if (!info) {
2094                 printk (KERN_ERR "radeonfb: could not allocate memory\n");
2095                 return -ENODEV;
2096         }
2097         rinfo = info->par;
2098         rinfo->info = info;
2099         rinfo->pdev = pdev;
2100
2101         spin_lock_init(&rinfo->reg_lock);
2102         init_timer(&rinfo->lvds_timer);
2103         rinfo->lvds_timer.function = radeon_lvds_timer_func;
2104         rinfo->lvds_timer.data = (unsigned long)rinfo;
2105
2106         strcpy(rinfo->name, "ATI Radeon XX ");
2107         rinfo->name[11] = ent->device >> 8;
2108         rinfo->name[12] = ent->device & 0xFF;
2109         rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2110         rinfo->chipset = pdev->device;
2111         rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2112         rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2113         rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2114
2115         /* Set base addrs */
2116         rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2117         rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2118
2119         /* request the mem regions */
2120         if (!request_mem_region (rinfo->fb_base_phys,
2121                                  pci_resource_len(pdev, 0), "radeonfb")) {
2122                 printk (KERN_ERR "radeonfb: cannot reserve FB region\n");
2123                 goto free_rinfo;
2124         }
2125
2126         if (!request_mem_region (rinfo->mmio_base_phys,
2127                                  pci_resource_len(pdev, 2), "radeonfb")) {
2128                 printk (KERN_ERR "radeonfb: cannot reserve MMIO region\n");
2129                 goto release_fb;
2130         }
2131
2132         /* map the regions */
2133         rinfo->mmio_base = (unsigned long) ioremap (rinfo->mmio_base_phys, RADEON_REGSIZE);
2134         if (!rinfo->mmio_base) {
2135                 printk (KERN_ERR "radeonfb: cannot map MMIO\n");
2136                 goto release_mmio;
2137         }
2138
2139         /* On PPC, the firmware sets up a memory mapping that tends
2140          * to cause lockups when enabling the engine. We reconfigure
2141          * the card internal memory mappings properly
2142          */
2143 #ifdef CONFIG_PPC_OF
2144         fixup_memory_mappings(rinfo);
2145 #else
2146         rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2147 #endif /* CONFIG_PPC_OF */
2148
2149         /* framebuffer size */
2150         if ((rinfo->family == CHIP_FAMILY_RS100) ||
2151             (rinfo->family == CHIP_FAMILY_RS200) ||
2152             (rinfo->family == CHIP_FAMILY_RS300)) {
2153           u32 tom = INREG(NB_TOM);
2154           tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2155
2156                 radeon_fifo_wait(6);
2157           OUTREG(MC_FB_LOCATION, tom);
2158           OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2159           OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2160           OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2161
2162           /* This is supposed to fix the crtc2 noise problem. */
2163           OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2164
2165           if ((rinfo->family == CHIP_FAMILY_RS100) ||
2166               (rinfo->family == CHIP_FAMILY_RS200)) {
2167              /* This is to workaround the asic bug for RMX, some versions
2168                 of BIOS dosen't have this register initialized correctly.
2169              */
2170              OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2171                      ~CRTC_H_CUTOFF_ACTIVE_EN);
2172           }
2173         } else {
2174           tmp = INREG(CONFIG_MEMSIZE);
2175         }
2176
2177         /* mem size is bits [28:0], mask off the rest */
2178         rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2179
2180         /* ram type */
2181         tmp = INREG(MEM_SDRAM_MODE_REG);
2182         switch ((MEM_CFG_TYPE & tmp) >> 30) {
2183         case 0:
2184                 /* SDR SGRAM (2:1) */
2185                 strcpy(rinfo->ram_type, "SDR SGRAM");
2186                 rinfo->ram.ml = 4;
2187                 rinfo->ram.mb = 4;
2188                 rinfo->ram.trcd = 1;
2189                 rinfo->ram.trp = 2;
2190                 rinfo->ram.twr = 1;
2191                 rinfo->ram.cl = 2;
2192                 rinfo->ram.loop_latency = 16;
2193                 rinfo->ram.rloop = 16;
2194                 break;
2195         case 1:
2196                 /* DDR SGRAM */
2197                 strcpy(rinfo->ram_type, "DDR SGRAM");
2198                 rinfo->ram.ml = 4;
2199                 rinfo->ram.mb = 4;
2200                 rinfo->ram.trcd = 3;
2201                 rinfo->ram.trp = 3;
2202                 rinfo->ram.twr = 2;
2203                 rinfo->ram.cl = 3;
2204                 rinfo->ram.tr2w = 1;
2205                 rinfo->ram.loop_latency = 16;
2206                 rinfo->ram.rloop = 16;
2207                 break;
2208         default:
2209                 /* 64-bit SDR SGRAM */
2210                 strcpy(rinfo->ram_type, "SDR SGRAM 64");
2211                 rinfo->ram.ml = 4;
2212                 rinfo->ram.mb = 8;
2213                 rinfo->ram.trcd = 3;
2214                 rinfo->ram.trp = 3;
2215                 rinfo->ram.twr = 1;
2216                 rinfo->ram.cl = 3;
2217                 rinfo->ram.tr2w = 1;
2218                 rinfo->ram.loop_latency = 17;
2219                 rinfo->ram.rloop = 17;
2220                 break;
2221         }
2222
2223         /*
2224          * Hack to get around some busted production M6's
2225          * reporting no ram
2226          */
2227         if (rinfo->video_ram == 0) {
2228                 switch (pdev->device) {
2229                 case PCI_CHIP_RADEON_LY:
2230                 case PCI_CHIP_RADEON_LZ:
2231                         rinfo->video_ram = 8192 * 1024;
2232                         break;
2233                 default:
2234                         break;
2235                 }
2236         }
2237
2238         RTRACE("radeonfb: probed %s %ldk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
2239
2240         rinfo->mapped_vram = MAX_MAPPED_VRAM;
2241         if (rinfo->video_ram < rinfo->mapped_vram)
2242                 rinfo->mapped_vram = rinfo->video_ram;
2243         for (;;) {
2244                 rinfo->fb_base = (unsigned long) ioremap (rinfo->fb_base_phys,
2245                                                           rinfo->mapped_vram);
2246                 if (rinfo->fb_base == 0 && rinfo->mapped_vram > MIN_MAPPED_VRAM) {
2247                         rinfo->mapped_vram /= 2;
2248                         continue;
2249                 }
2250                 memset_io(rinfo->fb_base, 0, rinfo->mapped_vram);
2251                 break;
2252         }
2253
2254         if (!rinfo->fb_base) {
2255                 printk (KERN_ERR "radeonfb: cannot map FB\n");
2256                 goto unmap_rom;
2257         }
2258
2259         RTRACE("radeonfb: mapped %ldk videoram\n", rinfo->mapped_vram/1024);
2260
2261
2262         /* Argh. Scary arch !!! */
2263 #ifdef CONFIG_PPC64
2264         rinfo->fb_base = IO_TOKEN_TO_ADDR(rinfo->fb_base);
2265 #endif
2266
2267         /*
2268          * Check for required workaround for PLL accesses
2269          */
2270         rinfo->R300_cg_workaround = (rinfo->family == CHIP_FAMILY_R300 &&
2271                                      (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2272                                      == CFG_ATI_REV_A11);
2273
2274         /*
2275          * Map the BIOS ROM if any and retreive PLL parameters from
2276          * either BIOS or Open Firmware
2277          */
2278         radeon_map_ROM(rinfo, pdev);
2279
2280         /*
2281          * On x86, the primary display on laptop may have it's BIOS
2282          * ROM elsewhere, try to locate it at the legacy memory hole.
2283          * We probably need to make sure this is the primary dispay,
2284          * but that is difficult without some arch support.
2285          */
2286 #ifdef __i386__
2287         if (rinfo->bios_seg == NULL)
2288                 radeon_find_mem_vbios(rinfo);
2289 #endif /* __i386__ */
2290
2291         /* Get informations about the board's PLL */
2292         radeon_get_pllinfo(rinfo);
2293
2294 #ifdef CONFIG_FB_RADEON_I2C
2295         /* Register I2C bus */
2296         radeon_create_i2c_busses(rinfo);
2297 #endif
2298
2299         /* set all the vital stuff */
2300         radeon_set_fbinfo (rinfo);
2301
2302         /* Probe screen types */
2303         radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2304
2305         /* Build mode list, check out panel native model */
2306         radeon_check_modes(rinfo, mode_option);
2307
2308         /* Register some sysfs stuff (should be done better) */
2309         if (rinfo->mon1_EDID)
2310                 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2311         if (rinfo->mon2_EDID)
2312                 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2313
2314         /* save current mode regs before we switch into the new one
2315          * so we can restore this upon __exit
2316          */
2317         radeon_save_state (rinfo, &rinfo->init_state);
2318
2319         pci_set_drvdata(pdev, info);
2320
2321         /* Enable PM on mobility chips */
2322         if (rinfo->is_mobility) {
2323                 /* Find PM registers in config space */
2324                 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
2325                 /* Enable dynamic PM of chip clocks */
2326                 radeon_pm_enable_dynamic_mode(rinfo);
2327                 printk("radeonfb: Power Management enabled for Mobility chipsets\n");
2328         }
2329
2330         if (register_framebuffer(info) < 0) {
2331                 printk (KERN_ERR "radeonfb: could not register framebuffer\n");
2332                 goto unmap_fb;
2333         }
2334
2335 #ifdef CONFIG_MTRR
2336         rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2337                                                  rinfo->video_ram,
2338                                                  MTRR_TYPE_WRCOMB, 1);
2339 #endif
2340
2341 #ifdef CONFIG_PMAC_BACKLIGHT
2342         if (rinfo->mon1_type == MT_LCD) {
2343                 register_backlight_controller(&radeon_backlight_controller,
2344                                               rinfo, "ati");
2345                 register_backlight_controller(&radeon_backlight_controller,
2346                                               rinfo, "mnca");
2347         }
2348 #endif
2349
2350         printk ("radeonfb: %s %s %ld MB\n", rinfo->name, rinfo->ram_type,
2351                 (rinfo->video_ram/(1024*1024)));
2352
2353         if (rinfo->bios_seg)
2354                 radeon_unmap_ROM(rinfo, pdev);
2355         RTRACE("radeonfb_pci_register END\n");
2356
2357         return 0;
2358 unmap_fb:
2359         iounmap ((void*)rinfo->fb_base);
2360 unmap_rom:
2361         if (rinfo->mon1_EDID)
2362             kfree(rinfo->mon1_EDID);
2363         if (rinfo->mon2_EDID)
2364             kfree(rinfo->mon2_EDID);
2365         if (rinfo->mon1_modedb)
2366                 fb_destroy_modedb(rinfo->mon1_modedb);
2367 #ifdef CONFIG_FB_RADEON_I2C
2368         radeon_delete_i2c_busses(rinfo);
2369 #endif
2370         if (rinfo->bios_seg)
2371                 radeon_unmap_ROM(rinfo, pdev);
2372         iounmap ((void*)rinfo->mmio_base);
2373 release_mmio:
2374         release_mem_region (rinfo->mmio_base_phys,
2375                             pci_resource_len(pdev, 2));
2376 release_fb:
2377         release_mem_region (rinfo->fb_base_phys,
2378                             pci_resource_len(pdev, 0));
2379 free_rinfo:
2380         framebuffer_release(info);
2381         return -ENODEV;
2382 }
2383
2384
2385
2386 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2387 {
2388         struct fb_info *info = pci_get_drvdata(pdev);
2389         struct radeonfb_info *rinfo = info->par;
2390
2391         if (!rinfo)
2392                 return;
2393
2394         /* restore original state
2395          *
2396          * Doesn't quite work yet, possibly because of the PPC hacking
2397          * I do on startup, disable for now. --BenH
2398          */
2399         radeon_write_mode (rinfo, &rinfo->init_state);
2400
2401         del_timer_sync(&rinfo->lvds_timer);
2402
2403 #ifdef CONFIG_MTRR
2404         if (rinfo->mtrr_hdl >= 0)
2405                 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2406 #endif
2407
2408         unregister_framebuffer(info);
2409
2410         iounmap ((void*)rinfo->mmio_base);
2411         iounmap ((void*)rinfo->fb_base);
2412
2413         release_mem_region (rinfo->mmio_base_phys,
2414                             pci_resource_len(pdev, 2));
2415         release_mem_region (rinfo->fb_base_phys,
2416                             pci_resource_len(pdev, 0));
2417
2418         if (rinfo->mon1_EDID)
2419                 kfree(rinfo->mon1_EDID);
2420         if (rinfo->mon2_EDID)
2421                 kfree(rinfo->mon2_EDID);
2422         if (rinfo->mon1_modedb)
2423                 fb_destroy_modedb(rinfo->mon1_modedb);
2424 #ifdef CONFIG_FB_RADEON_I2C
2425         radeon_delete_i2c_busses(rinfo);
2426 #endif
2427         framebuffer_release(info);
2428 }
2429
2430
2431 static struct pci_driver radeonfb_driver = {
2432         .name           = "radeonfb",
2433         .id_table       = radeonfb_pci_table,
2434         .probe          = radeonfb_pci_register,
2435         .remove         = __devexit_p(radeonfb_pci_unregister),
2436 #ifdef CONFIG_PM
2437         .suspend        = radeonfb_pci_suspend,
2438         .resume         = radeonfb_pci_resume,
2439 #endif /* CONFIG_PM */
2440 };
2441
2442
2443 int __init radeonfb_init (void)
2444 {
2445         radeonfb_noaccel = noaccel;
2446         return pci_module_init (&radeonfb_driver);
2447 }
2448
2449
2450 void __exit radeonfb_exit (void)
2451 {
2452         pci_unregister_driver (&radeonfb_driver);
2453 }
2454
2455 int __init radeonfb_setup (char *options)
2456 {
2457         char *this_opt;
2458
2459         if (!options || !*options)
2460                 return 0;
2461
2462         while ((this_opt = strsep (&options, ",")) != NULL) {
2463                 if (!*this_opt)
2464                         continue;
2465
2466                 if (!strncmp(this_opt, "noaccel", 7)) {
2467                         noaccel = radeonfb_noaccel = 1;
2468                 } else if (!strncmp(this_opt, "mirror", 6)) {
2469                         mirror = 1;
2470                 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2471                         force_dfp = 1;
2472                 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2473                         panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2474 #ifdef CONFIG_MTRR
2475                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2476                         nomtrr = 1;
2477 #endif
2478                 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2479                         nomodeset = 1;
2480                 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2481                         force_measure_pll = 1;
2482                 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2483                         ignore_edid = 1;
2484                 } else
2485                         mode_option = this_opt;
2486         }
2487         return 0;
2488 }
2489
2490
2491 #ifdef MODULE
2492 module_init(radeonfb_init);
2493 module_exit(radeonfb_exit);
2494 #endif
2495
2496 MODULE_AUTHOR("Ani Joshi");
2497 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2498 MODULE_LICENSE("GPL");
2499 module_param(noaccel, bool, 0);
2500 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2501 module_param(nomodeset, bool, 0);
2502 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2503 module_param(mirror, bool, 0);
2504 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2505 module_param(force_dfp, bool, 0);
2506 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2507 module_param(ignore_edid, bool, 0);
2508 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2509 module_param(monitor_layout, charp, 0);
2510 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2511 module_param(force_measure_pll, bool, 0);
2512 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2513 #ifdef CONFIG_MTRR
2514 module_param(nomtrr, bool, 0);
2515 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2516 #endif
2517 module_param(panel_yres, int, 0);
2518 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2519 module_param(mode_option, charp, 0);
2520 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");