2 * drivers/video/aty/radeon_pm.c
4 * Copyright 2003,2004 Ben. Herrenschmidt <benh@kernel.crashing.org>
5 * Copyright 2004 Paul Mackerras <paulus@samba.org>
7 * This is the power management code for ATI radeon chipsets. It contains
8 * some dynamic clock PM enable/disable code similar to what X.org does,
9 * some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
10 * and the necessary bits to re-initialize from scratch a few chips found
11 * on PowerMacs as well. The later could be extended to more platforms
12 * provided the memory controller configuration code be made more generic,
13 * and you can get the proper mode register commands for your RAMs.
14 * Those things may be found in the BIOS image...
19 #include <linux/console.h>
20 #include <linux/agp_backend.h>
22 #ifdef CONFIG_PPC_PMAC
23 #include <asm/processor.h>
25 #include <asm/pmac_feature.h>
28 /* For detecting supported PC laptops */
30 #include <linux/dmi.h>
36 /* This array holds a list of supported PC laptops.
37 * Currently only few IBM models are tested.
38 * If you want to experiment, use dmidecode to find out
39 * vendor and product codes for Your laptop.
41 static struct dmi_system_id __devinitdata radeonfb_dmi_table[] = {
43 /* Reported by George Avrunin <avrunin@math.umass.edu> */
44 .ident = "IBM ThinkPad T40 (2372-9CU)",
46 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
47 DMI_MATCH(DMI_PRODUCT_NAME, "23729CU"),
51 /* Reported by Pete Toscano <pete@verisignlabs.com> */
52 .ident = "IBM ThinkPad R40 (2722-B3G)",
54 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
55 DMI_MATCH(DMI_PRODUCT_NAME, "2722B3G"),
59 /* Reported by Klaus Kurzmann <mok@fluxnetz.de> */
60 .ident = "IBM ThinkPad T40 (2373-25G)",
62 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
63 DMI_MATCH(DMI_PRODUCT_NAME, "237325G"),
67 /* Reported by Antti Andreimann <Antti.Andreimann@mail.ee> */
68 .ident = "IBM ThinkPad T41 (2373-2FG)",
70 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
71 DMI_MATCH(DMI_PRODUCT_NAME, "23732FG"),
75 /* Reported by Antti P Miettinen <apm@brigitte.dna.fi> */
76 .ident = "IBM ThinkPad T40 (2373-4G2)",
78 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
79 DMI_MATCH(DMI_PRODUCT_NAME, "23734G2"),
83 /* Reported by Pete Toscano <pete@verisignlabs.com> */
84 .ident = "IBM ThinkPad T40 (2373-92G)",
86 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
87 DMI_MATCH(DMI_PRODUCT_NAME, "237392G"),
91 /* Reported by Pete Toscano <pete@verisignlabs.com> */
92 .ident = "IBM ThinkPad T40 (2373-8CG)",
94 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
95 DMI_MATCH(DMI_PRODUCT_NAME, "23738CG"),
99 /* Reported by Pete Toscano <pete@verisignlabs.com> */
100 .ident = "IBM ThinkPad T40 (2373-94U)",
102 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
103 DMI_MATCH(DMI_PRODUCT_NAME, "237394U"),
107 /* Reported by Manuel Carro <mcarro@fi.upm.es> */
108 .ident = "IBM ThinkPad T40 (2373-94G)",
110 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
111 DMI_MATCH(DMI_PRODUCT_NAME, "237394G"),
115 /* Reported by Peter Jones <pjones@redhat.com> */
116 .ident = "IBM ThinkPad T41 (2373-9FU)",
118 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
119 DMI_MATCH(DMI_PRODUCT_NAME, "23739FU"),
123 /* Reported by Ajay Ramaswamy <ajay@ramaswamy.net> */
124 .ident = "IBM ThinkPad T41 (2373-9HU)",
126 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
127 DMI_MATCH(DMI_PRODUCT_NAME, "23739HU"),
131 /* Reported by Peter Jones <pjones@redhat.com> */
132 .ident = "IBM ThinkPad T40 (2373-BU7)",
134 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
135 DMI_MATCH(DMI_PRODUCT_NAME, "2373BU7"),
139 /* Reported by Jerome Poggi <Jerome.Poggi@hsc.fr> */
140 .ident = "IBM ThinkPad T42 (2373-FWG)",
142 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
143 DMI_MATCH(DMI_PRODUCT_NAME, "2373FWG"),
147 /* Reported by Juerg Billeter <j@bitron.ch> */
148 .ident = "IBM ThinkPad T40p (2373-G1G)",
150 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
151 DMI_MATCH(DMI_PRODUCT_NAME, "2373G1G"),
155 /* Reported by Hartwig, Thomas <t.hartwig@itth.com> */
156 .ident = "IBM ThinkPad T40p (2373-G3G)",
158 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
159 DMI_MATCH(DMI_PRODUCT_NAME, "2373G3G"),
163 /* Reported by Eric Benson <eric_a_benson@yahoo.com> */
164 .ident = "IBM ThinkPad T41p (2373-GEU)",
166 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
167 DMI_MATCH(DMI_PRODUCT_NAME, "2373GEU"),
171 /* Reported by Dwight Barkley <barkley@maths.warwick.ac.uk> */
172 .ident = "IBM ThinkPad T42 (2373-JTU)",
174 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
175 DMI_MATCH(DMI_PRODUCT_NAME, "2373JTU"),
179 /* Reported by Vernon Mauery <vernux@us.ibm.com> */
180 .ident = "IBM ThinkPad T40 (2373-MU4)",
182 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
183 DMI_MATCH(DMI_PRODUCT_NAME, "2373MU4"),
187 /* Reported by Ajay Ramaswamy <ajay@ramaswamy.net> */
188 .ident = "IBM ThinkPad T41 (2373-XNX)",
190 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
191 DMI_MATCH(DMI_PRODUCT_NAME, "2373XNX"),
195 /* Reported by obi <graziano@cs.ucsb.edu> */
196 .ident = "IBM ThinkPad T41 (2378-DEU)",
198 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
199 DMI_MATCH(DMI_PRODUCT_NAME, "2378DEU"),
203 /* Reported by Volker Braun <vbraun@physics.upenn.edu> */
204 .ident = "IBM ThinkPad T41 (2379-DJU)",
206 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
207 DMI_MATCH(DMI_PRODUCT_NAME, "2379DJU"),
211 /* Reported by Pete Toscano <pete@verisignlabs.com> */
212 .ident = "IBM ThinkPad T42 (2373-FWG)",
214 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
215 DMI_MATCH(DMI_PRODUCT_NAME, "2373FWG"),
219 /* Reported by Frank Schmitt <tonne2004@gehheimdienst.de> */
220 .ident = "IBM ThinkPad R40 (2722-3GG)",
222 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
223 DMI_MATCH(DMI_PRODUCT_NAME, "27223GG"),
227 /* Reported by Nils Trebing <nils.trebing@uni-konstanz.de> */
228 .ident = "IBM ThinkPad R40 (2722-5MG)",
230 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
231 DMI_MATCH(DMI_PRODUCT_NAME, "27225MG"),
235 /* Reported by Paul Ionescu <i_p_a_u_l@yahoo.com> */
236 .ident = "IBM ThinkPad T41 (2373-TG5)",
238 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
239 DMI_MATCH(DMI_PRODUCT_NAME, "2373TG5"),
243 /* Reported by Michele Lamarca <lammic@gmail.com> */
244 .ident = "IBM ThinkPad T40 (2373-22G)",
246 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
247 DMI_MATCH(DMI_PRODUCT_NAME, "237322G"),
251 /* Reported by Henrik Brix Andersen <brix@gentoo.org> */
252 .ident = "IBM ThinkPad X31 (2672-XXH)",
254 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
255 DMI_MATCH(DMI_PRODUCT_NAME, "2672XXH"),
259 /* Reported by Matthew Saltzman <mjs@clemson.edu> */
260 .ident = "IBM ThinkPad T41 (2373-7JU)",
262 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
263 DMI_MATCH(DMI_PRODUCT_NAME, "23737JU"),
267 /* Negative reports: */
268 /* IBM thinkpad T30 2366 -> machine hangs
269 Reported by: Jakob Schiotz <schiotz@fysik.dtu.dk> */
270 /* IBM thinkpad T42p 2373-KUU -> machine hangs as X starts
271 Reported by: Dax Kelson <dax@gurulabs.com> */
272 /* IBM ThinkPad X31 2672-XXH -> works, but doesn't fix the LCD
273 backlight on during S3 issue.
274 Reported by: Henrik Brix Andersen <brix@gentoo.org> */
277 extern int radeon_force_sleep;
280 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
285 if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
286 if (rinfo->has_CRTC2) {
287 tmp = INPLL(pllSCLK_CNTL);
288 tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK;
289 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK;
290 OUTPLL(pllSCLK_CNTL, tmp);
292 tmp = INPLL(pllMCLK_CNTL);
293 tmp |= (MCLK_CNTL__FORCE_MCLKA |
294 MCLK_CNTL__FORCE_MCLKB |
295 MCLK_CNTL__FORCE_YCLKA |
296 MCLK_CNTL__FORCE_YCLKB |
297 MCLK_CNTL__FORCE_AIC |
298 MCLK_CNTL__FORCE_MC);
299 OUTPLL(pllMCLK_CNTL, tmp);
303 if (!rinfo->has_CRTC2) {
304 tmp = INPLL(pllSCLK_CNTL);
305 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_HDP |
306 SCLK_CNTL__FORCE_DISP1 | SCLK_CNTL__FORCE_TOP |
307 SCLK_CNTL__FORCE_E2 | SCLK_CNTL__FORCE_SE |
308 SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_VIP |
309 SCLK_CNTL__FORCE_RE | SCLK_CNTL__FORCE_PB |
310 SCLK_CNTL__FORCE_TAM | SCLK_CNTL__FORCE_TDM |
311 SCLK_CNTL__FORCE_RB);
312 OUTPLL(pllSCLK_CNTL, tmp);
316 if (rinfo->family == CHIP_FAMILY_RV350) {
317 /* for RV350/M10, no delays are required. */
318 tmp = INPLL(pllSCLK_CNTL2);
319 tmp |= (SCLK_CNTL2__R300_FORCE_TCL |
320 SCLK_CNTL2__R300_FORCE_GA |
321 SCLK_CNTL2__R300_FORCE_CBA);
322 OUTPLL(pllSCLK_CNTL2, tmp);
324 tmp = INPLL(pllSCLK_CNTL);
325 tmp |= (SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
326 SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
327 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
328 SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
329 SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
330 SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
331 SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
332 SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
333 OUTPLL(pllSCLK_CNTL, tmp);
335 tmp = INPLL(pllSCLK_MORE_CNTL);
336 tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS | SCLK_MORE_CNTL__FORCE_MC_GUI |
337 SCLK_MORE_CNTL__FORCE_MC_HOST);
338 OUTPLL(pllSCLK_MORE_CNTL, tmp);
340 tmp = INPLL(pllMCLK_CNTL);
341 tmp |= (MCLK_CNTL__FORCE_MCLKA |
342 MCLK_CNTL__FORCE_MCLKB |
343 MCLK_CNTL__FORCE_YCLKA |
344 MCLK_CNTL__FORCE_YCLKB |
345 MCLK_CNTL__FORCE_MC);
346 OUTPLL(pllMCLK_CNTL, tmp);
348 tmp = INPLL(pllVCLK_ECP_CNTL);
349 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
350 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb |
351 VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
352 OUTPLL(pllVCLK_ECP_CNTL, tmp);
354 tmp = INPLL(pllPIXCLKS_CNTL);
355 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
356 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
357 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
358 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
359 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
360 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
361 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
362 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
363 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
364 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
365 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
366 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
367 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
368 PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
369 OUTPLL(pllPIXCLKS_CNTL, tmp);
376 /* Force Core Clocks */
377 tmp = INPLL(pllSCLK_CNTL);
378 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2);
380 /* XFree doesn't do that case, but we had this code from Apple and it
381 * seem necessary for proper suspend/resume operations
383 if (rinfo->is_mobility) {
384 tmp |= SCLK_CNTL__FORCE_HDP|
385 SCLK_CNTL__FORCE_DISP1|
386 SCLK_CNTL__FORCE_DISP2|
387 SCLK_CNTL__FORCE_TOP|
389 SCLK_CNTL__FORCE_IDCT|
390 SCLK_CNTL__FORCE_VIP|
393 SCLK_CNTL__FORCE_TAM|
394 SCLK_CNTL__FORCE_TDM|
396 SCLK_CNTL__FORCE_TV_SCLK|
397 SCLK_CNTL__FORCE_SUBPIC|
398 SCLK_CNTL__FORCE_OV0;
400 else if (rinfo->family == CHIP_FAMILY_R300 ||
401 rinfo->family == CHIP_FAMILY_R350) {
402 tmp |= SCLK_CNTL__FORCE_HDP |
403 SCLK_CNTL__FORCE_DISP1 |
404 SCLK_CNTL__FORCE_DISP2 |
405 SCLK_CNTL__FORCE_TOP |
406 SCLK_CNTL__FORCE_IDCT |
407 SCLK_CNTL__FORCE_VIP;
409 OUTPLL(pllSCLK_CNTL, tmp);
412 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
413 tmp = INPLL(pllSCLK_CNTL2);
414 tmp |= SCLK_CNTL2__R300_FORCE_TCL |
415 SCLK_CNTL2__R300_FORCE_GA |
416 SCLK_CNTL2__R300_FORCE_CBA;
417 OUTPLL(pllSCLK_CNTL2, tmp);
421 tmp = INPLL(pllCLK_PIN_CNTL);
422 tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
423 OUTPLL(pllCLK_PIN_CNTL, tmp);
427 /* Weird ... X is _un_ forcing clocks here, I think it's
428 * doing backward. Imitate it for now...
430 tmp = INPLL(pllMCLK_CNTL);
431 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
432 MCLK_CNTL__FORCE_YCLKA);
433 OUTPLL(pllMCLK_CNTL, tmp);
436 /* Hrm... same shit, X doesn't do that but I have to */
437 else if (rinfo->is_mobility) {
438 tmp = INPLL(pllMCLK_CNTL);
439 tmp |= (MCLK_CNTL__FORCE_MCLKA |
440 MCLK_CNTL__FORCE_MCLKB |
441 MCLK_CNTL__FORCE_YCLKA |
442 MCLK_CNTL__FORCE_YCLKB);
443 OUTPLL(pllMCLK_CNTL, tmp);
446 tmp = INPLL(pllMCLK_MISC);
447 tmp &= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
448 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
449 MCLK_MISC__MC_MCLK_DYN_ENABLE|
450 MCLK_MISC__IO_MCLK_DYN_ENABLE);
451 OUTPLL(pllMCLK_MISC, tmp);
455 if (rinfo->is_mobility) {
456 tmp = INPLL(pllSCLK_MORE_CNTL);
457 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS|
458 SCLK_MORE_CNTL__FORCE_MC_GUI|
459 SCLK_MORE_CNTL__FORCE_MC_HOST;
460 OUTPLL(pllSCLK_MORE_CNTL, tmp);
464 tmp = INPLL(pllPIXCLKS_CNTL);
465 tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
466 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
467 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
468 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
469 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
470 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
471 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
472 OUTPLL(pllPIXCLKS_CNTL, tmp);
475 tmp = INPLL( pllVCLK_ECP_CNTL);
476 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
477 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
478 OUTPLL( pllVCLK_ECP_CNTL, tmp);
482 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
487 if (!rinfo->has_CRTC2) {
488 tmp = INPLL(pllSCLK_CNTL);
490 if ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
491 tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB);
492 tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
493 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_SE |
494 SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_RE |
495 SCLK_CNTL__FORCE_PB | SCLK_CNTL__FORCE_TAM |
496 SCLK_CNTL__FORCE_TDM);
497 OUTPLL(pllSCLK_CNTL, tmp);
502 if (rinfo->family == CHIP_FAMILY_RV350) {
503 tmp = INPLL(pllSCLK_CNTL2);
504 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
505 SCLK_CNTL2__R300_FORCE_GA |
506 SCLK_CNTL2__R300_FORCE_CBA);
507 tmp |= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT |
508 SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT |
509 SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT);
510 OUTPLL(pllSCLK_CNTL2, tmp);
512 tmp = INPLL(pllSCLK_CNTL);
513 tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
514 SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
515 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
516 SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
517 SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
518 SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
519 SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
520 SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
521 tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK;
522 OUTPLL(pllSCLK_CNTL, tmp);
524 tmp = INPLL(pllSCLK_MORE_CNTL);
525 tmp &= ~SCLK_MORE_CNTL__FORCEON;
526 tmp |= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT |
527 SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT |
528 SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT;
529 OUTPLL(pllSCLK_MORE_CNTL, tmp);
531 tmp = INPLL(pllVCLK_ECP_CNTL);
532 tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
533 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
534 OUTPLL(pllVCLK_ECP_CNTL, tmp);
536 tmp = INPLL(pllPIXCLKS_CNTL);
537 tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
538 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
539 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
540 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
541 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
542 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
543 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
544 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
545 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
546 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
547 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
548 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
549 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb);
550 OUTPLL(pllPIXCLKS_CNTL, tmp);
552 tmp = INPLL(pllMCLK_MISC);
553 tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE |
554 MCLK_MISC__IO_MCLK_DYN_ENABLE);
555 OUTPLL(pllMCLK_MISC, tmp);
557 tmp = INPLL(pllMCLK_CNTL);
558 tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB);
559 tmp &= ~(MCLK_CNTL__FORCE_YCLKA |
560 MCLK_CNTL__FORCE_YCLKB |
561 MCLK_CNTL__FORCE_MC);
563 /* Some releases of vbios have set DISABLE_MC_MCLKA
564 * and DISABLE_MC_MCLKB bits in the vbios table. Setting these
565 * bits will cause H/W hang when reading video memory with dynamic
568 if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) &&
569 (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) {
570 /* If both bits are set, then check the active channels */
571 tmp = INPLL(pllMCLK_CNTL);
572 if (rinfo->vram_width == 64) {
573 if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
574 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB;
576 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA;
578 tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA |
579 MCLK_CNTL__R300_DISABLE_MC_MCLKB);
582 OUTPLL(pllMCLK_CNTL, tmp);
587 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
588 tmp = INPLL(pllSCLK_CNTL);
589 tmp &= ~(SCLK_CNTL__R300_FORCE_VAP);
590 tmp |= SCLK_CNTL__FORCE_CP;
591 OUTPLL(pllSCLK_CNTL, tmp);
594 tmp = INPLL(pllSCLK_CNTL2);
595 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
596 SCLK_CNTL2__R300_FORCE_GA |
597 SCLK_CNTL2__R300_FORCE_CBA);
598 OUTPLL(pllSCLK_CNTL2, tmp);
603 tmp = INPLL( pllCLK_PWRMGT_CNTL);
604 tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
605 CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK|
606 CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK);
607 tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK |
608 (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT);
609 OUTPLL( pllCLK_PWRMGT_CNTL, tmp);
612 tmp = INPLL(pllCLK_PIN_CNTL);
613 tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
614 OUTPLL(pllCLK_PIN_CNTL, tmp);
617 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
618 * to lockup randomly, leave them as set by BIOS.
620 tmp = INPLL(pllSCLK_CNTL);
621 tmp &= ~SCLK_CNTL__FORCEON_MASK;
623 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
624 if ((rinfo->family == CHIP_FAMILY_RV250 &&
625 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
626 ((rinfo->family == CHIP_FAMILY_RV100) &&
627 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
628 tmp |= SCLK_CNTL__FORCE_CP;
629 tmp |= SCLK_CNTL__FORCE_VIP;
631 OUTPLL(pllSCLK_CNTL, tmp);
634 if ((rinfo->family == CHIP_FAMILY_RV200) ||
635 (rinfo->family == CHIP_FAMILY_RV250) ||
636 (rinfo->family == CHIP_FAMILY_RV280)) {
637 tmp = INPLL(pllSCLK_MORE_CNTL);
638 tmp &= ~SCLK_MORE_CNTL__FORCEON;
640 /* RV200::A11 A12 RV250::A11 A12 */
641 if (((rinfo->family == CHIP_FAMILY_RV200) ||
642 (rinfo->family == CHIP_FAMILY_RV250)) &&
643 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
644 tmp |= SCLK_MORE_CNTL__FORCEON;
646 OUTPLL(pllSCLK_MORE_CNTL, tmp);
651 /* RV200::A11 A12, RV250::A11 A12 */
652 if (((rinfo->family == CHIP_FAMILY_RV200) ||
653 (rinfo->family == CHIP_FAMILY_RV250)) &&
654 ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
655 tmp = INPLL(pllPLL_PWRMGT_CNTL);
656 tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
657 OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
661 tmp = INPLL(pllPIXCLKS_CNTL);
662 tmp |= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
663 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb|
664 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
665 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb|
666 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb|
667 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
668 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb;
669 OUTPLL(pllPIXCLKS_CNTL, tmp);
672 tmp = INPLL(pllVCLK_ECP_CNTL);
673 tmp |= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
674 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb;
675 OUTPLL(pllVCLK_ECP_CNTL, tmp);
677 /* X doesn't do that ... hrm, we do on mobility && Macs */
679 if (rinfo->is_mobility) {
680 tmp = INPLL(pllMCLK_CNTL);
681 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
682 MCLK_CNTL__FORCE_MCLKB |
683 MCLK_CNTL__FORCE_YCLKA |
684 MCLK_CNTL__FORCE_YCLKB);
685 OUTPLL(pllMCLK_CNTL, tmp);
688 tmp = INPLL(pllMCLK_MISC);
689 tmp |= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
690 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
691 MCLK_MISC__MC_MCLK_DYN_ENABLE|
692 MCLK_MISC__IO_MCLK_DYN_ENABLE;
693 OUTPLL(pllMCLK_MISC, tmp);
696 #endif /* CONFIG_PPC_OF */
701 static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
703 OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN);
704 OUTREG( MC_IND_DATA, value);
707 static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
709 OUTREG( MC_IND_INDEX, indx);
710 return INREG( MC_IND_DATA);
713 static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
715 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
716 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
717 rinfo->save_regs[2] = INPLL(MCLK_CNTL);
718 rinfo->save_regs[3] = INPLL(SCLK_CNTL);
719 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
720 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
721 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
722 rinfo->save_regs[7] = INPLL(MCLK_MISC);
723 rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
725 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
726 rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
727 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
728 rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
729 rinfo->save_regs[14] = INREG(BUS_CNTL1);
730 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
731 rinfo->save_regs[16] = INREG(AGP_CNTL);
732 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
733 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
734 rinfo->save_regs[19] = INREG(GPIOPAD_A);
735 rinfo->save_regs[20] = INREG(GPIOPAD_EN);
736 rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
737 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
738 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
739 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
740 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
741 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
742 rinfo->save_regs[27] = INREG(GPIO_MONID);
743 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
745 rinfo->save_regs[29] = INREG(SURFACE_CNTL);
746 rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
747 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
748 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
749 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
751 rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
752 rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
753 rinfo->save_regs[36] = INREG(BUS_CNTL);
754 rinfo->save_regs[39] = INREG(RBBM_CNTL);
755 rinfo->save_regs[40] = INREG(DAC_CNTL);
756 rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
757 rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
758 rinfo->save_regs[38] = INREG(FCP_CNTL);
760 if (rinfo->is_mobility) {
761 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
762 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
763 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
764 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
765 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
766 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
767 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
770 if (rinfo->family >= CHIP_FAMILY_RV200) {
771 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
772 rinfo->save_regs[46] = INREG(MC_CNTL);
773 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
774 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
775 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
776 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
777 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
778 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
779 rinfo->save_regs[53] = INREG(MC_DEBUG);
781 rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
782 rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
783 rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
784 rinfo->save_regs[57] = INREG(FW_CNTL);
786 if (rinfo->family >= CHIP_FAMILY_R300) {
787 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
788 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
789 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
790 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
791 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
792 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
793 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
794 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
795 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
796 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
797 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
798 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
799 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
800 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
801 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
802 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
804 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
805 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
806 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
807 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
808 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
809 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
812 rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
813 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
814 rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
815 rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
816 rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
817 rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
818 rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
820 rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
821 rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
822 rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
823 rinfo->save_regs[84] = INREG(TMDS_CNTL);
824 rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
825 rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
826 rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
827 rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
828 rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
829 rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
830 rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
831 rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
832 rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
833 rinfo->save_regs[96] = INREG(HDP_DEBUG);
834 rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
835 rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
836 rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
839 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
841 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
843 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
844 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
845 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
846 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
847 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
848 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
849 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
850 OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
851 if (rinfo->family == CHIP_FAMILY_RV350)
852 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
854 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
855 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
856 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
857 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
858 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
859 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
861 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
862 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
863 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
864 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
865 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
866 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
867 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
868 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
869 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
870 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
871 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
873 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
874 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
875 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
876 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
877 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
878 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
879 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
880 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
881 OUTREG(GPIO_MONID, rinfo->save_regs[27]);
882 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
885 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
887 OUTREG(GPIOPAD_MASK, 0x0001ffff);
888 OUTREG(GPIOPAD_EN, 0x00000400);
889 OUTREG(GPIOPAD_A, 0x00000000);
890 OUTREG(ZV_LCDPAD_MASK, 0x00000000);
891 OUTREG(ZV_LCDPAD_EN, 0x00000000);
892 OUTREG(ZV_LCDPAD_A, 0x00000000);
893 OUTREG(GPIO_VGA_DDC, 0x00030000);
894 OUTREG(GPIO_DVI_DDC, 0x00000000);
895 OUTREG(GPIO_MONID, 0x00030000);
896 OUTREG(GPIO_CRT2_DDC, 0x00000000);
899 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
901 /* Set v2clk to 65MHz */
902 if (rinfo->family <= CHIP_FAMILY_RV280) {
903 OUTPLL(pllPIXCLKS_CNTL,
904 __INPLL(rinfo, pllPIXCLKS_CNTL)
905 & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);
907 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
908 OUTPLL(pllP2PLL_CNTL, 0x0000bf00);
910 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
911 INPLL(pllP2PLL_REF_DIV);
912 OUTPLL(pllP2PLL_CNTL, 0x0000a700);
915 OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);
917 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
920 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
923 OUTPLL(pllPIXCLKS_CNTL,
924 (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)
925 | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
929 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
933 reg = INREG(BUS_CNTL1);
934 if (rinfo->family <= CHIP_FAMILY_RV280) {
935 reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
936 reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
940 OUTREG(BUS_CNTL1, reg);
942 reg = INPLL(PLL_PWRMGT_CNTL);
943 reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
944 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
945 reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
946 reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
947 OUTPLL(PLL_PWRMGT_CNTL, reg);
949 reg = INREG(TV_DAC_CNTL);
950 reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
951 reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
953 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
954 OUTREG(TV_DAC_CNTL, reg);
956 reg = INREG(TMDS_TRANSMITTER_CNTL);
957 reg &= ~(TMDS_PLL_EN | TMDS_PLLRST);
958 OUTREG(TMDS_TRANSMITTER_CNTL, reg);
960 reg = INREG(DAC_CNTL);
962 OUTREG(DAC_CNTL, reg);
964 reg = INREG(DAC_CNTL2);
966 OUTREG(DAC_CNTL2, reg);
968 reg = INREG(TV_DAC_CNTL);
969 reg &= ~TV_DAC_CNTL_DETECT;
970 OUTREG(TV_DAC_CNTL, reg);
973 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
976 u32 sclk_cntl, mclk_cntl, sclk_more_cntl;
987 /* Force Core Clocks */
988 sclk_cntl = INPLL( pllSCLK_CNTL);
989 sclk_cntl |= SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
990 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT|
991 SCLK_CNTL__RE_MAX_DYN_STOP_LAT|
992 SCLK_CNTL__PB_MAX_DYN_STOP_LAT|
993 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT|
994 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT|
995 SCLK_CNTL__RB_MAX_DYN_STOP_LAT|
997 SCLK_CNTL__FORCE_DISP2|
999 SCLK_CNTL__FORCE_HDP|
1000 SCLK_CNTL__FORCE_DISP1|
1001 SCLK_CNTL__FORCE_TOP|
1002 SCLK_CNTL__FORCE_E2|
1003 SCLK_CNTL__FORCE_SE|
1004 SCLK_CNTL__FORCE_IDCT|
1005 SCLK_CNTL__FORCE_VIP|
1007 SCLK_CNTL__FORCE_PB|
1008 SCLK_CNTL__FORCE_TAM|
1009 SCLK_CNTL__FORCE_TDM|
1010 SCLK_CNTL__FORCE_RB|
1011 SCLK_CNTL__FORCE_TV_SCLK|
1012 SCLK_CNTL__FORCE_SUBPIC|
1013 SCLK_CNTL__FORCE_OV0;
1014 if (rinfo->family <= CHIP_FAMILY_RV280)
1015 sclk_cntl |= SCLK_CNTL__FORCE_RE;
1017 sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
1018 SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
1019 SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
1020 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
1021 SCLK_CNTL__CP_MAX_DYN_STOP_LAT;
1023 OUTPLL( pllSCLK_CNTL, sclk_cntl);
1025 sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);
1026 sclk_more_cntl |= SCLK_MORE_CNTL__FORCE_DISPREGS |
1027 SCLK_MORE_CNTL__FORCE_MC_GUI |
1028 SCLK_MORE_CNTL__FORCE_MC_HOST;
1030 OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);
1033 mclk_cntl = INPLL( pllMCLK_CNTL);
1034 mclk_cntl &= ~( MCLK_CNTL__FORCE_MCLKA |
1035 MCLK_CNTL__FORCE_MCLKB |
1036 MCLK_CNTL__FORCE_YCLKA |
1037 MCLK_CNTL__FORCE_YCLKB |
1040 OUTPLL( pllMCLK_CNTL, mclk_cntl);
1042 /* Force Display clocks */
1043 vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);
1044 vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
1045 | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
1046 vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON;
1047 OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);
1050 pixclks_cntl = INPLL( pllPIXCLKS_CNTL);
1051 pixclks_cntl &= ~( PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
1052 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
1053 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
1054 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
1055 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
1056 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
1057 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
1059 OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
1061 /* Switch off LVDS interface */
1062 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) &
1063 ~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON));
1065 /* Enable System power management */
1066 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
1068 pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__SPLL_TURNOFF |
1069 PLL_PWRMGT_CNTL__MPLL_TURNOFF|
1070 PLL_PWRMGT_CNTL__PPLL_TURNOFF|
1071 PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
1072 PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
1074 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
1076 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
1078 clk_pwrmgt_cntl &= ~( CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF|
1079 CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF|
1080 CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF|
1081 CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF|
1082 CLK_PWRMGT_CNTL__MCLK_TURNOFF|
1083 CLK_PWRMGT_CNTL__SCLK_TURNOFF|
1084 CLK_PWRMGT_CNTL__PCLK_TURNOFF|
1085 CLK_PWRMGT_CNTL__P2CLK_TURNOFF|
1086 CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF|
1087 CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN|
1088 CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE|
1089 CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
1090 CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK
1093 clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
1094 | CLK_PWRMGT_CNTL__DISP_PM;
1096 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
1098 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
1100 clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND;
1102 /* because both INPLL and OUTPLL take the same lock, that's why. */
1103 tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
1104 OUTPLL( pllMCLK_MISC, tmp);
1106 /* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset
1107 * and radeon chip dependent. Thus we only enable it on Mac for
1108 * now (until we get more info on how to compute the correct
1109 * value for various X86 bridges).
1112 #ifdef CONFIG_PPC_PMAC
1113 /* AGP PLL control */
1114 if (rinfo->family <= CHIP_FAMILY_RV280) {
1115 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID);
1118 (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK)
1119 | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT)); // 440BX
1121 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
1122 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000);
1126 OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
1127 & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
1129 clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN;
1130 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
1131 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
1135 (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK))
1136 | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
1139 /* because both INPLL and OUTPLL take the same lock, that's why. */
1140 tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL;
1141 OUTPLL( pllPLL_PWRMGT_CNTL, tmp);
1144 disp_mis_cntl = INREG(DISP_MISC_CNTL);
1146 disp_mis_cntl &= ~( DISP_MISC_CNTL__SOFT_RESET_GRPH_PP |
1147 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
1148 DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
1149 DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
1150 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
1151 DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
1152 DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
1153 DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
1154 DISP_MISC_CNTL__SOFT_RESET_LVDS|
1155 DISP_MISC_CNTL__SOFT_RESET_TMDS|
1156 DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
1157 DISP_MISC_CNTL__SOFT_RESET_TV);
1159 OUTREG(DISP_MISC_CNTL, disp_mis_cntl);
1161 disp_pwr_man = INREG(DISP_PWR_MAN);
1163 disp_pwr_man &= ~( DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN |
1164 DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN |
1165 DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK|
1166 DISP_PWR_MAN__DISP_D3_RST|
1167 DISP_PWR_MAN__DISP_D3_REG_RST
1170 disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST|
1171 DISP_PWR_MAN__DISP_D3_SUBPIC_RST|
1172 DISP_PWR_MAN__DISP_D3_OV0_RST|
1173 DISP_PWR_MAN__DISP_D1D2_GRPH_RST|
1174 DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST|
1175 DISP_PWR_MAN__DISP_D1D2_OV0_RST|
1176 DISP_PWR_MAN__DIG_TMDS_ENABLE_RST|
1177 DISP_PWR_MAN__TV_ENABLE_RST|
1178 // DISP_PWR_MAN__AUTO_PWRUP_EN|
1181 OUTREG(DISP_PWR_MAN, disp_pwr_man);
1183 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
1184 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;
1185 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
1186 disp_pwr_man = INREG(DISP_PWR_MAN);
1190 clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM;
1191 pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK;
1192 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
1193 disp_pwr_man &= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
1194 | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK);
1196 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
1197 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
1198 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
1199 OUTREG(DISP_PWR_MAN, disp_pwr_man);
1201 /* disable display request & disable display */
1202 OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN)
1203 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1204 OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN)
1205 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1211 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
1213 u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1215 mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
1216 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1217 mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
1218 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1220 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
1221 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1222 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
1223 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1225 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1226 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1231 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
1233 u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1235 mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
1236 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1237 mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
1238 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1240 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
1241 mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1242 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
1243 mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1245 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1246 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1251 static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
1256 mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG);
1258 mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
1259 mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT)
1260 | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
1261 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1262 if (delay_required >= 2)
1265 mem_sdram_mode |= MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1266 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1267 if (delay_required >= 2)
1270 mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1271 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1272 if (delay_required >= 2)
1275 if (delay_required) {
1277 if (delay_required >= 2)
1279 } while ((INREG(MC_STATUS)
1280 & (MC_STATUS__MEM_PWRUP_COMPL_A |
1281 MC_STATUS__MEM_PWRUP_COMPL_B)) == 0);
1285 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
1289 for (cnt = 0; cnt < 100; ++cnt) {
1291 if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A
1292 | MC_STATUS__MEM_PWRUP_COMPL_B))
1298 static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
1300 #define DLL_RESET_DELAY 5
1301 #define DLL_SLEEP_DELAY 1
1303 u32 cko = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP
1304 | MDLL_CKO__MCKOA_RESET;
1305 u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP
1306 | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET
1307 | MDLL_RDCKA__MRDCKA1_RESET;
1308 u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP
1309 | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET
1310 | MDLL_RDCKB__MRDCKB1_RESET;
1312 /* Setting up the DLL range for write */
1313 OUTPLL(pllMDLL_CKO, cko);
1314 OUTPLL(pllMDLL_RDCKA, cka);
1315 OUTPLL(pllMDLL_RDCKB, ckb);
1317 mdelay(DLL_RESET_DELAY*2);
1319 cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
1320 OUTPLL(pllMDLL_CKO, cko);
1321 mdelay(DLL_SLEEP_DELAY);
1322 cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
1323 OUTPLL(pllMDLL_CKO, cko);
1324 mdelay(DLL_RESET_DELAY);
1326 cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
1327 OUTPLL(pllMDLL_RDCKA, cka);
1328 mdelay(DLL_SLEEP_DELAY);
1329 cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
1330 OUTPLL(pllMDLL_RDCKA, cka);
1331 mdelay(DLL_RESET_DELAY);
1333 ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
1334 OUTPLL(pllMDLL_RDCKB, ckb);
1335 mdelay(DLL_SLEEP_DELAY);
1336 ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
1337 OUTPLL(pllMDLL_RDCKB, ckb);
1338 mdelay(DLL_RESET_DELAY);
1341 #undef DLL_RESET_DELAY
1342 #undef DLL_SLEEP_DELAY
1345 static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
1348 u32 dll_sleep_mask = 0;
1349 u32 dll_reset_mask = 0;
1352 #define DLL_RESET_DELAY 5
1353 #define DLL_SLEEP_DELAY 1
1355 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1356 mc = INREG(MC_CNTL);
1357 /* Check which channels are enabled */
1363 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP;
1364 dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET;
1366 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP;
1367 dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET;
1374 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP;
1375 dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET;
1376 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP;
1377 dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET;
1380 dll_value = INPLL(pllMDLL_RDCKA);
1383 dll_value &= ~(dll_sleep_mask);
1384 OUTPLL(pllMDLL_RDCKA, dll_value);
1385 mdelay( DLL_SLEEP_DELAY);
1387 dll_value &= ~(dll_reset_mask);
1388 OUTPLL(pllMDLL_RDCKA, dll_value);
1389 mdelay( DLL_RESET_DELAY);
1391 #undef DLL_RESET_DELAY
1392 #undef DLL_SLEEP_DELAY
1396 static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
1398 u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl,
1399 fp_gen_cntl, fp2_gen_cntl;
1401 crtcGenCntl = INREG( CRTC_GEN_CNTL);
1402 crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
1404 crtc_more_cntl = INREG( CRTC_MORE_CNTL);
1405 fp_gen_cntl = INREG( FP_GEN_CNTL);
1406 fp2_gen_cntl = INREG( FP2_GEN_CNTL);
1409 OUTREG( CRTC_MORE_CNTL, 0);
1410 OUTREG( FP_GEN_CNTL, 0);
1411 OUTREG( FP2_GEN_CNTL,0);
1413 OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
1414 OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
1416 /* This is the code for the Aluminium PowerBooks M10 */
1417 if (rinfo->family == CHIP_FAMILY_RV350) {
1418 u32 sdram_mode_reg = rinfo->save_regs[35];
1419 static u32 default_mrtable[] =
1421 0x21321000, 0xa1321000, 0x21321000, 0xffffffff,
1422 0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1423 0x21321002, 0xa1321002, 0x21321002, 0xffffffff,
1424 0x21320132, 0xa1320132, 0x21320132, 0xffffffff,
1425 0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1428 u32 *mrtable = default_mrtable;
1429 int i, mrtable_size = ARRAY_SIZE(default_mrtable);
1433 /* Disable refresh */
1434 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1435 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1436 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1437 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1439 /* Configure and enable M & SPLLs */
1440 radeon_pm_enable_dll_m10(rinfo);
1441 radeon_pm_yclk_mclk_sync_m10(rinfo);
1443 #ifdef CONFIG_PPC_OF
1444 if (rinfo->of_node != NULL) {
1447 mrtable = (u32 *)get_property(rinfo->of_node, "ATY,MRT", &size);
1449 mrtable_size = size >> 2;
1451 mrtable = default_mrtable;
1453 #endif /* CONFIG_PPC_OF */
1455 /* Program the SDRAM */
1456 sdram_mode_reg = mrtable[0];
1457 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1458 for (i = 0; i < mrtable_size; i++) {
1459 if (mrtable[i] == 0xffffffffu)
1460 radeon_pm_m10_program_mode_wait(rinfo);
1462 sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
1463 | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
1464 | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET);
1465 sdram_mode_reg |= mrtable[i];
1467 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1472 /* Restore memory refresh */
1473 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl);
1477 /* Here come the desktop RV200 "QW" card */
1478 else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
1479 /* Disable refresh */
1480 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1481 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1482 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl
1483 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1487 OUTREG(MEM_SDRAM_MODE_REG,
1488 INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1490 radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
1491 radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
1492 radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
1494 OUTREG(MEM_SDRAM_MODE_REG,
1495 INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1497 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
1501 else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
1502 /* Disable refresh */
1503 memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20);
1504 OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20));
1507 OUTREG( MEM_SDRAM_MODE_REG,
1508 INREG( MEM_SDRAM_MODE_REG)
1509 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1512 radeon_pm_enable_dll(rinfo);
1514 /* MLCK / YCLK sync */
1515 radeon_pm_yclk_mclk_sync(rinfo);
1517 /* Program Mode Register */
1518 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1519 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1520 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1521 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1522 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1524 /* Complete & re-enable refresh */
1525 OUTREG( MEM_SDRAM_MODE_REG,
1526 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1528 OUTREG(EXT_MEM_CNTL, memRefreshCntl);
1530 /* And finally, the M7..M9 models, including M9+ (RV280) */
1531 else if (rinfo->is_mobility) {
1533 /* Disable refresh */
1534 memRefreshCntl = INREG( MEM_REFRESH_CNTL)
1535 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1536 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1537 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1540 OUTREG( MEM_SDRAM_MODE_REG,
1541 INREG( MEM_SDRAM_MODE_REG)
1542 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1545 radeon_pm_enable_dll(rinfo);
1547 /* MLCK / YCLK sync */
1548 radeon_pm_yclk_mclk_sync(rinfo);
1550 /* M6, M7 and M9 so far ... */
1551 if (rinfo->family <= CHIP_FAMILY_RV250) {
1552 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1553 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1554 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1555 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1556 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1558 /* M9+ (iBook G4) */
1559 else if (rinfo->family == CHIP_FAMILY_RV280) {
1560 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1561 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1562 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1565 /* Complete & re-enable refresh */
1566 OUTREG( MEM_SDRAM_MODE_REG,
1567 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1569 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
1572 OUTREG( CRTC_GEN_CNTL, crtcGenCntl);
1573 OUTREG( CRTC2_GEN_CNTL, crtcGenCntl2);
1574 OUTREG( FP_GEN_CNTL, fp_gen_cntl);
1575 OUTREG( FP2_GEN_CNTL, fp2_gen_cntl);
1577 OUTREG( CRTC_MORE_CNTL, crtc_more_cntl);
1582 #ifdef CONFIG_PPC_OF
1584 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
1589 /* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */
1590 INREG(PAD_CTLR_STRENGTH);
1591 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE);
1592 tmp = INREG(PAD_CTLR_STRENGTH);
1593 for (i = j = 0; i < 65; ++i) {
1595 tmp2 = INREG(PAD_CTLR_STRENGTH);
1601 printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't "
1609 static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
1613 tmp = INPLL(pllPPLL_CNTL);
1614 OUTPLL(pllPPLL_CNTL, tmp | 0x3);
1615 tmp = INPLL(pllP2PLL_CNTL);
1616 OUTPLL(pllP2PLL_CNTL, tmp | 0x3);
1617 tmp = INPLL(pllSPLL_CNTL);
1618 OUTPLL(pllSPLL_CNTL, tmp | 0x3);
1619 tmp = INPLL(pllMPLL_CNTL);
1620 OUTPLL(pllMPLL_CNTL, tmp | 0x3);
1623 static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
1627 /* Switch SPLL to PCI source */
1628 tmp = INPLL(pllSCLK_CNTL);
1629 OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);
1631 /* Reconfigure SPLL charge pump, VCO gain, duty cycle */
1632 tmp = INPLL(pllSPLL_CNTL);
1633 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1634 radeon_pll_errata_after_index(rinfo);
1635 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1636 radeon_pll_errata_after_data(rinfo);
1638 /* Set SPLL feedback divider */
1639 tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1640 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
1641 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1644 tmp = INPLL(pllSPLL_CNTL);
1645 OUTPLL(pllSPLL_CNTL, tmp & ~1);
1646 (void)INPLL(pllSPLL_CNTL);
1650 /* Release SPLL reset */
1651 tmp = INPLL(pllSPLL_CNTL);
1652 OUTPLL(pllSPLL_CNTL, tmp & ~0x2);
1653 (void)INPLL(pllSPLL_CNTL);
1657 /* Select SCLK source */
1658 tmp = INPLL(pllSCLK_CNTL);
1659 tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK;
1660 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
1661 OUTPLL(pllSCLK_CNTL, tmp);
1662 (void)INPLL(pllSCLK_CNTL);
1666 /* Reconfigure MPLL charge pump, VCO gain, duty cycle */
1667 tmp = INPLL(pllMPLL_CNTL);
1668 OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
1669 radeon_pll_errata_after_index(rinfo);
1670 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1671 radeon_pll_errata_after_data(rinfo);
1673 /* Set MPLL feedback divider */
1674 tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1675 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
1677 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1679 tmp = INPLL(pllMPLL_CNTL);
1680 OUTPLL(pllMPLL_CNTL, tmp & ~0x2);
1681 (void)INPLL(pllMPLL_CNTL);
1686 tmp = INPLL(pllMPLL_CNTL);
1687 OUTPLL(pllMPLL_CNTL, tmp & ~0x1);
1688 (void)INPLL(pllMPLL_CNTL);
1692 /* Select source for MCLK */
1693 tmp = INPLL(pllMCLK_CNTL);
1694 tmp |= rinfo->save_regs[2] & 0xffff;
1695 OUTPLL(pllMCLK_CNTL, tmp);
1696 (void)INPLL(pllMCLK_CNTL);
1701 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
1705 /* GACK ! I though we didn't have a DDA on Radeon's anymore
1706 * here we rewrite with the same value, ... I suppose we clear
1707 * some bits that are already clear ? Or maybe this 0x2ec
1708 * register is something new ?
1711 r2ec = INREG(VGA_DDA_ON_OFF);
1712 OUTREG(VGA_DDA_ON_OFF, r2ec);
1715 /* Spread spectrum PLLL off */
1716 OUTPLL(pllSSPLL_CNTL, 0xbf03);
1718 /* Spread spectrum disabled */
1719 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
1721 /* The trace shows read & rewrite of LVDS_PLL_CNTL here with same
1722 * value, not sure what for...
1726 OUTREG(VGA_DDA_ON_OFF, r2ec);
1730 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
1734 /* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore
1735 * here we rewrite with the same value, ... I suppose we clear/set
1736 * some bits that are already clear/set ?
1738 r2ec = INREG(VGA_DDA_ON_OFF);
1739 OUTREG(VGA_DDA_ON_OFF, r2ec);
1742 /* Enable spread spectrum */
1743 OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
1746 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
1747 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
1748 tmp = INPLL(pllSSPLL_CNTL);
1749 OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);
1751 tmp = INPLL(pllSSPLL_CNTL);
1752 OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);
1755 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
1758 OUTREG(VGA_DDA_ON_OFF, r2ec);
1761 /* Enable LVDS interface */
1762 tmp = INREG(LVDS_GEN_CNTL);
1763 OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN);
1765 /* Enable LVDS_PLL */
1766 tmp = INREG(LVDS_PLL_CNTL);
1769 OUTREG(LVDS_PLL_CNTL, tmp);
1771 OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
1772 OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
1774 /* The trace reads that one here, waiting for something to settle down ? */
1777 /* Ugh ? SS_TST_DEC is supposed to be a read register in the
1778 * R300 register spec at least...
1780 tmp = INPLL(pllSS_TST_CNTL);
1782 OUTPLL(pllSS_TST_CNTL, tmp);
1785 static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
1789 OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
1790 radeon_pll_errata_after_index(rinfo);
1791 OUTREG8(CLOCK_CNTL_DATA, 0);
1792 radeon_pll_errata_after_data(rinfo);
1794 tmp = INPLL(pllVCLK_ECP_CNTL);
1795 OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);
1798 tmp = INPLL(pllPPLL_REF_DIV);
1799 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1800 OUTPLL(pllPPLL_REF_DIV, tmp);
1801 INPLL(pllPPLL_REF_DIV);
1803 /* Reconfigure SPLL charge pump, VCO gain, duty cycle,
1804 * probably useless since we already did it ...
1806 tmp = INPLL(pllPPLL_CNTL);
1807 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1808 radeon_pll_errata_after_index(rinfo);
1809 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1810 radeon_pll_errata_after_data(rinfo);
1812 /* Restore our "reference" PPLL divider set by firmware
1813 * according to proper spread spectrum calculations
1815 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
1817 tmp = INPLL(pllPPLL_CNTL);
1818 OUTPLL(pllPPLL_CNTL, tmp & ~0x2);
1821 tmp = INPLL(pllPPLL_CNTL);
1822 OUTPLL(pllPPLL_CNTL, tmp & ~0x1);
1825 tmp = INPLL(pllVCLK_ECP_CNTL);
1826 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1829 tmp = INPLL(pllVCLK_ECP_CNTL);
1830 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1833 /* Switch pixel clock to firmware default div 0 */
1834 OUTREG8(CLOCK_CNTL_INDEX+1, 0);
1835 radeon_pll_errata_after_index(rinfo);
1836 radeon_pll_errata_after_data(rinfo);
1839 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
1841 OUTREG(MC_CNTL, rinfo->save_regs[46]);
1842 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1843 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1844 OUTREG(MEM_SDRAM_MODE_REG,
1845 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1846 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1847 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1848 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1849 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1850 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1851 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1853 OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
1854 OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
1855 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
1856 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
1857 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
1858 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
1859 OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
1860 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
1861 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
1862 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
1863 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
1864 OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
1865 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1866 OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
1867 OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
1868 OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
1869 OUTREG(MC_IND_INDEX, 0);
1872 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
1876 /* Restore a bunch of registers first */
1877 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1878 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1879 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1880 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1881 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1882 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
1883 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1884 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1885 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1886 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1887 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1888 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1889 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1890 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1893 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1895 /* Reset the PAD CTLR */
1896 radeon_pm_reset_pad_ctlr_strength(rinfo);
1898 /* Some PLLs are Read & written identically in the trace here...
1899 * I suppose it's actually to switch them all off & reset,
1900 * let's assume off is what we want. I'm just doing that for all major PLLs now.
1902 radeon_pm_all_ppls_off(rinfo);
1904 /* Clear tiling, reset swappers */
1905 INREG(SURFACE_CNTL);
1906 OUTREG(SURFACE_CNTL, 0);
1908 /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1909 * rather than hard coding...
1911 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1912 tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT;
1913 OUTREG(TV_DAC_CNTL, tmp);
1915 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1916 tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT;
1917 OUTREG(TV_DAC_CNTL, tmp);
1919 /* More registers restored */
1920 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1921 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
1922 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1924 /* Hrmmm ... What is that ? */
1925 tmp = rinfo->save_regs[1]
1926 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1927 CLK_PWRMGT_CNTL__MC_BUSY);
1928 OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1930 OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
1931 OUTREG(FW_CNTL, rinfo->save_regs[57]);
1932 OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
1933 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1934 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1935 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1937 /* Restore Memory Controller configuration */
1938 radeon_pm_m10_reconfigure_mc(rinfo);
1940 /* Make sure CRTC's dont touch memory */
1941 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)
1942 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1943 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)
1944 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1947 /* Disable SDRAM refresh */
1948 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1949 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1951 /* Restore XTALIN routing (CLK_PIN_CNTL) */
1952 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1954 /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */
1955 tmp = rinfo->save_regs[2] & 0xff000000;
1956 tmp |= MCLK_CNTL__FORCE_MCLKA |
1957 MCLK_CNTL__FORCE_MCLKB |
1958 MCLK_CNTL__FORCE_YCLKA |
1959 MCLK_CNTL__FORCE_YCLKB |
1960 MCLK_CNTL__FORCE_MC;
1961 OUTPLL(pllMCLK_CNTL, tmp);
1963 /* Force all clocks on in SCLK */
1964 tmp = INPLL(pllSCLK_CNTL);
1965 tmp |= SCLK_CNTL__FORCE_DISP2|
1966 SCLK_CNTL__FORCE_CP|
1967 SCLK_CNTL__FORCE_HDP|
1968 SCLK_CNTL__FORCE_DISP1|
1969 SCLK_CNTL__FORCE_TOP|
1970 SCLK_CNTL__FORCE_E2|
1971 SCLK_CNTL__FORCE_SE|
1972 SCLK_CNTL__FORCE_IDCT|
1973 SCLK_CNTL__FORCE_VIP|
1974 SCLK_CNTL__FORCE_PB|
1975 SCLK_CNTL__FORCE_TAM|
1976 SCLK_CNTL__FORCE_TDM|
1977 SCLK_CNTL__FORCE_RB|
1978 SCLK_CNTL__FORCE_TV_SCLK|
1979 SCLK_CNTL__FORCE_SUBPIC|
1980 SCLK_CNTL__FORCE_OV0;
1981 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT |
1982 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
1983 SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
1984 SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
1985 SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
1986 SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
1987 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT |
1988 SCLK_CNTL__RE_MAX_DYN_STOP_LAT |
1989 SCLK_CNTL__PB_MAX_DYN_STOP_LAT |
1990 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT |
1991 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT |
1992 SCLK_CNTL__RB_MAX_DYN_STOP_LAT;
1993 OUTPLL(pllSCLK_CNTL, tmp);
1995 OUTPLL(pllVCLK_ECP_CNTL, 0);
1996 OUTPLL(pllPIXCLKS_CNTL, 0);
1997 OUTPLL(pllMCLK_MISC,
1998 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1999 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
2003 /* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */
2004 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
2005 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
2006 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
2008 /* Now restore the major PLLs settings, keeping them off & reset though */
2009 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
2010 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
2011 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
2012 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
2014 /* Restore MC DLL state and switch it off/reset too */
2015 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
2017 /* Switch MDLL off & reset */
2018 OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
2021 /* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved
2022 * 0xa1100007... and MacOS writes 0xa1000007 ..
2024 OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2026 /* Restore more stuffs */
2027 OUTPLL(pllHTOTAL_CNTL, 0);
2028 OUTPLL(pllHTOTAL2_CNTL, 0);
2030 /* More PLL initial configuration */
2031 tmp = INPLL(pllSCLK_CNTL2); /* What for ? */
2032 OUTPLL(pllSCLK_CNTL2, tmp);
2034 tmp = INPLL(pllSCLK_MORE_CNTL);
2035 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS | /* a guess */
2036 SCLK_MORE_CNTL__FORCE_MC_GUI |
2037 SCLK_MORE_CNTL__FORCE_MC_HOST;
2038 OUTPLL(pllSCLK_MORE_CNTL, tmp);
2040 /* Now we actually start MCLK and SCLK */
2041 radeon_pm_start_mclk_sclk(rinfo);
2043 /* Full reset sdrams, this also re-inits the MDLL */
2044 radeon_pm_full_reset_sdram(rinfo);
2047 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
2048 for (i=0; i<256; i++)
2049 OUTREG(PALETTE_30_DATA, 0x15555555);
2050 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
2052 for (i=0; i<256; i++)
2053 OUTREG(PALETTE_30_DATA, 0x15555555);
2055 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
2059 OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
2060 OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
2062 /* Set LVDS registers but keep interface & pll down */
2063 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2064 ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
2065 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2067 OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
2069 /* Restore GPIOPAD state */
2070 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2071 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2072 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2074 /* write some stuff to the framebuffer... */
2075 for (i = 0; i < 0x8000; ++i)
2076 writeb(0, rinfo->fb_base + i);
2079 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
2082 /* Restore a few more things */
2083 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2084 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2086 /* Take care of spread spectrum & PPLLs now */
2087 radeon_pm_m10_disable_spread_spectrum(rinfo);
2088 radeon_pm_restore_pixel_pll(rinfo);
2090 /* GRRRR... I can't figure out the proper LVDS power sequence, and the
2091 * code I have for blank/unblank doesn't quite work on some laptop models
2092 * it seems ... Hrm. What I have here works most of the time ...
2094 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2097 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
2099 OUTREG(MC_CNTL, rinfo->save_regs[46]);
2100 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
2101 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
2102 OUTREG(MEM_SDRAM_MODE_REG,
2103 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
2104 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
2105 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
2106 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
2107 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
2108 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
2109 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
2111 OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
2112 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
2113 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
2114 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
2115 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
2116 OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
2117 OUTREG(MC_IND_INDEX, 0);
2118 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
2123 static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
2127 /* Restore a bunch of registers first */
2128 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2129 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2130 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2131 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2132 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2133 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
2134 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2135 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
2136 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
2137 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
2138 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2140 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
2141 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
2143 /* Reset the PAD CTLR */
2144 radeon_pm_reset_pad_ctlr_strength(rinfo);
2146 /* Some PLLs are Read & written identically in the trace here...
2147 * I suppose it's actually to switch them all off & reset,
2148 * let's assume off is what we want. I'm just doing that for all major PLLs now.
2150 radeon_pm_all_ppls_off(rinfo);
2152 /* Clear tiling, reset swappers */
2153 INREG(SURFACE_CNTL);
2154 OUTREG(SURFACE_CNTL, 0);
2156 /* Some black magic with TV_DAC_CNTL, we should restore those from backups
2157 * rather than hard coding...
2159 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
2160 tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT;
2161 OUTREG(TV_DAC_CNTL, tmp);
2163 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
2164 tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT;
2165 OUTREG(TV_DAC_CNTL, tmp);
2167 OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
2169 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
2170 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
2171 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
2173 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2174 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
2175 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2177 tmp = rinfo->save_regs[1]
2178 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
2179 CLK_PWRMGT_CNTL__MC_BUSY);
2180 OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
2182 OUTREG(FW_CNTL, rinfo->save_regs[57]);
2184 /* Disable SDRAM refresh */
2185 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
2186 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
2188 /* Restore XTALIN routing (CLK_PIN_CNTL) */
2189 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
2191 /* Force MCLK to be PCI sourced and forced ON */
2192 tmp = rinfo->save_regs[2] & 0xff000000;
2193 tmp |= MCLK_CNTL__FORCE_MCLKA |
2194 MCLK_CNTL__FORCE_MCLKB |
2195 MCLK_CNTL__FORCE_YCLKA |
2196 MCLK_CNTL__FORCE_YCLKB |
2197 MCLK_CNTL__FORCE_MC |
2198 MCLK_CNTL__FORCE_AIC;
2199 OUTPLL(pllMCLK_CNTL, tmp);
2201 /* Force SCLK to be PCI sourced with a bunch forced */
2203 SCLK_CNTL__FORCE_DISP2|
2204 SCLK_CNTL__FORCE_CP|
2205 SCLK_CNTL__FORCE_HDP|
2206 SCLK_CNTL__FORCE_DISP1|
2207 SCLK_CNTL__FORCE_TOP|
2208 SCLK_CNTL__FORCE_E2|
2209 SCLK_CNTL__FORCE_SE|
2210 SCLK_CNTL__FORCE_IDCT|
2211 SCLK_CNTL__FORCE_VIP|
2212 SCLK_CNTL__FORCE_RE|
2213 SCLK_CNTL__FORCE_PB|
2214 SCLK_CNTL__FORCE_TAM|
2215 SCLK_CNTL__FORCE_TDM|
2216 SCLK_CNTL__FORCE_RB;
2217 OUTPLL(pllSCLK_CNTL, tmp);
2219 /* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL */
2220 OUTPLL(pllVCLK_ECP_CNTL, 0);
2221 OUTPLL(pllPIXCLKS_CNTL, 0);
2223 /* Setup MCLK_MISC, non dynamic mode */
2224 OUTPLL(pllMCLK_MISC,
2225 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
2226 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
2230 /* Set back the default clock dividers */
2231 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
2232 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
2233 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
2235 /* PPLL and P2PLL default values & off */
2236 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
2237 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
2239 /* S and M PLLs are reset & off, configure them */
2240 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
2241 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
2243 /* Default values for MDLL ... fixme */
2244 OUTPLL(pllMDLL_CKO, 0x9c009c);
2245 OUTPLL(pllMDLL_RDCKA, 0x08830883);
2246 OUTPLL(pllMDLL_RDCKB, 0x08830883);
2249 /* Restore PLL_PWRMGT_CNTL */ // XXXX
2250 tmp = rinfo->save_regs[0];
2251 tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK;
2252 tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2253 OUTPLL(PLL_PWRMGT_CNTL, tmp);
2255 /* Clear HTOTAL_CNTL & HTOTAL2_CNTL */
2256 OUTPLL(pllHTOTAL_CNTL, 0);
2257 OUTPLL(pllHTOTAL2_CNTL, 0);
2259 /* All outputs off */
2260 OUTREG(CRTC_GEN_CNTL, 0x04000000);
2261 OUTREG(CRTC2_GEN_CNTL, 0x04000000);
2262 OUTREG(FP_GEN_CNTL, 0x00004008);
2263 OUTREG(FP2_GEN_CNTL, 0x00000008);
2264 OUTREG(LVDS_GEN_CNTL, 0x08000008);
2266 /* Restore Memory Controller configuration */
2267 radeon_pm_m9p_reconfigure_mc(rinfo);
2269 /* Now we actually start MCLK and SCLK */
2270 radeon_pm_start_mclk_sclk(rinfo);
2272 /* Full reset sdrams, this also re-inits the MDLL */
2273 radeon_pm_full_reset_sdram(rinfo);
2276 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
2277 for (i=0; i<256; i++)
2278 OUTREG(PALETTE_30_DATA, 0x15555555);
2279 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
2281 for (i=0; i<256; i++)
2282 OUTREG(PALETTE_30_DATA, 0x15555555);
2284 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
2287 /* Restore TV stuff, make sure TV DAC is down */
2288 OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
2289 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
2291 /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits,
2292 * possibly related to the weird PLL related workarounds and to the
2293 * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand,
2294 * but we keep things the simple way here
2296 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2297 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2298 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2300 /* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy
2301 * high bits from backup
2303 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2304 tmp |= rinfo->save_regs[34] & 0xffff0000;
2305 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2306 OUTPLL(pllSCLK_MORE_CNTL, tmp);
2308 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2309 tmp |= rinfo->save_regs[34] & 0xffff0000;
2310 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2311 OUTPLL(pllSCLK_MORE_CNTL, tmp);
2313 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2314 ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
2315 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON);
2316 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2319 /* write some stuff to the framebuffer... */
2320 for (i = 0; i < 0x8000; ++i)
2321 writeb(0, rinfo->fb_base + i);
2323 OUTREG(0x2ec, 0x6332a020);
2324 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
2325 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
2326 tmp = INPLL(pllSSPLL_CNTL);
2328 OUTPLL(pllSSPLL_CNTL, tmp);
2331 OUTPLL(pllSSPLL_CNTL, tmp);
2334 OUTPLL(pllSSPLL_CNTL, tmp);
2337 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
2338 OUTREG(0x2ec, 0x6332a3f0);
2341 OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);;
2342 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
2345 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
2348 /* Restore a few more things */
2349 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2350 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2352 /* Restore PPLL, spread spectrum & LVDS */
2353 radeon_pm_m10_disable_spread_spectrum(rinfo);
2354 radeon_pm_restore_pixel_pll(rinfo);
2355 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2358 #if 0 /* Not ready yet */
2359 static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
2366 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2367 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2368 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2369 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2370 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2371 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2373 INREG(PAD_CTLR_STRENGTH);
2374 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2375 for (i = 0; i < 65; ++i) {
2377 INREG(PAD_CTLR_STRENGTH);
2380 OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2381 OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2382 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2383 OUTREG(DAC_CNTL, 0xff00410a);
2384 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2385 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2387 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2388 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2389 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2390 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2392 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
2393 OUTREG(MC_IND_INDEX, 0);
2394 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
2395 OUTREG(MC_IND_INDEX, 0);
2397 OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2399 tmp = INPLL(pllVCLK_ECP_CNTL);
2400 OUTPLL(pllVCLK_ECP_CNTL, tmp);
2401 tmp = INPLL(pllPIXCLKS_CNTL);
2402 OUTPLL(pllPIXCLKS_CNTL, tmp);
2404 OUTPLL(MCLK_CNTL, 0xaa3f0000);
2405 OUTPLL(SCLK_CNTL, 0xffff0000);
2406 OUTPLL(pllMPLL_AUX_CNTL, 6);
2407 OUTPLL(pllSPLL_AUX_CNTL, 1);
2408 OUTPLL(MDLL_CKO, 0x9f009f);
2409 OUTPLL(MDLL_RDCKA, 0x830083);
2410 OUTPLL(pllMDLL_RDCKB, 0x830083);
2411 OUTPLL(PPLL_CNTL, 0xa433);
2412 OUTPLL(P2PLL_CNTL, 0xa433);
2413 OUTPLL(MPLL_CNTL, 0x0400a403);
2414 OUTPLL(SPLL_CNTL, 0x0400a433);
2416 tmp = INPLL(M_SPLL_REF_FB_DIV);
2417 OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2418 tmp = INPLL(M_SPLL_REF_FB_DIV);
2419 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2420 INPLL(M_SPLL_REF_FB_DIV);
2422 tmp = INPLL(MPLL_CNTL);
2423 OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2424 radeon_pll_errata_after_index(rinfo);
2425 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2426 radeon_pll_errata_after_data(rinfo);
2428 tmp = INPLL(M_SPLL_REF_FB_DIV);
2429 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2431 tmp = INPLL(MPLL_CNTL);
2432 OUTPLL(MPLL_CNTL, tmp & ~0x2);
2434 tmp = INPLL(MPLL_CNTL);
2435 OUTPLL(MPLL_CNTL, tmp & ~0x1);
2438 OUTPLL(MCLK_CNTL, 0xaa3f1212);
2441 INPLL(M_SPLL_REF_FB_DIV);
2443 INPLL(M_SPLL_REF_FB_DIV);
2445 tmp = INPLL(SPLL_CNTL);
2446 OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2447 radeon_pll_errata_after_index(rinfo);
2448 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2449 radeon_pll_errata_after_data(rinfo);
2451 tmp = INPLL(M_SPLL_REF_FB_DIV);
2452 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2454 tmp = INPLL(SPLL_CNTL);
2455 OUTPLL(SPLL_CNTL, tmp & ~0x1);
2457 tmp = INPLL(SPLL_CNTL);
2458 OUTPLL(SPLL_CNTL, tmp & ~0x2);
2461 tmp = INPLL(SCLK_CNTL);
2462 OUTPLL(SCLK_CNTL, tmp | 2);
2465 cko = INPLL(pllMDLL_CKO);
2466 cka = INPLL(pllMDLL_RDCKA);
2467 ckb = INPLL(pllMDLL_RDCKB);
2469 cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
2470 OUTPLL(pllMDLL_CKO, cko);
2472 cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
2473 OUTPLL(pllMDLL_CKO, cko);
2476 cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
2477 OUTPLL(pllMDLL_RDCKA, cka);
2479 cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
2480 OUTPLL(pllMDLL_RDCKA, cka);
2483 ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
2484 OUTPLL(pllMDLL_RDCKB, ckb);
2486 ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
2487 OUTPLL(pllMDLL_RDCKB, ckb);
2490 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
2491 OUTREG(MC_IND_INDEX, 0);
2492 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
2493 OUTREG(MC_IND_INDEX, 0);
2495 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
2496 OUTREG(MC_IND_INDEX, 0);
2497 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
2498 OUTREG(MC_IND_INDEX, 0);
2501 OUTPLL(pllHTOTAL_CNTL, 0);
2502 OUTPLL(pllHTOTAL2_CNTL, 0);
2504 OUTREG(MEM_CNTL, 0x29002901);
2505 OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */
2506 OUTREG(EXT_MEM_CNTL, 0x1a394333);
2507 OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
2508 OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
2509 OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218); /* XXX or save_regs[42]? */
2510 OUTREG(MC_DEBUG, 0);
2511 OUTREG(MEM_IO_OE_CNTL, 0x04300430);
2513 OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
2514 OUTREG(MC_IND_INDEX, 0);
2515 OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
2516 OUTREG(MC_IND_INDEX, 0);
2518 OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
2520 radeon_pm_full_reset_sdram(rinfo);
2523 OUTREG(TMDS_CNTL, 0x01000000); /* XXX ? */
2524 tmp = INREG(FP_GEN_CNTL);
2525 tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
2526 OUTREG(FP_GEN_CNTL, tmp);
2528 tmp = INREG(DISP_OUTPUT_CNTL);
2530 OUTREG(DISP_OUTPUT_CNTL, tmp);
2532 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2533 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2534 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2536 tmp = INPLL(MCLK_MISC);
2537 tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
2538 OUTPLL(MCLK_MISC, tmp);
2540 tmp = INPLL(SCLK_CNTL);
2541 OUTPLL(SCLK_CNTL, tmp);
2543 OUTREG(CRTC_MORE_CNTL, 0);
2544 OUTREG8(CRTC_GEN_CNTL+1, 6);
2545 OUTREG8(CRTC_GEN_CNTL+3, 1);
2546 OUTREG(CRTC_PITCH, 32);
2548 tmp = INPLL(VCLK_ECP_CNTL);
2549 OUTPLL(VCLK_ECP_CNTL, tmp);
2551 tmp = INPLL(PPLL_CNTL);
2552 OUTPLL(PPLL_CNTL, tmp);
2554 /* palette stuff and BIOS_1_SCRATCH... */
2556 tmp = INREG(FP_GEN_CNTL);
2557 tmp2 = INREG(TMDS_TRANSMITTER_CNTL);
2559 OUTREG(FP_GEN_CNTL, tmp);
2561 OUTREG(FP_GEN_CNTL, tmp);
2563 OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
2564 OUTREG(CRTC_MORE_CNTL, 0);
2567 tmp = INREG(CRTC_MORE_CNTL);
2568 OUTREG(CRTC_MORE_CNTL, tmp);
2570 cgc = INREG(CRTC_GEN_CNTL);
2571 cec = INREG(CRTC_EXT_CNTL);
2572 c2gc = INREG(CRTC2_GEN_CNTL);
2574 OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
2575 OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
2576 OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2577 radeon_pll_errata_after_index(rinfo);
2578 OUTREG8(CLOCK_CNTL_DATA, 0);
2579 radeon_pll_errata_after_data(rinfo);
2580 OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
2581 OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
2582 OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
2583 OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
2584 OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
2585 OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
2586 OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
2587 OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
2588 OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
2589 OUTREG(FP_HORZ_STRETCH, 0);
2590 OUTREG(FP_VERT_STRETCH, 0);
2592 OUTREG(OVR_WID_LEFT_RIGHT, 0);
2593 OUTREG(OVR_WID_TOP_BOTTOM, 0);
2595 tmp = INPLL(PPLL_REF_DIV);
2596 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2597 OUTPLL(PPLL_REF_DIV, tmp);
2598 INPLL(PPLL_REF_DIV);
2600 OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2601 radeon_pll_errata_after_index(rinfo);
2602 OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc);
2603 radeon_pll_errata_after_data(rinfo);
2605 tmp = INREG(CLOCK_CNTL_INDEX);
2606 radeon_pll_errata_after_index(rinfo);
2607 OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2608 radeon_pll_errata_after_index(rinfo);
2609 radeon_pll_errata_after_data(rinfo);
2611 OUTPLL(PPLL_DIV_0, 0x48090);
2613 tmp = INPLL(PPLL_CNTL);
2614 OUTPLL(PPLL_CNTL, tmp & ~0x2);
2616 tmp = INPLL(PPLL_CNTL);
2617 OUTPLL(PPLL_CNTL, tmp & ~0x1);
2620 tmp = INPLL(VCLK_ECP_CNTL);
2621 OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2624 tmp = INPLL(VCLK_ECP_CNTL);
2625 OUTPLL(VCLK_ECP_CNTL, tmp);
2627 c2gc |= CRTC2_DISP_REQ_EN_B;
2628 OUTREG(CRTC2_GEN_CNTL, c2gc);
2630 OUTREG(CRTC_GEN_CNTL, cgc);
2631 OUTREG(CRTC_EXT_CNTL, cec);
2632 OUTREG(CRTC_PITCH, 0xa0);
2633 OUTREG(CRTC_OFFSET, 0);
2634 OUTREG(CRTC_OFFSET_CNTL, 0);
2636 OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
2637 OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
2639 tmp2 = INREG(FP_GEN_CNTL);
2640 tmp = INREG(TMDS_TRANSMITTER_CNTL);
2641 OUTREG(0x2a8, 0x0000061b);
2643 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2645 tmp &= ~TMDS_PLLRST;
2646 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2649 OUTREG(FP_GEN_CNTL, tmp2);
2652 OUTREG(FP_GEN_CNTL, tmp2);
2654 OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
2655 cgc = INREG(CRTC_GEN_CNTL);
2656 OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
2658 OUTREG(CUR_OFFSET, 0);
2662 #endif /* CONFIG_PPC_OF */
2664 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2673 /* Set the chip into appropriate suspend mode (we use D2,
2674 * D3 would require a compete re-initialization of the chip,
2675 * including PCI config registers, clocks, AGP conf, ...)
2678 printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n",
2679 pci_name(rinfo->pdev));
2681 /* Disable dynamic power management of clocks for the
2682 * duration of the suspend/resume process
2684 radeon_pm_disable_dynamic_mode(rinfo);
2686 /* Save some registers */
2687 radeon_pm_save_regs(rinfo, 0);
2689 /* Prepare mobility chips for suspend.
2691 if (rinfo->is_mobility) {
2693 radeon_pm_program_v2clk(rinfo);
2695 /* Disable IO PADs */
2696 radeon_pm_disable_iopad(rinfo);
2698 /* Set low current */
2699 radeon_pm_low_current(rinfo);
2701 /* Prepare chip for power management */
2702 radeon_pm_setup_for_suspend(rinfo);
2704 if (rinfo->family <= CHIP_FAMILY_RV280) {
2705 /* Reset the MDLL */
2706 /* because both INPLL and OUTPLL take the same
2707 * lock, that's why. */
2708 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET
2709 | MDLL_CKO__MCKOB_RESET;
2710 OUTPLL( pllMDLL_CKO, tmp );
2714 for (i = 0; i < 64; ++i)
2715 pci_read_config_dword(rinfo->pdev, i * 4,
2716 &rinfo->cfg_save[i]);
2718 /* Switch PCI power managment to D2. */
2719 pci_disable_device(rinfo->pdev);
2721 pci_read_config_word(
2722 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2726 pci_write_config_word(
2727 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2728 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2732 printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n",
2733 pci_name(rinfo->pdev));
2735 /* Switch back PCI powermanagment to D0 */
2737 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2740 if (rinfo->family <= CHIP_FAMILY_RV250) {
2741 /* Reset the SDRAM controller */
2742 radeon_pm_full_reset_sdram(rinfo);
2744 /* Restore some registers */
2745 radeon_pm_restore_regs(rinfo);
2747 /* Restore registers first */
2748 radeon_pm_restore_regs(rinfo);
2749 /* init sdram controller */
2750 radeon_pm_full_reset_sdram(rinfo);
2755 static int radeon_restore_pci_cfg(struct radeonfb_info *rinfo)
2758 static u32 radeon_cfg_after_resume[64];
2760 for (i = 0; i < 64; ++i)
2761 pci_read_config_dword(rinfo->pdev, i * 4,
2762 &radeon_cfg_after_resume[i]);
2764 if (radeon_cfg_after_resume[PCI_BASE_ADDRESS_0/4]
2765 == rinfo->cfg_save[PCI_BASE_ADDRESS_0/4])
2766 return 0; /* assume everything is ok */
2768 for (i = PCI_BASE_ADDRESS_0/4; i < 64; ++i) {
2769 if (radeon_cfg_after_resume[i] != rinfo->cfg_save[i])
2770 pci_write_config_dword(rinfo->pdev, i * 4,
2771 rinfo->cfg_save[i]);
2773 pci_write_config_word(rinfo->pdev, PCI_CACHE_LINE_SIZE,
2774 rinfo->cfg_save[PCI_CACHE_LINE_SIZE/4]);
2775 pci_write_config_word(rinfo->pdev, PCI_COMMAND,
2776 rinfo->cfg_save[PCI_COMMAND/4]);
2781 int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2783 struct fb_info *info = pci_get_drvdata(pdev);
2784 struct radeonfb_info *rinfo = info->par;
2787 if (state == pdev->dev.power.power_state)
2790 printk(KERN_DEBUG "radeonfb (%s): suspending to state: %d...\n",
2791 pci_name(pdev), state);
2793 /* For suspend-to-disk, we cheat here. We don't suspend anything and
2794 * let fbcon continue drawing until we are all set. That shouldn't
2795 * really cause any problem at this point, provided that the wakeup
2796 * code knows that any state in memory may not match the HW
2798 if (state != PM_SUSPEND_MEM)
2801 acquire_console_sem();
2803 fb_set_suspend(info, 1);
2805 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2806 /* Make sure engine is reset */
2807 radeon_engine_idle();
2808 radeonfb_engine_reset(rinfo);
2809 radeon_engine_idle();
2812 /* Blank display and LCD */
2813 radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
2817 rinfo->lock_blank = 1;
2818 del_timer_sync(&rinfo->lvds_timer);
2820 #ifdef CONFIG_PPC_PMAC
2821 /* On powermac, we have hooks to properly suspend/resume AGP now,
2822 * use them here. We'll ultimately need some generic support here,
2823 * but the generic code isn't quite ready for that yet
2825 pmac_suspend_agp_for_card(pdev);
2826 #endif /* CONFIG_PPC_PMAC */
2828 /* If we support wakeup from poweroff, we save all regs we can including cfg
2831 if (rinfo->pm_mode & radeon_pm_off) {
2832 /* Always disable dynamic clocks or weird things are happening when
2833 * the chip goes off (basically the panel doesn't shut down properly
2834 * and we crash on wakeup),
2835 * also, we want the saved regs context to have no dynamic clocks in
2836 * it, we'll restore the dynamic clocks state on wakeup
2838 radeon_pm_disable_dynamic_mode(rinfo);
2840 radeon_pm_save_regs(rinfo, 1);
2842 if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
2843 /* Switch off LVDS interface */
2845 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN));
2847 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON));
2848 OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000);
2850 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON));
2852 // FIXME: Use PCI layer
2853 for (i = 0; i < 64; ++i)
2854 pci_read_config_dword(pdev, i * 4, &rinfo->cfg_save[i]);
2855 pci_disable_device(pdev);
2857 /* If we support D2, we go to it (should be fixed later with a flag forcing
2858 * D3 only for some laptops)
2860 if (rinfo->pm_mode & radeon_pm_d2)
2861 radeon_set_suspend(rinfo, 1);
2863 release_console_sem();
2866 pdev->dev.power.power_state = state;
2871 int radeonfb_pci_resume(struct pci_dev *pdev)
2873 struct fb_info *info = pci_get_drvdata(pdev);
2874 struct radeonfb_info *rinfo = info->par;
2877 if (pdev->dev.power.power_state == 0)
2880 if (rinfo->no_schedule) {
2881 if (try_acquire_console_sem())
2884 acquire_console_sem();
2886 printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n",
2887 pci_name(pdev), pdev->dev.power.power_state);
2890 if (pci_enable_device(pdev)) {
2892 printk(KERN_ERR "radeonfb (%s): can't enable PCI device !\n",
2896 pci_set_master(pdev);
2898 if (pdev->dev.power.power_state == PM_SUSPEND_MEM) {
2899 /* Wakeup chip. Check from config space if we were powered off
2900 * (todo: additionally, check CLK_PIN_CNTL too)
2902 if ((rinfo->pm_mode & radeon_pm_off) && radeon_restore_pci_cfg(rinfo)) {
2903 if (rinfo->reinit_func != NULL)
2904 rinfo->reinit_func(rinfo);
2906 printk(KERN_ERR "radeonfb (%s): can't resume radeon from"
2907 " D3 cold, need softboot !", pci_name(pdev));
2912 /* If we support D2, try to resume... we should check what was our
2913 * state though... (were we really in D2 state ?). Right now, this code
2914 * is only enable on Macs so it's fine.
2916 else if (rinfo->pm_mode & radeon_pm_d2)
2917 radeon_set_suspend(rinfo, 0);
2921 radeon_engine_idle();
2923 /* Restore display & engine */
2924 radeon_write_mode (rinfo, &rinfo->state, 1);
2925 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
2926 radeonfb_engine_init (rinfo);
2928 fb_pan_display(info, &info->var);
2929 fb_set_cmap(&info->cmap, info);
2932 fb_set_suspend(info, 0);
2935 rinfo->lock_blank = 0;
2936 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
2938 #ifdef CONFIG_PPC_PMAC
2939 /* On powermac, we have hooks to properly suspend/resume AGP now,
2940 * use them here. We'll ultimately need some generic support here,
2941 * but the generic code isn't quite ready for that yet
2943 pmac_resume_agp_for_card(pdev);
2944 #endif /* CONFIG_PPC_PMAC */
2947 /* Check status of dynclk */
2948 if (rinfo->dynclk == 1)
2949 radeon_pm_enable_dynamic_mode(rinfo);
2950 else if (rinfo->dynclk == 0)
2951 radeon_pm_disable_dynamic_mode(rinfo);
2953 pdev->dev.power.power_state = PMSG_ON;
2956 release_console_sem();
2961 #ifdef CONFIG_PPC_OF
2962 static void radeonfb_early_resume(void *data)
2964 struct radeonfb_info *rinfo = data;
2966 rinfo->no_schedule = 1;
2967 radeonfb_pci_resume(rinfo->pdev);
2968 rinfo->no_schedule = 0;
2970 #endif /* CONFIG_PPC_OF */
2972 #endif /* CONFIG_PM */
2974 void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk)
2976 /* Find PM registers in config space if any*/
2977 rinfo->pm_reg = pci_find_capability(rinfo->pdev, PCI_CAP_ID_PM);
2979 /* Enable/Disable dynamic clocks: TODO add sysfs access */
2980 rinfo->dynclk = dynclk;
2982 radeon_pm_enable_dynamic_mode(rinfo);
2983 printk("radeonfb: Dynamic Clock Power Management enabled\n");
2984 } else if (dynclk == 0) {
2985 radeon_pm_disable_dynamic_mode(rinfo);
2986 printk("radeonfb: Dynamic Clock Power Management disabled\n");
2989 /* Check if we can power manage on suspend/resume. We can do
2990 * D2 on M6, M7 and M9, and we can resume from D3 cold a few other
2991 * "Mac" cards, but that's all. We need more infos about what the
2992 * BIOS does tho. Right now, all this PM stuff is pmac-only for that
2995 #if defined(CONFIG_PM) && defined(CONFIG_PPC_OF)
2996 if (_machine == _MACH_Pmac && rinfo->of_node) {
2997 if (rinfo->is_mobility && rinfo->pm_reg &&
2998 rinfo->family <= CHIP_FAMILY_RV250)
2999 rinfo->pm_mode |= radeon_pm_d2;
3001 /* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip
3002 * in some desktop G4s), and Via (M9+ chip on iBook G4)
3004 if (!strcmp(rinfo->of_node->name, "ATY,JasperParent")) {
3005 rinfo->reinit_func = radeon_reinitialize_M10;
3006 rinfo->pm_mode |= radeon_pm_off;
3008 #if 0 /* Not ready yet */
3009 if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
3010 rinfo->reinit_func = radeon_reinitialize_QW;
3011 rinfo->pm_mode |= radeon_pm_off;
3014 if (!strcmp(rinfo->of_node->name, "ATY,ViaParent")) {
3015 rinfo->reinit_func = radeon_reinitialize_M9P;
3016 rinfo->pm_mode |= radeon_pm_off;
3019 /* If any of the above is set, we assume the machine can sleep/resume.
3020 * It's a bit of a "shortcut" but will work fine. Ideally, we need infos
3021 * from the platform about what happens to the chip...
3022 * Now we tell the platform about our capability
3024 if (rinfo->pm_mode != radeon_pm_none) {
3025 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
3026 pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
3030 /* Power down TV DAC, taht saves a significant amount of power,
3031 * we'll have something better once we actually have some TVOut
3034 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
3037 #endif /* defined(CONFIG_PM) && defined(CONFIG_PPC_OF) */
3039 /* The PM code also works on some PC laptops.
3040 * Only a few models are actually tested so Your mileage may vary.
3041 * We can do D2 on at least M7 and M9 on some IBM ThinkPad T41 models.
3043 #if defined(CONFIG_PM) && defined(CONFIG_X86)
3044 if (radeon_force_sleep || dmi_check_system(radeonfb_dmi_table)) {
3045 if (radeon_force_sleep)
3046 printk("radeonfb: forcefully enabling sleep mode\n");
3048 printk("radeonfb: enabling sleep mode\n");
3050 if (rinfo->is_mobility && rinfo->pm_reg &&
3051 rinfo->family <= CHIP_FAMILY_RV250)
3052 rinfo->pm_mode |= radeon_pm_d2;
3054 /* Power down TV DAC, that saves a significant amount of power,
3055 * we'll have something better once we actually have some TVOut
3058 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
3060 #endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */
3063 void radeonfb_pm_exit(struct radeonfb_info *rinfo)
3065 #if defined(CONFIG_PM) && defined(CONFIG_PPC_OF)
3066 if (rinfo->pm_mode != radeon_pm_none)
3067 pmac_set_early_video_resume(NULL, NULL);