2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #define CIRRUSFB_VERSION "2.0-pre2"
39 #include <linux/config.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/errno.h>
43 #include <linux/string.h>
45 #include <linux/tty.h>
46 #include <linux/slab.h>
47 #include <linux/delay.h>
49 #include <linux/init.h>
50 #include <linux/selection.h>
51 #include <asm/pgtable.h>
54 #include <linux/zorro.h>
57 #include <linux/pci.h>
60 #include <asm/amigahw.h>
62 #ifdef CONFIG_PPC_PREP
63 #include <asm/processor.h>
64 #define isPReP (_machine == _MACH_prep)
69 #include "video/vga.h"
70 #include "video/cirrus.h"
73 /*****************************************************************
75 * debugging and utility macros
79 /* enable debug output? */
80 /* #define CIRRUSFB_DEBUG 1 */
82 /* disable runtime assertions? */
83 /* #define CIRRUSFB_NDEBUG */
87 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
89 #define DPRINTK(fmt, args...)
92 /* debugging assertions */
93 #ifndef CIRRUSFB_NDEBUG
94 #define assert(expr) \
96 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
97 #expr,__FILE__,__FUNCTION__,__LINE__); \
112 #define MB_ (1024*1024)
115 #define MAX_NUM_BOARDS 7
118 /*****************************************************************
120 * chipset information
131 BT_PICASSO4, /* GD5446 */
132 BT_ALPINE, /* GD543x/4x */
134 BT_LAGUNA, /* GD546x */
139 * per-board-type information, used for enumerating and abstracting
140 * chip-specific information
141 * NOTE: MUST be in the same order as cirrusfb_board_t in order to
142 * use direct indexing on this array
143 * NOTE: '__initdata' cannot be used as some of this info
144 * is required at runtime. Maybe separate into an init-only and
147 static const struct cirrusfb_board_info_rec {
148 cirrusfb_board_t btype; /* chipset enum, not strictly necessary, as
149 * cirrusfb_board_info[] is directly indexed
151 char *name; /* ASCII name of chipset */
152 long maxclock[5]; /* maximum video clock */
153 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
154 unsigned init_sr07 : 1; /* init SR07 during init_vgachip() */
155 unsigned init_sr1f : 1; /* write SR1F during init_vgachip() */
156 unsigned scrn_start_bit19 : 1; /* construct bit 19 of screen start address */
158 /* initial SR07 value, then for each mode */
160 unsigned char sr07_1bpp;
161 unsigned char sr07_1bpp_mux;
162 unsigned char sr07_8bpp;
163 unsigned char sr07_8bpp_mux;
165 unsigned char sr1f; /* SR1F VGA initial register value */
166 } cirrusfb_board_info[] = {
167 { BT_NONE, }, /* dummy record */
170 { 140000, 140000, 140000, 140000, 140000, }, /* guess */
171 /* the SD64/P4 have a higher max. videoclock */
177 0, /* unused, does not multiplex */
179 0, /* unused, does not multiplex */
183 { 90000, 90000, 90000, 90000, 90000 }, /* guess */
189 0, /* unused, does not multiplex */
191 0, /* unused, does not multiplex */
195 { 90000, 90000, 90000, 90000, 90000, }, /* guess */
201 0, /* unused, does not multiplex */
203 0, /* unused, does not multiplex */
207 { 90000, 90000, 90000, 90000, 90000, }, /* guess */
213 0, /* unused, does not multiplex */
215 0, /* unused, does not multiplex */
219 { 135100, 135100, 85500, 85500, 0 },
225 0, /* unused, does not multiplex */
227 0, /* unused, does not multiplex */
231 { 85500, 85500, 50000, 28500, 0}, /* for the GD5430. GD5446 can do more... */
243 { 135100, 200000, 200000, 135100, 135100 },
249 0, /* unused, does not multiplex */
251 0, /* unused, does not multiplex */
255 { 135100, 135100, 135100, 135100, 135100, }, /* guess */
269 #define CHIP(id, btype) \
270 { PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_##id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
272 static struct pci_device_id cirrusfb_pci_table[] = {
273 CHIP( CIRRUS_5436, BT_ALPINE ),
274 CHIP( CIRRUS_5434_8, BT_ALPINE ),
275 CHIP( CIRRUS_5434_4, BT_ALPINE ),
276 CHIP( CIRRUS_5430, BT_ALPINE ), /* GD-5440 has identical id */
277 CHIP( CIRRUS_7543, BT_ALPINE ),
278 CHIP( CIRRUS_7548, BT_ALPINE ),
279 CHIP( CIRRUS_5480, BT_GD5480 ), /* MacPicasso probably */
280 CHIP( CIRRUS_5446, BT_PICASSO4 ), /* Picasso 4 is a GD5446 */
281 CHIP( CIRRUS_5462, BT_LAGUNA ), /* CL Laguna */
282 CHIP( CIRRUS_5464, BT_LAGUNA ), /* CL Laguna 3D */
283 CHIP( CIRRUS_5465, BT_LAGUNA ), /* CL Laguna 3DA*/
286 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
288 #endif /* CONFIG_PCI */
292 static const struct {
293 cirrusfb_board_t btype;
296 } cirrusfb_zorro_probe_list[] __initdata = {
298 ZORRO_PROD_HELFRICH_SD64_RAM,
299 ZORRO_PROD_HELFRICH_SD64_REG,
302 ZORRO_PROD_HELFRICH_PICCOLO_RAM,
303 ZORRO_PROD_HELFRICH_PICCOLO_REG,
306 ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
307 ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
310 ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
311 ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
314 ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
318 #endif /* CONFIG_ZORRO */
321 struct cirrusfb_regs {
322 __u32 line_length; /* in BYTES! */
334 long HorizRes; /* The x resolution in pixel */
337 long HorizBlankStart;
342 long VertRes; /* the physical y resolution in scanlines */
353 #ifdef CIRRUSFB_DEBUG
357 } cirrusfb_dbg_reg_class_t;
358 #endif /* CIRRUSFB_DEBUG */
363 /* info about board */
364 struct cirrusfb_info {
365 struct fb_info *info;
371 cirrusfb_board_t btype;
372 unsigned char SFR; /* Shadow of special function register */
374 unsigned long fbmem_phys;
375 unsigned long fbregs_phys;
377 struct cirrusfb_regs currentmode;
380 u32 pseudo_palette[17];
381 struct { u8 red, green, blue, pad; } palette[256];
384 unsigned long board_addr,
389 struct pci_dev *pdev;
394 static unsigned cirrusfb_def_mode = 1;
395 static int noaccel = 0;
398 * Predefined Video Modes
401 static const struct {
403 struct fb_var_screeninfo var;
404 } cirrusfb_predefined[] =
407 {"Autodetect", /* autodetect mode */
411 {"640x480", /* 640x480, 31.25 kHz, 60 Hz, 25 MHz PixClock */
413 640, 480, 640, 480, 0, 0, 8, 0,
418 0, 0, -1, -1, FB_ACCEL_NONE, 40000, 48, 16, 32, 8, 96, 4,
419 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
423 {"800x600", /* 800x600, 48 kHz, 76 Hz, 50 MHz PixClock */
425 800, 600, 800, 600, 0, 0, 8, 0,
430 0, 0, -1, -1, FB_ACCEL_NONE, 20000, 128, 16, 24, 2, 96, 6,
431 0, FB_VMODE_NONINTERLACED
436 Modeline from XF86Config:
437 Mode "1024x768" 80 1024 1136 1340 1432 768 770 774 805
439 {"1024x768", /* 1024x768, 55.8 kHz, 70 Hz, 80 MHz PixClock */
441 1024, 768, 1024, 768, 0, 0, 8, 0,
446 0, 0, -1, -1, FB_ACCEL_NONE, 12500, 144, 32, 30, 2, 192, 6,
447 0, FB_VMODE_NONINTERLACED
452 #define NUM_TOTAL_MODES ARRAY_SIZE(cirrusfb_predefined)
454 /****************************************************************************/
455 /**** BEGIN PROTOTYPES ******************************************************/
458 /*--- Interface used by the world ------------------------------------------*/
459 int cirrusfb_init (void);
460 int cirrusfb_setup (char *options);
462 int cirrusfb_open (struct fb_info *info, int user);
463 int cirrusfb_release (struct fb_info *info, int user);
464 int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
465 unsigned blue, unsigned transp,
466 struct fb_info *info);
467 int cirrusfb_check_var (struct fb_var_screeninfo *var,
468 struct fb_info *info);
469 int cirrusfb_set_par (struct fb_info *info);
470 int cirrusfb_pan_display (struct fb_var_screeninfo *var,
471 struct fb_info *info);
472 int cirrusfb_blank (int blank_mode, struct fb_info *info);
473 void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *region);
474 void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
475 void cirrusfb_imageblit(struct fb_info *info, const struct fb_image *image);
477 /* function table of the above functions */
478 static struct fb_ops cirrusfb_ops = {
479 .owner = THIS_MODULE,
480 .fb_open = cirrusfb_open,
481 .fb_release = cirrusfb_release,
482 .fb_setcolreg = cirrusfb_setcolreg,
483 .fb_check_var = cirrusfb_check_var,
484 .fb_set_par = cirrusfb_set_par,
485 .fb_pan_display = cirrusfb_pan_display,
486 .fb_blank = cirrusfb_blank,
487 .fb_fillrect = cirrusfb_fillrect,
488 .fb_copyarea = cirrusfb_copyarea,
489 .fb_imageblit = cirrusfb_imageblit,
490 .fb_cursor = soft_cursor,
493 /*--- Hardware Specific Routines -------------------------------------------*/
494 static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
495 struct cirrusfb_regs *regs,
496 const struct fb_info *info);
497 /*--- Internal routines ----------------------------------------------------*/
498 static void init_vgachip (struct cirrusfb_info *cinfo);
499 static void switch_monitor (struct cirrusfb_info *cinfo, int on);
500 static void WGen (const struct cirrusfb_info *cinfo,
501 int regnum, unsigned char val);
502 static unsigned char RGen (const struct cirrusfb_info *cinfo, int regnum);
503 static void AttrOn (const struct cirrusfb_info *cinfo);
504 static void WHDR (const struct cirrusfb_info *cinfo, unsigned char val);
505 static void WSFR (struct cirrusfb_info *cinfo, unsigned char val);
506 static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char val);
507 static void WClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
511 static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
512 unsigned char *green,
513 unsigned char *blue);
515 static void cirrusfb_WaitBLT (caddr_t regbase);
516 static void cirrusfb_BitBLT (caddr_t regbase, int bits_per_pixel,
517 u_short curx, u_short cury,
518 u_short destx, u_short desty,
519 u_short width, u_short height,
520 u_short line_length);
521 static void cirrusfb_RectFill (caddr_t regbase, int bits_per_pixel,
522 u_short x, u_short y,
523 u_short width, u_short height,
524 u_char color, u_short line_length);
526 static void bestclock (long freq, long *best,
527 long *nom, long *den,
528 long *div, long maxfreq);
530 #ifdef CIRRUSFB_DEBUG
531 static void cirrusfb_dump (void);
532 static void cirrusfb_dbg_reg_dump (caddr_t regbase);
533 static void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_class,...);
534 static void cirrusfb_dbg_print_byte (const char *name, unsigned char val);
535 #endif /* CIRRUSFB_DEBUG */
537 /*** END PROTOTYPES ********************************************************/
538 /*****************************************************************************/
539 /*** BEGIN Interface Used by the World ***************************************/
541 static int opencount = 0;
543 /*--- Open /dev/fbx ---------------------------------------------------------*/
544 int cirrusfb_open (struct fb_info *info, int user)
546 if (opencount++ == 0)
547 switch_monitor (info->par, 1);
551 /*--- Close /dev/fbx --------------------------------------------------------*/
552 int cirrusfb_release (struct fb_info *info, int user)
554 if (--opencount == 0)
555 switch_monitor (info->par, 0);
559 /**** END Interface used by the World *************************************/
560 /****************************************************************************/
561 /**** BEGIN Hardware specific Routines **************************************/
563 /* Get a good MCLK value */
564 static long cirrusfb_get_mclk (long freq, int bpp, long *div)
568 assert (div != NULL);
570 /* Calculate MCLK, in case VCLK is high enough to require > 50MHz.
571 * Assume a 64-bit data path for now. The formula is:
572 * ((B * PCLK * 2)/W) * 1.2
573 * B = bytes per pixel, PCLK = pixclock, W = data width in bytes */
574 mclk = ((bpp / 8) * freq * 2) / 4;
575 mclk = (mclk * 12) / 10;
578 DPRINTK ("Use MCLK of %ld kHz\n", mclk);
580 /* Calculate value for SR1F. Multiply by 2 so we can round up. */
581 mclk = ((mclk * 16) / 14318);
582 mclk = (mclk + 1) / 2;
583 DPRINTK ("Set SR1F[5:0] to 0x%lx\n", mclk);
585 /* Determine if we should use MCLK instead of VCLK, and if so, what we
586 * should divide it by to get VCLK */
588 case 24751 ... 25249:
590 DPRINTK ("Using VCLK = MCLK/2\n");
592 case 49501 ... 50499:
594 DPRINTK ("Using VCLK = MCLK\n");
604 int cirrusfb_check_var(struct fb_var_screeninfo *var,
605 struct fb_info *info)
607 struct cirrusfb_info *cinfo = info->par;
608 int nom, den; /* translyting from pixels->bytes */
610 static struct { int xres, yres; } modes[] =
618 switch (var->bits_per_pixel) {
620 var->bits_per_pixel = 1;
623 break; /* 8 pixel per byte, only 1/4th of mem usable */
625 var->bits_per_pixel = 8;
628 break; /* 1 pixel == 1 byte */
630 var->bits_per_pixel = 16;
633 break; /* 2 bytes per pixel */
635 var->bits_per_pixel = 24;
638 break; /* 3 bytes per pixel */
640 var->bits_per_pixel = 32;
643 break; /* 4 bytes per pixel */
645 printk ("cirrusfb: mode %dx%dx%d rejected...color depth not supported.\n",
646 var->xres, var->yres, var->bits_per_pixel);
647 DPRINTK ("EXIT - EINVAL error\n");
651 if (var->xres * nom / den * var->yres > cinfo->size) {
652 printk ("cirrusfb: mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
653 var->xres, var->yres, var->bits_per_pixel);
654 DPRINTK ("EXIT - EINVAL error\n");
658 /* use highest possible virtual resolution */
659 if (var->xres_virtual == -1 &&
660 var->yres_virtual == -1) {
661 printk ("cirrusfb: using maximum available virtual resolution\n");
662 for (i = 0; modes[i].xres != -1; i++) {
663 if (modes[i].xres * nom / den * modes[i].yres < cinfo->size / 2)
666 if (modes[i].xres == -1) {
667 printk ("cirrusfb: could not find a virtual resolution that fits into video memory!!\n");
668 DPRINTK ("EXIT - EINVAL error\n");
671 var->xres_virtual = modes[i].xres;
672 var->yres_virtual = modes[i].yres;
674 printk ("cirrusfb: virtual resolution set to maximum of %dx%d\n",
675 var->xres_virtual, var->yres_virtual);
678 if (var->xres_virtual < var->xres)
679 var->xres_virtual = var->xres;
680 if (var->yres_virtual < var->yres)
681 var->yres_virtual = var->yres;
683 if (var->xoffset < 0)
685 if (var->yoffset < 0)
688 /* truncate xoffset and yoffset to maximum if too high */
689 if (var->xoffset > var->xres_virtual - var->xres)
690 var->xoffset = var->xres_virtual - var->xres - 1;
691 if (var->yoffset > var->yres_virtual - var->yres)
692 var->yoffset = var->yres_virtual - var->yres - 1;
694 switch (var->bits_per_pixel) {
701 var->green.offset = 0;
702 var->green.length = 6;
703 var->blue.offset = 0;
704 var->blue.length = 6;
710 var->green.offset = -3;
711 var->blue.offset = 8;
713 var->red.offset = 10;
714 var->green.offset = 5;
715 var->blue.offset = 0;
718 var->green.length = 5;
719 var->blue.length = 5;
725 var->green.offset = 16;
726 var->blue.offset = 24;
728 var->red.offset = 16;
729 var->green.offset = 8;
730 var->blue.offset = 0;
733 var->green.length = 8;
734 var->blue.length = 8;
740 var->green.offset = 16;
741 var->blue.offset = 24;
743 var->red.offset = 16;
744 var->green.offset = 8;
745 var->blue.offset = 0;
748 var->green.length = 8;
749 var->blue.length = 8;
753 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
755 /* should never occur */
760 var->green.msb_right =
761 var->blue.msb_right =
764 var->transp.msb_right = 0;
767 if (var->vmode & FB_VMODE_DOUBLE)
769 else if (var->vmode & FB_VMODE_INTERLACED)
770 yres = (yres + 1) / 2;
773 printk (KERN_WARNING "cirrusfb: ERROR: VerticalTotal >= 1280; special treatment required! (TODO)\n");
774 DPRINTK ("EXIT - EINVAL error\n");
781 static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
782 struct cirrusfb_regs *regs,
783 const struct fb_info *info)
788 struct cirrusfb_info *cinfo = info->par;
789 int xres, hfront, hsync, hback;
790 int yres, vfront, vsync, vback;
792 switch(var->bits_per_pixel) {
794 regs->line_length = var->xres_virtual / 8;
795 regs->visual = FB_VISUAL_MONO10;
800 regs->line_length = var->xres_virtual;
801 regs->visual = FB_VISUAL_PSEUDOCOLOR;
806 regs->line_length = var->xres_virtual * 2;
807 regs->visual = FB_VISUAL_DIRECTCOLOR;
812 regs->line_length = var->xres_virtual * 3;
813 regs->visual = FB_VISUAL_DIRECTCOLOR;
818 regs->line_length = var->xres_virtual * 4;
819 regs->visual = FB_VISUAL_DIRECTCOLOR;
824 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
826 /* should never occur */
830 regs->type = FB_TYPE_PACKED_PIXELS;
832 /* convert from ps to kHz */
833 freq = 1000000000 / var->pixclock;
835 DPRINTK ("desired pixclock: %ld kHz\n", freq);
837 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
838 regs->multiplexing = 0;
840 /* If the frequency is greater than we can support, we might be able
841 * to use multiplexing for the video mode */
842 if (freq > maxclock) {
843 switch (cinfo->btype) {
846 regs->multiplexing = 1;
850 printk (KERN_WARNING "cirrusfb: ERROR: Frequency greater than maxclock (%ld kHz)\n", maxclock);
851 DPRINTK ("EXIT - return -EINVAL\n");
856 /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
857 * the VCLK is double the pixel clock. */
858 switch (var->bits_per_pixel) {
861 if (regs->HorizRes <= 800)
862 freq /= 2; /* Xbh has this type of clock for 32-bit */
867 bestclock (freq, ®s->freq, ®s->nom, ®s->den, ®s->div,
869 regs->mclk = cirrusfb_get_mclk (freq, var->bits_per_pixel, ®s->divMCLK);
872 hfront = var->right_margin;
873 hsync = var->hsync_len;
874 hback = var->left_margin;
877 vfront = var->lower_margin;
878 vsync = var->vsync_len;
879 vback = var->upper_margin;
881 if (var->vmode & FB_VMODE_DOUBLE) {
886 } else if (var->vmode & FB_VMODE_INTERLACED) {
887 yres = (yres + 1) / 2;
888 vfront = (vfront + 1) / 2;
889 vsync = (vsync + 1) / 2;
890 vback = (vback + 1) / 2;
892 regs->HorizRes = xres;
893 regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
894 regs->HorizDispEnd = xres / 8 - 1;
895 regs->HorizBlankStart = xres / 8;
896 regs->HorizBlankEnd = regs->HorizTotal + 5; /* does not count with "-5" */
897 regs->HorizSyncStart = (xres + hfront) / 8 + 1;
898 regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
900 regs->VertRes = yres;
901 regs->VertTotal = yres + vfront + vsync + vback - 2;
902 regs->VertDispEnd = yres - 1;
903 regs->VertBlankStart = yres;
904 regs->VertBlankEnd = regs->VertTotal;
905 regs->VertSyncStart = yres + vfront - 1;
906 regs->VertSyncEnd = yres + vfront + vsync - 1;
908 if (regs->VertRes >= 1024) {
909 regs->VertTotal /= 2;
910 regs->VertSyncStart /= 2;
911 regs->VertSyncEnd /= 2;
912 regs->VertDispEnd /= 2;
914 if (regs->multiplexing) {
915 regs->HorizTotal /= 2;
916 regs->HorizSyncStart /= 2;
917 regs->HorizSyncEnd /= 2;
918 regs->HorizDispEnd /= 2;
925 static void cirrusfb_set_mclk (const struct cirrusfb_info *cinfo, int val, int div)
927 assert (cinfo != NULL);
931 unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E);
932 vga_wseq (cinfo->regbase, CL_SEQR1E, old | 0x1);
933 vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
934 } else if (div == 1) {
936 unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E);
937 vga_wseq (cinfo->regbase, CL_SEQR1E, old & ~0x1);
938 vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
940 vga_wseq (cinfo->regbase, CL_SEQR1F, val & 0x3f);
944 /*************************************************************************
945 cirrusfb_set_par_foo()
947 actually writes the values for a new video mode into the hardware,
948 **************************************************************************/
949 static int cirrusfb_set_par_foo (struct fb_info *info)
951 struct cirrusfb_info *cinfo = info->par;
952 struct fb_var_screeninfo *var = &info->var;
953 struct cirrusfb_regs regs;
954 caddr_t regbase = cinfo->regbase;
957 const struct cirrusfb_board_info_rec *bi;
960 DPRINTK ("Requested mode: %dx%dx%d\n",
961 var->xres, var->yres, var->bits_per_pixel);
962 DPRINTK ("pixclock: %d\n", var->pixclock);
964 init_vgachip (cinfo);
966 err = cirrusfb_decode_var(var, ®s, info);
968 /* should never happen */
969 DPRINTK("mode change aborted. invalid var.\n");
973 bi = &cirrusfb_board_info[cinfo->btype];
976 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
977 vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
979 /* if debugging is enabled, all parameters get output before writing */
980 DPRINTK ("CRT0: %ld\n", regs.HorizTotal);
981 vga_wcrt (regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
983 DPRINTK ("CRT1: %ld\n", regs.HorizDispEnd);
984 vga_wcrt (regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
986 DPRINTK ("CRT2: %ld\n", regs.HorizBlankStart);
987 vga_wcrt (regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
989 DPRINTK ("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32); /* + 128: Compatible read */
990 vga_wcrt (regbase, VGA_CRTC_H_BLANK_END, 128 + (regs.HorizBlankEnd % 32));
992 DPRINTK ("CRT4: %ld\n", regs.HorizSyncStart);
993 vga_wcrt (regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
995 tmp = regs.HorizSyncEnd % 32;
996 if (regs.HorizBlankEnd & 32)
998 DPRINTK ("CRT5: %d\n", tmp);
999 vga_wcrt (regbase, VGA_CRTC_H_SYNC_END, tmp);
1001 DPRINTK ("CRT6: %ld\n", regs.VertTotal & 0xff);
1002 vga_wcrt (regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
1004 tmp = 16; /* LineCompare bit #9 */
1005 if (regs.VertTotal & 256)
1007 if (regs.VertDispEnd & 256)
1009 if (regs.VertSyncStart & 256)
1011 if (regs.VertBlankStart & 256)
1013 if (regs.VertTotal & 512)
1015 if (regs.VertDispEnd & 512)
1017 if (regs.VertSyncStart & 512)
1019 DPRINTK ("CRT7: %d\n", tmp);
1020 vga_wcrt (regbase, VGA_CRTC_OVERFLOW, tmp);
1022 tmp = 0x40; /* LineCompare bit #8 */
1023 if (regs.VertBlankStart & 512)
1025 if (var->vmode & FB_VMODE_DOUBLE)
1027 DPRINTK ("CRT9: %d\n", tmp);
1028 vga_wcrt (regbase, VGA_CRTC_MAX_SCAN, tmp);
1030 DPRINTK ("CRT10: %ld\n", regs.VertSyncStart & 0xff);
1031 vga_wcrt (regbase, VGA_CRTC_V_SYNC_START, (regs.VertSyncStart & 0xff));
1033 DPRINTK ("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
1034 vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, (regs.VertSyncEnd % 16 + 64 + 32));
1036 DPRINTK ("CRT12: %ld\n", regs.VertDispEnd & 0xff);
1037 vga_wcrt (regbase, VGA_CRTC_V_DISP_END, (regs.VertDispEnd & 0xff));
1039 DPRINTK ("CRT15: %ld\n", regs.VertBlankStart & 0xff);
1040 vga_wcrt (regbase, VGA_CRTC_V_BLANK_START, (regs.VertBlankStart & 0xff));
1042 DPRINTK ("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
1043 vga_wcrt (regbase, VGA_CRTC_V_BLANK_END, (regs.VertBlankEnd & 0xff));
1045 DPRINTK ("CRT18: 0xff\n");
1046 vga_wcrt (regbase, VGA_CRTC_LINE_COMPARE, 0xff);
1049 if (var->vmode & FB_VMODE_INTERLACED)
1051 if (regs.HorizBlankEnd & 64)
1053 if (regs.HorizBlankEnd & 128)
1055 if (regs.VertBlankEnd & 256)
1057 if (regs.VertBlankEnd & 512)
1060 DPRINTK ("CRT1a: %d\n", tmp);
1061 vga_wcrt (regbase, CL_CRT1A, tmp);
1064 /* hardware RefClock: 14.31818 MHz */
1065 /* formula: VClk = (OSC * N) / (D * (1+P)) */
1066 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
1068 vga_wseq (regbase, CL_SEQRB, regs.nom);
1069 tmp = regs.den << 1;
1073 if ((cinfo->btype == BT_SD64) ||
1074 (cinfo->btype == BT_ALPINE) ||
1075 (cinfo->btype == BT_GD5480))
1076 tmp |= 0x80; /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
1078 DPRINTK ("CL_SEQR1B: %ld\n", (long) tmp);
1079 vga_wseq (regbase, CL_SEQR1B, tmp);
1081 if (regs.VertRes >= 1024)
1083 vga_wcrt (regbase, VGA_CRTC_MODE, 0xc7);
1085 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
1086 * address wrap, no compat. */
1087 vga_wcrt (regbase, VGA_CRTC_MODE, 0xc3);
1089 /* HAEH? vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20); * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
1091 /* don't know if it would hurt to also program this if no interlaced */
1092 /* mode is used, but I feel better this way.. :-) */
1093 if (var->vmode & FB_VMODE_INTERLACED)
1094 vga_wcrt (regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
1096 vga_wcrt (regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
1098 vga_wseq (regbase, VGA_SEQ_CHARACTER_MAP, 0);
1100 /* adjust horizontal/vertical sync type (low/high) */
1101 tmp = 0x03; /* enable display memory & CRTC I/O address for color mode */
1102 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1104 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1106 WGen (cinfo, VGA_MIS_W, tmp);
1108 vga_wcrt (regbase, VGA_CRTC_PRESET_ROW, 0); /* Screen A Preset Row-Scan register */
1109 vga_wcrt (regbase, VGA_CRTC_CURSOR_START, 0); /* text cursor on and start line */
1110 vga_wcrt (regbase, VGA_CRTC_CURSOR_END, 31); /* text cursor end line */
1112 /******************************************************
1118 /* programming for different color depths */
1119 if (var->bits_per_pixel == 1) {
1120 DPRINTK ("cirrusfb: preparing for 1 bit deep display\n");
1121 vga_wgfx (regbase, VGA_GFX_MODE, 0); /* mode register */
1124 switch (cinfo->btype) {
1132 DPRINTK (" (for GD54xx)\n");
1133 vga_wseq (regbase, CL_SEQR7,
1135 bi->sr07_1bpp_mux : bi->sr07_1bpp);
1139 DPRINTK (" (for GD546x)\n");
1140 vga_wseq (regbase, CL_SEQR7,
1141 vga_rseq (regbase, CL_SEQR7) & ~0x01);
1145 printk (KERN_WARNING "cirrusfb: unknown Board\n");
1149 /* Extended Sequencer Mode */
1150 switch (cinfo->btype) {
1152 /* setting the SEQRF on SD64 is not necessary (only during init) */
1153 DPRINTK ("(for SD64)\n");
1154 vga_wseq (regbase, CL_SEQR1F, 0x1a); /* MCLK select */
1158 DPRINTK ("(for Piccolo)\n");
1159 /* ### ueberall 0x22? */
1160 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 1c MCLK select */
1161 vga_wseq (regbase, CL_SEQRF, 0xb0); /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
1165 DPRINTK ("(for Picasso)\n");
1166 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 22 MCLK select */
1167 vga_wseq (regbase, CL_SEQRF, 0xd0); /* ## vorher d0 avoid FIFO underruns..? */
1171 DPRINTK ("(for Spectrum)\n");
1172 /* ### ueberall 0x22? */
1173 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 1c MCLK select */
1174 vga_wseq (regbase, CL_SEQRF, 0xb0); /* evtl d0? avoid FIFO underruns..? */
1181 DPRINTK (" (for GD54xx)\n");
1186 printk (KERN_WARNING "cirrusfb: unknown Board\n");
1190 WGen (cinfo, VGA_PEL_MSK, 0x01); /* pixel mask: pass-through for first plane */
1191 if (regs.multiplexing)
1192 WHDR (cinfo, 0x4a); /* hidden dac reg: 1280x1024 */
1194 WHDR (cinfo, 0); /* hidden dac: nothing */
1195 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x06); /* memory mode: odd/even, ext. memory */
1196 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0x01); /* plane mask: only write to first plane */
1197 offset = var->xres_virtual / 16;
1200 /******************************************************
1206 else if (var->bits_per_pixel == 8) {
1207 DPRINTK ("cirrusfb: preparing for 8 bit deep display\n");
1208 switch (cinfo->btype) {
1216 DPRINTK (" (for GD54xx)\n");
1217 vga_wseq (regbase, CL_SEQR7,
1219 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1223 DPRINTK (" (for GD546x)\n");
1224 vga_wseq (regbase, CL_SEQR7,
1225 vga_rseq (regbase, CL_SEQR7) | 0x01);
1229 printk (KERN_WARNING "cirrusfb: unknown Board\n");
1233 switch (cinfo->btype) {
1235 vga_wseq (regbase, CL_SEQR1F, 0x1d); /* MCLK select */
1239 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */
1240 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1244 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */
1245 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1249 vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */
1250 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1255 vga_wseq (regbase, CL_SEQRF, 0xb8); /* ### INCOMPLETE!! */
1257 /* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
1261 DPRINTK (" (for GD543x)\n");
1262 cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
1263 /* We already set SRF and SR1F */
1268 DPRINTK (" (for GD54xx)\n");
1273 printk (KERN_WARNING "cirrusfb: unknown Board\n");
1277 vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */
1278 WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */
1279 if (regs.multiplexing)
1280 WHDR (cinfo, 0x4a); /* hidden dac reg: 1280x1024 */
1282 WHDR (cinfo, 0); /* hidden dac: nothing */
1283 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */
1284 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */
1285 offset = var->xres_virtual / 8;
1288 /******************************************************
1294 else if (var->bits_per_pixel == 16) {
1295 DPRINTK ("cirrusfb: preparing for 16 bit deep display\n");
1296 switch (cinfo->btype) {
1298 vga_wseq (regbase, CL_SEQR7, 0xf7); /* Extended Sequencer Mode: 256c col. mode */
1299 vga_wseq (regbase, CL_SEQR1F, 0x1e); /* MCLK select */
1303 vga_wseq (regbase, CL_SEQR7, 0x87);
1304 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1305 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1309 vga_wseq (regbase, CL_SEQR7, 0x27);
1310 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1311 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1315 vga_wseq (regbase, CL_SEQR7, 0x87);
1316 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1317 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1321 vga_wseq (regbase, CL_SEQR7, 0x27);
1322 /* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
1326 DPRINTK (" (for GD543x)\n");
1327 if (regs.HorizRes >= 1024)
1328 vga_wseq (regbase, CL_SEQR7, 0xa7);
1330 vga_wseq (regbase, CL_SEQR7, 0xa3);
1331 cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
1335 DPRINTK (" (for GD5480)\n");
1336 vga_wseq (regbase, CL_SEQR7, 0x17);
1337 /* We already set SRF and SR1F */
1341 DPRINTK (" (for GD546x)\n");
1342 vga_wseq (regbase, CL_SEQR7,
1343 vga_rseq (regbase, CL_SEQR7) & ~0x01);
1347 printk (KERN_WARNING "CIRRUSFB: unknown Board\n");
1351 vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */
1352 WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */
1354 WHDR (cinfo, 0xc0); /* Copy Xbh */
1355 #elif defined(CONFIG_ZORRO)
1356 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1357 WHDR (cinfo, 0xa0); /* hidden dac reg: nothing special */
1359 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */
1360 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */
1361 offset = var->xres_virtual / 4;
1364 /******************************************************
1370 else if (var->bits_per_pixel == 32) {
1371 DPRINTK ("cirrusfb: preparing for 24/32 bit deep display\n");
1372 switch (cinfo->btype) {
1374 vga_wseq (regbase, CL_SEQR7, 0xf9); /* Extended Sequencer Mode: 256c col. mode */
1375 vga_wseq (regbase, CL_SEQR1F, 0x1e); /* MCLK select */
1379 vga_wseq (regbase, CL_SEQR7, 0x85);
1380 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1381 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1385 vga_wseq (regbase, CL_SEQR7, 0x25);
1386 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1387 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1391 vga_wseq (regbase, CL_SEQR7, 0x85);
1392 vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
1393 vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
1397 vga_wseq (regbase, CL_SEQR7, 0x25);
1398 /* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
1402 DPRINTK (" (for GD543x)\n");
1403 vga_wseq (regbase, CL_SEQR7, 0xa9);
1404 cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
1408 DPRINTK (" (for GD5480)\n");
1409 vga_wseq (regbase, CL_SEQR7, 0x19);
1410 /* We already set SRF and SR1F */
1414 DPRINTK (" (for GD546x)\n");
1415 vga_wseq (regbase, CL_SEQR7,
1416 vga_rseq (regbase, CL_SEQR7) & ~0x01);
1420 printk (KERN_WARNING "cirrusfb: unknown Board\n");
1424 vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */
1425 WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */
1426 WHDR (cinfo, 0xc5); /* hidden dac reg: 8-8-8 mode (24 or 32) */
1427 vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */
1428 vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */
1429 offset = var->xres_virtual / 4;
1432 /******************************************************
1434 * unknown/unsupported bpp
1439 printk (KERN_ERR "cirrusfb: What's this?? requested color depth == %d.\n",
1440 var->bits_per_pixel);
1443 vga_wcrt (regbase, VGA_CRTC_OFFSET, offset & 0xff);
1446 tmp |= 0x10; /* offset overflow bit */
1448 vga_wcrt (regbase, CL_CRT1B, tmp); /* screen start addr #16-18, fastpagemode cycles */
1450 if (cinfo->btype == BT_SD64 ||
1451 cinfo->btype == BT_PICASSO4 ||
1452 cinfo->btype == BT_ALPINE ||
1453 cinfo->btype == BT_GD5480)
1454 vga_wcrt (regbase, CL_CRT1D, 0x00); /* screen start address bit 19 */
1456 vga_wcrt (regbase, VGA_CRTC_CURSOR_HI, 0); /* text cursor location high */
1457 vga_wcrt (regbase, VGA_CRTC_CURSOR_LO, 0); /* text cursor location low */
1458 vga_wcrt (regbase, VGA_CRTC_UNDERLINE, 0); /* underline row scanline = at very bottom */
1460 vga_wattr (regbase, VGA_ATC_MODE, 1); /* controller mode */
1461 vga_wattr (regbase, VGA_ATC_OVERSCAN, 0); /* overscan (border) color */
1462 vga_wattr (regbase, VGA_ATC_PLANE_ENABLE, 15); /* color plane enable */
1463 vga_wattr (regbase, CL_AR33, 0); /* pixel panning */
1464 vga_wattr (regbase, VGA_ATC_COLOR_PAGE, 0); /* color select */
1466 /* [ EGS: SetOffset(); ] */
1467 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1470 vga_wgfx (regbase, VGA_GFX_SR_VALUE, 0); /* set/reset register */
1471 vga_wgfx (regbase, VGA_GFX_SR_ENABLE, 0); /* set/reset enable */
1472 vga_wgfx (regbase, VGA_GFX_COMPARE_VALUE, 0); /* color compare */
1473 vga_wgfx (regbase, VGA_GFX_DATA_ROTATE, 0); /* data rotate */
1474 vga_wgfx (regbase, VGA_GFX_PLANE_READ, 0); /* read map select */
1475 vga_wgfx (regbase, VGA_GFX_MISC, 1); /* miscellaneous register */
1476 vga_wgfx (regbase, VGA_GFX_COMPARE_MASK, 15); /* color don't care */
1477 vga_wgfx (regbase, VGA_GFX_BIT_MASK, 255); /* bit mask */
1479 vga_wseq (regbase, CL_SEQR12, 0x0); /* graphics cursor attributes: nothing special */
1481 /* finally, turn on everything - turn off "FullBandwidth" bit */
1482 /* also, set "DotClock%2" bit where requested */
1485 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1486 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1490 vga_wseq (regbase, VGA_SEQ_CLOCK_MODE, tmp);
1491 DPRINTK ("CL_SEQR1: %d\n", tmp);
1493 cinfo->currentmode = regs;
1494 info->fix.type = regs.type;
1495 info->fix.visual = regs.visual;
1496 info->fix.line_length = regs.line_length;
1498 /* pan to requested offset */
1499 cirrusfb_pan_display (var, info);
1501 #ifdef CIRRUSFB_DEBUG
1509 /* for some reason incomprehensible to me, cirrusfb requires that you write
1510 * the registers twice for the settings to take..grr. -dte */
1511 int cirrusfb_set_par (struct fb_info *info)
1513 cirrusfb_set_par_foo (info);
1514 return cirrusfb_set_par_foo (info);
1517 int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1518 unsigned blue, unsigned transp,
1519 struct fb_info *info)
1521 struct cirrusfb_info *cinfo = info->par;
1526 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1528 red >>= (16 - info->var.red.length);
1529 green >>= (16 - info->var.green.length);
1530 blue >>= (16 - info->var.blue.length);
1534 v = (red << info->var.red.offset) |
1535 (green << info->var.green.offset) |
1536 (blue << info->var.blue.offset);
1538 switch (info->var.bits_per_pixel) {
1540 ((u8*)(info->pseudo_palette))[regno] = v;
1543 ((u16*)(info->pseudo_palette))[regno] = v;
1547 ((u32*)(info->pseudo_palette))[regno] = v;
1553 cinfo->palette[regno].red = red;
1554 cinfo->palette[regno].green = green;
1555 cinfo->palette[regno].blue = blue;
1557 if (info->var.bits_per_pixel == 8) {
1558 WClut (cinfo, regno, red >> 10, green >> 10, blue >> 10);
1565 /*************************************************************************
1566 cirrusfb_pan_display()
1568 performs display panning - provided hardware permits this
1569 **************************************************************************/
1570 int cirrusfb_pan_display (struct fb_var_screeninfo *var,
1571 struct fb_info *info)
1576 unsigned char tmp = 0, tmp2 = 0, xpix;
1577 struct cirrusfb_info *cinfo = info->par;
1579 DPRINTK ("ENTER\n");
1580 DPRINTK ("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1582 /* no range checks for xoffset and yoffset, */
1583 /* as fb_pan_display has already done this */
1584 if (var->vmode & FB_VMODE_YWRAP)
1587 info->var.xoffset = var->xoffset;
1588 info->var.yoffset = var->yoffset;
1590 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1591 yoffset = var->yoffset;
1593 base = yoffset * cinfo->currentmode.line_length + xoffset;
1595 if (info->var.bits_per_pixel == 1) {
1596 /* base is already correct */
1597 xpix = (unsigned char) (var->xoffset % 8);
1600 xpix = (unsigned char) ((xoffset % 4) * 2);
1603 cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
1605 /* lower 8 + 8 bits of screen start address */
1606 vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, (unsigned char) (base & 0xff));
1607 vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, (unsigned char) (base >> 8));
1609 /* construct bits 16, 17 and 18 of screen start address */
1617 tmp2 = (vga_rcrt (cinfo->regbase, CL_CRT1B) & 0xf2) | tmp; /* 0xf2 is %11110010, exclude tmp bits */
1618 vga_wcrt (cinfo->regbase, CL_CRT1B, tmp2);
1620 /* construct bit 19 of screen start address */
1621 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1625 vga_wcrt (cinfo->regbase, CL_CRT1D, tmp2);
1628 /* write pixel panning value to AR33; this does not quite work in 8bpp */
1629 /* ### Piccolo..? Will this work? */
1630 if (info->var.bits_per_pixel == 1)
1631 vga_wattr (cinfo->regbase, CL_AR33, xpix);
1633 cirrusfb_WaitBLT (cinfo->regbase);
1640 int cirrusfb_blank (int blank_mode, struct fb_info *info)
1643 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1644 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
1645 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
1646 * to e.g. a video mode which doesn't support it. Implements VESA suspend
1647 * and powerdown modes on hardware that supports disabling hsync/vsync:
1648 * blank_mode == 2: suspend vsync
1649 * blank_mode == 3: suspend hsync
1650 * blank_mode == 4: powerdown
1653 struct cirrusfb_info *cinfo = info->par;
1654 int current_mode = cinfo->blank_mode;
1656 DPRINTK ("ENTER, blank mode = %d\n", blank_mode);
1658 if (info->state != FBINFO_STATE_RUNNING ||
1659 current_mode == blank_mode) {
1660 DPRINTK ("EXIT, returning 0\n");
1665 if (current_mode != VESA_NO_BLANKING) {
1666 /* unblank the screen */
1667 val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1668 vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf); /* clear "FullBandwidth" bit */
1669 /* and undo VESA suspend trickery */
1670 vga_wgfx (cinfo->regbase, CL_GRE, 0x00);
1674 if(blank_mode != VESA_NO_BLANKING) {
1675 /* blank the screen */
1676 val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1677 vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20); /* set "FullBandwidth" bit */
1680 switch (blank_mode) {
1681 case VESA_NO_BLANKING:
1683 case VESA_VSYNC_SUSPEND:
1684 vga_wgfx (cinfo->regbase, CL_GRE, 0x04);
1686 case VESA_HSYNC_SUSPEND:
1687 vga_wgfx (cinfo->regbase, CL_GRE, 0x02);
1689 case VESA_POWERDOWN:
1690 vga_wgfx (cinfo->regbase, CL_GRE, 0x06);
1693 DPRINTK ("EXIT, returning 1\n");
1697 cinfo->blank_mode = blank_mode;
1698 DPRINTK ("EXIT, returning 0\n");
1701 /**** END Hardware specific Routines **************************************/
1702 /****************************************************************************/
1703 /**** BEGIN Internal Routines ***********************************************/
1705 static void init_vgachip (struct cirrusfb_info *cinfo)
1707 const struct cirrusfb_board_info_rec *bi;
1709 DPRINTK ("ENTER\n");
1711 assert (cinfo != NULL);
1713 bi = &cirrusfb_board_info[cinfo->btype];
1715 /* reset board globally */
1716 switch (cinfo->btype) {
1724 WSFR2 (cinfo, 0xff);
1735 vga_wcrt (cinfo->regbase, CL_CRT51, 0x00); /* disable flickerfixer */
1737 vga_wgfx (cinfo->regbase, CL_GR2F, 0x00); /* from Klaus' NetBSD driver: */
1738 vga_wgfx (cinfo->regbase, CL_GR33, 0x00); /* put blitter into 542x compat */
1739 vga_wgfx (cinfo->regbase, CL_GR31, 0x00); /* mode */
1743 vga_wgfx (cinfo->regbase, CL_GR2F, 0x00); /* from Klaus' NetBSD driver: */
1747 /* Nothing to do to reset the board. */
1751 printk (KERN_ERR "cirrusfb: Warning: Unknown board type\n");
1755 assert (cinfo->size > 0); /* make sure RAM size set by this point */
1757 /* the P4 is not fully initialized here; I rely on it having been */
1758 /* inited under AmigaOS already, which seems to work just fine */
1759 /* (Klaus advised to do it this way) */
1761 if (cinfo->btype != BT_PICASSO4) {
1762 WGen (cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1763 WGen (cinfo, CL_POS102, 0x01);
1764 WGen (cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1766 if (cinfo->btype != BT_SD64)
1767 WGen (cinfo, CL_VSSM2, 0x01);
1769 vga_wseq (cinfo->regbase, CL_SEQR0, 0x03); /* reset sequencer logic */
1771 vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21); /* FullBandwidth (video off) and 8/9 dot clock */
1772 WGen (cinfo, VGA_MIS_W, 0xc1); /* polarity (-/-), disable access to display memory, VGA_CRTC_START_HI base address: color */
1774 /* vga_wgfx (cinfo->regbase, CL_GRA, 0xce); "magic cookie" - doesn't make any sense to me.. */
1775 vga_wseq (cinfo->regbase, CL_SEQR6, 0x12); /* unlock all extension registers */
1777 vga_wgfx (cinfo->regbase, CL_GR31, 0x04); /* reset blitter */
1779 switch (cinfo->btype) {
1781 vga_wseq (cinfo->regbase, CL_SEQRF, 0x98);
1786 vga_wseq (cinfo->regbase, CL_SEQRF, 0xb8);
1789 vga_wseq (cinfo->regbase, CL_SEQR16, 0x0f);
1790 vga_wseq (cinfo->regbase, CL_SEQRF, 0xb0);
1794 vga_wseq (cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: nothing */
1795 vga_wseq (cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); /* character map select: doesn't even matter in gx mode */
1796 vga_wseq (cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e); /* memory mode: chain-4, no odd/even, ext. memory */
1798 /* controller-internal base address of video memory */
1800 vga_wseq (cinfo->regbase, CL_SEQR7, bi->sr07);
1802 /* vga_wseq (cinfo->regbase, CL_SEQR8, 0x00); *//* EEPROM control: shouldn't be necessary to write to this at all.. */
1804 vga_wseq (cinfo->regbase, CL_SEQR10, 0x00); /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1805 vga_wseq (cinfo->regbase, CL_SEQR11, 0x00); /* graphics cursor Y position (..."... ) */
1806 vga_wseq (cinfo->regbase, CL_SEQR12, 0x00); /* graphics cursor attributes */
1807 vga_wseq (cinfo->regbase, CL_SEQR13, 0x00); /* graphics cursor pattern address */
1809 /* writing these on a P4 might give problems.. */
1810 if (cinfo->btype != BT_PICASSO4) {
1811 vga_wseq (cinfo->regbase, CL_SEQR17, 0x00); /* configuration readback and ext. color */
1812 vga_wseq (cinfo->regbase, CL_SEQR18, 0x02); /* signature generator */
1815 /* MCLK select etc. */
1817 vga_wseq (cinfo->regbase, CL_SEQR1F, bi->sr1f);
1819 vga_wcrt (cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); /* Screen A preset row scan: none */
1820 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); /* Text cursor start: disable text cursor */
1821 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00); /* Text cursor end: - */
1822 vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, 0x00); /* Screen start address high: 0 */
1823 vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, 0x00); /* Screen start address low: 0 */
1824 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); /* text cursor location high: 0 */
1825 vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); /* text cursor location low: 0 */
1827 vga_wcrt (cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); /* Underline Row scanline: - */
1828 vga_wcrt (cinfo->regbase, VGA_CRTC_MODE, 0xc3); /* mode control: timing enable, byte mode, no compat modes */
1829 vga_wcrt (cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00); /* Line Compare: not needed */
1830 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1831 vga_wcrt (cinfo->regbase, CL_CRT1B, 0x02); /* ext. display controls: ext.adr. wrap */
1833 vga_wgfx (cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); /* Set/Reset registes: - */
1834 vga_wgfx (cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); /* Set/Reset enable: - */
1835 vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); /* Color Compare: - */
1836 vga_wgfx (cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00); /* Data Rotate: - */
1837 vga_wgfx (cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); /* Read Map Select: - */
1838 vga_wgfx (cinfo->regbase, VGA_GFX_MODE, 0x00); /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1839 vga_wgfx (cinfo->regbase, VGA_GFX_MISC, 0x01); /* Miscellaneous: memory map base address, graphics mode */
1840 vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f); /* Color Don't care: involve all planes */
1841 vga_wgfx (cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); /* Bit Mask: no mask at all */
1842 if (cinfo->btype == BT_ALPINE)
1843 vga_wgfx (cinfo->regbase, CL_GRB, 0x20); /* (5434 can't have bit 3 set for bitblt) */
1845 vga_wgfx (cinfo->regbase, CL_GRB, 0x28); /* Graphics controller mode extensions: finer granularity, 8byte data latches */
1847 vga_wgfx (cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1848 vga_wgfx (cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1849 vga_wgfx (cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1850 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); *//* Background color byte 1: - */
1851 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1853 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE0, 0x00); /* Attribute Controller palette registers: "identity mapping" */
1854 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1855 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1856 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1857 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1858 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1859 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1860 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1861 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1862 vga_wattr (cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1863 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1864 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1865 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1866 vga_wattr (cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1867 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1868 vga_wattr (cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1870 vga_wattr (cinfo->regbase, VGA_ATC_MODE, 0x01); /* Attribute Controller mode: graphics mode */
1871 vga_wattr (cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); /* Overscan color reg.: reg. 0 */
1872 vga_wattr (cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); /* Color Plane enable: Enable all 4 planes */
1873 /* ### vga_wattr (cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
1874 vga_wattr (cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00); /* Color Select: - */
1876 WGen (cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1878 if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
1879 WGen (cinfo, VGA_MIS_W, 0xc3); /* polarity (-/-), enable display mem, VGA_CRTC_START_HI i/o base = color */
1881 vga_wgfx (cinfo->regbase, CL_GR31, 0x04); /* BLT Start/status: Blitter reset */
1882 vga_wgfx (cinfo->regbase, CL_GR31, 0x00); /* - " - : "end-of-reset" */
1885 WHDR (cinfo, 0); /* Hidden DAC register: - */
1887 printk (KERN_DEBUG "cirrusfb: This board has %ld bytes of DRAM memory\n", cinfo->size);
1892 static void switch_monitor (struct cirrusfb_info *cinfo, int on)
1894 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1895 static int IsOn = 0; /* XXX not ok for multiple boards */
1897 DPRINTK ("ENTER\n");
1899 if (cinfo->btype == BT_PICASSO4)
1900 return; /* nothing to switch */
1901 if (cinfo->btype == BT_ALPINE)
1902 return; /* nothing to switch */
1903 if (cinfo->btype == BT_GD5480)
1904 return; /* nothing to switch */
1905 if (cinfo->btype == BT_PICASSO) {
1906 if ((on && !IsOn) || (!on && IsOn))
1913 switch (cinfo->btype) {
1915 WSFR (cinfo, cinfo->SFR | 0x21);
1918 WSFR (cinfo, cinfo->SFR | 0x28);
1923 default: /* do nothing */ break;
1926 switch (cinfo->btype) {
1928 WSFR (cinfo, cinfo->SFR & 0xde);
1931 WSFR (cinfo, cinfo->SFR & 0xd7);
1936 default: /* do nothing */ break;
1941 #endif /* CONFIG_ZORRO */
1945 /******************************************/
1946 /* Linux 2.6-style accelerated functions */
1947 /******************************************/
1949 static void cirrusfb_prim_fillrect(struct cirrusfb_info *cinfo,
1950 const struct fb_fillrect *region)
1952 int m; /* bytes per pixel */
1953 if(cinfo->info->var.bits_per_pixel == 1) {
1954 cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.bits_per_pixel,
1955 region->dx / 8, region->dy,
1956 region->width / 8, region->height,
1958 cinfo->currentmode.line_length);
1960 m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8;
1961 cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.bits_per_pixel,
1962 region->dx * m, region->dy,
1963 region->width * m, region->height,
1965 cinfo->currentmode.line_length);
1970 void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *region)
1972 struct cirrusfb_info *cinfo = info->par;
1973 struct fb_fillrect modded;
1976 if (info->state != FBINFO_STATE_RUNNING)
1978 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1979 cfb_fillrect(info, region);
1983 vxres = info->var.xres_virtual;
1984 vyres = info->var.yres_virtual;
1986 memcpy(&modded, region, sizeof(struct fb_fillrect));
1988 if(!modded.width || !modded.height ||
1989 modded.dx >= vxres || modded.dy >= vyres)
1992 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
1993 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
1995 cirrusfb_prim_fillrect(cinfo, &modded);
1998 static void cirrusfb_prim_copyarea(struct cirrusfb_info *cinfo,
1999 const struct fb_copyarea *area)
2001 int m; /* bytes per pixel */
2002 if(cinfo->info->var.bits_per_pixel == 1) {
2003 cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
2004 area->sx / 8, area->sy,
2005 area->dx / 8, area->dy,
2006 area->width / 8, area->height,
2007 cinfo->currentmode.line_length);
2009 m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8;
2010 cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
2011 area->sx * m, area->sy,
2012 area->dx * m, area->dy,
2013 area->width * m, area->height,
2014 cinfo->currentmode.line_length);
2020 void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
2022 struct cirrusfb_info *cinfo = info->par;
2023 struct fb_copyarea modded;
2025 modded.sx = area->sx;
2026 modded.sy = area->sy;
2027 modded.dx = area->dx;
2028 modded.dy = area->dy;
2029 modded.width = area->width;
2030 modded.height = area->height;
2032 if (info->state != FBINFO_STATE_RUNNING)
2034 if (info->flags & FBINFO_HWACCEL_DISABLED) {
2035 cfb_copyarea(info, area);
2039 vxres = info->var.xres_virtual;
2040 vyres = info->var.yres_virtual;
2042 if(!modded.width || !modded.height ||
2043 modded.sx >= vxres || modded.sy >= vyres ||
2044 modded.dx >= vxres || modded.dy >= vyres)
2047 if(modded.sx + modded.width > vxres) modded.width = vxres - modded.sx;
2048 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
2049 if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
2050 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
2052 cirrusfb_prim_copyarea(cinfo, &modded);
2055 void cirrusfb_imageblit(struct fb_info *info, const struct fb_image *image)
2057 struct cirrusfb_info *cinfo = info->par;
2059 cirrusfb_WaitBLT(cinfo->regbase);
2060 cfb_imageblit(info, image);
2064 #ifdef CONFIG_PPC_PREP
2065 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
2066 #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
2067 static void get_prep_addrs (unsigned long *display, unsigned long *registers)
2069 DPRINTK ("ENTER\n");
2071 *display = PREP_VIDEO_BASE;
2072 *registers = (unsigned long) PREP_IO_BASE;
2077 #endif /* CONFIG_PPC_PREP */
2081 static int release_io_ports = 0;
2083 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
2084 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
2085 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
2087 static unsigned int cirrusfb_get_memsize (caddr_t regbase)
2092 DPRINTK ("ENTER\n");
2094 SRF = vga_rseq (regbase, CL_SEQRF);
2095 switch ((SRF & 0x18)) {
2096 case 0x08: mem = 512 * 1024; break;
2097 case 0x10: mem = 1024 * 1024; break;
2098 /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory
2100 case 0x18: mem = 2048 * 1024; break;
2101 default: printk ("CLgenfb: Unknown memory size!\n");
2105 /* If DRAM bank switching is enabled, there must be twice as much
2106 * memory installed. (4MB on the 5434) */
2109 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
2117 static void get_pci_addrs (const struct pci_dev *pdev,
2118 unsigned long *display, unsigned long *registers)
2120 assert (pdev != NULL);
2121 assert (display != NULL);
2122 assert (registers != NULL);
2124 DPRINTK ("ENTER\n");
2129 /* This is a best-guess for now */
2131 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
2132 *display = pci_resource_start(pdev, 1);
2133 *registers = pci_resource_start(pdev, 0);
2135 *display = pci_resource_start(pdev, 0);
2136 *registers = pci_resource_start(pdev, 1);
2139 assert (*display != 0);
2145 static void __devexit cirrusfb_pci_unmap (struct cirrusfb_info *cinfo)
2147 struct pci_dev *pdev = cinfo->pdev;
2149 iounmap(cinfo->fbmem);
2150 #if 0 /* if system didn't claim this region, we would... */
2151 release_mem_region(0xA0000, 65535);
2153 if (release_io_ports)
2154 release_region(0x3C0, 32);
2155 pci_release_regions(pdev);
2156 framebuffer_release(cinfo->info);
2157 pci_disable_device(pdev);
2161 static struct cirrusfb_info *cirrusfb_pci_setup (struct pci_dev *pdev,
2162 const struct pci_device_id *ent)
2164 struct cirrusfb_info *cinfo;
2165 struct fb_info *info;
2166 cirrusfb_board_t btype;
2167 unsigned long board_addr, board_size;
2170 ret = pci_enable_device(pdev);
2172 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2176 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2178 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2186 cinfo->btype = btype = (cirrusfb_board_t) ent->driver_data;
2188 DPRINTK (" Found PCI device, base address 0 is 0x%lx, btype set to %d\n",
2189 pdev->resource[0].start, btype);
2190 DPRINTK (" base address 1 is 0x%lx\n", pdev->resource[1].start);
2193 pci_write_config_dword (pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2194 #ifdef CONFIG_PPC_PREP
2195 get_prep_addrs (&board_addr, &cinfo->fbregs_phys);
2197 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2198 cinfo->regbase = (char *) cinfo->fbregs_phys;
2200 DPRINTK ("Attempt to get PCI info for Cirrus Graphics Card\n");
2201 get_pci_addrs (pdev, &board_addr, &cinfo->fbregs_phys);
2202 cinfo->regbase = NULL; /* FIXME: this forces VGA. alternatives? */
2205 DPRINTK ("Board address: 0x%lx, register address: 0x%lx\n", board_addr, cinfo->fbregs_phys);
2207 board_size = (btype == BT_GD5480) ?
2208 32 * MB_ : cirrusfb_get_memsize (cinfo->regbase);
2210 ret = pci_request_regions(pdev, "cirrusfb");
2212 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n",
2214 goto err_release_fb;
2216 #if 0 /* if the system didn't claim this region, we would... */
2217 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2218 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n"
2222 goto err_release_regions;
2225 if (request_region(0x3C0, 32, "cirrusfb"))
2226 release_io_ports = 1;
2228 cinfo->fbmem = ioremap(board_addr, board_size);
2229 if (!cinfo->fbmem) {
2231 goto err_release_legacy;
2234 cinfo->fbmem_phys = board_addr;
2235 cinfo->size = board_size;
2237 printk (" RAM (%lu kB) at 0xx%lx, ", cinfo->size / KB_, board_addr);
2238 printk ("Cirrus Logic chipset on PCI bus\n");
2243 if (release_io_ports)
2244 release_region(0x3C0, 32);
2246 release_mem_region(0xA0000, 65535);
2247 err_release_regions:
2249 pci_release_regions(pdev);
2251 framebuffer_release(info);
2253 pci_disable_device(pdev);
2255 return ERR_PTR(ret);
2257 #endif /* CONFIG_PCI */
2263 static int cirrusfb_zorro_find (struct zorro_dev **z_o,
2264 struct zorro_dev **z2_o,
2265 cirrusfb_board_t *btype, unsigned long *size)
2267 struct zorro_dev *z = NULL;
2270 assert (z_o != NULL);
2271 assert (btype != NULL);
2273 for (i = 0; i < ARRAY_SIZE(cirrusfb_zorro_probe_list); i++)
2274 if ((z = zorro_find_device(cirrusfb_zorro_probe_list[i].id, NULL)))
2279 if (cirrusfb_zorro_probe_list[i].id2)
2280 *z2_o = zorro_find_device(cirrusfb_zorro_probe_list[i].id2, NULL);
2284 *btype = cirrusfb_zorro_probe_list[i].btype;
2285 *size = cirrusfb_zorro_probe_list[i].size;
2287 printk (KERN_INFO "cirrusfb: %s board detected; ",
2288 cirrusfb_board_info[*btype].name);
2293 printk (KERN_NOTICE "cirrusfb: no supported board found.\n");
2298 static void __devexit cirrusfb_zorro_unmap (struct cirrusfb_info *cinfo)
2300 release_mem_region(cinfo->board_addr, cinfo->board_size);
2302 if (cinfo->btype == BT_PICASSO4) {
2303 cinfo->regbase -= 0x600000;
2304 iounmap ((void *)cinfo->regbase);
2305 iounmap ((void *)cinfo->fbmem);
2307 if (cinfo->board_addr > 0x01000000)
2308 iounmap ((void *)cinfo->fbmem);
2310 framebuffer_release(cinfo->info);
2314 static struct cirrusfb_info *cirrusfb_zorro_setup(void)
2316 struct cirrusfb_info *cinfo;
2317 struct fb_info *info;
2318 cirrusfb_board_t btype;
2319 struct zorro_dev *z = NULL, *z2 = NULL;
2320 unsigned long board_addr, board_size, size;
2323 ret = cirrusfb_zorro_find (&z, &z2, &btype, &size);
2327 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2329 printk (KERN_ERR "cirrusfb: could not allocate memory\n");
2336 cinfo->btype = btype;
2340 assert (btype != BT_NONE);
2342 cinfo->board_addr = board_addr = z->resource.start;
2343 cinfo->board_size = board_size = z->resource.end-z->resource.start+1;
2346 if (!request_mem_region(board_addr, board_size, "cirrusfb")) {
2347 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n",
2350 goto err_release_fb;
2353 printk (" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr);
2357 if (btype == BT_PICASSO4) {
2358 printk (" REG at $%lx\n", board_addr + 0x600000);
2360 /* To be precise, for the P4 this is not the */
2361 /* begin of the board, but the begin of RAM. */
2362 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2363 /* (note the ugly hardcoded 16M number) */
2364 cinfo->regbase = ioremap (board_addr, 16777216);
2365 if (!cinfo->regbase)
2366 goto err_release_region;
2368 DPRINTK ("cirrusfb: Virtual address for board set to: $%p\n", cinfo->regbase);
2369 cinfo->regbase += 0x600000;
2370 cinfo->fbregs_phys = board_addr + 0x600000;
2372 cinfo->fbmem_phys = board_addr + 16777216;
2373 cinfo->fbmem = ioremap (info->fbmem_phys, 16777216);
2375 goto err_unmap_regbase;
2377 printk (" REG at $%lx\n", (unsigned long) z2->resource.start);
2379 cinfo->fbmem_phys = board_addr;
2380 if (board_addr > 0x01000000)
2381 cinfo->fbmem = ioremap (board_addr, board_size);
2383 cinfo->fbmem = (caddr_t) ZTWO_VADDR (board_addr);
2385 goto err_release_region;
2387 /* set address for REG area of board */
2388 cinfo->regbase = (caddr_t) ZTWO_VADDR (z2->resource.start);
2389 cinfo->fbregs_phys = z2->resource.start;
2391 DPRINTK ("cirrusfb: Virtual address for board set to: $%p\n", cinfo->regbase);
2394 printk (KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
2399 /* Parental advisory: explicit hack */
2400 iounmap(cinfo->regbase - 0x600000);
2402 release_region(board_addr, board_size);
2404 framebuffer_release(info);
2406 return ERR_PTR(ret);
2408 #endif /* CONFIG_ZORRO */
2410 static int cirrusfb_set_fbinfo(struct cirrusfb_info *cinfo)
2412 struct fb_info *info = cinfo->info;
2413 struct fb_var_screeninfo *var = &info->var;
2417 info->pseudo_palette = cinfo->pseudo_palette;
2418 info->flags = FBINFO_DEFAULT
2419 | FBINFO_HWACCEL_XPAN
2420 | FBINFO_HWACCEL_YPAN
2421 | FBINFO_HWACCEL_FILLRECT
2422 | FBINFO_HWACCEL_COPYAREA;
2424 info->flags |= FBINFO_HWACCEL_DISABLED;
2425 info->fbops = &cirrusfb_ops;
2426 info->screen_base = cinfo->fbmem;
2427 if (cinfo->btype == BT_GD5480) {
2428 if (var->bits_per_pixel == 16)
2429 info->screen_base += 1 * MB_;
2430 if (var->bits_per_pixel == 24 || var->bits_per_pixel == 32)
2431 info->screen_base += 2 * MB_;
2434 /* Fill fix common fields */
2435 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2436 sizeof(info->fix.id));
2438 /* monochrome: only 1 memory plane */
2439 /* 8 bit and above: Use whole memory area */
2440 info->fix.smem_start = cinfo->fbmem_phys;
2441 info->fix.smem_len = (var->bits_per_pixel == 1) ? cinfo->size / 4 : cinfo->size;
2442 info->fix.type = cinfo->currentmode.type;
2443 info->fix.type_aux = 0;
2444 info->fix.visual = cinfo->currentmode.visual;
2445 info->fix.xpanstep = 1;
2446 info->fix.ypanstep = 1;
2447 info->fix.ywrapstep = 0;
2448 info->fix.line_length = cinfo->currentmode.line_length;
2450 /* FIXME: map region at 0xB8000 if available, fill in here */
2451 info->fix.mmio_start = cinfo->fbregs_phys;
2452 info->fix.mmio_len = 0;
2453 info->fix.accel = FB_ACCEL_NONE;
2455 fb_alloc_cmap(&info->cmap, 256, 0);
2460 #if defined(CONFIG_PCI)
2461 #define cirrusfb_unmap cirrusfb_pci_unmap
2462 #define cirrusfb_bus_setup cirrusfb_pci_setup
2463 #elif defined(CONFIG_ZORRO)
2464 #define cirrusfb_unmap cirrusfb_zorro_unmap
2465 #define cirrusfb_bus_setup cirrusfb_zorro_setup
2469 static int cirrusfb_pci_register (struct pci_dev *pdev,
2470 const struct pci_device_id *ent)
2472 struct fb_info *info;
2473 struct cirrusfb_info *cinfo = NULL;
2475 cirrusfb_board_t btype;
2477 DPRINTK ("ENTER\n");
2479 printk (KERN_INFO "cirrusfb: Driver for Cirrus Logic based graphic boards, v" CIRRUSFB_VERSION "\n");
2481 cinfo = cirrusfb_bus_setup(pdev, ent);
2483 if (IS_ERR(cinfo)) {
2484 err = PTR_ERR(cinfo);
2489 btype = cinfo->btype;
2492 assert (btype != BT_NONE);
2493 assert (btype == cirrusfb_board_info[btype].btype);
2495 DPRINTK ("cirrusfb: (RAM start set to: 0x%p)\n", cinfo->fbmem);
2497 /* Make pretend we've set the var so our structures are in a "good" */
2498 /* state, even though we haven't written the mode to the hw yet... */
2499 info->var = cirrusfb_predefined[cirrusfb_def_mode].var;
2500 info->var.activate = FB_ACTIVATE_NOW;
2502 err = cirrusfb_decode_var(&info->var, &cinfo->currentmode, info);
2504 /* should never happen */
2505 DPRINTK("choking on default var... umm, no good.\n");
2506 goto err_unmap_cirrusfb;
2509 /* set all the vital stuff */
2510 cirrusfb_set_fbinfo(cinfo);
2512 pci_set_drvdata(pdev, info);
2514 err = register_framebuffer(info);
2516 printk (KERN_ERR "cirrusfb: could not register fb device; err = %d!\n", err);
2517 goto err_dealloc_cmap;
2520 DPRINTK ("EXIT, returning 0\n");
2524 fb_dealloc_cmap(&info->cmap);
2526 cirrusfb_unmap(cinfo);
2532 static void __devexit cirrusfb_cleanup (struct fb_info *info)
2534 struct cirrusfb_info *cinfo = info->par;
2535 DPRINTK ("ENTER\n");
2538 switch_monitor (cinfo, 0);
2541 unregister_framebuffer (info);
2542 fb_dealloc_cmap (&info->cmap);
2543 printk ("Framebuffer unregistered\n");
2544 cirrusfb_unmap (cinfo);
2550 void __devexit cirrusfb_pci_unregister (struct pci_dev *pdev)
2552 struct fb_info *info = pci_get_drvdata(pdev);
2553 DPRINTK ("ENTER\n");
2555 cirrusfb_cleanup (info);
2560 static struct pci_driver cirrusfb_driver = {
2562 .id_table = cirrusfb_pci_table,
2563 .probe = cirrusfb_pci_register,
2564 .remove = __devexit_p(cirrusfb_pci_unregister),
2567 .suspend = cirrusfb_pci_suspend,
2568 .resume = cirrusfb_pci_resume,
2573 int __init cirrusfb_init(void)
2576 return cirrusfb_pci_register(NULL, NULL);
2578 return pci_module_init(&cirrusfb_driver);
2585 int __init cirrusfb_setup(char *options) {
2586 char *this_opt, s[32];
2589 DPRINTK ("ENTER\n");
2591 if (!options || !*options)
2594 while ((this_opt = strsep (&options, ",")) != NULL) {
2595 if (!*this_opt) continue;
2597 DPRINTK("cirrusfb_setup: option '%s'\n", this_opt);
2599 for (i = 0; i < NUM_TOTAL_MODES; i++) {
2600 sprintf (s, "mode:%s", cirrusfb_predefined[i].name);
2601 if (strcmp (this_opt, s) == 0)
2602 cirrusfb_def_mode = i;
2604 if (!strcmp(this_opt, "noaccel"))
2616 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2617 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2618 MODULE_LICENSE("GPL");
2620 void __exit cirrusfb_exit (void)
2622 pci_unregister_driver (&cirrusfb_driver);
2626 module_init(cirrusfb_init);
2627 module_exit(cirrusfb_exit);
2631 /**********************************************************************/
2632 /* about the following functions - I have used the same names for the */
2633 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2634 /* they just made sense for this purpose. Apart from that, I wrote */
2635 /* these functions myself. */
2636 /**********************************************************************/
2638 /*** WGen() - write into one of the external/general registers ***/
2639 static void WGen (const struct cirrusfb_info *cinfo,
2640 int regnum, unsigned char val)
2642 unsigned long regofs = 0;
2644 if (cinfo->btype == BT_PICASSO) {
2645 /* Picasso II specific hack */
2646 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */
2647 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2651 vga_w (cinfo->regbase, regofs + regnum, val);
2654 /*** RGen() - read out one of the external/general registers ***/
2655 static unsigned char RGen (const struct cirrusfb_info *cinfo, int regnum)
2657 unsigned long regofs = 0;
2659 if (cinfo->btype == BT_PICASSO) {
2660 /* Picasso II specific hack */
2661 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */
2662 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2666 return vga_r (cinfo->regbase, regofs + regnum);
2669 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2670 static void AttrOn (const struct cirrusfb_info *cinfo)
2672 assert (cinfo != NULL);
2674 DPRINTK ("ENTER\n");
2676 if (vga_rcrt (cinfo->regbase, CL_CRT24) & 0x80) {
2677 /* if we're just in "write value" mode, write back the */
2678 /* same value as before to not modify anything */
2679 vga_w (cinfo->regbase, VGA_ATT_IW,
2680 vga_r (cinfo->regbase, VGA_ATT_R));
2682 /* turn on video bit */
2683 /* vga_w (cinfo->regbase, VGA_ATT_IW, 0x20); */
2684 vga_w (cinfo->regbase, VGA_ATT_IW, 0x33);
2686 /* dummy write on Reg0 to be on "write index" mode next time */
2687 vga_w (cinfo->regbase, VGA_ATT_IW, 0x00);
2692 /*** WHDR() - write into the Hidden DAC register ***/
2693 /* as the HDR is the only extension register that requires special treatment
2694 * (the other extension registers are accessible just like the "ordinary"
2695 * registers of their functional group) here is a specialized routine for
2698 static void WHDR (const struct cirrusfb_info *cinfo, unsigned char val)
2700 unsigned char dummy;
2702 if (cinfo->btype == BT_PICASSO) {
2703 /* Klaus' hint for correct access to HDR on some boards */
2704 /* first write 0 to pixel mask (3c6) */
2705 WGen (cinfo, VGA_PEL_MSK, 0x00);
2707 /* next read dummy from pixel address (3c8) */
2708 dummy = RGen (cinfo, VGA_PEL_IW);
2711 /* now do the usual stuff to access the HDR */
2713 dummy = RGen (cinfo, VGA_PEL_MSK);
2715 dummy = RGen (cinfo, VGA_PEL_MSK);
2717 dummy = RGen (cinfo, VGA_PEL_MSK);
2719 dummy = RGen (cinfo, VGA_PEL_MSK);
2722 WGen (cinfo, VGA_PEL_MSK, val);
2725 if (cinfo->btype == BT_PICASSO) {
2726 /* now first reset HDR access counter */
2727 dummy = RGen (cinfo, VGA_PEL_IW);
2730 /* and at the end, restore the mask value */
2731 /* ## is this mask always 0xff? */
2732 WGen (cinfo, VGA_PEL_MSK, 0xff);
2738 /*** WSFR() - write to the "special function register" (SFR) ***/
2739 static void WSFR (struct cirrusfb_info *cinfo, unsigned char val)
2742 assert (cinfo->regbase != NULL);
2744 z_writeb (val, cinfo->regbase + 0x8000);
2748 /* The Picasso has a second register for switching the monitor bit */
2749 static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char val)
2752 /* writing an arbitrary value to this one causes the monitor switcher */
2753 /* to flip to Amiga display */
2754 assert (cinfo->regbase != NULL);
2756 z_writeb (val, cinfo->regbase + 0x9000);
2761 /*** WClut - set CLUT entry (range: 0..63) ***/
2762 static void WClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2763 unsigned char green, unsigned char blue)
2765 unsigned int data = VGA_PEL_D;
2767 /* address write mode register is not translated.. */
2768 vga_w (cinfo->regbase, VGA_PEL_IW, regnum);
2770 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2771 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2772 /* but DAC data register IS, at least for Picasso II */
2773 if (cinfo->btype == BT_PICASSO)
2775 vga_w (cinfo->regbase, data, red);
2776 vga_w (cinfo->regbase, data, green);
2777 vga_w (cinfo->regbase, data, blue);
2779 vga_w (cinfo->regbase, data, blue);
2780 vga_w (cinfo->regbase, data, green);
2781 vga_w (cinfo->regbase, data, red);
2787 /*** RClut - read CLUT entry (range 0..63) ***/
2788 static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2789 unsigned char *green, unsigned char *blue)
2791 unsigned int data = VGA_PEL_D;
2793 vga_w (cinfo->regbase, VGA_PEL_IR, regnum);
2795 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2796 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2797 if (cinfo->btype == BT_PICASSO)
2799 *red = vga_r (cinfo->regbase, data);
2800 *green = vga_r (cinfo->regbase, data);
2801 *blue = vga_r (cinfo->regbase, data);
2803 *blue = vga_r (cinfo->regbase, data);
2804 *green = vga_r (cinfo->regbase, data);
2805 *red = vga_r (cinfo->regbase, data);
2811 /*******************************************************************
2814 Wait for the BitBLT engine to complete a possible earlier job
2815 *********************************************************************/
2817 /* FIXME: use interrupts instead */
2818 static void cirrusfb_WaitBLT (caddr_t regbase)
2820 /* now busy-wait until we're done */
2821 while (vga_rgfx (regbase, CL_GR31) & 0x08)
2825 /*******************************************************************
2828 perform accelerated "scrolling"
2829 ********************************************************************/
2831 static void cirrusfb_BitBLT (caddr_t regbase, int bits_per_pixel,
2832 u_short curx, u_short cury, u_short destx, u_short desty,
2833 u_short width, u_short height, u_short line_length)
2835 u_short nwidth, nheight;
2839 DPRINTK ("ENTER\n");
2842 nheight = height - 1;
2845 /* if source adr < dest addr, do the Blt backwards */
2846 if (cury <= desty) {
2847 if (cury == desty) {
2848 /* if src and dest are on the same line, check x */
2855 /* standard case: forward blitting */
2856 nsrc = (cury * line_length) + curx;
2857 ndest = (desty * line_length) + destx;
2859 /* this means start addresses are at the end, counting backwards */
2860 nsrc = cury * line_length + curx + nheight * line_length + nwidth;
2861 ndest = desty * line_length + destx + nheight * line_length + nwidth;
2865 run-down of registers to be programmed:
2873 VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
2877 cirrusfb_WaitBLT(regbase);
2879 /* pitch: set to line_length */
2880 vga_wgfx (regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
2881 vga_wgfx (regbase, CL_GR25, (line_length >> 8)); /* dest pitch hi */
2882 vga_wgfx (regbase, CL_GR26, line_length & 0xff); /* source pitch low */
2883 vga_wgfx (regbase, CL_GR27, (line_length >> 8)); /* source pitch hi */
2885 /* BLT width: actual number of pixels - 1 */
2886 vga_wgfx (regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
2887 vga_wgfx (regbase, CL_GR21, (nwidth >> 8)); /* BLT width hi */
2889 /* BLT height: actual number of lines -1 */
2890 vga_wgfx (regbase, CL_GR22, nheight & 0xff); /* BLT height low */
2891 vga_wgfx (regbase, CL_GR23, (nheight >> 8)); /* BLT width hi */
2893 /* BLT destination */
2894 vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff)); /* BLT dest low */
2895 vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8)); /* BLT dest mid */
2896 vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16)); /* BLT dest hi */
2899 vga_wgfx (regbase, CL_GR2C, (u_char) (nsrc & 0xff)); /* BLT src low */
2900 vga_wgfx (regbase, CL_GR2D, (u_char) (nsrc >> 8)); /* BLT src mid */
2901 vga_wgfx (regbase, CL_GR2E, (u_char) (nsrc >> 16)); /* BLT src hi */
2904 vga_wgfx (regbase, CL_GR30, bltmode); /* BLT mode */
2906 /* BLT ROP: SrcCopy */
2907 vga_wgfx (regbase, CL_GR32, 0x0d); /* BLT ROP */
2909 /* and finally: GO! */
2910 vga_wgfx (regbase, CL_GR31, 0x02); /* BLT Start/status */
2916 /*******************************************************************
2919 perform accelerated rectangle fill
2920 ********************************************************************/
2922 static void cirrusfb_RectFill (caddr_t regbase, int bits_per_pixel,
2923 u_short x, u_short y, u_short width, u_short height,
2924 u_char color, u_short line_length)
2926 u_short nwidth, nheight;
2930 DPRINTK ("ENTER\n");
2933 nheight = height - 1;
2935 ndest = (y * line_length) + x;
2937 cirrusfb_WaitBLT(regbase);
2939 /* pitch: set to line_length */
2940 vga_wgfx (regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
2941 vga_wgfx (regbase, CL_GR25, (line_length >> 8)); /* dest pitch hi */
2942 vga_wgfx (regbase, CL_GR26, line_length & 0xff); /* source pitch low */
2943 vga_wgfx (regbase, CL_GR27, (line_length >> 8)); /* source pitch hi */
2945 /* BLT width: actual number of pixels - 1 */
2946 vga_wgfx (regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
2947 vga_wgfx (regbase, CL_GR21, (nwidth >> 8)); /* BLT width hi */
2949 /* BLT height: actual number of lines -1 */
2950 vga_wgfx (regbase, CL_GR22, nheight & 0xff); /* BLT height low */
2951 vga_wgfx (regbase, CL_GR23, (nheight >> 8)); /* BLT width hi */
2953 /* BLT destination */
2954 vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff)); /* BLT dest low */
2955 vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8)); /* BLT dest mid */
2956 vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16)); /* BLT dest hi */
2958 /* BLT source: set to 0 (is a dummy here anyway) */
2959 vga_wgfx (regbase, CL_GR2C, 0x00); /* BLT src low */
2960 vga_wgfx (regbase, CL_GR2D, 0x00); /* BLT src mid */
2961 vga_wgfx (regbase, CL_GR2E, 0x00); /* BLT src hi */
2963 /* This is a ColorExpand Blt, using the */
2964 /* same color for foreground and background */
2965 vga_wgfx (regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
2966 vga_wgfx (regbase, VGA_GFX_SR_ENABLE, color); /* background color */
2969 if (bits_per_pixel == 16) {
2970 vga_wgfx (regbase, CL_GR10, color); /* foreground color */
2971 vga_wgfx (regbase, CL_GR11, color); /* background color */
2974 } else if (bits_per_pixel == 32) {
2975 vga_wgfx (regbase, CL_GR10, color); /* foreground color */
2976 vga_wgfx (regbase, CL_GR11, color); /* background color */
2977 vga_wgfx (regbase, CL_GR12, color); /* foreground color */
2978 vga_wgfx (regbase, CL_GR13, color); /* background color */
2979 vga_wgfx (regbase, CL_GR14, 0); /* foreground color */
2980 vga_wgfx (regbase, CL_GR15, 0); /* background color */
2984 /* BLT mode: color expand, Enable 8x8 copy (faster?) */
2985 vga_wgfx (regbase, CL_GR30, op); /* BLT mode */
2987 /* BLT ROP: SrcCopy */
2988 vga_wgfx (regbase, CL_GR32, 0x0d); /* BLT ROP */
2990 /* and finally: GO! */
2991 vga_wgfx (regbase, CL_GR31, 0x02); /* BLT Start/status */
2997 /**************************************************************************
2998 * bestclock() - determine closest possible clock lower(?) than the
2999 * desired pixel clock
3000 **************************************************************************/
3001 static void bestclock (long freq, long *best, long *nom,
3002 long *den, long *div, long maxfreq)
3006 assert (best != NULL);
3007 assert (nom != NULL);
3008 assert (den != NULL);
3009 assert (div != NULL);
3010 assert (maxfreq > 0);
3016 DPRINTK ("ENTER\n");
3027 for (n = 32; n < 128; n++) {
3028 d = (143181 * n) / f;
3029 if ((d >= 7) && (d <= 63)) {
3032 h = (14318 * n) / d;
3033 if (abs (h - freq) < abs (*best - freq)) {
3045 d = ((143181 * n) + f - 1) / f;
3046 if ((d >= 7) && (d <= 63)) {
3049 h = (14318 * n) / d;
3050 if (abs (h - freq) < abs (*best - freq)) {
3064 DPRINTK ("Best possible values for given frequency:\n");
3065 DPRINTK (" best: %ld kHz nom: %ld den: %ld div: %ld\n",
3066 freq, *nom, *den, *div);
3072 /* -------------------------------------------------------------------------
3074 * debugging functions
3076 * -------------------------------------------------------------------------
3079 #ifdef CIRRUSFB_DEBUG
3082 * cirrusfb_dbg_print_byte
3083 * @name: name associated with byte value to be displayed
3084 * @val: byte value to be displayed
3087 * Display an indented string, along with a hexidecimal byte value, and
3088 * its decoded bits. Bits 7 through 0 are listed in left-to-right
3093 void cirrusfb_dbg_print_byte (const char *name, unsigned char val)
3095 DPRINTK ("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
3097 val & 0x80 ? '1' : '0',
3098 val & 0x40 ? '1' : '0',
3099 val & 0x20 ? '1' : '0',
3100 val & 0x10 ? '1' : '0',
3101 val & 0x08 ? '1' : '0',
3102 val & 0x04 ? '1' : '0',
3103 val & 0x02 ? '1' : '0',
3104 val & 0x01 ? '1' : '0');
3109 * cirrusfb_dbg_print_regs
3110 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3111 * @reg_class: type of registers to read: %CRT, or %SEQ
3114 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
3115 * old-style I/O ports are queried for information, otherwise MMIO is
3116 * used at the given @base address to query the information.
3120 void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_class,...)
3123 unsigned char val = 0;
3127 va_start (list, reg_class);
3129 name = va_arg (list, char *);
3130 while (name != NULL) {
3131 reg = va_arg (list, int);
3133 switch (reg_class) {
3135 val = vga_rcrt (regbase, (unsigned char) reg);
3138 val = vga_rseq (regbase, (unsigned char) reg);
3141 /* should never occur */
3146 cirrusfb_dbg_print_byte (name, val);
3148 name = va_arg (list, char *);
3163 void cirrusfb_dump (void)
3165 cirrusfb_dbg_reg_dump (NULL);
3170 * cirrusfb_dbg_reg_dump
3171 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3174 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
3175 * old-style I/O ports are queried for information, otherwise MMIO is
3176 * used at the given @base address to query the information.
3180 void cirrusfb_dbg_reg_dump (caddr_t regbase)
3182 DPRINTK ("CIRRUSFB VGA CRTC register dump:\n");
3184 cirrusfb_dbg_print_regs (regbase, CRT,
3236 DPRINTK ("CIRRUSFB VGA SEQ register dump:\n");
3238 cirrusfb_dbg_print_regs (regbase, SEQ,
3270 #endif /* CIRRUSFB_DEBUG */