3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
11 /* general, but fairly heavy, debugging */
14 /* heavy debugging: */
15 /* -- logs putc[s], so everytime a char is displayed, it's logged */
16 #undef MATROXFB_DEBUG_HEAVY
18 /* This one _could_ cause infinite loops */
19 /* It _does_ cause lots and lots of messages during idle loops */
20 #undef MATROXFB_DEBUG_LOOP
22 /* Debug register calls, too? */
23 #undef MATROXFB_DEBUG_REG
25 /* Guard accelerator accesses with spin_lock_irqsave... */
26 #undef MATROXFB_USE_SPINLOCKS
28 #include <linux/config.h>
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/errno.h>
32 #include <linux/string.h>
34 #include <linux/tty.h>
35 #include <linux/slab.h>
36 #include <linux/delay.h>
38 #include <linux/console.h>
39 #include <linux/selection.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/timer.h>
43 #include <linux/pci.h>
44 #include <linux/spinlock.h>
48 #include <asm/unaligned.h>
53 #include "../console/fbcon.h"
55 #if defined(CONFIG_PPC_PMAC)
57 #include <asm/pci-bridge.h>
58 #include "../macmodes.h"
61 /* always compile support for 32MB... It cost almost nothing */
62 #define CONFIG_FB_MATROX_32MB
67 #define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x));
69 #ifdef MATROXFB_DEBUG_HEAVY
70 #define DBG_HEAVY(x) DBG(x)
71 #else /* MATROXFB_DEBUG_HEAVY */
72 #define DBG_HEAVY(x) /* DBG_HEAVY */
73 #endif /* MATROXFB_DEBUG_HEAVY */
75 #ifdef MATROXFB_DEBUG_LOOP
76 #define DBG_LOOP(x) DBG(x)
77 #else /* MATROXFB_DEBUG_LOOP */
78 #define DBG_LOOP(x) /* DBG_LOOP */
79 #endif /* MATROXFB_DEBUG_LOOP */
81 #ifdef MATROXFB_DEBUG_REG
82 #define DBG_REG(x) DBG(x)
83 #else /* MATROXFB_DEBUG_REG */
84 #define DBG_REG(x) /* DBG_REG */
85 #endif /* MATROXFB_DEBUG_REG */
87 #else /* MATROXFB_DEBUG */
89 #define DBG(x) /* DBG */
90 #define DBG_HEAVY(x) /* DBG_HEAVY */
91 #define DBG_REG(x) /* DBG_REG */
92 #define DBG_LOOP(x) /* DBG_LOOP */
94 #endif /* MATROXFB_DEBUG */
96 #if !defined(__i386__) && !defined(__x86_64__)
97 #ifndef ioremap_nocache
98 #define ioremap_nocache(X,Y) ioremap(X,Y)
102 #if defined(__alpha__) || defined(__mc68000__)
104 #define MEMCPYTOIO_WORKS
107 /* recheck __ppc__, maybe that __ppc__ needs MEMCPYTOIO_WRITEL */
108 /* I benchmarked PII/350MHz with G200... MEMCPY, MEMCPYTOIO and WRITEL are on same speed ( <2% diff) */
109 /* so that means that G200 speed (or AGP speed?) is our limit... I do not have benchmark to test, how */
110 /* much of PCI bandwidth is used during transfers... */
111 #if defined(__i386__) || defined(__x86_64__)
112 #define MEMCPYTOIO_MEMCPY
114 #define MEMCPYTOIO_WRITEL
118 #if defined(__mc68000__)
119 #define MAP_BUSTOVIRT
125 #define dprintk(X...) printk(X)
127 #define dprintk(X...)
130 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
131 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
133 #ifndef PCI_SS_VENDOR_ID_MATROX
134 #define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX
137 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
138 #define PCI_SS_ID_MATROX_GENERIC 0xFF00
139 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
140 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
141 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
142 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
143 #define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
144 #define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
145 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179
146 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */
147 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */
150 #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
151 #define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR
152 #define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR
154 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
156 /* G-series and Mystique have (almost) same DAC */
158 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G100)
159 #define NEED_DAC1064 1
167 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
168 return readb(va.vaddr + offs);
171 static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) {
172 return readw(va.vaddr + offs);
175 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
176 return readl(va.vaddr + offs);
179 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
180 writeb(value, va.vaddr + offs);
183 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
184 writew(value, va.vaddr + offs);
187 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
188 writel(value, va.vaddr + offs);
191 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
192 return *(volatile u_int8_t*)(va.vaddr + offs);
195 static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) {
196 return *(volatile u_int16_t*)(va.vaddr + offs);
199 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
200 return *(volatile u_int32_t*)(va.vaddr + offs);
203 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
204 *(volatile u_int8_t*)(va.vaddr + offs) = value;
207 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
208 *(volatile u_int16_t*)(va.vaddr + offs) = value;
211 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
212 *(volatile u_int32_t*)(va.vaddr + offs) = value;
216 static inline void mga_memcpy_toio(vaddr_t va, unsigned int offs, const void* src, int len) {
217 #ifdef MEMCPYTOIO_WORKS
218 memcpy_toio(va.vaddr + offs, src, len);
219 #elif defined(MEMCPYTOIO_WRITEL)
222 mga_writel(va, offs, get_unaligned((u32 *)src));
229 mga_writel(va, offs, *(u32 *)src);
238 memcpy(&tmp, src, len);
239 mga_writel(va, offs, tmp);
241 #elif defined(MEMCPYTOIO_MEMCPY)
242 memcpy(va.vaddr + offs, src, len);
244 #error "Sorry, do not know how to write block of data to device"
248 static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
252 static inline void* vaddr_va(vaddr_t va) {
256 #define MGA_IOREMAP_NORMAL 0
257 #define MGA_IOREMAP_NOCACHE 1
259 #define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE
260 #define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE
261 static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) {
263 if (flags & MGA_IOREMAP_NOCACHE)
264 virt->vaddr = ioremap_nocache(phys, size);
266 virt->vaddr = ioremap(phys, size);
269 virt->vaddr = bus_to_virt(phys);
271 #error "Your architecture does not have neither ioremap nor bus_to_virt... Giving up"
274 return (virt->vaddr == 0); /* 0, !0... 0, error_code in future */
277 static inline void mga_iounmap(vaddr_t va) {
284 unsigned int pixclock;
287 unsigned int HDisplay;
288 unsigned int HSyncStart;
289 unsigned int HSyncEnd;
291 unsigned int VDisplay;
292 unsigned int VSyncStart;
293 unsigned int VSyncEnd;
298 unsigned int delay; /* CRTC delay */
301 enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL };
303 struct matrox_pll_cache {
306 unsigned int mnp_key;
307 unsigned int mnp_value;
311 struct matrox_pll_limits {
316 struct matrox_pll_features {
317 unsigned int vco_freq_min;
318 unsigned int ref_freq;
319 unsigned int feed_div_min;
320 unsigned int feed_div_max;
321 unsigned int in_div_min;
322 unsigned int in_div_max;
323 unsigned int post_shift_max;
328 unsigned int final_bppShift;
329 unsigned int cmap_len;
337 struct matrox_fb_info;
339 struct matrox_DAC1064_features {
344 struct matrox_accel_features {
348 /* current hardware status */
360 struct matrox_crtc2 {
364 struct matrox_hw_state {
365 u_int32_t MXoptionReg;
366 unsigned char DACclk[6];
367 unsigned char DACreg[80];
368 unsigned char MiscOutReg;
369 unsigned char DACpal[768];
370 unsigned char CRTC[25];
371 unsigned char CRTCEXT[9];
372 unsigned char SEQ[5];
373 /* unused for MGA mode, but who knows... */
374 unsigned char GCTL[9];
375 /* unused for MGA mode, but who knows... */
376 unsigned char ATTR[21];
379 struct mavenregs maven;
381 struct matrox_crtc2 crtc2;
384 struct matrox_accel_data {
385 #ifdef CONFIG_FB_MATROX_MILLENIUM
386 unsigned char ramdac_rev;
388 u_int32_t m_dwg_rect;
392 struct v4l2_queryctrl;
395 struct matrox_altout {
397 int (*compute)(void* altout_dev, struct my_timming* input);
398 int (*program)(void* altout_dev);
399 int (*start)(void* altout_dev);
400 int (*verifymode)(void* altout_dev, u_int32_t mode);
401 int (*getqueryctrl)(void* altout_dev,
402 struct v4l2_queryctrl* ctrl);
403 int (*getctrl)(void* altout_dev,
404 struct v4l2_control* ctrl);
405 int (*setctrl)(void* altout_dev,
406 struct v4l2_control* ctrl);
409 #define MATROXFB_SRC_NONE 0
410 #define MATROXFB_SRC_CRTC1 1
411 #define MATROXFB_SRC_CRTC2 2
413 enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 };
416 unsigned int bios_valid : 1;
417 unsigned int pins_len;
418 unsigned char pins[128];
420 unsigned char vMaj, vMin, vRev;
423 unsigned char state, tvout;
427 extern struct display fb_display[];
429 struct matrox_switch;
430 struct matroxfb_driver;
431 struct matroxfb_dh_fb_info;
433 struct matrox_vsync {
434 wait_queue_head_t wait;
438 struct matrox_fb_info {
439 struct fb_info fbcon;
441 struct list_head next_fb;
444 unsigned int usecount;
446 unsigned int userusecount;
447 unsigned long irq_flags;
449 struct matroxfb_par curr;
450 struct matrox_hw_state hw;
452 struct matrox_accel_data accel;
454 struct pci_dev* pcidev;
457 struct matrox_vsync vsync;
458 unsigned int pixclock;
463 struct matrox_vsync vsync;
464 unsigned int pixclock;
466 struct matroxfb_dh_fb_info* info;
467 struct rw_semaphore lock;
470 struct rw_semaphore lock;
472 int brightness, contrast, saturation, hue, gamma;
473 int testout, deflicker;
476 #define MATROXFB_MAX_OUTPUTS 3
479 struct matrox_altout* output;
482 unsigned int default_src;
483 } outputs[MATROXFB_MAX_OUTPUTS];
485 #define MATROXFB_MAX_FB_DRIVERS 5
486 struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
487 void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
488 unsigned int drivers_count;
491 unsigned long base; /* physical */
492 vaddr_t vbase; /* CPU view */
494 unsigned int len_usable;
495 unsigned int len_maximum;
499 unsigned long base; /* physical */
500 vaddr_t vbase; /* CPU view */
504 unsigned int max_pixel_clock;
506 struct matrox_switch* hw_switch;
509 struct matrox_pll_features pll;
510 struct matrox_DAC1064_features DAC1064;
511 struct matrox_accel_features accel;
545 #ifdef CONFIG_FB_MATROX_32MB
554 unsigned int vgastep;
555 unsigned int textmode;
556 unsigned int textstep;
557 unsigned int textvram; /* character cells */
558 unsigned int ydstorg; /* offset in bytes from video start to usable memory */
559 /* 0 except for 6MB Millenium */
563 int panellink; /* G400 DFP possible (not G450/G550) */
565 unsigned int fbResource;
568 struct matrox_bios bios;
570 struct matrox_pll_limits pixel;
571 struct matrox_pll_limits system;
572 struct matrox_pll_limits video;
575 struct matrox_pll_cache pixel;
576 struct matrox_pll_cache system;
577 struct matrox_pll_cache video;
589 u_int32_t mctlwtst_core;
603 #define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
605 #ifdef CONFIG_FB_MATROX_MULTIHEAD
606 #define ACCESS_FBINFO2(info, x) (info->x)
607 #define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
611 #define WPMINFO2 struct matrox_fb_info* minfo
612 #define WPMINFO WPMINFO2 ,
613 #define CPMINFO2 const struct matrox_fb_info* minfo
614 #define CPMINFO CPMINFO2 ,
615 #define PMINFO2 minfo
616 #define PMINFO PMINFO2 ,
618 #define MINFO_FROM(x) struct matrox_fb_info* minfo = x
621 extern struct matrox_fb_info matroxfb_global_mxinfo;
623 #define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x)
624 #define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x)
626 #define MINFO (&matroxfb_global_mxinfo)
628 #define WPMINFO2 void
630 #define CPMINFO2 void
635 #define MINFO_FROM(x)
639 #define MINFO_FROM_INFO(x) MINFO_FROM(info2minfo(x))
641 struct matrox_switch {
642 int (*preinit)(WPMINFO2);
643 void (*reset)(WPMINFO2);
644 int (*init)(WPMINFO struct my_timming*);
645 void (*restore)(WPMINFO2);
648 struct matroxfb_driver {
649 struct list_head node;
651 void* (*probe)(struct matrox_fb_info* info);
652 void (*remove)(struct matrox_fb_info* info, void* data);
655 int matroxfb_register_driver(struct matroxfb_driver* drv);
656 void matroxfb_unregister_driver(struct matroxfb_driver* drv);
658 #define PCI_OPTION_REG 0x40
659 #define PCI_OPTION_ENABLE_ROM 0x40000000
661 #define PCI_MGA_INDEX 0x44
662 #define PCI_MGA_DATA 0x48
663 #define PCI_OPTION2_REG 0x50
664 #define PCI_OPTION3_REG 0x54
665 #define PCI_MEMMISC_REG 0x58
667 #define M_DWGCTL 0x1C00
668 #define M_MACCESS 0x1C04
669 #define M_CTLWTST 0x1C08
671 #define M_PLNWT 0x1C1C
673 #define M_BCOL 0x1C20
674 #define M_FCOL 0x1C24
686 #define M_CXBNDRY 0x1C80
687 #define M_FXBNDRY 0x1C84
688 #define M_YDSTLEN 0x1C88
689 #define M_PITCH 0x1C8C
690 #define M_YDST 0x1C90
691 #define M_YDSTORG 0x1C94
692 #define M_YTOP 0x1C98
693 #define M_YBOT 0x1C9C
696 #define M_CACHEFLUSH 0x1FFF
698 #define M_EXEC 0x0100
700 #define M_DWG_TRAP 0x04
701 #define M_DWG_BITBLT 0x08
702 #define M_DWG_ILOAD 0x09
704 #define M_DWG_LINEAR 0x0080
705 #define M_DWG_SOLID 0x0800
706 #define M_DWG_ARZERO 0x1000
707 #define M_DWG_SGNZERO 0x2000
708 #define M_DWG_SHIFTZERO 0x4000
710 #define M_DWG_REPLACE 0x000C0000
711 #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
712 #define M_DWG_XOR 0x00060010
714 #define M_DWG_BFCOL 0x04000000
715 #define M_DWG_BMONOWF 0x08000000
717 #define M_DWG_TRANSC 0x40000000
719 #define M_FIFOSTATUS 0x1E10
720 #define M_STATUS 0x1E14
721 #define M_ICLEAR 0x1E18
724 #define M_VCOUNT 0x1E20
726 #define M_RESET 0x1E40
727 #define M_MEMRDBK 0x1E44
729 #define M_AGP2PLL 0x1E4C
731 #define M_OPMODE 0x1E54
732 #define M_OPMODE_DMA_GEN_WRITE 0x00
733 #define M_OPMODE_DMA_BLIT 0x04
734 #define M_OPMODE_DMA_VECTOR_WRITE 0x08
735 #define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */
736 #define M_OPMODE_DMA_BE_8BPP 0x0000
737 #define M_OPMODE_DMA_BE_16BPP 0x0100
738 #define M_OPMODE_DMA_BE_32BPP 0x0200
739 #define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */
740 #define M_OPMODE_DIR_BE_8BPP 0x000000
741 #define M_OPMODE_DIR_BE_16BPP 0x010000
742 #define M_OPMODE_DIR_BE_32BPP 0x020000
744 #define M_ATTR_INDEX 0x1FC0
745 #define M_ATTR_DATA 0x1FC1
747 #define M_MISC_REG 0x1FC2
748 #define M_3C2_RD 0x1FC2
750 #define M_SEQ_INDEX 0x1FC4
751 #define M_SEQ_DATA 0x1FC5
753 #define M_MISC_REG_READ 0x1FCC
755 #define M_GRAPHICS_INDEX 0x1FCE
756 #define M_GRAPHICS_DATA 0x1FCF
758 #define M_CRTC_INDEX 0x1FD4
760 #define M_ATTR_RESET 0x1FDA
761 #define M_3DA_WR 0x1FDA
762 #define M_INSTS1 0x1FDA
764 #define M_EXTVGA_INDEX 0x1FDE
765 #define M_EXTVGA_DATA 0x1FDF
768 #define M_SRCORG 0x2CB4
769 #define M_DSTORG 0x2CB8
771 #define M_RAMDAC_BASE 0x3C00
773 /* fortunately, same on TVP3026 and MGA1064 */
774 #define M_DAC_REG (M_RAMDAC_BASE+0)
775 #define M_DAC_VAL (M_RAMDAC_BASE+1)
776 #define M_PALETTE_MASK (M_RAMDAC_BASE+2)
778 #define M_X_INDEX 0x00
779 #define M_X_DATAREG 0x0A
781 #define DAC_XGENIOCTRL 0x2A
782 #define DAC_XGENIODATA 0x2B
784 #define M_C2CTL 0x3E10
786 #ifdef __LITTLE_ENDIAN
787 #define MX_OPTION_BSWAP 0x00000000
789 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
790 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
791 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
792 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
793 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
796 #define MX_OPTION_BSWAP 0x80000000
798 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */
799 #define M_OPMODE_8BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT)
800 #define M_OPMODE_16BPP (M_OPMODE_DMA_BE_16BPP | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
801 #define M_OPMODE_24BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */
802 #define M_OPMODE_32BPP (M_OPMODE_DMA_BE_32BPP | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
804 #error "Byte ordering have to be defined. Cannot continue."
808 #define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr))
809 #define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr))
810 #define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val))
811 #define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val))
812 #define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val))
813 #define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
814 #ifdef __LITTLE_ENDIAN
815 #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
817 #define mga_setr(addr,port,val) do { mga_outb(addr, port); mga_outb((addr)+1, val); } while (0)
820 #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
822 #define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000)
825 #ifdef CONFIG_FB_MATROX_MILLENIUM
826 #define isInterleave(x) (x->interleave)
827 #define isMillenium(x) (x->millenium)
828 #define isMilleniumII(x) (x->milleniumII)
830 #define isInterleave(x) (0)
831 #define isMillenium(x) (0)
832 #define isMilleniumII(x) (0)
835 #define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC))
836 #define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC))
837 #define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags)
838 #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags)
839 extern void matroxfb_DAC_out(CPMINFO int reg, int val);
840 extern int matroxfb_DAC_in(CPMINFO int reg);
841 extern struct list_head matroxfb_list;
842 extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
843 extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc);
844 extern int matroxfb_enable_irq(WPMINFO int reenable);
846 #ifdef MATROXFB_USE_SPINLOCKS
847 #define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags);
848 #define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags);
849 #define CRITFLAGS unsigned long critflags;
856 #endif /* __MATROXFB_H__ */