2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
18 #include <linux/tty.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
29 #include <asm/pci-bridge.h>
31 #ifdef CONFIG_PMAC_BACKLIGHT
32 #include <asm/backlight.h>
34 #ifdef CONFIG_BOOTX_TEXT
35 #include <asm/btext.h>
43 #ifndef CONFIG_PCI /* sanity check */
44 #error This driver requires PCI support.
47 #undef CONFIG_FB_NVIDIA_DEBUG
48 #ifdef CONFIG_FB_NVIDIA_DEBUG
49 #define NVTRACE printk
51 #define NVTRACE if (0) printk
54 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
55 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
57 #ifdef CONFIG_FB_NVIDIA_DEBUG
58 #define assert(expr) \
60 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
61 #expr,__FILE__,__FUNCTION__,__LINE__); \
68 #define PFX "nvidiafb: "
70 /* HW cursor parameters */
73 static struct pci_device_id nvidiafb_pci_tbl[] = {
74 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
75 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
76 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
77 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
78 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
79 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
80 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN,
81 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
82 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
83 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
84 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
85 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
86 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
87 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
88 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
89 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
90 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
91 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
92 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
93 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
94 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
95 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
96 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
97 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
98 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
99 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
100 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
102 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
104 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
106 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
108 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
110 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
112 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
114 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
116 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
118 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
120 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
122 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
124 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
126 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
128 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
130 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
132 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
134 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
136 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
138 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
140 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
142 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
144 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
146 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
148 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO,
149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
150 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL,
151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
152 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC,
153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
154 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS,
155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
156 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
158 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
160 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
162 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
164 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
166 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
168 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
170 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
172 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
174 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
176 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
178 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
180 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
182 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
184 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
186 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
188 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
190 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
192 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
194 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
196 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
198 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
200 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
202 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
204 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
206 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
208 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
210 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
212 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
214 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200,
215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
216 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
218 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
220 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
222 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
224 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
226 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
228 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
230 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
232 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
234 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
236 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
238 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
240 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
242 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT,
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
244 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA,
245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
246 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000,
247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
248 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA,
249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
250 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700,
251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
252 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE,
253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
254 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE,
255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
256 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
258 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2,
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
260 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000,
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
262 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100,
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
264 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500,
265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
266 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100,
267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
268 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700,
269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
270 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT,
271 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
272 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA,
273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
274 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800,
275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
276 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE,
277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
278 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
280 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000,
281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
282 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT,
283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
284 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600,
285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
286 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL,
287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
288 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540,
289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
290 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200,
291 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
292 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1,
293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
294 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1,
295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
296 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2,
297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
298 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1,
299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
300 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
301 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
302 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280,
303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
304 {PCI_VENDOR_ID_NVIDIA, 0x0252,
305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
306 {PCI_VENDOR_ID_NVIDIA, 0x0313,
307 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
308 {PCI_VENDOR_ID_NVIDIA, 0x0316,
309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
310 {PCI_VENDOR_ID_NVIDIA, 0x0317,
311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
312 {PCI_VENDOR_ID_NVIDIA, 0x031D,
313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
314 {PCI_VENDOR_ID_NVIDIA, 0x031E,
315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
316 {PCI_VENDOR_ID_NVIDIA, 0x031F,
317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
318 {PCI_VENDOR_ID_NVIDIA, 0x0329,
319 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
320 {PCI_VENDOR_ID_NVIDIA, 0x032F,
321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
322 {PCI_VENDOR_ID_NVIDIA, 0x0345,
323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
324 {PCI_VENDOR_ID_NVIDIA, 0x0349,
325 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
326 {PCI_VENDOR_ID_NVIDIA, 0x034B,
327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
328 {PCI_VENDOR_ID_NVIDIA, 0x034F,
329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
330 {PCI_VENDOR_ID_NVIDIA, 0x00c0,
331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
332 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A,
333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
334 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A_LE,
335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
336 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800,
337 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
338 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA,
339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
340 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_GO1400,
341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
342 {PCI_VENDOR_ID_NVIDIA, 0x00cd,
343 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
344 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_1400,
345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
346 {PCI_VENDOR_ID_NVIDIA, 0x0142,
347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
348 {PCI_VENDOR_ID_NVIDIA, 0x0143,
349 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
350 {PCI_VENDOR_ID_NVIDIA, 0x0144,
351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
352 {PCI_VENDOR_ID_NVIDIA, 0x0145,
353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
354 {PCI_VENDOR_ID_NVIDIA, 0x0146,
355 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
356 {PCI_VENDOR_ID_NVIDIA, 0x0147,
357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
358 {PCI_VENDOR_ID_NVIDIA, 0x0148,
359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
360 {PCI_VENDOR_ID_NVIDIA, 0x0149,
361 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
362 {PCI_VENDOR_ID_NVIDIA, 0x014b,
363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
364 {PCI_VENDOR_ID_NVIDIA, 0x14c,
365 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
366 {PCI_VENDOR_ID_NVIDIA, 0x014d,
367 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
368 {PCI_VENDOR_ID_NVIDIA, 0x0160,
369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
370 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE,
371 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
372 {PCI_VENDOR_ID_NVIDIA, 0x0162,
373 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
374 {PCI_VENDOR_ID_NVIDIA, 0x0163,
375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
376 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200,
377 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
378 {PCI_VENDOR_ID_NVIDIA, 0x0165,
379 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
380 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250,
381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
382 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1,
383 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
384 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1,
385 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
386 {PCI_VENDOR_ID_NVIDIA, 0x0169,
387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
388 {PCI_VENDOR_ID_NVIDIA, 0x016b,
389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
390 {PCI_VENDOR_ID_NVIDIA, 0x016c,
391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
392 {PCI_VENDOR_ID_NVIDIA, 0x016d,
393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
394 {PCI_VENDOR_ID_NVIDIA, 0x016e,
395 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
396 {PCI_VENDOR_ID_NVIDIA, 0x0210,
397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
398 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B,
399 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
400 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE,
401 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
402 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT,
403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
404 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT,
405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
406 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX,
407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
408 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800,
409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
410 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX,
411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
412 {PCI_VENDOR_ID_NVIDIA, 0x021d,
413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
414 {PCI_VENDOR_ID_NVIDIA, 0x021e,
415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
416 {PCI_VENDOR_ID_NVIDIA, 0x0220,
417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
418 {PCI_VENDOR_ID_NVIDIA, 0x0221,
419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
420 {PCI_VENDOR_ID_NVIDIA, 0x0222,
421 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
422 {PCI_VENDOR_ID_NVIDIA, 0x0228,
423 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
424 {0,} /* terminate list */
427 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
429 /* command line data, set in nvidiafb_setup() */
430 static int flatpanel __devinitdata = -1; /* Autodetect later */
431 static int fpdither __devinitdata = -1;
432 static int forceCRTC __devinitdata = -1;
433 static int hwcur __devinitdata = 0;
434 static int noaccel __devinitdata = 0;
435 static int noscale __devinitdata = 0;
436 static int paneltweak __devinitdata = 0;
437 static int vram __devinitdata = 0;
438 static int bpp __devinitdata = 8;
440 static int nomtrr __devinitdata = 0;
443 static char *mode_option __devinitdata = NULL;
445 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
446 .type = FB_TYPE_PACKED_PIXELS,
451 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
461 .activate = FB_ACTIVATE_NOW,
471 .vmode = FB_VMODE_NONINTERLACED
477 #ifdef CONFIG_PMAC_BACKLIGHT
479 static int nvidia_backlight_levels[] = {
498 /* ------------------------------------------------------------------------- *
500 * Backlight operations
502 * ------------------------------------------------------------------------- */
504 static int nvidia_set_backlight_enable(int on, int level, void *data)
506 struct nvidia_par *par = data;
507 u32 tmp_pcrt, tmp_pmc, fpcontrol;
509 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
510 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
511 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
513 if (on && (level > BACKLIGHT_OFF)) {
515 tmp_pmc |= (1 << 31); // backlight bit
516 tmp_pmc |= nvidia_backlight_levels[level - 1] << 16;
520 fpcontrol |= par->fpSyncs;
522 fpcontrol |= 0x20000022;
524 NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
525 NV_WR32(par->PMC, 0x10F0, tmp_pmc);
526 NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
531 static int nvidia_set_backlight_level(int level, void *data)
533 return nvidia_set_backlight_enable(1, level, data);
536 static struct backlight_controller nvidia_backlight_controller = {
537 nvidia_set_backlight_enable,
538 nvidia_set_backlight_level
541 #endif /* CONFIG_PMAC_BACKLIGHT */
543 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
544 u16 bg, u16 fg, u32 w, u32 h)
546 u32 *data = (u32 *) data8;
552 for (i = 0; i < h; i++) {
556 for (j = 0; j < w / 2; j++) {
558 #if defined (__BIG_ENDIAN)
559 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
561 tmp |= (b & (1 << 31)) ? fg : bg;
564 tmp = (b & 1) ? fg : bg;
566 tmp |= (b & 1) ? fg << 16 : bg << 16;
569 NV_WR32(&par->CURSOR[k++], 0, tmp);
571 k += (MAX_CURS - w) / 2;
575 static void nvidia_write_clut(struct nvidia_par *par,
576 u8 regnum, u8 red, u8 green, u8 blue)
578 NVWriteDacMask(par, 0xff);
579 NVWriteDacWriteAddr(par, regnum);
580 NVWriteDacData(par, red);
581 NVWriteDacData(par, green);
582 NVWriteDacData(par, blue);
585 static void nvidia_read_clut(struct nvidia_par *par,
586 u8 regnum, u8 * red, u8 * green, u8 * blue)
588 NVWriteDacMask(par, 0xff);
589 NVWriteDacReadAddr(par, regnum);
590 *red = NVReadDacData(par);
591 *green = NVReadDacData(par);
592 *blue = NVReadDacData(par);
595 static int nvidia_panel_tweak(struct nvidia_par *par,
596 struct _riva_hw_state *state)
600 if (par->paneltweak) {
601 tweak = par->paneltweak;
603 /* begin flat panel hacks */
604 /* This is unfortunate, but some chips need this register
605 tweaked or else you get artifacts where adjacent pixels are
606 swapped. There are no hard rules for what to set here so all
607 we can do is experiment and apply hacks. */
609 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
610 /* At least one NV34 laptop needs this workaround. */
614 if((par->Chipset & 0xfff0) == 0x0310) {
617 /* end flat panel hacks */
623 static void nvidia_save_vga(struct nvidia_par *par,
624 struct _riva_hw_state *state)
629 NVLockUnlock(par, 0);
631 NVUnloadStateExt(par, state);
633 state->misc_output = NVReadMiscOut(par);
635 for (i = 0; i < NUM_CRT_REGS; i++)
636 state->crtc[i] = NVReadCrtc(par, i);
638 for (i = 0; i < NUM_ATC_REGS; i++)
639 state->attr[i] = NVReadAttr(par, i);
641 for (i = 0; i < NUM_GRC_REGS; i++)
642 state->gra[i] = NVReadGr(par, i);
644 for (i = 0; i < NUM_SEQ_REGS; i++)
645 state->seq[i] = NVReadSeq(par, i);
651 static void nvidia_write_regs(struct nvidia_par *par)
653 struct _riva_hw_state *state = &par->ModeReg;
658 NVLoadStateExt(par, state);
660 NVWriteMiscOut(par, state->misc_output);
662 for (i = 1; i < NUM_SEQ_REGS; i++) {
664 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
666 NVWriteSeq(par, i, state->seq[i]);
669 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
670 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
672 for (i = 0; i < NUM_CRT_REGS; i++) {
679 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
681 NVWriteCrtc(par, i, state->crtc[i]);
685 for (i = 0; i < NUM_GRC_REGS; i++) {
687 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
689 NVWriteGr(par, i, state->gra[i]);
692 for (i = 0; i < NUM_ATC_REGS; i++) {
694 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
696 NVWriteAttr(par, i, state->attr[i]);
702 static void nvidia_vga_protect(struct nvidia_par *par, int on)
708 * Turn off screen and disable sequencer.
710 tmp = NVReadSeq(par, 0x01);
712 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
713 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
716 * Reenable sequencer, then turn on screen.
719 tmp = NVReadSeq(par, 0x01);
721 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
722 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
728 static int nvidia_calc_regs(struct fb_info *info)
730 struct nvidia_par *par = info->par;
731 struct _riva_hw_state *state = &par->ModeReg;
732 int i, depth = fb_get_color_depth(&info->var, &info->fix);
733 int h_display = info->var.xres / 8 - 1;
734 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
735 int h_end = (info->var.xres + info->var.right_margin +
736 info->var.hsync_len) / 8 - 1;
737 int h_total = (info->var.xres + info->var.right_margin +
738 info->var.hsync_len + info->var.left_margin) / 8 - 5;
739 int h_blank_s = h_display;
740 int h_blank_e = h_total + 4;
741 int v_display = info->var.yres - 1;
742 int v_start = info->var.yres + info->var.lower_margin - 1;
743 int v_end = (info->var.yres + info->var.lower_margin +
744 info->var.vsync_len) - 1;
745 int v_total = (info->var.yres + info->var.lower_margin +
746 info->var.vsync_len + info->var.upper_margin) - 2;
747 int v_blank_s = v_display;
748 int v_blank_e = v_total + 1;
751 * Set all CRTC values.
754 if (info->var.vmode & FB_VMODE_INTERLACED)
757 if (par->FlatPanel == 1) {
758 v_start = v_total - 3;
761 h_start = h_total - 5;
763 h_blank_e = h_total + 4;
766 state->crtc[0x0] = Set8Bits(h_total);
767 state->crtc[0x1] = Set8Bits(h_display);
768 state->crtc[0x2] = Set8Bits(h_blank_s);
769 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
771 state->crtc[0x4] = Set8Bits(h_start);
772 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
773 | SetBitField(h_end, 4: 0, 4:0);
774 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
775 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
776 | SetBitField(v_display, 8: 8, 1:1)
777 | SetBitField(v_start, 8: 8, 2:2)
778 | SetBitField(v_blank_s, 8: 8, 3:3)
780 | SetBitField(v_total, 9: 9, 5:5)
781 | SetBitField(v_display, 9: 9, 6:6)
782 | SetBitField(v_start, 9: 9, 7:7);
783 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
785 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
786 state->crtc[0x10] = Set8Bits(v_start);
787 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
788 state->crtc[0x12] = Set8Bits(v_display);
789 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
790 (info->var.bits_per_pixel / 8));
791 state->crtc[0x15] = Set8Bits(v_blank_s);
792 state->crtc[0x16] = Set8Bits(v_blank_e);
794 state->attr[0x10] = 0x01;
797 state->attr[0x11] = 0x00;
799 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
800 | SetBitField(v_blank_s, 10: 10, 3:3)
801 | SetBitField(v_start, 10: 10, 2:2)
802 | SetBitField(v_display, 10: 10, 1:1)
803 | SetBitField(v_total, 10: 10, 0:0);
805 state->horiz = SetBitField(h_total, 8: 8, 0:0)
806 | SetBitField(h_display, 8: 8, 1:1)
807 | SetBitField(h_blank_s, 8: 8, 2:2)
808 | SetBitField(h_start, 8: 8, 3:3);
810 state->extra = SetBitField(v_total, 11: 11, 0:0)
811 | SetBitField(v_display, 11: 11, 2:2)
812 | SetBitField(v_start, 11: 11, 4:4)
813 | SetBitField(v_blank_s, 11: 11, 6:6);
815 if (info->var.vmode & FB_VMODE_INTERLACED) {
816 h_total = (h_total >> 1) & ~1;
817 state->interlace = Set8Bits(h_total);
818 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
820 state->interlace = 0xff; /* interlace off */
824 * Calculate the extended registers.
832 if (par->Architecture >= NV_ARCH_10)
833 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
836 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
837 state->misc_output &= ~0x40;
839 state->misc_output |= 0x40;
840 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
841 state->misc_output &= ~0x80;
843 state->misc_output |= 0x80;
845 NVCalcStateExt(par, state, i, info->var.xres_virtual,
846 info->var.xres, info->var.yres_virtual,
847 1000000000 / info->var.pixclock, info->var.vmode);
849 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
850 if (par->FlatPanel == 1) {
851 state->pixel |= (1 << 7);
853 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
854 || (par->fpHeight <= info->var.yres)) {
855 state->scale |= (1 << 8);
858 if (!par->crtcSync_read) {
859 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
860 par->crtcSync_read = 1;
863 par->PanelTweak = nvidia_panel_tweak(par, state);
866 state->vpll = state->pll;
867 state->vpll2 = state->pll;
868 state->vpllB = state->pllB;
869 state->vpll2B = state->pllB;
871 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
872 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
874 if (par->CRTCnumber) {
875 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
876 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
877 state->crtcOwner = 3;
878 state->pllsel |= 0x20000800;
879 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
880 if (par->twoStagePLL)
881 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
882 } else if (par->twoHeads) {
883 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
884 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
885 state->crtcOwner = 0;
886 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
887 if (par->twoStagePLL)
888 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
891 state->cursorConfig = 0x00000100;
893 if (info->var.vmode & FB_VMODE_DOUBLE)
894 state->cursorConfig |= (1 << 4);
896 if (par->alphaCursor) {
897 if ((par->Chipset & 0x0ff0) != 0x0110)
898 state->cursorConfig |= 0x04011000;
900 state->cursorConfig |= 0x14011000;
901 state->general |= (1 << 29);
903 state->cursorConfig |= 0x02000000;
906 if ((par->Chipset & 0x0ff0) == 0x0110) {
907 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
910 state->dither |= 0x00010000;
912 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
920 state->displayV = info->var.xres;
925 static void nvidia_init_vga(struct fb_info *info)
927 struct nvidia_par *par = info->par;
928 struct _riva_hw_state *state = &par->ModeReg;
931 for (i = 0; i < 0x10; i++)
933 state->attr[0x10] = 0x41;
934 state->attr[0x11] = 0xff;
935 state->attr[0x12] = 0x0f;
936 state->attr[0x13] = 0x00;
937 state->attr[0x14] = 0x00;
939 memset(state->crtc, 0x00, NUM_CRT_REGS);
940 state->crtc[0x0a] = 0x20;
941 state->crtc[0x17] = 0xe3;
942 state->crtc[0x18] = 0xff;
943 state->crtc[0x28] = 0x40;
945 memset(state->gra, 0x00, NUM_GRC_REGS);
946 state->gra[0x05] = 0x40;
947 state->gra[0x06] = 0x05;
948 state->gra[0x07] = 0x0f;
949 state->gra[0x08] = 0xff;
951 state->seq[0x00] = 0x03;
952 state->seq[0x01] = 0x01;
953 state->seq[0x02] = 0x0f;
954 state->seq[0x03] = 0x00;
955 state->seq[0x04] = 0x0e;
957 state->misc_output = 0xeb;
960 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
962 struct nvidia_par *par = info->par;
963 u8 data[MAX_CURS * MAX_CURS / 8];
964 int i, set = cursor->set;
967 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
970 NVShowHideCursor(par, 0);
972 if (par->cursor_reset) {
974 par->cursor_reset = 0;
977 if (set & FB_CUR_SETSIZE)
978 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
980 if (set & FB_CUR_SETPOS) {
983 yy = cursor->image.dy - info->var.yoffset;
984 xx = cursor->image.dx - info->var.xoffset;
988 NV_WR32(par->PRAMDAC, 0x0000300, temp);
991 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
992 u32 bg_idx = cursor->image.bg_color;
993 u32 fg_idx = cursor->image.fg_color;
994 u32 s_pitch = (cursor->image.width + 7) >> 3;
995 u32 d_pitch = MAX_CURS / 8;
996 u8 *dat = (u8 *) cursor->image.data;
997 u8 *msk = (u8 *) cursor->mask;
1000 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1003 switch (cursor->rop) {
1005 for (i = 0; i < s_pitch * cursor->image.height; i++)
1006 src[i] = dat[i] ^ msk[i];
1010 for (i = 0; i < s_pitch * cursor->image.height; i++)
1011 src[i] = dat[i] & msk[i];
1015 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1016 cursor->image.height);
1018 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1019 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1020 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
1022 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1023 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1024 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
1026 NVLockUnlock(par, 0);
1028 nvidiafb_load_cursor_image(par, data, bg, fg,
1029 cursor->image.width,
1030 cursor->image.height);
1036 NVShowHideCursor(par, 1);
1041 static int nvidiafb_set_par(struct fb_info *info)
1043 struct nvidia_par *par = info->par;
1047 NVLockUnlock(par, 1);
1048 if (!par->FlatPanel || !par->twoHeads)
1051 if (par->FPDither < 0) {
1052 if ((par->Chipset & 0x0ff0) == 0x0110)
1053 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
1056 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
1057 printk(KERN_INFO PFX "Flat panel dithering %s\n",
1058 par->FPDither ? "enabled" : "disabled");
1061 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1062 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1064 nvidia_init_vga(info);
1065 nvidia_calc_regs(info);
1067 NVLockUnlock(par, 0);
1068 if (par->twoHeads) {
1069 VGA_WR08(par->PCIO, 0x03D4, 0x44);
1070 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
1071 NVLockUnlock(par, 0);
1074 nvidia_vga_protect(par, 1);
1076 nvidia_write_regs(par);
1078 #if defined (__BIG_ENDIAN)
1079 /* turn on LFB swapping */
1083 VGA_WR08(par->PCIO, 0x3d4, 0x46);
1084 tmp = VGA_RD08(par->PCIO, 0x3d5);
1086 VGA_WR08(par->PCIO, 0x3d5, tmp);
1090 info->fix.line_length = (info->var.xres_virtual *
1091 info->var.bits_per_pixel) >> 3;
1092 if (info->var.accel_flags) {
1093 info->fbops->fb_imageblit = nvidiafb_imageblit;
1094 info->fbops->fb_fillrect = nvidiafb_fillrect;
1095 info->fbops->fb_copyarea = nvidiafb_copyarea;
1096 info->fbops->fb_sync = nvidiafb_sync;
1097 info->pixmap.scan_align = 4;
1098 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1099 NVResetGraphics(info);
1101 info->fbops->fb_imageblit = cfb_imageblit;
1102 info->fbops->fb_fillrect = cfb_fillrect;
1103 info->fbops->fb_copyarea = cfb_copyarea;
1104 info->fbops->fb_sync = NULL;
1105 info->pixmap.scan_align = 1;
1106 info->flags |= FBINFO_HWACCEL_DISABLED;
1109 par->cursor_reset = 1;
1111 nvidia_vga_protect(par, 0);
1113 #ifdef CONFIG_BOOTX_TEXT
1114 /* Update debug text engine */
1115 btext_update_display(info->fix.smem_start,
1116 info->var.xres, info->var.yres,
1117 info->var.bits_per_pixel, info->fix.line_length);
1124 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1125 unsigned blue, unsigned transp,
1126 struct fb_info *info)
1128 struct nvidia_par *par = info->par;
1132 if (regno >= (1 << info->var.green.length))
1135 if (info->var.grayscale) {
1136 /* gray = 0.30*R + 0.59*G + 0.11*B */
1137 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1140 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1141 ((u32 *) info->pseudo_palette)[regno] =
1142 (regno << info->var.red.offset) |
1143 (regno << info->var.green.offset) |
1144 (regno << info->var.blue.offset);
1147 switch (info->var.bits_per_pixel) {
1149 /* "transparent" stuff is completely ignored. */
1150 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1153 if (info->var.green.length == 5) {
1154 for (i = 0; i < 8; i++) {
1155 nvidia_write_clut(par, regno * 8 + i, red >> 8,
1156 green >> 8, blue >> 8);
1162 for (i = 0; i < 8; i++) {
1163 nvidia_write_clut(par, regno * 8 + i,
1164 red >> 8, green >> 8,
1169 nvidia_read_clut(par, regno * 4, &r, &g, &b);
1171 for (i = 0; i < 4; i++)
1172 nvidia_write_clut(par, regno * 4 + i, r,
1177 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1188 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
1189 struct fb_info *info)
1191 struct nvidia_par *par = info->par;
1192 int memlen, vramlen, mode_valid = 0;
1197 var->transp.offset = 0;
1198 var->transp.length = 0;
1202 if (var->bits_per_pixel <= 8)
1203 var->bits_per_pixel = 8;
1204 else if (var->bits_per_pixel <= 16)
1205 var->bits_per_pixel = 16;
1207 var->bits_per_pixel = 32;
1209 switch (var->bits_per_pixel) {
1211 var->red.offset = 0;
1212 var->red.length = 8;
1213 var->green.offset = 0;
1214 var->green.length = 8;
1215 var->blue.offset = 0;
1216 var->blue.length = 8;
1217 var->transp.offset = 0;
1218 var->transp.length = 0;
1221 var->green.length = (var->green.length < 6) ? 5 : 6;
1222 var->red.length = 5;
1223 var->blue.length = 5;
1224 var->transp.length = 6 - var->green.length;
1225 var->blue.offset = 0;
1226 var->green.offset = 5;
1227 var->red.offset = 5 + var->green.length;
1228 var->transp.offset = (5 + var->red.offset) & 15;
1230 case 32: /* RGBA 8888 */
1231 var->red.offset = 16;
1232 var->red.length = 8;
1233 var->green.offset = 8;
1234 var->green.length = 8;
1235 var->blue.offset = 0;
1236 var->blue.length = 8;
1237 var->transp.length = 8;
1238 var->transp.offset = 24;
1242 var->red.msb_right = 0;
1243 var->green.msb_right = 0;
1244 var->blue.msb_right = 0;
1245 var->transp.msb_right = 0;
1247 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
1248 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1251 /* calculate modeline if supported by monitor */
1252 if (!mode_valid && info->monspecs.gtf) {
1253 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1258 struct fb_videomode *mode;
1260 mode = fb_find_best_mode(var, &info->modelist);
1262 fb_videomode_to_var(var, mode);
1267 if (!mode_valid && info->monspecs.modedb_len)
1270 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
1271 par->fpHeight < var->yres))
1274 if (var->yres_virtual < var->yres)
1275 var->yres_virtual = var->yres;
1277 if (var->xres_virtual < var->xres)
1278 var->xres_virtual = var->xres;
1280 var->xres_virtual = (var->xres_virtual + 63) & ~63;
1282 vramlen = info->screen_size;
1283 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
1284 memlen = pitch * var->yres_virtual;
1286 if (memlen > vramlen) {
1287 var->yres_virtual = vramlen / pitch;
1289 if (var->yres_virtual < var->yres) {
1290 var->yres_virtual = var->yres;
1291 var->xres_virtual = vramlen / var->yres_virtual;
1292 var->xres_virtual /= var->bits_per_pixel / 8;
1293 var->xres_virtual &= ~63;
1294 pitch = (var->xres_virtual *
1295 var->bits_per_pixel + 7) / 8;
1296 memlen = pitch * var->yres;
1298 if (var->xres_virtual < var->xres) {
1299 printk("nvidiafb: required video memory, "
1300 "%d bytes, for %dx%d-%d (virtual) "
1301 "is out of range\n",
1302 memlen, var->xres_virtual,
1303 var->yres_virtual, var->bits_per_pixel);
1309 if (var->accel_flags) {
1310 if (var->yres_virtual > 0x7fff)
1311 var->yres_virtual = 0x7fff;
1312 if (var->xres_virtual > 0x7fff)
1313 var->xres_virtual = 0x7fff;
1316 var->xres_virtual &= ~63;
1323 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
1324 struct fb_info *info)
1326 struct nvidia_par *par = info->par;
1329 total = var->yoffset * info->fix.line_length + var->xoffset;
1331 NVSetStartAddress(par, total);
1336 static int nvidiafb_blank(int blank, struct fb_info *info)
1338 struct nvidia_par *par = info->par;
1339 unsigned char tmp, vesa;
1341 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
1342 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
1350 case FB_BLANK_UNBLANK:
1351 case FB_BLANK_NORMAL:
1353 case FB_BLANK_VSYNC_SUSPEND:
1356 case FB_BLANK_HSYNC_SUSPEND:
1359 case FB_BLANK_POWERDOWN:
1364 NVWriteSeq(par, 0x01, tmp);
1365 NVWriteCrtc(par, 0x1a, vesa);
1367 #ifdef CONFIG_PMAC_BACKLIGHT
1368 if (par->FlatPanel && _machine == _MACH_Pmac) {
1369 set_backlight_enable(!blank);
1378 static struct fb_ops nvidia_fb_ops = {
1379 .owner = THIS_MODULE,
1380 .fb_check_var = nvidiafb_check_var,
1381 .fb_set_par = nvidiafb_set_par,
1382 .fb_setcolreg = nvidiafb_setcolreg,
1383 .fb_pan_display = nvidiafb_pan_display,
1384 .fb_blank = nvidiafb_blank,
1385 .fb_fillrect = nvidiafb_fillrect,
1386 .fb_copyarea = nvidiafb_copyarea,
1387 .fb_imageblit = nvidiafb_imageblit,
1388 .fb_cursor = nvidiafb_cursor,
1389 .fb_sync = nvidiafb_sync,
1392 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1394 struct fb_monspecs *specs = &info->monspecs;
1395 struct fb_videomode modedb;
1396 struct nvidia_par *par = info->par;
1400 info->flags = FBINFO_DEFAULT
1401 | FBINFO_HWACCEL_IMAGEBLIT
1402 | FBINFO_HWACCEL_FILLRECT
1403 | FBINFO_HWACCEL_COPYAREA
1404 | FBINFO_HWACCEL_YPAN;
1406 fb_videomode_to_modelist(info->monspecs.modedb,
1407 info->monspecs.modedb_len, &info->modelist);
1408 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1422 if (specs->modedb != NULL) {
1423 struct fb_videomode *modedb;
1425 modedb = fb_find_best_display(specs, &info->modelist);
1426 fb_videomode_to_var(&nvidiafb_default_var, modedb);
1427 nvidiafb_default_var.bits_per_pixel = bpp;
1428 } else if (par->fpWidth && par->fpHeight) {
1432 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1433 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1434 specs->modedb_len, &modedb, bpp);
1438 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1439 specs->modedb, specs->modedb_len, &modedb, bpp);
1441 info->var = nvidiafb_default_var;
1442 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1443 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1444 info->pseudo_palette = par->pseudo_palette;
1445 fb_alloc_cmap(&info->cmap, 256, 0);
1446 fb_destroy_modedb(info->monspecs.modedb);
1447 info->monspecs.modedb = NULL;
1449 /* maximize virtual vertical length */
1450 lpitch = info->var.xres_virtual *
1451 ((info->var.bits_per_pixel + 7) >> 3);
1452 info->var.yres_virtual = info->screen_size / lpitch;
1454 info->pixmap.scan_align = 4;
1455 info->pixmap.buf_align = 4;
1456 info->pixmap.access_align = 32;
1457 info->pixmap.size = 8 * 1024;
1458 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1461 info->fbops->fb_cursor = NULL;
1463 info->var.accel_flags = (!noaccel);
1465 switch (par->Architecture) {
1467 info->fix.accel = FB_ACCEL_NV4;
1470 info->fix.accel = FB_ACCEL_NV_10;
1473 info->fix.accel = FB_ACCEL_NV_20;
1476 info->fix.accel = FB_ACCEL_NV_30;
1479 info->fix.accel = FB_ACCEL_NV_40;
1485 return nvidiafb_check_var(&info->var, info);
1488 static u32 __devinit nvidia_get_chipset(struct fb_info *info)
1490 struct nvidia_par *par = info->par;
1491 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1493 printk("nvidiafb: PCI id - %x\n", id);
1494 if ((id & 0xfff0) == 0x00f0) {
1496 printk("nvidiafb: PCI-E card\n");
1497 id = NV_RD32(par->REGS, 0x1800);
1499 if ((id & 0x0000ffff) == 0x000010DE)
1500 id = 0x10DE0000 | (id >> 16);
1501 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1502 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1503 ((id >> 8) & 0x000000ff);
1506 printk("nvidiafb: Actual id - %x\n", id);
1510 static u32 __devinit nvidia_get_arch(struct fb_info *info)
1512 struct nvidia_par *par = info->par;
1515 switch (par->Chipset & 0x0ff0) {
1516 case 0x0100: /* GeForce 256 */
1517 case 0x0110: /* GeForce2 MX */
1518 case 0x0150: /* GeForce2 */
1519 case 0x0170: /* GeForce4 MX */
1520 case 0x0180: /* GeForce4 MX (8x AGP) */
1521 case 0x01A0: /* nForce */
1522 case 0x01F0: /* nForce2 */
1525 case 0x0200: /* GeForce3 */
1526 case 0x0250: /* GeForce4 Ti */
1527 case 0x0280: /* GeForce4 Ti (8x AGP) */
1530 case 0x0300: /* GeForceFX 5800 */
1531 case 0x0310: /* GeForceFX 5600 */
1532 case 0x0320: /* GeForceFX 5200 */
1533 case 0x0330: /* GeForceFX 5900 */
1534 case 0x0340: /* GeForceFX 5700 */
1537 case 0x0040: /* GeForce 6800 */
1538 case 0x00C0: /* GeForce 6800 */
1539 case 0x0120: /* GeForce 6800 */
1541 case 0x0140: /* GeForce 6600 */
1542 case 0x0160: /* GeForce 6200 */
1543 case 0x01D0: /* GeForce 7200, 7300, 7400 */
1544 case 0x0090: /* GeForce 7800 */
1545 case 0x0210: /* GeForce 6800 */
1546 case 0x0220: /* GeForce 6200 */
1548 case 0x0240: /* GeForce 6100 */
1549 case 0x0290: /* GeForce 7900 */
1550 case 0x0390: /* GeForce 7600 */
1553 case 0x0020: /* TNT, TNT2 */
1556 default: /* unknown architecture */
1563 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1564 const struct pci_device_id *ent)
1566 struct nvidia_par *par;
1567 struct fb_info *info;
1574 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1582 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1584 if (info->pixmap.addr == NULL)
1587 memset(info->pixmap.addr, 0, 8 * 1024);
1589 if (pci_enable_device(pd)) {
1590 printk(KERN_ERR PFX "cannot enable PCI device\n");
1591 goto err_out_enable;
1594 if (pci_request_regions(pd, "nvidiafb")) {
1595 printk(KERN_ERR PFX "cannot request PCI regions\n");
1596 goto err_out_request;
1599 par->FlatPanel = flatpanel;
1601 printk(KERN_INFO PFX "flatpanel support enabled\n");
1602 par->FPDither = fpdither;
1604 par->CRTCnumber = forceCRTC;
1605 par->FpScale = (!noscale);
1606 par->paneltweak = paneltweak;
1608 /* enable IO and mem if not already done */
1609 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1610 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1611 pci_write_config_word(pd, PCI_COMMAND, cmd);
1613 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1614 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1615 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1617 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1620 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1621 goto err_out_free_base0;
1624 par->Chipset = nvidia_get_chipset(info);
1625 printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset);
1626 par->Architecture = nvidia_get_arch(info);
1628 if (par->Architecture == 0) {
1629 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1633 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1635 if (NVCommonSetup(info))
1638 par->FbAddress = nvidiafb_fix.smem_start;
1639 par->FbMapSize = par->RamAmountKBytes * 1024;
1640 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1641 par->FbMapSize = vram * 1024 * 1024;
1643 /* Limit amount of vram to 64 MB */
1644 if (par->FbMapSize > 64 * 1024 * 1024)
1645 par->FbMapSize = 64 * 1024 * 1024;
1647 if(par->Architecture >= NV_ARCH_40)
1648 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1650 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1651 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1653 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1654 par->CursorStart = par->FbUsableSize + (32 * 1024);
1656 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1657 info->screen_size = par->FbUsableSize;
1658 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1660 if (!info->screen_base) {
1661 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1662 goto err_out_free_base1;
1665 par->FbStart = info->screen_base;
1669 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1670 par->RamAmountKBytes * 1024,
1671 MTRR_TYPE_WRCOMB, 1);
1672 if (par->mtrr.vram < 0) {
1673 printk(KERN_ERR PFX "unable to setup MTRR\n");
1675 par->mtrr.vram_valid = 1;
1676 /* let there be speed */
1677 printk(KERN_INFO PFX "MTRR set to ON\n");
1680 #endif /* CONFIG_MTRR */
1682 info->fbops = &nvidia_fb_ops;
1683 info->fix = nvidiafb_fix;
1685 if (nvidia_set_fbinfo(info) < 0) {
1686 printk(KERN_ERR PFX "error setting initial video mode\n");
1687 goto err_out_iounmap_fb;
1690 nvidia_save_vga(par, &par->SavedReg);
1692 if (register_framebuffer(info) < 0) {
1693 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1694 goto err_out_iounmap_fb;
1697 pci_set_drvdata(pd, info);
1699 printk(KERN_INFO PFX
1700 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1702 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1703 #ifdef CONFIG_PMAC_BACKLIGHT
1704 if (par->FlatPanel && _machine == _MACH_Pmac)
1705 register_backlight_controller(&nvidia_backlight_controller,
1712 iounmap(info->screen_base);
1714 fb_destroy_modedb(info->monspecs.modedb);
1715 nvidia_delete_i2c_busses(par);
1719 pci_release_regions(pd);
1721 pci_disable_device(pd);
1723 kfree(info->pixmap.addr);
1725 framebuffer_release(info);
1730 static void __exit nvidiafb_remove(struct pci_dev *pd)
1732 struct fb_info *info = pci_get_drvdata(pd);
1733 struct nvidia_par *par = info->par;
1739 unregister_framebuffer(info);
1741 if (par->mtrr.vram_valid)
1742 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1743 info->fix.smem_len);
1744 #endif /* CONFIG_MTRR */
1746 iounmap(info->screen_base);
1747 fb_destroy_modedb(info->monspecs.modedb);
1748 nvidia_delete_i2c_busses(par);
1750 pci_release_regions(pd);
1751 pci_disable_device(pd);
1752 kfree(info->pixmap.addr);
1753 framebuffer_release(info);
1754 pci_set_drvdata(pd, NULL);
1758 /* ------------------------------------------------------------------------- *
1762 * ------------------------------------------------------------------------- */
1765 static int __devinit nvidiafb_setup(char *options)
1770 if (!options || !*options)
1773 while ((this_opt = strsep(&options, ",")) != NULL) {
1774 if (!strncmp(this_opt, "forceCRTC", 9)) {
1780 forceCRTC = *p - '0';
1781 if (forceCRTC < 0 || forceCRTC > 1)
1783 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1785 } else if (!strncmp(this_opt, "hwcur", 5)) {
1787 } else if (!strncmp(this_opt, "noaccel", 6)) {
1789 } else if (!strncmp(this_opt, "noscale", 7)) {
1791 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1792 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1793 } else if (!strncmp(this_opt, "vram:", 5)) {
1794 vram = simple_strtoul(this_opt+5, NULL, 0);
1796 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1799 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1800 fpdither = simple_strtol(this_opt+9, NULL, 0);
1801 } else if (!strncmp(this_opt, "bpp:", 4)) {
1802 bpp = simple_strtoul(this_opt+4, NULL, 0);
1804 mode_option = this_opt;
1809 #endif /* !MODULE */
1811 static struct pci_driver nvidiafb_driver = {
1813 .id_table = nvidiafb_pci_tbl,
1814 .probe = nvidiafb_probe,
1815 .remove = __exit_p(nvidiafb_remove),
1818 /* ------------------------------------------------------------------------- *
1822 * ------------------------------------------------------------------------- */
1824 static int __devinit nvidiafb_init(void)
1827 char *option = NULL;
1829 if (fb_get_options("nvidiafb", &option))
1831 nvidiafb_setup(option);
1833 return pci_register_driver(&nvidiafb_driver);
1836 module_init(nvidiafb_init);
1839 static void __exit nvidiafb_exit(void)
1841 pci_unregister_driver(&nvidiafb_driver);
1844 module_exit(nvidiafb_exit);
1846 module_param(flatpanel, int, 0);
1847 MODULE_PARM_DESC(flatpanel,
1848 "Enables experimental flat panel support for some chipsets. "
1849 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1850 module_param(fpdither, int, 0);
1851 MODULE_PARM_DESC(fpdither,
1852 "Enables dithering of flat panel for 6 bits panels. "
1853 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1854 module_param(hwcur, int, 0);
1855 MODULE_PARM_DESC(hwcur,
1856 "Enables hardware cursor implementation. (0 or 1=enabled) "
1858 module_param(noaccel, int, 0);
1859 MODULE_PARM_DESC(noaccel,
1860 "Disables hardware acceleration. (0 or 1=disable) "
1862 module_param(noscale, int, 0);
1863 MODULE_PARM_DESC(noscale,
1864 "Disables screen scaleing. (0 or 1=disable) "
1865 "(default=0, do scaling)");
1866 module_param(paneltweak, int, 0);
1867 MODULE_PARM_DESC(paneltweak,
1868 "Tweak display settings for flatpanels. "
1869 "(default=0, no tweaks)");
1870 module_param(forceCRTC, int, 0);
1871 MODULE_PARM_DESC(forceCRTC,
1872 "Forces usage of a particular CRTC in case autodetection "
1873 "fails. (0 or 1) (default=autodetect)");
1874 module_param(vram, int, 0);
1875 MODULE_PARM_DESC(vram,
1876 "amount of framebuffer memory to remap in MiB"
1877 "(default=0 - remap entire memory)");
1878 module_param(mode_option, charp, 0);
1879 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1880 module_param(bpp, int, 0);
1881 MODULE_PARM_DESC(bpp, "pixel width in bits"
1884 module_param(nomtrr, bool, 0);
1885 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1889 MODULE_AUTHOR("Antonino Daplas");
1890 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1891 MODULE_LICENSE("GPL");