2 * Permedia2 framebuffer driver.
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
16 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86.
17 * I have no access to other pm2fb implementations, and cannot test
18 * on them. Therefore for now I am omitting Sparc and CVision code.
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
30 #include <linux/config.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
36 #include <linux/tty.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
43 #include <video/permedia2.h>
44 #include <video/cvisionppc.h>
46 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
47 #error "The endianness of the target host has not been defined."
50 #if defined(__BIG_ENDIAN) && !defined(__sparc__)
51 #define PM2FB_BE_APERTURE
54 #if !defined(CONFIG_PCI)
55 #error "Only generic PCI cards supported."
58 #undef PM2FB_MASTER_DEBUG
59 #ifdef PM2FB_MASTER_DEBUG
60 #define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
62 #define DPRINTK(a,b...)
66 * The 2.4 driver calls reset_card() at init time, where it also sets the
67 * initial mode. I don't think the driver should touch the chip until
68 * the console sets a video mode. So I was calling this at the start
69 * of setting a mode. However, certainly on 1280x1024 depth 16 on my
70 * PCI Graphics Blaster Exxtreme this causes the display to smear
71 * slightly. I don't know why. Guesses to jim.hague@acm.org.
73 #undef RESET_CARD_ON_MODE_SET
78 static char *mode __initdata = NULL;
81 * The XFree GLINT driver will (I think to implement hardware cursor
82 * support on TVP4010 and similar where there is no RAMDAC - see
83 * comment in set_video) always request +ve sync regardless of what
84 * the mode requires. This screws me because I have a Sun
85 * fixed-frequency monitor which absolutely has to have -ve sync. So
86 * these flags allow the user to specify that requests for +ve sync
87 * should be silently turned in -ve sync.
89 static int lowhsync __initdata = 0;
90 static int lowvsync __initdata = 0;
93 * The hardware state of the graphics card that isn't part of the
98 pm2type_t type; /* Board type */
99 u32 fb_size; /* framebuffer memory size */
100 unsigned char* v_fb; /* virtual address of frame buffer */
101 unsigned char* v_regs; /* virtual address of p_regs */
102 u32 memclock; /* memclock */
103 u32 video; /* video flags before blanking */
107 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
108 * if we don't use modedb.
110 static struct fb_fix_screeninfo pm2fb_fix __initdata = {
112 .type = FB_TYPE_PACKED_PIXELS,
113 .visual = FB_VISUAL_PSEUDOCOLOR,
117 .accel = FB_ACCEL_NONE,
121 * Default video mode. In case the modedb doesn't work, or we're
122 * a module (in which case modedb doesn't really work).
124 static struct fb_var_screeninfo pm2fb_var __initdata = {
125 /* "640x480, 8 bpp @ 60 Hz */
134 .activate = FB_ACTIVATE_NOW,
145 .vmode = FB_VMODE_NONINTERLACED
152 inline static u32 RD32(unsigned char* base, s32 off)
154 return fb_readl(base + off);
157 inline static void WR32(unsigned char* base, s32 off, u32 v)
159 fb_writel(v, base + off);
162 inline static u32 pm2_RD(struct pm2fb_par* p, s32 off)
164 return RD32(p->v_regs, off);
167 inline static void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
169 WR32(p->v_regs, off, v);
172 inline static u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
174 int index = PM2R_RD_INDEXED_DATA;
176 case PM2_TYPE_PERMEDIA2:
177 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
179 case PM2_TYPE_PERMEDIA2V:
180 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
181 index = PM2VR_RD_INDEXED_DATA;
185 return pm2_RD(p, index);
188 inline static void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
190 int index = PM2R_RD_INDEXED_DATA;
192 case PM2_TYPE_PERMEDIA2:
193 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
195 case PM2_TYPE_PERMEDIA2V:
196 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
197 index = PM2VR_RD_INDEXED_DATA;
204 inline static u32 pm2v_RDAC_RD(struct pm2fb_par* p, s32 idx)
206 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
208 return pm2_RD(p, PM2VR_RD_INDEXED_DATA);
211 inline static void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
213 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
215 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
218 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
219 #define WAIT_FIFO(p,a)
221 inline static void WAIT_FIFO(struct pm2fb_par* p, u32 a)
223 while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );
229 * partial products for the supported horizontal resolutions.
231 #define PACKPP(p0,p1,p2) (((p2) << 6) | ((p1) << 3) | (p0))
232 static const struct {
236 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
237 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
238 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
239 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
240 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
241 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
242 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
243 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
244 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
245 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
246 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
247 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
248 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
249 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
250 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
251 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
254 static u32 partprod(u32 xres)
258 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
260 if ( pp_table[i].width == 0 )
261 DPRINTK("invalid width %u\n", xres);
262 return pp_table[i].pp;
265 static u32 to3264(u32 timing, int bpp, int is64)
275 timing = (timing * 3) >> (2 + is64);
285 static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
296 for (n = 2; n < 15; n++) {
297 for (m = 2; m; m++) {
298 f = PM2_REFERENCE_CLOCK * m / n;
299 if (f >= 150000 && f <= 300000) {
300 for ( p = 0; p < 5; p++, f >>= 1) {
301 curr = ( clk > f ) ? clk - f : f - clk;
302 if ( curr < delta ) {
314 static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
324 for (n = 1; n; n++) {
325 for ( m = 1; m; m++) {
326 for ( p = 0; p < 2; p++) {
327 f = PM2_REFERENCE_CLOCK * n / (m * (1 << (p + 1)));
328 if ( clk > f - delta && clk < f + delta ) {
329 delta = ( clk > f ) ? clk - f : f - clk;
339 static void clear_palette(struct pm2fb_par* p) {
343 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
347 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
348 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
349 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
353 #ifdef RESET_CARD_ON_MODE_SET
354 static void reset_card(struct pm2fb_par* p)
356 if (p->type == PM2_TYPE_PERMEDIA2V)
357 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
358 pm2_WR(p, PM2R_RESET_STATUS, 0);
360 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
363 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
364 DPRINTK("FIFO disconnect enabled\n");
365 pm2_WR(p, PM2R_FIFO_DISCON, 1);
371 static void reset_config(struct pm2fb_par* p)
374 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG)&
375 ~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));
376 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
377 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
378 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
379 pm2_WR(p, PM2R_APERTURE_ONE, 0);
380 pm2_WR(p, PM2R_APERTURE_TWO, 0);
381 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
382 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
383 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
384 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
385 pm2_WR(p, PM2R_LB_READ_MODE, 0);
386 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
387 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
388 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
389 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
390 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
391 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
392 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
393 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
394 pm2_WR(p, PM2R_DITHER_MODE, 0);
395 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
396 pm2_WR(p, PM2R_DEPTH_MODE, 0);
397 pm2_WR(p, PM2R_STENCIL_MODE, 0);
398 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
399 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
400 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
401 pm2_WR(p, PM2R_YUV_MODE, 0);
402 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
403 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
404 pm2_WR(p, PM2R_FOG_MODE, 0);
405 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
406 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
407 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
408 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
409 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
411 case PM2_TYPE_PERMEDIA2:
412 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
413 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
414 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
416 case PM2_TYPE_PERMEDIA2V:
417 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
420 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
421 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
422 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
423 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
424 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
427 static void set_aperture(struct pm2fb_par* p, u32 depth)
430 #ifdef __LITTLE_ENDIAN
431 pm2_WR(p, PM2R_APERTURE_ONE, 0);
432 pm2_WR(p, PM2R_APERTURE_TWO, 0);
437 pm2_WR(p, PM2R_APERTURE_ONE, 0);
438 pm2_WR(p, PM2R_APERTURE_TWO, 1);
441 pm2_WR(p, PM2R_APERTURE_ONE, 2);
442 pm2_WR(p, PM2R_APERTURE_TWO, 1);
445 pm2_WR(p, PM2R_APERTURE_ONE, 1);
446 pm2_WR(p, PM2R_APERTURE_TWO, 1);
452 static void set_color(struct pm2fb_par* p, unsigned char regno,
453 unsigned char r, unsigned char g, unsigned char b)
456 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
458 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
460 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
462 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
465 static void set_pixclock(struct pm2fb_par* par, u32 clk)
468 unsigned char m, n, p;
471 case PM2_TYPE_PERMEDIA2:
472 pm2_mnp(clk, &m, &n, &p);
474 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
476 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
477 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
479 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
481 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
484 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
488 case PM2_TYPE_PERMEDIA2V:
489 pm2v_mnp(clk/2, &m, &n, &p);
491 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
492 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
493 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
494 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
495 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
500 static void set_video(struct pm2fb_par* p, u32 video) {
506 DPRINTK("video = 0x%x\n", video);
509 * The hardware cursor needs +vsync to recognise vert retrace.
510 * We may not be using the hardware cursor, but the X Glint
511 * driver may well. So always set +hsync/+vsync and then set
512 * the RAMDAC to invert the sync if necessary.
514 vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);
515 vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;
518 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
521 case PM2_TYPE_PERMEDIA2:
522 tmp = PM2F_RD_PALETTE_WIDTH_8;
523 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
524 tmp |= 4; /* invert hsync */
525 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
526 tmp |= 8; /* invert vsync */
527 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
529 case PM2_TYPE_PERMEDIA2V:
531 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
532 tmp |= 1; /* invert hsync */
533 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
534 tmp |= 4; /* invert vsync */
535 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
536 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
546 * pm2fb_check_var - Optional function. Validates a var passed in.
547 * @var: frame buffer variable screen structure
548 * @info: frame buffer structure that represents a single frame buffer
550 * Checks to see if the hardware supports the state requested by
553 * Returns negative errno on error, or zero on success.
555 static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
559 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
560 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
561 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
565 if (var->xres != var->xres_virtual) {
566 DPRINTK("virtual x resolution != physical x resolution not supported\n");
570 if (var->yres > var->yres_virtual) {
571 DPRINTK("virtual y resolution < physical y resolution not possible\n");
576 DPRINTK("xoffset not supported\n");
580 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
581 DPRINTK("interlace not supported\n");
585 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
586 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
588 if (var->xres < 320 || var->xres > 1600) {
589 DPRINTK("width not supported: %u\n", var->xres);
593 if (var->yres < 200 || var->yres > 1200) {
594 DPRINTK("height not supported: %u\n", var->yres);
598 if (lpitch * var->yres_virtual > info->fix.smem_len) {
599 DPRINTK("no memory for screen (%ux%ux%u)\n",
600 var->xres, var->yres_virtual, var->bits_per_pixel);
604 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
605 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
609 switch(var->bits_per_pixel) {
611 var->red.length = var->green.length = var->blue.length = 8;
614 var->red.offset = 11;
616 var->green.offset = 5;
617 var->green.length = 6;
618 var->blue.offset = 0;
619 var->blue.length = 5;
622 var->red.offset = 16;
623 var->green.offset = 8;
624 var->blue.offset = 0;
625 var->red.length = var->green.length = var->blue.length = 8;
627 var->red.offset = 16;
628 var->green.offset = 8;
629 var->blue.offset = 0;
630 var->red.length = var->green.length = var->blue.length = 8;
633 var->height = var->width = -1;
635 var->accel_flags = 0; /* Can't mmap if this is on */
637 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
638 var->xres, var->yres, var->bits_per_pixel);
643 * pm2fb_set_par - Alters the hardware state.
644 * @info: frame buffer structure that represents a single frame buffer
646 * Using the fb_var_screeninfo in fb_info we set the resolution of the
647 * this particular framebuffer.
649 static int pm2fb_set_par(struct fb_info *info)
651 struct pm2fb_par *par = (struct pm2fb_par *) info->par;
653 u32 width, height, depth;
654 u32 hsstart, hsend, hbend, htotal;
655 u32 vsstart, vsend, vbend, vtotal;
659 u32 clrmode = PM2F_RD_COLOR_MODE_RGB;
666 #ifdef RESET_CARD_ON_MODE_SET
672 width = (info->var.xres_virtual + 7) & ~7;
673 height = info->var.yres_virtual;
674 depth = (info->var.bits_per_pixel + 7) & ~7;
675 depth = (depth > 32) ? 32 : depth;
676 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
678 xres = (info->var.xres + 31) & ~31;
679 pixclock = PICOS2KHZ(info->var.pixclock);
680 if (pixclock > PM2_MAX_PIXCLOCK) {
681 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
685 hsstart = to3264(info->var.right_margin, depth, data64);
686 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
687 hbend = hsend + to3264(info->var.left_margin, depth, data64);
688 htotal = to3264(xres, depth, data64) + hbend - 1;
689 vsstart = (info->var.lower_margin)
690 ? info->var.lower_margin - 1
692 vsend = info->var.lower_margin + info->var.vsync_len - 1;
693 vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;
694 vtotal = info->var.yres + vbend - 1;
695 stride = to3264(width, depth, 1);
696 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
698 video |= PM2F_DATA_64_ENABLE;
700 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
702 DPRINTK("ignoring +hsync, using -hsync.\n");
703 video |= PM2F_HSYNC_ACT_LOW;
705 video |= PM2F_HSYNC_ACT_HIGH;
708 video |= PM2F_HSYNC_ACT_LOW;
709 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
711 DPRINTK("ignoring +vsync, using -vsync.\n");
712 video |= PM2F_VSYNC_ACT_LOW;
714 video |= PM2F_VSYNC_ACT_HIGH;
717 video |= PM2F_VSYNC_ACT_LOW;
718 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {
719 DPRINTK("interlaced not supported\n");
722 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)
723 video |= PM2F_LINE_DOUBLE;
724 if (info->var.activate==FB_ACTIVATE_NOW)
725 video |= PM2F_VIDEO_ENABLE;
729 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
730 info->fix.line_length = info->var.xres * depth / 8;
731 info->cmap.len = 256;
734 * Settings calculated. Now write them out.
736 if (par->type == PM2_TYPE_PERMEDIA2V) {
738 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
741 set_aperture(par, depth);
745 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
746 ( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
749 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
753 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
754 clrmode |= PM2F_RD_TRUECOLOR | 0x06;
755 txtmap = PM2F_TEXTEL_SIZE_16;
760 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
761 clrmode |= PM2F_RD_TRUECOLOR | 0x08;
762 txtmap = PM2F_TEXTEL_SIZE_32;
767 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
768 clrmode |= PM2F_RD_TRUECOLOR | 0x09;
769 #ifndef PM2FB_BE_APERTURE
770 clrmode &= ~PM2F_RD_COLOR_MODE_RGB;
772 txtmap = PM2F_TEXTEL_SIZE_24;
777 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
778 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
779 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
780 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
781 pm2_WR(par, PM2R_H_TOTAL, htotal);
782 pm2_WR(par, PM2R_HS_START, hsstart);
783 pm2_WR(par, PM2R_HS_END, hsend);
784 pm2_WR(par, PM2R_HG_END, hbend);
785 pm2_WR(par, PM2R_HB_END, hbend);
786 pm2_WR(par, PM2R_V_TOTAL, vtotal);
787 pm2_WR(par, PM2R_VS_START, vsstart);
788 pm2_WR(par, PM2R_VS_END, vsend);
789 pm2_WR(par, PM2R_VB_END, vbend);
790 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
792 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
793 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
794 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
796 pm2_WR(par, PM2R_SCREEN_BASE, base);
798 set_video(par, video);
801 case PM2_TYPE_PERMEDIA2:
802 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE,
803 PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE | clrmode);
805 case PM2_TYPE_PERMEDIA2V:
806 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
807 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
810 set_pixclock(par, pixclock);
811 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
812 info->var.xres, info->var.yres, info->var.bits_per_pixel);
817 * pm2fb_setcolreg - Sets a color register.
818 * @regno: boolean, 0 copy local, 1 get_user() function
819 * @red: frame buffer colormap structure
820 * @green: The green value which can be up to 16 bits wide
821 * @blue: The blue value which can be up to 16 bits wide.
822 * @transp: If supported the alpha value which can be up to 16 bits wide.
823 * @info: frame buffer info structure
825 * Set a single color register. The values supplied have a 16 bit
826 * magnitude which needs to be scaled in this function for the hardware.
827 * Pretty much a direct lift from tdfxfb.c.
829 * Returns negative errno on error, or zero on success.
831 static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
832 unsigned blue, unsigned transp,
833 struct fb_info *info)
835 struct pm2fb_par *par = (struct pm2fb_par *) info->par;
837 if (regno >= info->cmap.len) /* no. of hw registers */
840 * Program hardware... do anything you want with transp
843 /* grayscale works only partially under directcolor */
844 if (info->var.grayscale) {
845 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
846 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
850 * var->{color}.offset contains start of bitfield
851 * var->{color}.length contains length of bitfield
852 * {hardwarespecific} contains width of DAC
853 * cmap[X] is programmed to
854 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
855 * RAMDAC[X] is programmed to (red, green, blue)
858 * uses offset = 0 && length = DAC register width.
859 * var->{color}.offset is 0
860 * var->{color}.length contains widht of DAC
862 * DAC[X] is programmed to (red, green, blue)
864 * does not use RAMDAC (usually has 3 of them).
865 * var->{color}.offset contains start of bitfield
866 * var->{color}.length contains length of bitfield
867 * cmap is programmed to
868 * (red << red.offset) | (green << green.offset) |
869 * (blue << blue.offset) | (transp << transp.offset)
870 * RAMDAC does not exist
872 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
873 switch (info->fix.visual) {
874 case FB_VISUAL_TRUECOLOR:
875 case FB_VISUAL_PSEUDOCOLOR:
876 red = CNVT_TOHW(red, info->var.red.length);
877 green = CNVT_TOHW(green, info->var.green.length);
878 blue = CNVT_TOHW(blue, info->var.blue.length);
879 transp = CNVT_TOHW(transp, info->var.transp.length);
880 set_color(par, regno, red, green, blue);
882 case FB_VISUAL_DIRECTCOLOR:
883 /* example here assumes 8 bit DAC. Might be different
884 * for your hardware */
885 red = CNVT_TOHW(red, 8);
886 green = CNVT_TOHW(green, 8);
887 blue = CNVT_TOHW(blue, 8);
888 /* hey, there is bug in transp handling... */
889 transp = CNVT_TOHW(transp, 8);
893 /* Truecolor has hardware independent palette */
894 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
900 v = (red << info->var.red.offset) |
901 (green << info->var.green.offset) |
902 (blue << info->var.blue.offset) |
903 (transp << info->var.transp.offset);
905 switch (info->var.bits_per_pixel) {
907 /* Yes some hand held devices have this. */
908 ((u8*)(info->pseudo_palette))[regno] = v;
911 ((u16*)(info->pseudo_palette))[regno] = v;
915 ((u32*)(info->pseudo_palette))[regno] = v;
925 * pm2fb_pan_display - Pans the display.
926 * @var: frame buffer variable screen structure
927 * @info: frame buffer structure that represents a single frame buffer
929 * Pan (or wrap, depending on the `vmode' field) the display using the
930 * `xoffset' and `yoffset' fields of the `var' structure.
931 * If the values don't fit, return -EINVAL.
933 * Returns negative errno on error, or zero on success.
936 static int pm2fb_pan_display(struct fb_var_screeninfo *var,
937 struct fb_info *info)
939 struct pm2fb_par *p = (struct pm2fb_par *) info->par;
944 xres = (var->xres + 31) & ~31;
945 depth = (var->bits_per_pixel + 7) & ~7;
946 depth = (depth > 32) ? 32 : depth;
947 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
949 pm2_WR(p, PM2R_SCREEN_BASE, base);
954 * pm2fb_blank - Blanks the display.
955 * @blank_mode: the blank mode we want.
956 * @info: frame buffer structure that represents a single frame buffer
958 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
959 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
960 * video mode which doesn't support it. Implements VESA suspend
961 * and powerdown modes on hardware that supports disabling hsync/vsync:
962 * blank_mode == 2: suspend vsync
963 * blank_mode == 3: suspend hsync
964 * blank_mode == 4: powerdown
966 * Returns negative errno on error, or zero on success.
969 static int pm2fb_blank(int blank_mode, struct fb_info *info)
971 struct pm2fb_par *par = (struct pm2fb_par *) info->par;
972 u32 video = par->video;
974 DPRINTK("blank_mode %d\n", blank_mode);
976 /* Turn everything on, then disable as requested. */
977 video |= (PM2F_VIDEO_ENABLE | PM2F_HSYNC_MASK | PM2F_VSYNC_MASK);
979 switch (blank_mode) {
980 case 0: /* Screen: On; HSync: On, VSync: On */
982 case 1: /* Screen: Off; HSync: On, VSync: On */
983 video &= ~PM2F_VIDEO_ENABLE;
985 case 2: /* Screen: Off; HSync: On, VSync: Off */
986 video &= ~(PM2F_VIDEO_ENABLE | PM2F_VSYNC_MASK | PM2F_BLANK_LOW );
988 case 3: /* Screen: Off; HSync: Off, VSync: On */
989 video &= ~(PM2F_VIDEO_ENABLE | PM2F_HSYNC_MASK | PM2F_BLANK_LOW );
991 case 4: /* Screen: Off; HSync: Off, VSync: Off */
992 video &= ~(PM2F_VIDEO_ENABLE | PM2F_VSYNC_MASK | PM2F_HSYNC_MASK|
996 set_video(par, video);
1000 /* ------------ Hardware Independent Functions ------------ */
1003 * Frame buffer operations
1006 static struct fb_ops pm2fb_ops = {
1007 .owner = THIS_MODULE,
1008 .fb_check_var = pm2fb_check_var,
1009 .fb_set_par = pm2fb_set_par,
1010 .fb_setcolreg = pm2fb_setcolreg,
1011 .fb_blank = pm2fb_blank,
1012 .fb_pan_display = pm2fb_pan_display,
1013 .fb_fillrect = cfb_fillrect,
1014 .fb_copyarea = cfb_copyarea,
1015 .fb_imageblit = cfb_imageblit,
1016 .fb_cursor = soft_cursor,
1025 * Device initialisation
1027 * Initialise and allocate resource for PCI device.
1029 * @param pdev PCI device.
1030 * @param id PCI device ID.
1032 static int __devinit pm2fb_probe(struct pci_dev *pdev,
1033 const struct pci_device_id *id)
1035 struct pm2fb_par *default_par;
1036 struct fb_info *info;
1039 int err_retval = -ENXIO;
1041 err = pci_enable_device(pdev);
1043 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1047 size = sizeof(struct pm2fb_par) + 256 * sizeof(u32);
1048 info = framebuffer_alloc(size, &pdev->dev);
1051 default_par = (struct pm2fb_par *) info->par;
1053 switch (pdev->device) {
1054 case PCI_DEVICE_ID_TI_TVP4020:
1055 strcpy(pm2fb_fix.id, "TVP4020");
1056 default_par->type = PM2_TYPE_PERMEDIA2;
1058 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1059 strcpy(pm2fb_fix.id, "Permedia2");
1060 default_par->type = PM2_TYPE_PERMEDIA2;
1062 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1063 strcpy(pm2fb_fix.id, "Permedia2v");
1064 default_par->type = PM2_TYPE_PERMEDIA2V;
1068 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1069 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1071 #ifdef PM2FB_BE_APERTURE
1072 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1075 /* Registers - request region and map it. */
1076 if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1077 "pm2fb regbase") ) {
1078 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1079 goto err_exit_neither;
1081 default_par->v_regs =
1082 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1083 if ( !default_par->v_regs ) {
1084 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1086 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1087 goto err_exit_neither;
1090 /* Now work out how big lfb is going to be. */
1091 pci_mem_config = RD32(default_par->v_regs, PM2R_MEM_CONFIG);
1092 switch(pci_mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1093 case PM2F_MEM_BANKS_1:
1094 default_par->fb_size=0x200000;
1096 case PM2F_MEM_BANKS_2:
1097 default_par->fb_size=0x400000;
1099 case PM2F_MEM_BANKS_3:
1100 default_par->fb_size=0x600000;
1102 case PM2F_MEM_BANKS_4:
1103 default_par->fb_size=0x800000;
1106 default_par->memclock = CVPPC_MEMCLOCK;
1107 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1108 pm2fb_fix.smem_len = default_par->fb_size;
1110 /* Linear frame buffer - request region and map it. */
1111 if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1113 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1116 info->screen_base = default_par->v_fb =
1117 ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1118 if ( !default_par->v_fb ) {
1119 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1120 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1124 info->fbops = &pm2fb_ops;
1125 info->fix = pm2fb_fix;
1126 info->pseudo_palette = (void *)(default_par + 1);
1127 info->flags = FBINFO_FLAG_DEFAULT;
1131 mode = "640x480@60";
1133 err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
1134 if (!err || err == 4)
1136 info->var = pm2fb_var;
1138 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
1141 if (register_framebuffer(info) < 0)
1144 printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
1145 info->node, info->fix.id, default_par->fb_size / 1024);
1150 pci_set_drvdata(pdev, info);
1155 fb_dealloc_cmap(&info->cmap);
1157 iounmap((void*) pm2fb_fix.smem_start);
1158 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1160 iounmap((void*) pm2fb_fix.mmio_start);
1161 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1163 framebuffer_release(info);
1170 * Release all device resources.
1172 * @param pdev PCI device to clean up.
1174 static void __devexit pm2fb_remove(struct pci_dev *pdev)
1176 struct fb_info* info = pci_get_drvdata(pdev);
1177 struct fb_fix_screeninfo* fix = &info->fix;
1179 unregister_framebuffer(info);
1181 iounmap((void*) fix->smem_start);
1182 release_mem_region(fix->smem_start, fix->smem_len);
1183 iounmap((void*) fix->mmio_start);
1184 release_mem_region(fix->mmio_start, fix->mmio_len);
1186 pci_set_drvdata(pdev, NULL);
1190 static struct pci_device_id pm2fb_id_table[] = {
1191 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1192 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1194 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1195 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1197 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1198 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1203 static struct pci_driver pm2fb_driver = {
1205 .id_table = pm2fb_id_table,
1206 .probe = pm2fb_probe,
1207 .remove = __devexit_p(pm2fb_remove),
1210 MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1217 int __init pm2fb_init(void)
1219 return pci_module_init(&pm2fb_driver);
1226 static void __exit pm2fb_exit(void)
1228 pci_unregister_driver(&pm2fb_driver);
1236 * Parse user speficied options.
1238 * This is, comma-separated options following `video=pm2fb:'.
1240 int __init pm2fb_setup(char *options)
1244 if (!options || !*options)
1247 while ((this_opt = strsep(&options, ",")) != NULL) {
1250 if(!strcmp(this_opt, "lowhsync")) {
1252 } else if(!strcmp(this_opt, "lowvsync")) {
1262 /* ------------------------------------------------------------------------- */
1264 /* ------------------------------------------------------------------------- */
1269 module_init(pm2fb_init);
1271 module_exit(pm2fb_exit);
1273 MODULE_PARM(mode,"s");
1274 MODULE_PARM(lowhsync,"i");
1275 MODULE_PARM(lowvsync,"i");
1277 MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1278 MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1279 MODULE_LICENSE("GPL");