2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/kernel.h>
29 #include <linux/sched.h>
30 #include <linux/errno.h>
31 #include <linux/string.h>
32 #include <linux/interrupt.h>
33 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/device.h>
40 #include <linux/dma-mapping.h>
42 #include <asm/hardware.h>
45 #include <asm/mach-types.h>
46 #include <asm/uaccess.h>
47 #include <asm/arch/bitfield.h>
48 #include <asm/arch/pxafb.h>
51 * Complain if VAR is out of range.
57 /* Bits which should not be set in machine configuration structures */
58 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
59 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
61 static void (*pxafb_backlight_power)(int);
62 static void (*pxafb_lcd_power)(int);
64 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
65 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
67 #ifdef CONFIG_FB_PXA_PARAMETERS
68 #define PXAFB_OPTIONS_SIZE 256
69 static char g_options[PXAFB_OPTIONS_SIZE] __initdata = "";
72 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
76 local_irq_save(flags);
78 * We need to handle two requests being made at the same time.
79 * There are two important cases:
80 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
81 * We must perform the unblanking, which will do our REENABLE for us.
82 * 2. When we are blanking, but immediately unblank before we have
83 * blanked. We do the "REENABLE" thing here as well, just to be sure.
85 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
87 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
90 if (state != (u_int)-1) {
91 fbi->task_state = state;
92 schedule_work(&fbi->task);
94 local_irq_restore(flags);
97 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
100 chan >>= 16 - bf->length;
101 return chan << bf->offset;
105 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
106 u_int trans, struct fb_info *info)
108 struct pxafb_info *fbi = (struct pxafb_info *)info;
111 if (regno < fbi->palette_size) {
112 val = ((red >> 0) & 0xf800);
113 val |= ((green >> 5) & 0x07e0);
114 val |= ((blue >> 11) & 0x001f);
116 fbi->palette_cpu[regno] = val;
123 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
124 u_int trans, struct fb_info *info)
126 struct pxafb_info *fbi = (struct pxafb_info *)info;
131 * If inverse mode was selected, invert all the colours
132 * rather than the register number. The register number
133 * is what you poke into the framebuffer to produce the
134 * colour you requested.
136 if (fbi->cmap_inverse) {
138 green = 0xffff - green;
139 blue = 0xffff - blue;
143 * If greyscale is true, then we convert the RGB value
144 * to greyscale no matter what visual we are using.
146 if (fbi->fb.var.grayscale)
147 red = green = blue = (19595 * red + 38470 * green +
150 switch (fbi->fb.fix.visual) {
151 case FB_VISUAL_TRUECOLOR:
153 * 12 or 16-bit True Colour. We encode the RGB value
154 * according to the RGB bitfield information.
157 u32 *pal = fbi->fb.pseudo_palette;
159 val = chan_to_field(red, &fbi->fb.var.red);
160 val |= chan_to_field(green, &fbi->fb.var.green);
161 val |= chan_to_field(blue, &fbi->fb.var.blue);
168 case FB_VISUAL_STATIC_PSEUDOCOLOR:
169 case FB_VISUAL_PSEUDOCOLOR:
170 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
178 * pxafb_bpp_to_lccr3():
179 * Convert a bits per pixel value to the correct bit pattern for LCCR3
181 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
184 switch (var->bits_per_pixel) {
185 case 1: ret = LCCR3_1BPP; break;
186 case 2: ret = LCCR3_2BPP; break;
187 case 4: ret = LCCR3_4BPP; break;
188 case 8: ret = LCCR3_8BPP; break;
189 case 16: ret = LCCR3_16BPP; break;
194 #ifdef CONFIG_CPU_FREQ
196 * pxafb_display_dma_period()
197 * Calculate the minimum period (in picoseconds) between two DMA
198 * requests for the LCD controller. If we hit this, it means we're
199 * doing nothing but LCD DMA.
201 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
204 * Period = pixclock * bits_per_byte * bytes_per_transfer
205 * / memory_bits_per_pixel;
207 return var->pixclock * 8 * 16 / var->bits_per_pixel;
210 extern unsigned int get_clk_frequency_khz(int info);
215 * Get the video params out of 'var'. If a value doesn't fit, round it up,
216 * if it's too big, return -EINVAL.
218 * Round up in the following order: bits_per_pixel, xres,
219 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
220 * bitfields, horizontal timing, vertical timing.
222 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
224 struct pxafb_info *fbi = (struct pxafb_info *)info;
226 if (var->xres < MIN_XRES)
227 var->xres = MIN_XRES;
228 if (var->yres < MIN_YRES)
229 var->yres = MIN_YRES;
230 if (var->xres > fbi->max_xres)
231 var->xres = fbi->max_xres;
232 if (var->yres > fbi->max_yres)
233 var->yres = fbi->max_yres;
235 max(var->xres_virtual, var->xres);
237 max(var->yres_virtual, var->yres);
240 * Setup the RGB parameters for this display.
242 * The pixel packing format is described on page 7-11 of the
243 * PXA2XX Developer's Manual.
245 if ( var->bits_per_pixel == 16 ) {
246 var->red.offset = 11; var->red.length = 5;
247 var->green.offset = 5; var->green.length = 6;
248 var->blue.offset = 0; var->blue.length = 5;
249 var->transp.offset = var->transp.length = 0;
251 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
253 var->green.length = 8;
254 var->blue.length = 8;
255 var->transp.length = 0;
258 #ifdef CONFIG_CPU_FREQ
259 DPRINTK("dma period = %d ps, clock = %d kHz\n",
260 pxafb_display_dma_period(var),
261 get_clk_frequency_khz(0));
267 static inline void pxafb_set_truecolor(u_int is_true_color)
269 DPRINTK("true_color = %d\n", is_true_color);
270 // do your machine-specific setup if needed
275 * Set the user defined part of the display for the specified console
277 static int pxafb_set_par(struct fb_info *info)
279 struct pxafb_info *fbi = (struct pxafb_info *)info;
280 struct fb_var_screeninfo *var = &info->var;
281 unsigned long palette_mem_size;
283 DPRINTK("set_par\n");
285 if (var->bits_per_pixel == 16)
286 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
287 else if (!fbi->cmap_static)
288 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
291 * Some people have weird ideas about wanting static
292 * pseudocolor maps. I suspect their user space
293 * applications are broken.
295 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
298 fbi->fb.fix.line_length = var->xres_virtual *
299 var->bits_per_pixel / 8;
300 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
302 palette_mem_size = fbi->palette_size * sizeof(u16);
304 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
306 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
307 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
310 * Set (any) board control register to handle new color depth
312 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
314 pxafb_activate_var(var, fbi);
320 * Formal definition of the VESA spec:
322 * This refers to the state of the display when it is in full operation
324 * This defines an optional operating state of minimal power reduction with
325 * the shortest recovery time
327 * This refers to a level of power management in which substantial power
328 * reduction is achieved by the display. The display can have a longer
329 * recovery time from this state than from the Stand-by state
331 * This indicates that the display is consuming the lowest level of power
332 * and is non-operational. Recovery from this state may optionally require
333 * the user to manually power on the monitor
335 * Now, the fbdev driver adds an additional state, (blank), where they
336 * turn off the video (maybe by colormap tricks), but don't mess with the
337 * video itself: think of it semantically between on and Stand-By.
339 * So here's what we should do in our fbdev blank routine:
341 * VESA_NO_BLANKING (mode 0) Video on, front/back light on
342 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
343 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
344 * VESA_POWERDOWN (mode 3) Video off, front/back light off
346 * This will match the matrox implementation.
351 * Blank the display by setting all palette values to zero. Note, the
352 * 12 and 16 bpp modes don't really use the palette, so this will not
353 * blank the display in all modes.
355 static int pxafb_blank(int blank, struct fb_info *info)
357 struct pxafb_info *fbi = (struct pxafb_info *)info;
360 DPRINTK("pxafb_blank: blank=%d\n", blank);
364 case VESA_VSYNC_SUSPEND:
365 case VESA_HSYNC_SUSPEND:
366 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
367 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
368 for (i = 0; i < fbi->palette_size; i++)
369 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
371 pxafb_schedule_work(fbi, C_DISABLE);
372 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
375 case VESA_NO_BLANKING:
376 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
377 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
378 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
379 fb_set_cmap(&fbi->fb.cmap, 1, info);
380 pxafb_schedule_work(fbi, C_ENABLE);
385 static struct fb_ops pxafb_ops = {
386 .owner = THIS_MODULE,
387 .fb_check_var = pxafb_check_var,
388 .fb_set_par = pxafb_set_par,
389 .fb_setcolreg = pxafb_setcolreg,
390 .fb_fillrect = cfb_fillrect,
391 .fb_copyarea = cfb_copyarea,
392 .fb_imageblit = cfb_imageblit,
393 .fb_blank = pxafb_blank,
394 .fb_cursor = soft_cursor,
398 * Calculate the PCD value from the clock rate (in picoseconds).
399 * We take account of the PPCR clock setting.
400 * From PXA Developer's Manual:
411 * LCLK = LCD/Memory Clock
414 * PixelClock here is in Hz while the pixclock argument given is the
415 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
417 * The function get_lclk_frequency_10khz returns LCLK in units of
418 * 10khz. Calling the result of this function lclk gives us the
421 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
422 * -------------------------------------- - 1
425 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
427 static inline unsigned int get_pcd(unsigned int pixclock)
429 unsigned long long pcd;
431 /* FIXME: Need to take into account Double Pixel Clock mode
432 * (DPC) bit? or perhaps set it based on the various clock
435 pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
436 pcd /= 100000000 * 2;
437 /* no need for this, since we should subtract 1 anyway. they cancel */
438 /* pcd += 1; */ /* make up for integer math truncations */
439 return (unsigned int)pcd;
443 * pxafb_activate_var():
444 * Configures LCD Controller based on entries in var parameter. Settings are
445 * only written to the controller if changes were made.
447 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
449 struct pxafb_lcd_reg new_regs;
451 u_int lines_per_panel, pcd = get_pcd(var->pixclock);
453 DPRINTK("Configuring PXA LCD\n");
455 DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
456 var->xres, var->hsync_len,
457 var->left_margin, var->right_margin);
458 DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
459 var->yres, var->vsync_len,
460 var->upper_margin, var->lower_margin);
461 DPRINTK("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
464 if (var->xres < 16 || var->xres > 1024)
465 printk(KERN_ERR "%s: invalid xres %d\n",
466 fbi->fb.fix.id, var->xres);
467 switch(var->bits_per_pixel) {
475 printk(KERN_ERR "%s: invalid bit depth %d\n",
476 fbi->fb.fix.id, var->bits_per_pixel);
479 if (var->hsync_len < 1 || var->hsync_len > 64)
480 printk(KERN_ERR "%s: invalid hsync_len %d\n",
481 fbi->fb.fix.id, var->hsync_len);
482 if (var->left_margin < 1 || var->left_margin > 255)
483 printk(KERN_ERR "%s: invalid left_margin %d\n",
484 fbi->fb.fix.id, var->left_margin);
485 if (var->right_margin < 1 || var->right_margin > 255)
486 printk(KERN_ERR "%s: invalid right_margin %d\n",
487 fbi->fb.fix.id, var->right_margin);
488 if (var->yres < 1 || var->yres > 1024)
489 printk(KERN_ERR "%s: invalid yres %d\n",
490 fbi->fb.fix.id, var->yres);
491 if (var->vsync_len < 1 || var->vsync_len > 64)
492 printk(KERN_ERR "%s: invalid vsync_len %d\n",
493 fbi->fb.fix.id, var->vsync_len);
494 if (var->upper_margin < 0 || var->upper_margin > 255)
495 printk(KERN_ERR "%s: invalid upper_margin %d\n",
496 fbi->fb.fix.id, var->upper_margin);
497 if (var->lower_margin < 0 || var->lower_margin > 255)
498 printk(KERN_ERR "%s: invalid lower_margin %d\n",
499 fbi->fb.fix.id, var->lower_margin);
502 new_regs.lccr0 = fbi->lccr0 |
503 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
504 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
507 LCCR1_DisWdth(var->xres) +
508 LCCR1_HorSnchWdth(var->hsync_len) +
509 LCCR1_BegLnDel(var->left_margin) +
510 LCCR1_EndLnDel(var->right_margin);
513 * If we have a dual scan LCD, we need to halve
514 * the YRES parameter.
516 lines_per_panel = var->yres;
517 if (fbi->lccr0 & LCCR0_SDS)
518 lines_per_panel /= 2;
521 LCCR2_DisHght(lines_per_panel) +
522 LCCR2_VrtSnchWdth(var->vsync_len) +
523 LCCR2_BegFrmDel(var->upper_margin) +
524 LCCR2_EndFrmDel(var->lower_margin);
526 new_regs.lccr3 = fbi->lccr3 |
527 pxafb_bpp_to_lccr3(var) |
528 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
529 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
532 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
534 DPRINTK("nlccr0 = 0x%08x\n", new_regs.lccr0);
535 DPRINTK("nlccr1 = 0x%08x\n", new_regs.lccr1);
536 DPRINTK("nlccr2 = 0x%08x\n", new_regs.lccr2);
537 DPRINTK("nlccr3 = 0x%08x\n", new_regs.lccr3);
539 /* Update shadow copy atomically */
540 local_irq_save(flags);
542 /* setup dma descriptors */
543 fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
544 fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
545 fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
547 fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
548 fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
549 fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
551 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
553 /* populate descriptors */
554 fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
555 fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
556 fbi->dmadesc_fblow_cpu->fidr = 0;
557 fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
559 fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
561 fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
562 fbi->dmadesc_fbhigh_cpu->fidr = 0;
563 fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
565 fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
566 fbi->dmadesc_palette_cpu->fidr = 0;
567 fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
569 if( var->bits_per_pixel < 12)
571 /* assume any mode with <12 bpp is palette driven */
572 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
573 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
574 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
578 /* palette shouldn't be loaded in true-color mode */
579 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
580 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
581 /* init it to something, even though we won't be using it */
582 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
586 DPRINTK("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
587 DPRINTK("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
588 DPRINTK("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
589 DPRINTK("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
590 DPRINTK("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
591 DPRINTK("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
593 DPRINTK("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
594 DPRINTK("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
595 DPRINTK("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
597 DPRINTK("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
598 DPRINTK("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
599 DPRINTK("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
601 DPRINTK("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
602 DPRINTK("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
603 DPRINTK("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
606 fbi->reg_lccr0 = new_regs.lccr0;
607 fbi->reg_lccr1 = new_regs.lccr1;
608 fbi->reg_lccr2 = new_regs.lccr2;
609 fbi->reg_lccr3 = new_regs.lccr3;
610 local_irq_restore(flags);
613 * Only update the registers if the controller is enabled
614 * and something has changed.
616 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
617 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
618 (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1))
619 pxafb_schedule_work(fbi, C_REENABLE);
625 * NOTE! The following functions are purely helpers for set_ctrlr_state.
626 * Do not call them directly; set_ctrlr_state does the correct serialisation
627 * to ensure that things happen in the right way 100% of time time.
630 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
632 DPRINTK("backlight o%s\n", on ? "n" : "ff");
634 if (pxafb_backlight_power)
635 pxafb_backlight_power(on);
638 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
640 DPRINTK("LCD power o%s\n", on ? "n" : "ff");
646 static void pxafb_setup_gpio(struct pxafb_info *fbi)
648 unsigned int lccr0 = fbi->lccr0;
651 * setup is based on type of panel supported
654 /* 4 bit interface */
655 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
656 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
657 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
660 GPDR1 |= (0xf << 26);
661 GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
664 GPDR2 |= (0xf << 10);
665 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
668 /* 8 bit interface */
669 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
670 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
671 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
672 (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
675 GPDR1 |= (0x3f << 26);
678 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
679 GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
682 GPDR2 |= (0xf << 10);
683 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
686 /* 16 bit interface */
687 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
688 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
691 GPDR1 |= (0x3f << 26);
694 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
695 GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
699 printk( KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
703 static void pxafb_enable_controller(struct pxafb_info *fbi)
705 DPRINTK("Enabling LCD controller\n");
706 DPRINTK("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
707 DPRINTK("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
708 DPRINTK("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
709 DPRINTK("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
710 DPRINTK("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
711 DPRINTK("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
713 /* Sequence from 11.7.10 */
714 LCCR3 = fbi->reg_lccr3;
715 LCCR2 = fbi->reg_lccr2;
716 LCCR1 = fbi->reg_lccr1;
717 LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
719 FDADR0 = fbi->fdadr0;
720 FDADR1 = fbi->fdadr1;
723 DPRINTK("FDADR0 0x%08x\n", (unsigned int) FDADR0);
724 DPRINTK("FDADR1 0x%08x\n", (unsigned int) FDADR1);
725 DPRINTK("LCCR0 0x%08x\n", (unsigned int) LCCR0);
726 DPRINTK("LCCR1 0x%08x\n", (unsigned int) LCCR1);
727 DPRINTK("LCCR2 0x%08x\n", (unsigned int) LCCR2);
728 DPRINTK("LCCR3 0x%08x\n", (unsigned int) LCCR3);
731 static void pxafb_disable_controller(struct pxafb_info *fbi)
733 DECLARE_WAITQUEUE(wait, current);
735 DPRINTK("Disabling LCD controller\n");
737 add_wait_queue(&fbi->ctrlr_wait, &wait);
738 set_current_state(TASK_UNINTERRUPTIBLE);
740 LCSR = 0xffffffff; /* Clear LCD Status Register */
741 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
742 LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */
744 schedule_timeout(20 * HZ / 1000);
745 remove_wait_queue(&fbi->ctrlr_wait, &wait);
749 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
751 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
753 struct pxafb_info *fbi = dev_id;
754 unsigned int lcsr = LCSR;
756 if (lcsr & LCSR_LDD) {
758 wake_up(&fbi->ctrlr_wait);
766 * This function must be called from task context only, since it will
767 * sleep when disabling the LCD controller, or if we get two contending
768 * processes trying to alter state.
770 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
774 down(&fbi->ctrlr_sem);
776 old_state = fbi->state;
779 * Hack around fbcon initialisation.
781 if (old_state == C_STARTUP && state == C_REENABLE)
785 case C_DISABLE_CLKCHANGE:
787 * Disable controller for clock change. If the
788 * controller is already disabled, then do nothing.
790 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
792 //TODO __pxafb_lcd_power(fbi, 0);
793 pxafb_disable_controller(fbi);
802 if (old_state != C_DISABLE) {
804 __pxafb_backlight_power(fbi, 0);
805 __pxafb_lcd_power(fbi, 0);
806 if (old_state != C_DISABLE_CLKCHANGE)
807 pxafb_disable_controller(fbi);
811 case C_ENABLE_CLKCHANGE:
813 * Enable the controller after clock change. Only
814 * do this if we were disabled for the clock change.
816 if (old_state == C_DISABLE_CLKCHANGE) {
817 fbi->state = C_ENABLE;
818 pxafb_enable_controller(fbi);
819 //TODO __pxafb_lcd_power(fbi, 1);
825 * Re-enable the controller only if it was already
826 * enabled. This is so we reprogram the control
829 if (old_state == C_ENABLE) {
830 pxafb_disable_controller(fbi);
831 pxafb_setup_gpio(fbi);
832 pxafb_enable_controller(fbi);
838 * Re-enable the controller after PM. This is not
839 * perfect - think about the case where we were doing
840 * a clock change, and we suspended half-way through.
842 if (old_state != C_DISABLE_PM)
848 * Power up the LCD screen, enable controller, and
849 * turn on the backlight.
851 if (old_state != C_ENABLE) {
852 fbi->state = C_ENABLE;
853 pxafb_setup_gpio(fbi);
854 pxafb_enable_controller(fbi);
855 __pxafb_lcd_power(fbi, 1);
856 __pxafb_backlight_power(fbi, 1);
864 * Our LCD controller task (which is called when we blank or unblank)
867 static void pxafb_task(void *dummy)
869 struct pxafb_info *fbi = dummy;
870 u_int state = xchg(&fbi->task_state, -1);
872 set_ctrlr_state(fbi, state);
875 #ifdef CONFIG_CPU_FREQ
877 * CPU clock speed change handler. We need to adjust the LCD timing
878 * parameters when the CPU clock is adjusted by the power management
881 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
884 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
886 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
887 //TODO struct cpufreq_freqs *f = data;
891 case CPUFREQ_PRECHANGE:
892 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
895 case CPUFREQ_POSTCHANGE:
896 pcd = get_pcd(fbi->fb.var.pixclock);
897 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
898 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
905 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
907 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
908 struct fb_var_screeninfo *var = &fbi->fb.var;
909 struct cpufreq_policy *policy = data;
913 case CPUFREQ_INCOMPATIBLE:
914 printk(KERN_DEBUG "min dma period: %d ps, "
915 "new clock %d kHz\n", pxafb_display_dma_period(var),
917 // TODO: fill in min/max values
921 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
923 /* todo: panic if min/max values aren't fulfilled
924 * [can't really happen unless there's a bug in the
925 * CPU policy verification process *
936 * Power management hooks. Note that we won't be called from IRQ context,
937 * unlike the blank functions above, so we may sleep.
939 static int pxafb_suspend(struct device *dev, u32 state, u32 level)
941 struct pxafb_info *fbi = dev_get_drvdata(dev);
943 if (level == SUSPEND_DISABLE || level == SUSPEND_POWER_DOWN)
944 set_ctrlr_state(fbi, C_DISABLE_PM);
948 static int pxafb_resume(struct device *dev, u32 level)
950 struct pxafb_info *fbi = dev_get_drvdata(dev);
952 if (level == RESUME_ENABLE)
953 set_ctrlr_state(fbi, C_ENABLE_PM);
957 #define pxafb_suspend NULL
958 #define pxafb_resume NULL
962 * pxafb_map_video_memory():
963 * Allocates the DRAM memory for the frame buffer. This buffer is
964 * remapped into a non-cached, non-buffered, memory region to
965 * allow palette and pixel writes to occur without flushing the
966 * cache. Once this area is remapped, all virtual memory
967 * access to the video memory should occur at the new region.
969 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
971 u_long palette_mem_size;
974 * We reserve one page for the palette, plus the size
975 * of the framebuffer.
977 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
978 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
979 &fbi->map_dma, GFP_KERNEL);
982 /* prevent initial garbage on screen */
983 memset(fbi->map_cpu, 0, fbi->map_size);
984 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
985 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
987 * FIXME: this is actually the wrong thing to place in
988 * smem_start. But fbdev suffers from the problem that
989 * it needs an API which doesn't exist (in this case,
990 * dma_writecombine_mmap)
992 fbi->fb.fix.smem_start = fbi->screen_dma;
994 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
996 palette_mem_size = fbi->palette_size * sizeof(u16);
997 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
999 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1000 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1003 return fbi->map_cpu ? 0 : -ENOMEM;
1006 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1008 struct pxafb_info *fbi;
1010 struct pxafb_mach_info *inf = dev->platform_data;
1012 /* Alloc the pxafb_info and pseudo_palette in one step */
1013 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 17, GFP_KERNEL);
1017 memset(fbi, 0, sizeof(struct pxafb_info));
1020 strcpy(fbi->fb.fix.id, PXA_NAME);
1022 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1023 fbi->fb.fix.type_aux = 0;
1024 fbi->fb.fix.xpanstep = 0;
1025 fbi->fb.fix.ypanstep = 0;
1026 fbi->fb.fix.ywrapstep = 0;
1027 fbi->fb.fix.accel = FB_ACCEL_NONE;
1029 fbi->fb.var.nonstd = 0;
1030 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1031 fbi->fb.var.height = -1;
1032 fbi->fb.var.width = -1;
1033 fbi->fb.var.accel_flags = 0;
1034 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1036 fbi->fb.fbops = &pxafb_ops;
1037 fbi->fb.flags = FBINFO_FLAG_DEFAULT;
1039 fbi->fb.currcon = -1;
1042 addr = addr + sizeof(struct pxafb_info);
1043 fbi->fb.pseudo_palette = addr;
1045 fbi->max_xres = inf->xres;
1046 fbi->fb.var.xres = inf->xres;
1047 fbi->fb.var.xres_virtual = inf->xres;
1048 fbi->max_yres = inf->yres;
1049 fbi->fb.var.yres = inf->yres;
1050 fbi->fb.var.yres_virtual = inf->yres;
1051 fbi->max_bpp = inf->bpp;
1052 fbi->fb.var.bits_per_pixel = inf->bpp;
1053 fbi->fb.var.pixclock = inf->pixclock;
1054 fbi->fb.var.hsync_len = inf->hsync_len;
1055 fbi->fb.var.left_margin = inf->left_margin;
1056 fbi->fb.var.right_margin = inf->right_margin;
1057 fbi->fb.var.vsync_len = inf->vsync_len;
1058 fbi->fb.var.upper_margin = inf->upper_margin;
1059 fbi->fb.var.lower_margin = inf->lower_margin;
1060 fbi->fb.var.sync = inf->sync;
1061 fbi->fb.var.grayscale = inf->cmap_greyscale;
1062 fbi->cmap_inverse = inf->cmap_inverse;
1063 fbi->cmap_static = inf->cmap_static;
1064 fbi->lccr0 = inf->lccr0;
1065 fbi->lccr3 = inf->lccr3;
1066 fbi->state = C_STARTUP;
1067 fbi->task_state = (u_char)-1;
1068 fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
1071 init_waitqueue_head(&fbi->ctrlr_wait);
1072 INIT_WORK(&fbi->task, pxafb_task, fbi);
1073 init_MUTEX(&fbi->ctrlr_sem);
1078 #ifdef CONFIG_FB_PXA_PARAMETERS
1079 static int __init pxafb_parse_options(struct device *dev, char *options)
1081 struct pxafb_mach_info *inf = dev->platform_data;
1084 if (!options || !*options)
1087 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1089 /* could be made table driven or similar?... */
1090 while ((this_opt = strsep(&options, ",")) != NULL) {
1091 if (!strncmp(this_opt, "mode:", 5)) {
1092 const char *name = this_opt+5;
1093 unsigned int namelen = strlen(name);
1094 int res_specified = 0, bpp_specified = 0;
1095 unsigned int xres = 0, yres = 0, bpp = 0;
1096 int yres_specified = 0;
1098 for (i = namelen-1; i >= 0; i--) {
1102 if (!bpp_specified && !yres_specified) {
1103 bpp = simple_strtoul(&name[i+1], NULL, 0);
1109 if (!yres_specified) {
1110 yres = simple_strtoul(&name[i+1], NULL, 0);
1121 if (i < 0 && yres_specified) {
1122 xres = simple_strtoul(name, NULL, 0);
1126 if ( res_specified ) {
1127 dev_info(dev, "overriding resolution: %dx%x\n", xres, yres);
1128 inf->xres = xres; inf->yres = yres;
1130 if ( bpp_specified )
1138 dev_info(dev, "overriding bit depth: %d\n", bpp);
1141 dev_err(dev, "Depth %d is not valid\n", bpp);
1143 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1144 inf->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1145 dev_info(dev, "override pixclock: %u\n", inf->pixclock);
1146 } else if (!strncmp(this_opt, "left:", 5)) {
1147 inf->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1148 dev_info(dev, "override left: %u\n", inf->left_margin);
1149 } else if (!strncmp(this_opt, "right:", 6)) {
1150 inf->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1151 dev_info(dev, "override right: %u\n", inf->right_margin);
1152 } else if (!strncmp(this_opt, "upper:", 6)) {
1153 inf->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1154 dev_info(dev, "override upper: %u\n", inf->upper_margin);
1155 } else if (!strncmp(this_opt, "lower:", 6)) {
1156 inf->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1157 dev_info(dev, "override lower: %u\n", inf->lower_margin);
1158 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1159 inf->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1160 dev_info(dev, "override hsynclen: %u\n", inf->hsync_len);
1161 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1162 inf->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1163 dev_info(dev, "override vsynclen: %u\n", inf->vsync_len);
1164 } else if (!strncmp(this_opt, "hsync:", 6)) {
1165 if ( simple_strtoul(this_opt+6, NULL, 0) == 0 ) {
1166 dev_info(dev, "override hsync: Active Low\n");
1167 inf->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1169 dev_info(dev, "override hsync: Active High\n");
1170 inf->sync |= FB_SYNC_HOR_HIGH_ACT;
1172 } else if (!strncmp(this_opt, "vsync:", 6)) {
1173 if ( simple_strtoul(this_opt+6, NULL, 0) == 0 ) {
1174 dev_info(dev, "override vsync: Active Low\n");
1175 inf->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1177 dev_info(dev, "override vsync: Active High\n");
1178 inf->sync |= FB_SYNC_VERT_HIGH_ACT;
1180 } else if (!strncmp(this_opt, "dpc:", 4)) {
1181 if ( simple_strtoul(this_opt+4, NULL, 0) == 0 ) {
1182 dev_info(dev, "override double pixel clock: false\n");
1183 inf->lccr3 &= ~LCCR3_DPC;
1185 dev_info(dev, "override double pixel clock: true\n");
1186 inf->lccr3 |= LCCR3_DPC;
1188 } else if (!strncmp(this_opt, "outputen:", 9)) {
1189 if ( simple_strtoul(this_opt+9, NULL, 0) == 0 ) {
1190 dev_info(dev, "override output enable: active low\n");
1191 inf->lccr3 = ( inf->lccr3 & ~LCCR3_OEP ) | LCCR3_OutEnL;
1193 dev_info(dev, "override output enable: active high\n");
1194 inf->lccr3 = ( inf->lccr3 & ~LCCR3_OEP ) | LCCR3_OutEnH;
1196 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1197 if ( simple_strtoul(this_opt+12, NULL, 0) == 0 ) {
1198 dev_info(dev, "override pixel clock polarity: falling edge\n");
1199 inf->lccr3 = ( inf->lccr3 & ~LCCR3_PCP ) | LCCR3_PixFlEdg;
1201 dev_info(dev, "override pixel clock polarity: rising edge\n");
1202 inf->lccr3 = ( inf->lccr3 & ~LCCR3_PCP ) | LCCR3_PixRsEdg;
1204 } else if (!strncmp(this_opt, "color", 5)) {
1205 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1206 } else if (!strncmp(this_opt, "mono", 4)) {
1207 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1208 } else if (!strncmp(this_opt, "active", 6)) {
1209 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1210 } else if (!strncmp(this_opt, "passive", 7)) {
1211 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1212 } else if (!strncmp(this_opt, "single", 6)) {
1213 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1214 } else if (!strncmp(this_opt, "dual", 4)) {
1215 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1216 } else if (!strncmp(this_opt, "4pix", 4)) {
1217 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1218 } else if (!strncmp(this_opt, "8pix", 4)) {
1219 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1221 dev_err(dev, "unknown option: %s\n", this_opt);
1230 int __init pxafb_probe(struct device *dev)
1232 struct pxafb_info *fbi;
1233 struct pxafb_mach_info *inf;
1234 unsigned long flags;
1237 dev_dbg(dev, "pxafb_probe\n");
1239 inf = dev->platform_data;
1245 #ifdef CONFIG_FB_PXA_PARAMETERS
1246 ret = pxafb_parse_options(dev, g_options);
1252 /* Check for various illegal bit-combinations. Currently only
1253 * a warning is given. */
1255 if ( inf->lccr0 & LCCR0_INVALID_CONFIG_MASK )
1256 dev_warn(dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1257 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1258 if ( inf->lccr3 & LCCR3_INVALID_CONFIG_MASK )
1259 dev_warn(dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1260 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1261 if ( inf->lccr0 & LCCR0_DPD &&
1262 ( ( inf->lccr0 & LCCR0_PAS ) != LCCR0_Pas ||
1263 ( inf->lccr0 & LCCR0_SDS ) != LCCR0_Sngl ||
1264 ( inf->lccr0 & LCCR0_CMS ) != LCCR0_Mono ) )
1265 dev_warn(dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1266 " single panel mode\n");
1267 if ( (inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1268 ( inf->lccr0 & LCCR0_SDS ) == LCCR0_Dual )
1269 dev_warn(dev, "Dual panel only valid in passive mode\n");
1270 if ( (inf->lccr0 & LCCR0_PAS ) == LCCR0_Pas &&
1271 (inf->upper_margin || inf->lower_margin) )
1272 dev_warn(dev, "Upper and lower margins must be 0 in passive mode\n");
1275 dev_dbg(dev, "got a %dx%dx%d LCD\n",inf->xres, inf->yres, inf->bpp);
1276 if (inf->xres == 0 || inf->yres == 0 || inf->bpp == 0) {
1277 dev_err(dev, "Invalid resolution or bit depth\n");
1281 pxafb_backlight_power = inf->pxafb_backlight_power;
1282 pxafb_lcd_power = inf->pxafb_lcd_power;
1283 fbi = pxafb_init_fbinfo(dev);
1285 dev_err(dev, "Failed to initialize framebuffer device\n");
1286 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1290 /* Initialize video memory */
1291 ret = pxafb_map_video_memory(fbi);
1293 dev_err(dev, "Failed to allocate video RAM: %d\n", ret);
1297 /* enable LCD controller clock */
1298 local_irq_save(flags);
1300 local_irq_restore(flags);
1302 ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi);
1304 dev_err(dev, "request_irq failed: %d\n", ret);
1310 * This makes sure that our colour bitfield
1311 * descriptors are correctly initialised.
1313 pxafb_check_var(&fbi->fb.var, &fbi->fb);
1314 pxafb_set_par(&fbi->fb);
1316 dev_set_drvdata(dev, fbi);
1318 ret = register_framebuffer(&fbi->fb);
1320 dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
1328 #ifdef CONFIG_CPU_FREQ
1329 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1330 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1331 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1332 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1336 * Ok, now enable the LCD controller
1338 set_ctrlr_state(fbi, C_ENABLE);
1343 dev_set_drvdata(dev, NULL);
1349 static struct device_driver pxafb_driver = {
1351 .bus = &platform_bus_type,
1352 .probe = pxafb_probe,
1354 .suspend = pxafb_suspend,
1355 .resume = pxafb_resume,
1359 int __devinit pxafb_init(void)
1361 return driver_register(&pxafb_driver);
1365 int __devinit pxafb_setup(char *options)
1367 # ifdef CONFIG_FB_PXA_PARAMETERS
1368 strlcpy(g_options, options, sizeof(g_options));
1373 module_init(pxafb_init);
1374 # ifdef CONFIG_FB_PXA_PARAMETERS
1375 module_param_string(options, g_options, sizeof(g_options), 0);
1376 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1380 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1381 MODULE_LICENSE("GPL");