2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
6 * Copyright 1999-2000 Jeff Garzik
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
17 * Paul Richards: Bug fixes, updates
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
32 #include <linux/config.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/string.h>
38 #include <linux/tty.h>
39 #include <linux/slab.h>
40 #include <linux/delay.h>
42 #include <linux/init.h>
43 #include <linux/pci.h>
49 #include <asm/pci-bridge.h>
55 #ifndef CONFIG_PCI /* sanity check */
56 #error This driver requires PCI support.
59 /* version number of this driver */
60 #define RIVAFB_VERSION "0.9.5b"
62 /* ------------------------------------------------------------------------- *
64 * various helpful macros and constants
66 * ------------------------------------------------------------------------- */
70 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
72 #define DPRINTK(fmt, args...)
76 #define assert(expr) \
78 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
79 #expr,__FILE__,__FUNCTION__,__LINE__); \
86 #define PFX "rivafb: "
88 /* macro that allows you to set overflow bits */
89 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
90 #define SetBit(n) (1<<(n))
91 #define Set8Bits(value) ((value)&0xff)
93 /* HW cursor parameters */
96 /* ------------------------------------------------------------------------- *
100 * ------------------------------------------------------------------------- */
102 static int rivafb_blank(int blank, struct fb_info *info);
104 /* ------------------------------------------------------------------------- *
106 * card identification
108 * ------------------------------------------------------------------------- */
134 CH_GEFORCE4_420_GO_M32,
136 CH_GEFORCE4_440_GO_M64,
153 /* directly indexed by riva_chips enum, above */
154 static struct riva_chip_info {
157 } riva_chip_info[] __initdata = {
158 { "RIVA-128", NV_ARCH_03 },
159 { "RIVA-TNT", NV_ARCH_04 },
160 { "RIVA-TNT2", NV_ARCH_04 },
161 { "RIVA-UTNT2", NV_ARCH_04 },
162 { "RIVA-VTNT2", NV_ARCH_04 },
163 { "RIVA-UVTNT2", NV_ARCH_04 },
164 { "RIVA-ITNT2", NV_ARCH_04 },
165 { "GeForce-SDR", NV_ARCH_10 },
166 { "GeForce-DDR", NV_ARCH_10 },
167 { "Quadro", NV_ARCH_10 },
168 { "GeForce2-MX", NV_ARCH_10 },
169 { "GeForce2-MX", NV_ARCH_10 },
170 { "GeForce2-GO", NV_ARCH_10 },
171 { "Quadro2-MXR", NV_ARCH_10 },
172 { "GeForce2-GTS", NV_ARCH_10 },
173 { "GeForce2-GTS", NV_ARCH_10 },
174 { "GeForce2-ULTRA", NV_ARCH_10 },
175 { "Quadro2-PRO", NV_ARCH_10 },
176 { "GeForce4-MX-460", NV_ARCH_20 },
177 { "GeForce4-MX-440", NV_ARCH_20 },
178 { "GeForce4-MX-420", NV_ARCH_20 },
179 { "GeForce4-440-GO", NV_ARCH_20 },
180 { "GeForce4-420-GO", NV_ARCH_20 },
181 { "GeForce4-420-GO-M32", NV_ARCH_20 },
182 { "Quadro4-500-XGL", NV_ARCH_20 },
183 { "GeForce4-440-GO-M64", NV_ARCH_20 },
184 { "Quadro4-200", NV_ARCH_20 },
185 { "Quadro4-550-XGL", NV_ARCH_20 },
186 { "Quadro4-500-GOGL", NV_ARCH_20 },
187 { "GeForce2", NV_ARCH_20 },
188 { "GeForce3", NV_ARCH_20 },
189 { "GeForce3 Ti 200", NV_ARCH_20 },
190 { "GeForce3 Ti 500", NV_ARCH_20 },
191 { "Quadro DDC", NV_ARCH_20 },
192 { "GeForce4 Ti 4600", NV_ARCH_20 },
193 { "GeForce4 Ti 4400", NV_ARCH_20 },
194 { "GeForce4 Ti 4200", NV_ARCH_20 },
195 { "Quadro4-900-XGL", NV_ARCH_20 },
196 { "Quadro4-750-XGL", NV_ARCH_20 },
197 { "Quadro4-700-XGL", NV_ARCH_20 }
200 static struct pci_device_id rivafb_pci_tbl[] = {
201 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_128 },
203 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT },
205 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT2 },
207 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_UTNT2 },
209 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 },
211 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 },
213 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_ITNT2 },
215 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_SDR },
217 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_DDR },
219 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO },
221 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX },
223 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX2 },
225 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GO },
227 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_MXR },
229 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS },
231 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS2 },
233 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_ULTRA },
235 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_PRO },
237 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_460 },
239 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_440 },
241 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_420 },
243 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO },
245 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO },
247 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO_M32 },
249 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500XGL },
251 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO_M64 },
253 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_200 },
255 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_550XGL },
257 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500_GOGL },
259 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_IGEFORCE2 },
261 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3 },
263 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_1 },
265 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_2 },
267 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO_DDC },
269 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4600 },
271 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4400 },
273 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4200 },
275 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_900XGL },
277 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_750XGL },
279 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_700XGL },
281 { 0, } /* terminate list */
283 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
285 /* ------------------------------------------------------------------------- *
289 * ------------------------------------------------------------------------- */
291 /* command line data, set in rivafb_setup() */
292 static u32 pseudo_palette[17];
293 static int flatpanel __initdata = -1; /* Autodetect later */
294 static int forceCRTC __initdata = -1;
296 static int nomtrr __initdata = 0;
299 static char *mode_option __initdata = NULL;
300 static int strictmode = 0;
302 static struct fb_fix_screeninfo rivafb_fix = {
304 .type = FB_TYPE_PACKED_PIXELS,
309 static struct fb_var_screeninfo rivafb_default_var = {
319 .activate = FB_ACTIVATE_NOW,
322 .accel_flags = FB_ACCELF_TEXT,
330 .vmode = FB_VMODE_NONINTERLACED
334 static const struct riva_regs reg_template = {
335 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
336 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
337 0x41, 0x01, 0x0F, 0x00, 0x00},
338 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
339 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
340 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
341 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
342 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
343 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
344 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
345 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
348 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
350 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
354 /* ------------------------------------------------------------------------- *
358 * ------------------------------------------------------------------------- */
360 static inline void CRTCout(struct riva_par *par, unsigned char index,
363 VGA_WR08(par->riva.PCIO, 0x3d4, index);
364 VGA_WR08(par->riva.PCIO, 0x3d5, val);
367 static inline unsigned char CRTCin(struct riva_par *par,
370 VGA_WR08(par->riva.PCIO, 0x3d4, index);
371 return (VGA_RD08(par->riva.PCIO, 0x3d5));
374 static inline void GRAout(struct riva_par *par, unsigned char index,
377 VGA_WR08(par->riva.PVIO, 0x3ce, index);
378 VGA_WR08(par->riva.PVIO, 0x3cf, val);
381 static inline unsigned char GRAin(struct riva_par *par,
384 VGA_WR08(par->riva.PVIO, 0x3ce, index);
385 return (VGA_RD08(par->riva.PVIO, 0x3cf));
388 static inline void SEQout(struct riva_par *par, unsigned char index,
391 VGA_WR08(par->riva.PVIO, 0x3c4, index);
392 VGA_WR08(par->riva.PVIO, 0x3c5, val);
395 static inline unsigned char SEQin(struct riva_par *par,
398 VGA_WR08(par->riva.PVIO, 0x3c4, index);
399 return (VGA_RD08(par->riva.PVIO, 0x3c5));
402 static inline void ATTRout(struct riva_par *par, unsigned char index,
405 VGA_WR08(par->riva.PCIO, 0x3c0, index);
406 VGA_WR08(par->riva.PCIO, 0x3c0, val);
409 static inline unsigned char ATTRin(struct riva_par *par,
412 VGA_WR08(par->riva.PCIO, 0x3c0, index);
413 return (VGA_RD08(par->riva.PCIO, 0x3c1));
416 static inline void MISCout(struct riva_par *par, unsigned char val)
418 VGA_WR08(par->riva.PVIO, 0x3c2, val);
421 static inline unsigned char MISCin(struct riva_par *par)
423 return (VGA_RD08(par->riva.PVIO, 0x3cc));
426 static u8 byte_rev[256] = {
427 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
428 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
429 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
430 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
431 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
432 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
433 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
434 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
435 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
436 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
437 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
438 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
439 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
440 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
441 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
442 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
443 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
444 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
445 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
446 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
447 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
448 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
449 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
450 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
451 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
452 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
453 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
454 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
455 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
456 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
457 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
458 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
461 static inline void reverse_order(u32 *l)
464 *a = byte_rev[*a], a++;
465 *a = byte_rev[*a], a++;
466 *a = byte_rev[*a], a++;
470 /* ------------------------------------------------------------------------- *
474 * ------------------------------------------------------------------------- */
477 * rivafb_load_cursor_image - load cursor image to hardware
478 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
479 * @par: pointer to private data
480 * @w: width of cursor image in pixels
481 * @h: height of cursor image in scanlines
482 * @bg: background color (ARGB1555) - alpha bit determines opacity
483 * @fg: foreground color (ARGB1555)
486 * Loads cursor image based on a monochrome source and mask bitmap. The
487 * image bits determines the color of the pixel, 0 for background, 1 for
488 * foreground. Only the affected region (as determined by @w and @h
489 * parameters) will be updated.
494 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
495 u16 bg, u16 fg, u32 w, u32 h)
499 u32 *data = (u32 *)data8;
501 for (i = 0; i < h; i++) {
505 for (j = 0; j < w/2; j++) {
507 #if defined (__BIG_ENDIAN)
508 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
510 tmp |= (b & (1 << 31)) ? fg : bg;
513 tmp = (b & 1) ? fg : bg;
515 tmp |= (b & 1) ? fg << 16 : bg << 16;
518 writel(tmp, &par->riva.CURSOR[k++]);
520 k += (MAX_CURS - w)/2;
524 /* ------------------------------------------------------------------------- *
526 * general utility functions
528 * ------------------------------------------------------------------------- */
531 * riva_wclut - set CLUT entry
532 * @chip: pointer to RIVA_HW_INST object
533 * @regnum: register number
534 * @red: red component
535 * @green: green component
536 * @blue: blue component
539 * Sets color register @regnum.
544 static void riva_wclut(RIVA_HW_INST *chip,
545 unsigned char regnum, unsigned char red,
546 unsigned char green, unsigned char blue)
548 VGA_WR08(chip->PDIO, 0x3c8, regnum);
549 VGA_WR08(chip->PDIO, 0x3c9, red);
550 VGA_WR08(chip->PDIO, 0x3c9, green);
551 VGA_WR08(chip->PDIO, 0x3c9, blue);
555 * riva_rclut - read fromCLUT register
556 * @chip: pointer to RIVA_HW_INST object
557 * @regnum: register number
558 * @red: red component
559 * @green: green component
560 * @blue: blue component
563 * Reads red, green, and blue from color register @regnum.
568 static void riva_rclut(RIVA_HW_INST *chip,
569 unsigned char regnum, unsigned char *red,
570 unsigned char *green, unsigned char *blue)
573 VGA_WR08(chip->PDIO, 0x3c8, regnum);
574 *red = VGA_RD08(chip->PDIO, 0x3c9);
575 *green = VGA_RD08(chip->PDIO, 0x3c9);
576 *blue = VGA_RD08(chip->PDIO, 0x3c9);
580 * riva_save_state - saves current chip state
581 * @par: pointer to riva_par object containing info for current riva board
582 * @regs: pointer to riva_regs object
585 * Saves current chip state to @regs.
591 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
595 par->riva.LockUnlock(&par->riva, 0);
597 par->riva.UnloadStateExt(&par->riva, ®s->ext);
599 regs->misc_output = MISCin(par);
601 for (i = 0; i < NUM_CRT_REGS; i++)
602 regs->crtc[i] = CRTCin(par, i);
604 for (i = 0; i < NUM_ATC_REGS; i++)
605 regs->attr[i] = ATTRin(par, i);
607 for (i = 0; i < NUM_GRC_REGS; i++)
608 regs->gra[i] = GRAin(par, i);
610 for (i = 0; i < NUM_SEQ_REGS; i++)
611 regs->seq[i] = SEQin(par, i);
615 * riva_load_state - loads current chip state
616 * @par: pointer to riva_par object containing info for current riva board
617 * @regs: pointer to riva_regs object
620 * Loads chip state from @regs.
623 * riva_load_video_mode()
628 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
630 RIVA_HW_STATE *state = ®s->ext;
633 CRTCout(par, 0x11, 0x00);
635 par->riva.LockUnlock(&par->riva, 0);
637 par->riva.LoadStateExt(&par->riva, state);
639 MISCout(par, regs->misc_output);
641 for (i = 0; i < NUM_CRT_REGS; i++) {
647 CRTCout(par, i, regs->crtc[i]);
651 for (i = 0; i < NUM_ATC_REGS; i++)
652 ATTRout(par, i, regs->attr[i]);
654 for (i = 0; i < NUM_GRC_REGS; i++)
655 GRAout(par, i, regs->gra[i]);
657 for (i = 0; i < NUM_SEQ_REGS; i++)
658 SEQout(par, i, regs->seq[i]);
662 * riva_load_video_mode - calculate timings
663 * @info: pointer to fb_info object containing info for current riva board
666 * Calculate some timings and then send em off to riva_load_state().
671 static void riva_load_video_mode(struct fb_info *info)
673 int bpp, width, hDisplaySize, hDisplay, hStart,
674 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
675 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
676 struct riva_par *par = (struct riva_par *) info->par;
677 struct riva_regs newmode;
679 /* time to calculate */
680 rivafb_blank(1, info);
682 bpp = info->var.bits_per_pixel;
683 if (bpp == 16 && info->var.green.length == 5)
685 width = info->var.xres_virtual;
686 hDisplaySize = info->var.xres;
687 hDisplay = (hDisplaySize / 8) - 1;
688 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
689 hEnd = (hDisplaySize + info->var.right_margin +
690 info->var.hsync_len) / 8 - 1;
691 hTotal = (hDisplaySize + info->var.right_margin +
692 info->var.hsync_len + info->var.left_margin) / 8 - 5;
693 hBlankStart = hDisplay;
694 hBlankEnd = hTotal + 4;
696 height = info->var.yres_virtual;
697 vDisplay = info->var.yres - 1;
698 vStart = info->var.yres + info->var.lower_margin - 1;
699 vEnd = info->var.yres + info->var.lower_margin +
700 info->var.vsync_len - 1;
701 vTotal = info->var.yres + info->var.lower_margin +
702 info->var.vsync_len + info->var.upper_margin + 2;
703 vBlankStart = vDisplay;
704 vBlankEnd = vTotal + 1;
705 dotClock = 1000000000 / info->var.pixclock;
707 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
709 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
712 if (par->FlatPanel) {
715 vBlankStart = vStart;
718 hBlankEnd = hTotal + 4;
721 newmode.crtc[0x0] = Set8Bits (hTotal);
722 newmode.crtc[0x1] = Set8Bits (hDisplay);
723 newmode.crtc[0x2] = Set8Bits (hBlankStart);
724 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
725 newmode.crtc[0x4] = Set8Bits (hStart);
726 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
727 | SetBitField (hEnd, 4: 0, 4:0);
728 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
729 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
730 | SetBitField (vDisplay, 8: 8, 1:1)
731 | SetBitField (vStart, 8: 8, 2:2)
732 | SetBitField (vBlankStart, 8: 8, 3:3)
734 | SetBitField (vTotal, 9: 9, 5:5)
735 | SetBitField (vDisplay, 9: 9, 6:6)
736 | SetBitField (vStart, 9: 9, 7:7);
737 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
739 newmode.crtc[0x10] = Set8Bits (vStart);
740 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
742 newmode.crtc[0x12] = Set8Bits (vDisplay);
743 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
744 newmode.crtc[0x15] = Set8Bits (vBlankStart);
745 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
747 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
748 | SetBitField(vBlankStart,10:10,3:3)
749 | SetBitField(vStart,10:10,2:2)
750 | SetBitField(vDisplay,10:10,1:1)
751 | SetBitField(vTotal,10:10,0:0);
752 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
753 | SetBitField(hDisplay,8:8,1:1)
754 | SetBitField(hBlankStart,8:8,2:2)
755 | SetBitField(hStart,8:8,3:3);
756 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
757 | SetBitField(vDisplay,11:11,2:2)
758 | SetBitField(vStart,11:11,4:4)
759 | SetBitField(vBlankStart,11:11,6:6);
761 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
762 int tmp = (hTotal >> 1) & ~1;
763 newmode.ext.interlace = Set8Bits(tmp);
764 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
766 newmode.ext.interlace = 0xff; /* interlace off */
768 if (par->riva.Architecture >= NV_ARCH_10)
769 par->riva.CURSOR = (U032 *)(info->screen_base + par->riva.CursorStart);
771 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
772 newmode.misc_output &= ~0x40;
774 newmode.misc_output |= 0x40;
775 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
776 newmode.misc_output &= ~0x80;
778 newmode.misc_output |= 0x80;
780 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
781 hDisplaySize, height, dotClock);
783 newmode.ext.scale = par->riva.PRAMDAC[0x00000848/4] & 0xfff000ff;
784 if (par->FlatPanel == 1) {
785 newmode.ext.pixel |= (1 << 7);
786 newmode.ext.scale |= (1 << 8);
788 if (par->SecondCRTC) {
789 newmode.ext.head = par->riva.PCRTC0[0x00000860/4] & ~0x00001000;
790 newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] | 0x00001000;
791 newmode.ext.crtcOwner = 3;
792 newmode.ext.pllsel |= 0x20000800;
793 newmode.ext.vpll2 = newmode.ext.vpll;
794 } else if (par->riva.twoHeads) {
795 newmode.ext.head = par->riva.PCRTC0[0x00000860/4] | 0x00001000;
796 newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] & ~0x00001000;
797 newmode.ext.crtcOwner = 0;
798 newmode.ext.vpll2 = par->riva.PRAMDAC0[0x00000520/4];
800 if (par->FlatPanel == 1) {
801 newmode.ext.pixel |= (1 << 7);
802 newmode.ext.scale |= (1 << 8);
804 newmode.ext.cursorConfig = 0x02000100;
805 par->current_state = newmode;
806 riva_load_state(par, &par->current_state);
807 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
808 rivafb_blank(0, info);
811 static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
813 var->xres = var->xres_virtual = modedb->xres;
814 var->yres = modedb->yres;
815 if (var->yres_virtual < var->yres)
816 var->yres_virtual = var->yres;
817 var->xoffset = var->yoffset = 0;
818 var->pixclock = modedb->pixclock;
819 var->left_margin = modedb->left_margin;
820 var->right_margin = modedb->right_margin;
821 var->upper_margin = modedb->upper_margin;
822 var->lower_margin = modedb->lower_margin;
823 var->hsync_len = modedb->hsync_len;
824 var->vsync_len = modedb->vsync_len;
825 var->sync = modedb->sync;
826 var->vmode = modedb->vmode;
830 * rivafb_do_maximize -
831 * @info: pointer to fb_info object containing info for current riva board
840 * -EINVAL on failure, 0 on success
846 static int rivafb_do_maximize(struct fb_info *info,
847 struct fb_var_screeninfo *var,
862 /* use highest possible virtual resolution */
863 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
864 printk(KERN_WARNING PFX
865 "using maximum available virtual resolution\n");
866 for (i = 0; modes[i].xres != -1; i++) {
867 if (modes[i].xres * nom / den * modes[i].yres <
871 if (modes[i].xres == -1) {
873 "could not find a virtual resolution that fits into video memory!!\n");
874 DPRINTK("EXIT - EINVAL error\n");
877 var->xres_virtual = modes[i].xres;
878 var->yres_virtual = modes[i].yres;
881 "virtual resolution set to maximum of %dx%d\n",
882 var->xres_virtual, var->yres_virtual);
883 } else if (var->xres_virtual == -1) {
884 var->xres_virtual = (info->fix.smem_len * den /
885 (nom * var->yres_virtual)) & ~15;
886 printk(KERN_WARNING PFX
887 "setting virtual X resolution to %d\n", var->xres_virtual);
888 } else if (var->yres_virtual == -1) {
889 var->xres_virtual = (var->xres_virtual + 15) & ~15;
890 var->yres_virtual = info->fix.smem_len * den /
891 (nom * var->xres_virtual);
892 printk(KERN_WARNING PFX
893 "setting virtual Y resolution to %d\n", var->yres_virtual);
895 var->xres_virtual = (var->xres_virtual + 15) & ~15;
896 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
898 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
899 var->xres, var->yres, var->bits_per_pixel);
900 DPRINTK("EXIT - EINVAL error\n");
905 if (var->xres_virtual * nom / den >= 8192) {
906 printk(KERN_WARNING PFX
907 "virtual X resolution (%d) is too high, lowering to %d\n",
908 var->xres_virtual, 8192 * den / nom - 16);
909 var->xres_virtual = 8192 * den / nom - 16;
912 if (var->xres_virtual < var->xres) {
914 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
918 if (var->yres_virtual < var->yres) {
920 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
923 if (var->yres_virtual > 0x7fff/nom)
924 var->yres_virtual = 0x7fff/nom;
925 if (var->xres_virtual > 0x7fff/nom)
926 var->xres_virtual = 0x7fff/nom;
932 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
934 RIVA_FIFO_FREE(par->riva, Patt, 4);
935 par->riva.Patt->Color0 = clr0;
936 par->riva.Patt->Color1 = clr1;
937 par->riva.Patt->Monochrome[0] = pat0;
938 par->riva.Patt->Monochrome[1] = pat1;
941 /* acceleration routines */
942 inline void wait_for_idle(struct riva_par *par)
944 while (par->riva.Busy(&par->riva));
948 * Set ROP. Translate X rop into ROP3. Internal routine.
951 riva_set_rop_solid(struct riva_par *par, int rop)
953 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
954 RIVA_FIFO_FREE(par->riva, Rop, 1);
955 par->riva.Rop->Rop3 = rop;
959 void riva_setup_accel(struct fb_info *info)
961 struct riva_par *par = (struct riva_par *) info->par;
963 RIVA_FIFO_FREE(par->riva, Clip, 2);
964 par->riva.Clip->TopLeft = 0x0;
965 par->riva.Clip->WidthHeight = (info->var.xres_virtual & 0xffff) |
966 (info->var.yres_virtual << 16);
967 riva_set_rop_solid(par, 0xcc);
972 * riva_get_cmap_len - query current color map length
973 * @var: standard kernel fb changeable data
976 * Get current color map length.
979 * Length of color map
984 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
986 int rc = 256; /* reasonable default */
988 switch (var->green.length) {
990 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
993 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
996 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
999 /* should not occur */
1005 /* ------------------------------------------------------------------------- *
1007 * framebuffer operations
1009 * ------------------------------------------------------------------------- */
1011 static int rivafb_open(struct fb_info *info, int user)
1013 struct riva_par *par = (struct riva_par *) info->par;
1014 int cnt = atomic_read(&par->ref_count);
1017 memset(&par->state, 0, sizeof(struct vgastate));
1018 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1019 /* save the DAC for Riva128 */
1020 if (par->riva.Architecture == NV_ARCH_03)
1021 par->state.flags |= VGA_SAVE_CMAP;
1022 save_vga(&par->state);
1024 RivaGetConfig(&par->riva, par->Chipset);
1025 /* vgaHWunlock() + riva unlock (0x7F) */
1026 CRTCout(par, 0x11, 0xFF);
1027 par->riva.LockUnlock(&par->riva, 0);
1029 riva_save_state(par, &par->initial_state);
1031 atomic_inc(&par->ref_count);
1035 static int rivafb_release(struct fb_info *info, int user)
1037 struct riva_par *par = (struct riva_par *) info->par;
1038 int cnt = atomic_read(&par->ref_count);
1043 par->riva.LockUnlock(&par->riva, 0);
1044 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1045 riva_load_state(par, &par->initial_state);
1046 restore_vga(&par->state);
1047 par->riva.LockUnlock(&par->riva, 1);
1049 atomic_dec(&par->ref_count);
1053 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1055 struct fb_monspecs *specs = &info->monspecs;
1056 int nom, den; /* translating from pixels->bytes */
1059 switch (var->bits_per_pixel) {
1061 var->red.offset = var->green.offset = var->blue.offset = 0;
1062 var->red.length = var->green.length = var->blue.length = 8;
1063 var->bits_per_pixel = 8;
1067 var->green.length = 5;
1070 var->bits_per_pixel = 16;
1071 if (var->green.length == 5) {
1072 /* 0rrrrrgg gggbbbbb */
1073 var->red.offset = 10;
1074 var->green.offset = 5;
1075 var->blue.offset = 0;
1076 var->red.length = 5;
1077 var->green.length = 5;
1078 var->blue.length = 5;
1080 /* rrrrrggg gggbbbbb */
1081 var->red.offset = 11;
1082 var->green.offset = 5;
1083 var->blue.offset = 0;
1084 var->red.length = 5;
1085 var->green.length = 6;
1086 var->blue.length = 5;
1092 var->red.length = var->green.length = var->blue.length = 8;
1093 var->bits_per_pixel = 32;
1094 var->red.offset = 16;
1095 var->green.offset = 8;
1096 var->blue.offset = 0;
1102 "mode %dx%dx%d rejected...color depth not supported.\n",
1103 var->xres, var->yres, var->bits_per_pixel);
1104 DPRINTK("EXIT, returning -EINVAL\n");
1109 if (!fb_validate_mode(var, info))
1113 /* find best mode from modedb */
1114 if (!mode_valid && specs->modedb_len) {
1115 int i, best, best_refresh, best_x, best_y, diff_x, diff_y;
1117 best_refresh = best = best_x = best_y = 0;
1118 diff_x = diff_y = -1;
1120 for (i = 0; i < specs->modedb_len; i++) {
1121 if (var->xres <= specs->modedb[i].xres &&
1122 !(specs->modedb[i].flag & FB_MODE_IS_CALCULATED) &&
1123 specs->modedb[i].xres - var->xres < diff_x) {
1124 best_x = specs->modedb[i].xres;
1125 diff_x = best_x - var->xres;
1131 for (i = 0; i < specs->modedb_len; i++) {
1132 if (best_x == specs->modedb[i].xres &&
1133 var->yres <= specs->modedb[i].yres &&
1134 !(specs->modedb[i].flag &
1135 FB_MODE_IS_CALCULATED) &&
1136 specs->modedb[i].yres-var->yres < diff_y) {
1137 best_y = specs->modedb[i].yres;
1138 diff_y = best_y - var->yres;
1145 for (i = 0; i < specs->modedb_len; i++) {
1146 if (best_x == specs->modedb[i].xres &&
1147 best_y == specs->modedb[i].yres &&
1148 !(specs->modedb[i].flag &
1149 FB_MODE_IS_CALCULATED) &&
1150 specs->modedb[i].refresh > best_refresh) {
1151 best_refresh=specs->modedb[i].refresh;
1158 riva_update_var(var, &specs->modedb[best]);
1163 /* calculate modeline if supported by monitor */
1164 if (!mode_valid && info->monspecs.gtf) {
1165 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1168 if (!mode_valid && info->monspecs.modedb_len)
1171 if (var->xres_virtual < var->xres)
1172 var->xres_virtual = var->xres;
1173 if (var->yres_virtual <= var->yres)
1174 var->yres_virtual = -1;
1175 if (rivafb_do_maximize(info, var, nom, den) < 0)
1178 if (var->xoffset < 0)
1180 if (var->yoffset < 0)
1183 /* truncate xoffset and yoffset to maximum if too high */
1184 if (var->xoffset > var->xres_virtual - var->xres)
1185 var->xoffset = var->xres_virtual - var->xres - 1;
1187 if (var->yoffset > var->yres_virtual - var->yres)
1188 var->yoffset = var->yres_virtual - var->yres - 1;
1190 var->red.msb_right =
1191 var->green.msb_right =
1192 var->blue.msb_right =
1193 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1197 static int rivafb_set_par(struct fb_info *info)
1199 struct riva_par *par = (struct riva_par *) info->par;
1201 riva_common_setup(par);
1202 RivaGetConfig(&par->riva, par->Chipset);
1203 /* vgaHWunlock() + riva unlock (0x7F) */
1204 CRTCout(par, 0x11, 0xFF);
1205 par->riva.LockUnlock(&par->riva, 0);
1207 riva_load_video_mode(info);
1208 riva_setup_accel(info);
1210 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1211 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1212 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1213 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1218 * rivafb_pan_display
1219 * @var: standard kernel fb changeable data
1221 * @info: pointer to fb_info object containing info for current riva board
1224 * Pan (or wrap, depending on the `vmode' field) the display using the
1225 * `xoffset' and `yoffset' fields of the `var' structure.
1226 * If the values don't fit, return -EINVAL.
1228 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1230 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1231 struct fb_info *info)
1233 struct riva_par *par = (struct riva_par *)info->par;
1236 if (var->xoffset > (var->xres_virtual - var->xres))
1238 if (var->yoffset > (var->yres_virtual - var->yres))
1241 if (var->vmode & FB_VMODE_YWRAP) {
1242 if (var->yoffset < 0
1243 || var->yoffset >= info->var.yres_virtual
1244 || var->xoffset) return -EINVAL;
1246 if (var->xoffset + info->var.xres > info->var.xres_virtual ||
1247 var->yoffset + info->var.yres > info->var.yres_virtual)
1251 base = var->yoffset * info->fix.line_length + var->xoffset;
1253 par->riva.SetStartAddress(&par->riva, base);
1255 info->var.xoffset = var->xoffset;
1256 info->var.yoffset = var->yoffset;
1258 if (var->vmode & FB_VMODE_YWRAP)
1259 info->var.vmode |= FB_VMODE_YWRAP;
1261 info->var.vmode &= ~FB_VMODE_YWRAP;
1265 static int rivafb_blank(int blank, struct fb_info *info)
1267 struct riva_par *par= (struct riva_par *)info->par;
1268 unsigned char tmp, vesa;
1270 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1271 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1275 switch (blank - 1) {
1276 case VESA_NO_BLANKING:
1278 case VESA_VSYNC_SUSPEND:
1281 case VESA_HSYNC_SUSPEND:
1284 case VESA_POWERDOWN:
1289 SEQout(par, 0x01, tmp);
1290 CRTCout(par, 0x1a, vesa);
1296 * @regno: register index
1297 * @red: red component
1298 * @green: green component
1299 * @blue: blue component
1300 * @transp: transparency
1301 * @info: pointer to fb_info object containing info for current riva board
1304 * Set a single color register. The values supplied have a 16 bit
1308 * Return != 0 for invalid regno.
1311 * fbcmap.c:fb_set_cmap()
1313 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1314 unsigned blue, unsigned transp,
1315 struct fb_info *info)
1317 struct riva_par *par = (struct riva_par *)info->par;
1318 RIVA_HW_INST *chip = &par->riva;
1321 if (regno >= riva_get_cmap_len(&info->var))
1324 if (info->var.grayscale) {
1325 /* gray = 0.30*R + 0.59*G + 0.11*B */
1326 red = green = blue =
1327 (red * 77 + green * 151 + blue * 28) >> 8;
1330 switch (info->var.bits_per_pixel) {
1332 /* "transparent" stuff is completely ignored. */
1333 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1336 if (info->var.green.length == 5) {
1338 /* 0rrrrrgg gggbbbbb */
1339 ((u32 *)info->pseudo_palette)[regno] =
1340 ((red & 0xf800) >> 1) |
1341 ((green & 0xf800) >> 6) |
1342 ((blue & 0xf800) >> 11);
1344 for (i = 0; i < 8; i++)
1345 riva_wclut(chip, regno*8+i, red >> 8,
1346 green >> 8, blue >> 8);
1351 /* rrrrrggg gggbbbbb */
1352 ((u32 *)info->pseudo_palette)[regno] =
1353 ((red & 0xf800) >> 0) |
1354 ((green & 0xf800) >> 5) |
1355 ((blue & 0xf800) >> 11);
1358 for (i = 0; i < 8; i++) {
1359 riva_wclut(chip, regno*8+i, red >> 8,
1360 green >> 8, blue >> 8);
1363 for (i = 0; i < 4; i++) {
1364 riva_rclut(chip, regno*2+i, &r, &g, &b);
1365 riva_wclut(chip, regno*4+i, r, green >> 8, b);
1371 ((u32 *)info->pseudo_palette)[regno] =
1372 ((red & 0xff00) << 8) |
1373 ((green & 0xff00)) | ((blue & 0xff00) >> 8);
1376 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1386 * rivafb_fillrect - hardware accelerated color fill function
1387 * @info: pointer to fb_info structure
1388 * @rect: pointer to fb_fillrect structure
1391 * This function fills up a region of framebuffer memory with a solid
1392 * color with a choice of two different ROP's, copy or invert.
1397 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1399 struct riva_par *par = (struct riva_par *) info->par;
1400 u_int color, rop = 0;
1402 if (info->var.bits_per_pixel == 8)
1403 color = rect->color;
1405 color = ((u32 *)info->pseudo_palette)[rect->color];
1407 switch (rect->rop) {
1417 riva_set_rop_solid(par, rop);
1419 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1420 par->riva.Bitmap->Color1A = color;
1422 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1423 par->riva.Bitmap->UnclippedRectangle[0].TopLeft =
1424 (rect->dx << 16) | rect->dy;
1426 par->riva.Bitmap->UnclippedRectangle[0].WidthHeight =
1427 (rect->width << 16) | rect->height;
1429 riva_set_rop_solid(par, 0xcc);
1434 * rivafb_copyarea - hardware accelerated blit function
1435 * @info: pointer to fb_info structure
1436 * @region: pointer to fb_copyarea structure
1439 * This copies an area of pixels from one location to another
1444 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1446 struct riva_par *par = (struct riva_par *) info->par;
1448 RIVA_FIFO_FREE(par->riva, Blt, 3);
1449 par->riva.Blt->TopLeftSrc = (region->sy << 16) | region->sx;
1450 par->riva.Blt->TopLeftDst = (region->dy << 16) | region->dx;
1452 par->riva.Blt->WidthHeight = (region->height << 16) | region->width;
1456 static inline void convert_bgcolor_16(u32 *col)
1458 *col = ((*col & 0x0000F800) << 8)
1459 | ((*col & 0x00007E0) << 5)
1460 | ((*col & 0x0000001F) << 3)
1466 * rivafb_imageblit: hardware accelerated color expand function
1467 * @info: pointer to fb_info structure
1468 * @image: pointer to fb_image structure
1471 * If the source is a monochrome bitmap, the function fills up a a region
1472 * of framebuffer memory with pixels whose color is determined by the bit
1473 * setting of the bitmap, 1 - foreground, 0 - background.
1475 * If the source is not a monochrome bitmap, color expansion is not done.
1476 * In this case, it is channeled to a software function.
1481 static void rivafb_imageblit(struct fb_info *info,
1482 const struct fb_image *image)
1484 struct riva_par *par = (struct riva_par *) info->par;
1485 u32 fgx = 0, bgx = 0, width, tmp;
1486 u8 *cdat = (u8 *) image->data;
1490 if (image->depth != 1) {
1491 cfb_imageblit(info, image);
1495 switch (info->var.bits_per_pixel) {
1497 fgx = image->fg_color;
1498 bgx = image->bg_color;
1501 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1502 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1503 if (info->var.green.length == 6)
1504 convert_bgcolor_16(&bgx);
1507 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1508 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1512 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1513 par->riva.Bitmap->ClipE.TopLeft =
1514 (image->dy << 16) | (image->dx & 0xFFFF);
1515 par->riva.Bitmap->ClipE.BottomRight =
1516 (((image->dy + image->height) << 16) |
1517 ((image->dx + image->width) & 0xffff));
1518 par->riva.Bitmap->Color0E = bgx;
1519 par->riva.Bitmap->Color1E = fgx;
1520 par->riva.Bitmap->WidthHeightInE =
1521 (image->height << 16) | ((image->width + 31) & ~31);
1522 par->riva.Bitmap->WidthHeightOutE =
1523 (image->height << 16) | ((image->width + 31) & ~31);
1524 par->riva.Bitmap->PointE =
1525 (image->dy << 16) | (image->dx & 0xFFFF);
1527 d = &par->riva.Bitmap->MonochromeData01E;
1529 width = (image->width + 31)/32;
1530 size = width * image->height;
1531 while (size >= 16) {
1532 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1533 for (i = 0; i < 16; i++) {
1534 tmp = *((u32 *)cdat);
1535 cdat = (u8 *)((u32 *)cdat + 1);
1536 reverse_order(&tmp);
1542 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1543 for (i = 0; i < size; i++) {
1544 tmp = *((u32 *) cdat);
1545 cdat = (u8 *)((u32 *)cdat + 1);
1546 reverse_order(&tmp);
1553 * rivafb_cursor - hardware cursor function
1554 * @info: pointer to info structure
1555 * @cursor: pointer to fbcursor structure
1558 * A cursor function that supports displaying a cursor image via hardware.
1559 * Within the kernel, copy and invert rops are supported. If exported
1560 * to user space, only the copy rop will be supported.
1565 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1567 struct riva_par *par = (struct riva_par *) info->par;
1568 u8 data[MAX_CURS * MAX_CURS/8];
1572 par->riva.ShowHideCursor(&par->riva, 0);
1574 if (cursor->set & FB_CUR_SETPOS) {
1577 info->cursor.image.dx = cursor->image.dx;
1578 info->cursor.image.dy = cursor->image.dy;
1579 yy = cursor->image.dy - info->var.yoffset;
1580 xx = cursor->image.dx - info->var.xoffset;
1584 par->riva.PRAMDAC[0x0000300/4] = temp;
1587 if (cursor->set & FB_CUR_SETSIZE) {
1588 info->cursor.image.height = cursor->image.height;
1589 info->cursor.image.width = cursor->image.width;
1590 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1593 if (cursor->set & FB_CUR_SETCMAP) {
1594 info->cursor.image.bg_color = cursor->image.bg_color;
1595 info->cursor.image.fg_color = cursor->image.fg_color;
1598 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETCUR)) {
1599 u32 bg_idx = info->cursor.image.bg_color;
1600 u32 fg_idx = info->cursor.image.fg_color;
1601 u32 s_pitch = (info->cursor.image.width+7) >> 3;
1602 u32 d_pitch = MAX_CURS/8;
1603 u8 *dat = (u8 *) cursor->image.data;
1604 u8 *msk = (u8 *) info->cursor.mask;
1607 info->cursor.image.data = cursor->image.data;
1608 switch (info->cursor.rop) {
1610 for (i = 0; i < s_pitch * info->cursor.image.height;
1612 src[i] = dat[i] ^ msk[i];
1616 for (i = 0; i < s_pitch * info->cursor.image.height;
1618 src[i] = dat[i] & msk[i];
1622 fb_sysmove_buf_aligned(info, &info->sprite, data, d_pitch, src,
1623 s_pitch, info->cursor.image.height);
1625 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1626 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1627 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
1629 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1630 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1631 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
1633 par->riva.LockUnlock(&par->riva, 0);
1635 rivafb_load_cursor_image(par, data, bg, fg,
1636 info->cursor.image.width,
1637 info->cursor.image.height);
1639 if (info->cursor.enable)
1640 par->riva.ShowHideCursor(&par->riva, 1);
1644 static int rivafb_sync(struct fb_info *info)
1646 struct riva_par *par = (struct riva_par *)info->par;
1652 /* ------------------------------------------------------------------------- *
1654 * initialization helper functions
1656 * ------------------------------------------------------------------------- */
1658 /* kernel interface */
1659 static struct fb_ops riva_fb_ops = {
1660 .owner = THIS_MODULE,
1661 .fb_open = rivafb_open,
1662 .fb_release = rivafb_release,
1663 .fb_check_var = rivafb_check_var,
1664 .fb_set_par = rivafb_set_par,
1665 .fb_setcolreg = rivafb_setcolreg,
1666 .fb_pan_display = rivafb_pan_display,
1667 .fb_blank = rivafb_blank,
1668 .fb_fillrect = rivafb_fillrect,
1669 .fb_copyarea = rivafb_copyarea,
1670 .fb_imageblit = rivafb_imageblit,
1671 .fb_cursor = rivafb_cursor,
1672 .fb_sync = rivafb_sync,
1675 static int __devinit riva_set_fbinfo(struct fb_info *info)
1677 unsigned int cmap_len;
1679 info->flags = FBINFO_DEFAULT
1680 | FBINFO_HWACCEL_XPAN
1681 | FBINFO_HWACCEL_YPAN
1682 | FBINFO_HWACCEL_COPYAREA
1683 | FBINFO_HWACCEL_FILLRECT
1684 | FBINFO_HWACCEL_IMAGEBLIT
1685 | FBINFO_MISC_MODESWITCHLATE;
1686 info->var = rivafb_default_var;
1687 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1688 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1689 info->pseudo_palette = pseudo_palette;
1691 cmap_len = riva_get_cmap_len(&info->var);
1692 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1694 info->pixmap.size = 64 * 1024;
1695 info->pixmap.buf_align = 4;
1696 info->pixmap.scan_align = 4;
1697 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1698 info->var.yres_virtual = -1;
1699 return (rivafb_check_var(&info->var, info));
1702 #ifdef CONFIG_PPC_OF
1703 static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1705 struct riva_par *par = (struct riva_par *) info->par;
1706 struct device_node *dp;
1707 unsigned char *pedid = NULL;
1708 unsigned char *disptype = NULL;
1709 static char *propnames[] = {
1710 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1713 dp = pci_device_to_OF_node(pd);
1714 for (; dp != NULL; dp = dp->child) {
1715 disptype = (unsigned char *)get_property(dp, "display-type", NULL);
1716 if (disptype == NULL)
1718 if (strncmp(disptype, "LCD", 3) != 0)
1720 for (i = 0; propnames[i] != NULL; ++i) {
1721 pedid = (unsigned char *)
1722 get_property(dp, propnames[i], NULL);
1723 if (pedid != NULL) {
1731 #endif /* CONFIG_PPC_OF */
1733 static void riva_update_default_var(struct fb_var_screeninfo *var, struct fb_info *info)
1735 struct fb_monspecs *specs = &info->monspecs;
1736 struct fb_videomode modedb;
1738 /* respect mode options */
1740 fb_find_mode(var, info, mode_option,
1741 specs->modedb, specs->modedb_len,
1743 } else if (specs->modedb != NULL) {
1744 /* get preferred timing */
1745 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1748 for (i = 0; i < specs->modedb_len; i++) {
1749 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1750 modedb = specs->modedb[i];
1755 /* otherwise, get first mode in database */
1756 modedb = specs->modedb[0];
1758 var->bits_per_pixel = 8;
1759 riva_update_var(var, &modedb);
1761 var->accel_flags |= FB_ACCELF_TEXT;
1765 static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1767 #ifdef CONFIG_PPC_OF
1768 if (!riva_get_EDID_OF(info, pdev))
1769 printk("rivafb: could not retrieve EDID from OF\n");
1771 /* XXX use other methods later */
1772 #ifdef CONFIG_FB_RIVA_I2C
1773 struct riva_par *par = (struct riva_par *) info->par;
1776 riva_create_i2c_busses(par);
1777 for (i = par->bus; i >= 1; i--) {
1778 riva_probe_i2c_connector(par, i, &par->EDID);
1780 printk("rivafb: Found EDID Block from BUS %i\n", i);
1784 riva_delete_i2c_busses(par);
1790 static void riva_get_edidinfo(struct fb_info *info)
1792 struct fb_var_screeninfo *var = &rivafb_default_var;
1793 struct riva_par *par = (struct riva_par *) info->par;
1795 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1796 riva_update_default_var(var, info);
1798 /* if user specified flatpanel, we respect that */
1799 if (info->monspecs.input & FB_DISP_DDI)
1803 /* ------------------------------------------------------------------------- *
1807 * ------------------------------------------------------------------------- */
1809 static int __devinit rivafb_probe(struct pci_dev *pd,
1810 const struct pci_device_id *ent)
1812 struct riva_chip_info *rci = &riva_chip_info[ent->driver_data];
1813 struct riva_par *default_par;
1814 struct fb_info *info;
1817 assert(rci != NULL);
1819 info = kmalloc(sizeof(struct fb_info), GFP_KERNEL);
1823 default_par = kmalloc(sizeof(struct riva_par), GFP_KERNEL);
1827 memset(info, 0, sizeof(struct fb_info));
1828 memset(default_par, 0, sizeof(struct riva_par));
1829 default_par->pdev = pd;
1831 info->pixmap.addr = kmalloc(64 * 1024, GFP_KERNEL);
1832 if (info->pixmap.addr == NULL)
1833 goto err_out_kfree1;
1834 memset(info->pixmap.addr, 0, 64 * 1024);
1836 if (pci_enable_device(pd)) {
1837 printk(KERN_ERR PFX "cannot enable PCI device\n");
1838 goto err_out_enable;
1841 if (pci_request_regions(pd, "rivafb")) {
1842 printk(KERN_ERR PFX "cannot request PCI regions\n");
1843 goto err_out_request;
1846 strcat(rivafb_fix.id, rci->name);
1847 default_par->riva.Architecture = rci->arch_rev;
1849 default_par->Chipset = (pd->vendor << 16) | pd->device;
1850 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1852 default_par->FlatPanel = flatpanel;
1854 printk(KERN_INFO PFX "flatpanel support enabled\n");
1855 default_par->forceCRTC = forceCRTC;
1857 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1858 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1861 /* enable IO and mem if not already done */
1864 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1865 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1866 pci_write_config_word(pd, PCI_COMMAND, cmd);
1869 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1870 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1872 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1873 rivafb_fix.mmio_len);
1874 if (!default_par->ctrl_base) {
1875 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1876 goto err_out_free_base0;
1879 info->par = default_par;
1881 switch (default_par->riva.Architecture) {
1883 /* Riva128's PRAMIN is in the "framebuffer" space
1884 * Since these cards were never made with more than 8 megabytes
1885 * we can safely allocate this separately.
1887 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1888 if (!default_par->riva.PRAMIN) {
1889 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1890 goto err_out_free_nv3_pramin;
1892 rivafb_fix.accel = FB_ACCEL_NV3;
1893 default_par->bus = 1;
1898 default_par->riva.PCRTC0 = (unsigned *)(default_par->ctrl_base + 0x00600000);
1899 default_par->riva.PRAMIN = (unsigned *)(default_par->ctrl_base + 0x00710000);
1900 rivafb_fix.accel = FB_ACCEL_NV4;
1901 default_par->bus = 2;
1905 riva_common_setup(default_par);
1907 if (default_par->riva.Architecture == NV_ARCH_03) {
1908 default_par->riva.PCRTC = default_par->riva.PCRTC0 = default_par->riva.PGRAPH;
1911 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
1912 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
1914 info->screen_base = ioremap(rivafb_fix.smem_start,
1915 rivafb_fix.smem_len);
1916 if (!info->screen_base) {
1917 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1918 goto err_out_free_base1;
1923 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
1924 rivafb_fix.smem_len,
1925 MTRR_TYPE_WRCOMB, 1);
1926 if (default_par->mtrr.vram < 0) {
1927 printk(KERN_ERR PFX "unable to setup MTRR\n");
1929 default_par->mtrr.vram_valid = 1;
1930 /* let there be speed */
1931 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
1934 #endif /* CONFIG_MTRR */
1936 info->fbops = &riva_fb_ops;
1937 info->fix = rivafb_fix;
1938 riva_get_EDID(info, pd);
1939 riva_get_edidinfo(info);
1941 if (riva_set_fbinfo(info) < 0) {
1942 printk(KERN_ERR PFX "error setting initial video mode\n");
1943 goto err_out_iounmap_fb;
1946 if (register_framebuffer(info) < 0) {
1948 "error registering riva framebuffer\n");
1949 goto err_out_iounmap_fb;
1952 pci_set_drvdata(pd, info);
1954 printk(KERN_INFO PFX
1955 "PCI nVidia NV%x framebuffer ver %s (%s, %dMB @ 0x%lX)\n",
1956 default_par->riva.Architecture,
1959 info->fix.smem_len / (1024 * 1024),
1960 info->fix.smem_start);
1964 iounmap(info->screen_base);
1966 if (default_par->riva.Architecture == NV_ARCH_03)
1967 iounmap((caddr_t)default_par->riva.PRAMIN);
1968 err_out_free_nv3_pramin:
1969 iounmap(default_par->ctrl_base);
1971 pci_release_regions(pd);
1973 pci_disable_device(pd);
1975 kfree(info->pixmap.addr);
1984 static void __exit rivafb_remove(struct pci_dev *pd)
1986 struct fb_info *info = pci_get_drvdata(pd);
1987 struct riva_par *par = (struct riva_par *) info->par;
1992 unregister_framebuffer(info);
1994 if (par->mtrr.vram_valid)
1995 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1996 info->fix.smem_len);
1997 #endif /* CONFIG_MTRR */
1999 iounmap(par->ctrl_base);
2000 iounmap(info->screen_base);
2001 if (par->riva.Architecture == NV_ARCH_03)
2002 iounmap((caddr_t)par->riva.PRAMIN);
2003 pci_release_regions(pd);
2004 pci_disable_device(pd);
2005 fb_destroy_modedb(info->monspecs.modedb);
2006 kfree(info->pixmap.addr);
2009 pci_set_drvdata(pd, NULL);
2012 /* ------------------------------------------------------------------------- *
2016 * ------------------------------------------------------------------------- */
2019 int __init rivafb_setup(char *options)
2023 if (!options || !*options)
2026 while ((this_opt = strsep(&options, ",")) != NULL) {
2027 if (!strncmp(this_opt, "forceCRTC", 9)) {
2031 if (!*p || !*(++p)) continue;
2032 forceCRTC = *p - '0';
2033 if (forceCRTC < 0 || forceCRTC > 1)
2035 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2038 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2041 } else if (!strncmp(this_opt, "strictmode", 10)) {
2044 mode_option = this_opt;
2048 #endif /* !MODULE */
2050 static struct pci_driver rivafb_driver = {
2052 .id_table = rivafb_pci_tbl,
2053 .probe = rivafb_probe,
2054 .remove = __exit_p(rivafb_remove),
2059 /* ------------------------------------------------------------------------- *
2063 * ------------------------------------------------------------------------- */
2065 int __init rivafb_init(void)
2067 if (pci_register_driver(&rivafb_driver) > 0)
2069 pci_unregister_driver(&rivafb_driver);
2075 static void __exit rivafb_exit(void)
2077 pci_unregister_driver(&rivafb_driver);
2080 module_init(rivafb_init);
2081 module_exit(rivafb_exit);
2083 MODULE_PARM(flatpanel, "i");
2084 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2085 MODULE_PARM(forceCRTC, "i");
2086 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2089 MODULE_PARM(nomtrr, "i");
2090 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2091 MODULE_PARM(strictmode, "i");
2092 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2096 MODULE_AUTHOR("Ani Joshi, maintainer");
2097 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2098 MODULE_LICENSE("GPL");