2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
6 * Copyright 1999-2000 Jeff Garzik
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
17 * Paul Richards: Bug fixes, updates
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
32 #include <linux/config.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/string.h>
38 #include <linux/tty.h>
39 #include <linux/slab.h>
40 #include <linux/delay.h>
42 #include <linux/init.h>
43 #include <linux/pci.h>
49 #include <asm/pci-bridge.h>
51 #ifdef CONFIG_PMAC_BACKLIGHT
52 #include <asm/backlight.h>
58 #ifndef CONFIG_PCI /* sanity check */
59 #error This driver requires PCI support.
62 /* version number of this driver */
63 #define RIVAFB_VERSION "0.9.5b"
65 /* ------------------------------------------------------------------------- *
67 * various helpful macros and constants
69 * ------------------------------------------------------------------------- */
70 #ifdef CONFIG_FB_RIVA_DEBUG
71 #define NVTRACE printk
73 #define NVTRACE if(0) printk
76 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
77 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
79 #ifdef CONFIG_FB_RIVA_DEBUG
80 #define assert(expr) \
82 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
83 #expr,__FILE__,__FUNCTION__,__LINE__); \
90 #define PFX "rivafb: "
92 /* macro that allows you to set overflow bits */
93 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
94 #define SetBit(n) (1<<(n))
95 #define Set8Bits(value) ((value)&0xff)
97 /* HW cursor parameters */
100 /* ------------------------------------------------------------------------- *
104 * ------------------------------------------------------------------------- */
106 static int rivafb_blank(int blank, struct fb_info *info);
108 /* ------------------------------------------------------------------------- *
110 * card identification
112 * ------------------------------------------------------------------------- */
114 static struct pci_device_id rivafb_pci_tbl[] = {
115 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
157 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
195 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
197 { 0, } /* terminate list */
199 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
201 /* ------------------------------------------------------------------------- *
205 * ------------------------------------------------------------------------- */
207 /* command line data, set in rivafb_setup() */
208 static int flatpanel __initdata = -1; /* Autodetect later */
209 static int forceCRTC __initdata = -1;
210 static int noaccel __initdata = 0;
212 static int nomtrr __initdata = 0;
215 static char *mode_option __initdata = NULL;
216 static int strictmode = 0;
218 static struct fb_fix_screeninfo __initdata rivafb_fix = {
219 .type = FB_TYPE_PACKED_PIXELS,
224 static struct fb_var_screeninfo __initdata rivafb_default_var = {
234 .activate = FB_ACTIVATE_NOW,
244 .vmode = FB_VMODE_NONINTERLACED
248 static const struct riva_regs reg_template = {
249 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
250 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
251 0x41, 0x01, 0x0F, 0x00, 0x00},
252 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
253 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
254 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
255 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
256 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
257 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
262 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
264 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
271 #ifdef CONFIG_PMAC_BACKLIGHT
273 static int riva_backlight_levels[] = {
292 static int riva_set_backlight_enable(int on, int level, void *data);
293 static int riva_set_backlight_level(int level, void *data);
294 static struct backlight_controller riva_backlight_controller = {
295 riva_set_backlight_enable,
296 riva_set_backlight_level
298 #endif /* CONFIG_PMAC_BACKLIGHT */
300 /* ------------------------------------------------------------------------- *
304 * ------------------------------------------------------------------------- */
306 static inline void CRTCout(struct riva_par *par, unsigned char index,
309 VGA_WR08(par->riva.PCIO, 0x3d4, index);
310 VGA_WR08(par->riva.PCIO, 0x3d5, val);
313 static inline unsigned char CRTCin(struct riva_par *par,
316 VGA_WR08(par->riva.PCIO, 0x3d4, index);
317 return (VGA_RD08(par->riva.PCIO, 0x3d5));
320 static inline void GRAout(struct riva_par *par, unsigned char index,
323 VGA_WR08(par->riva.PVIO, 0x3ce, index);
324 VGA_WR08(par->riva.PVIO, 0x3cf, val);
327 static inline unsigned char GRAin(struct riva_par *par,
330 VGA_WR08(par->riva.PVIO, 0x3ce, index);
331 return (VGA_RD08(par->riva.PVIO, 0x3cf));
334 static inline void SEQout(struct riva_par *par, unsigned char index,
337 VGA_WR08(par->riva.PVIO, 0x3c4, index);
338 VGA_WR08(par->riva.PVIO, 0x3c5, val);
341 static inline unsigned char SEQin(struct riva_par *par,
344 VGA_WR08(par->riva.PVIO, 0x3c4, index);
345 return (VGA_RD08(par->riva.PVIO, 0x3c5));
348 static inline void ATTRout(struct riva_par *par, unsigned char index,
351 VGA_WR08(par->riva.PCIO, 0x3c0, index);
352 VGA_WR08(par->riva.PCIO, 0x3c0, val);
355 static inline unsigned char ATTRin(struct riva_par *par,
358 VGA_WR08(par->riva.PCIO, 0x3c0, index);
359 return (VGA_RD08(par->riva.PCIO, 0x3c1));
362 static inline void MISCout(struct riva_par *par, unsigned char val)
364 VGA_WR08(par->riva.PVIO, 0x3c2, val);
367 static inline unsigned char MISCin(struct riva_par *par)
369 return (VGA_RD08(par->riva.PVIO, 0x3cc));
372 static u8 byte_rev[256] = {
373 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
374 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
375 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
376 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
377 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
378 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
379 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
380 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
381 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
382 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
383 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
384 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
385 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
386 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
387 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
388 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
389 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
390 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
391 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
392 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
393 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
394 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
395 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
396 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
397 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
398 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
399 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
400 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
401 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
402 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
403 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
404 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
407 static inline void reverse_order(u32 *l)
410 *a = byte_rev[*a], a++;
411 *a = byte_rev[*a], a++;
412 *a = byte_rev[*a], a++;
416 /* ------------------------------------------------------------------------- *
420 * ------------------------------------------------------------------------- */
423 * rivafb_load_cursor_image - load cursor image to hardware
424 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
425 * @par: pointer to private data
426 * @w: width of cursor image in pixels
427 * @h: height of cursor image in scanlines
428 * @bg: background color (ARGB1555) - alpha bit determines opacity
429 * @fg: foreground color (ARGB1555)
432 * Loads cursor image based on a monochrome source and mask bitmap. The
433 * image bits determines the color of the pixel, 0 for background, 1 for
434 * foreground. Only the affected region (as determined by @w and @h
435 * parameters) will be updated.
440 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
441 u16 bg, u16 fg, u32 w, u32 h)
445 u32 *data = (u32 *)data8;
446 bg = le16_to_cpu(bg);
447 fg = le16_to_cpu(fg);
451 for (i = 0; i < h; i++) {
455 for (j = 0; j < w/2; j++) {
457 #if defined (__BIG_ENDIAN)
458 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
460 tmp |= (b & (1 << 31)) ? fg : bg;
463 tmp = (b & 1) ? fg : bg;
465 tmp |= (b & 1) ? fg << 16 : bg << 16;
468 writel(tmp, &par->riva.CURSOR[k++]);
470 k += (MAX_CURS - w)/2;
474 /* ------------------------------------------------------------------------- *
476 * general utility functions
478 * ------------------------------------------------------------------------- */
481 * riva_wclut - set CLUT entry
482 * @chip: pointer to RIVA_HW_INST object
483 * @regnum: register number
484 * @red: red component
485 * @green: green component
486 * @blue: blue component
489 * Sets color register @regnum.
494 static void riva_wclut(RIVA_HW_INST *chip,
495 unsigned char regnum, unsigned char red,
496 unsigned char green, unsigned char blue)
498 VGA_WR08(chip->PDIO, 0x3c8, regnum);
499 VGA_WR08(chip->PDIO, 0x3c9, red);
500 VGA_WR08(chip->PDIO, 0x3c9, green);
501 VGA_WR08(chip->PDIO, 0x3c9, blue);
505 * riva_rclut - read fromCLUT register
506 * @chip: pointer to RIVA_HW_INST object
507 * @regnum: register number
508 * @red: red component
509 * @green: green component
510 * @blue: blue component
513 * Reads red, green, and blue from color register @regnum.
518 static void riva_rclut(RIVA_HW_INST *chip,
519 unsigned char regnum, unsigned char *red,
520 unsigned char *green, unsigned char *blue)
523 VGA_WR08(chip->PDIO, 0x3c7, regnum);
524 *red = VGA_RD08(chip->PDIO, 0x3c9);
525 *green = VGA_RD08(chip->PDIO, 0x3c9);
526 *blue = VGA_RD08(chip->PDIO, 0x3c9);
530 * riva_save_state - saves current chip state
531 * @par: pointer to riva_par object containing info for current riva board
532 * @regs: pointer to riva_regs object
535 * Saves current chip state to @regs.
541 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
546 par->riva.LockUnlock(&par->riva, 0);
548 par->riva.UnloadStateExt(&par->riva, ®s->ext);
550 regs->misc_output = MISCin(par);
552 for (i = 0; i < NUM_CRT_REGS; i++)
553 regs->crtc[i] = CRTCin(par, i);
555 for (i = 0; i < NUM_ATC_REGS; i++)
556 regs->attr[i] = ATTRin(par, i);
558 for (i = 0; i < NUM_GRC_REGS; i++)
559 regs->gra[i] = GRAin(par, i);
561 for (i = 0; i < NUM_SEQ_REGS; i++)
562 regs->seq[i] = SEQin(par, i);
567 * riva_load_state - loads current chip state
568 * @par: pointer to riva_par object containing info for current riva board
569 * @regs: pointer to riva_regs object
572 * Loads chip state from @regs.
575 * riva_load_video_mode()
580 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
582 RIVA_HW_STATE *state = ®s->ext;
586 CRTCout(par, 0x11, 0x00);
588 par->riva.LockUnlock(&par->riva, 0);
590 par->riva.LoadStateExt(&par->riva, state);
592 MISCout(par, regs->misc_output);
594 for (i = 0; i < NUM_CRT_REGS; i++) {
600 CRTCout(par, i, regs->crtc[i]);
604 for (i = 0; i < NUM_ATC_REGS; i++)
605 ATTRout(par, i, regs->attr[i]);
607 for (i = 0; i < NUM_GRC_REGS; i++)
608 GRAout(par, i, regs->gra[i]);
610 for (i = 0; i < NUM_SEQ_REGS; i++)
611 SEQout(par, i, regs->seq[i]);
616 * riva_load_video_mode - calculate timings
617 * @info: pointer to fb_info object containing info for current riva board
620 * Calculate some timings and then send em off to riva_load_state().
625 static void riva_load_video_mode(struct fb_info *info)
627 int bpp, width, hDisplaySize, hDisplay, hStart,
628 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
629 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
630 struct riva_par *par = (struct riva_par *) info->par;
631 struct riva_regs newmode;
634 /* time to calculate */
635 rivafb_blank(1, info);
637 bpp = info->var.bits_per_pixel;
638 if (bpp == 16 && info->var.green.length == 5)
640 width = info->var.xres_virtual;
641 hDisplaySize = info->var.xres;
642 hDisplay = (hDisplaySize / 8) - 1;
643 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
644 hEnd = (hDisplaySize + info->var.right_margin +
645 info->var.hsync_len) / 8 - 1;
646 hTotal = (hDisplaySize + info->var.right_margin +
647 info->var.hsync_len + info->var.left_margin) / 8 - 5;
648 hBlankStart = hDisplay;
649 hBlankEnd = hTotal + 4;
651 height = info->var.yres_virtual;
652 vDisplay = info->var.yres - 1;
653 vStart = info->var.yres + info->var.lower_margin - 1;
654 vEnd = info->var.yres + info->var.lower_margin +
655 info->var.vsync_len - 1;
656 vTotal = info->var.yres + info->var.lower_margin +
657 info->var.vsync_len + info->var.upper_margin + 2;
658 vBlankStart = vDisplay;
659 vBlankEnd = vTotal + 1;
660 dotClock = 1000000000 / info->var.pixclock;
662 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
664 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
667 if (par->FlatPanel) {
670 vBlankStart = vStart;
673 hBlankEnd = hTotal + 4;
676 newmode.crtc[0x0] = Set8Bits (hTotal);
677 newmode.crtc[0x1] = Set8Bits (hDisplay);
678 newmode.crtc[0x2] = Set8Bits (hBlankStart);
679 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
680 newmode.crtc[0x4] = Set8Bits (hStart);
681 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
682 | SetBitField (hEnd, 4: 0, 4:0);
683 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
684 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
685 | SetBitField (vDisplay, 8: 8, 1:1)
686 | SetBitField (vStart, 8: 8, 2:2)
687 | SetBitField (vBlankStart, 8: 8, 3:3)
689 | SetBitField (vTotal, 9: 9, 5:5)
690 | SetBitField (vDisplay, 9: 9, 6:6)
691 | SetBitField (vStart, 9: 9, 7:7);
692 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
694 newmode.crtc[0x10] = Set8Bits (vStart);
695 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
697 newmode.crtc[0x12] = Set8Bits (vDisplay);
698 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
699 newmode.crtc[0x15] = Set8Bits (vBlankStart);
700 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
702 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
703 | SetBitField(vBlankStart,10:10,3:3)
704 | SetBitField(vStart,10:10,2:2)
705 | SetBitField(vDisplay,10:10,1:1)
706 | SetBitField(vTotal,10:10,0:0);
707 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
708 | SetBitField(hDisplay,8:8,1:1)
709 | SetBitField(hBlankStart,8:8,2:2)
710 | SetBitField(hStart,8:8,3:3);
711 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
712 | SetBitField(vDisplay,11:11,2:2)
713 | SetBitField(vStart,11:11,4:4)
714 | SetBitField(vBlankStart,11:11,6:6);
716 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
717 int tmp = (hTotal >> 1) & ~1;
718 newmode.ext.interlace = Set8Bits(tmp);
719 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
721 newmode.ext.interlace = 0xff; /* interlace off */
723 if (par->riva.Architecture >= NV_ARCH_10)
724 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
726 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
727 newmode.misc_output &= ~0x40;
729 newmode.misc_output |= 0x40;
730 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
731 newmode.misc_output &= ~0x80;
733 newmode.misc_output |= 0x80;
735 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
736 hDisplaySize, height, dotClock);
738 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
740 if (par->FlatPanel == 1) {
741 newmode.ext.pixel |= (1 << 7);
742 newmode.ext.scale |= (1 << 8);
744 if (par->SecondCRTC) {
745 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
747 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
749 newmode.ext.crtcOwner = 3;
750 newmode.ext.pllsel |= 0x20000800;
751 newmode.ext.vpll2 = newmode.ext.vpll;
752 } else if (par->riva.twoHeads) {
753 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
755 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
757 newmode.ext.crtcOwner = 0;
758 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
760 if (par->FlatPanel == 1) {
761 newmode.ext.pixel |= (1 << 7);
762 newmode.ext.scale |= (1 << 8);
764 newmode.ext.cursorConfig = 0x02000100;
765 par->current_state = newmode;
766 riva_load_state(par, &par->current_state);
767 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
768 rivafb_blank(0, info);
772 static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
775 var->xres = var->xres_virtual = modedb->xres;
776 var->yres = modedb->yres;
777 if (var->yres_virtual < var->yres)
778 var->yres_virtual = var->yres;
779 var->xoffset = var->yoffset = 0;
780 var->pixclock = modedb->pixclock;
781 var->left_margin = modedb->left_margin;
782 var->right_margin = modedb->right_margin;
783 var->upper_margin = modedb->upper_margin;
784 var->lower_margin = modedb->lower_margin;
785 var->hsync_len = modedb->hsync_len;
786 var->vsync_len = modedb->vsync_len;
787 var->sync = modedb->sync;
788 var->vmode = modedb->vmode;
793 * rivafb_do_maximize -
794 * @info: pointer to fb_info object containing info for current riva board
803 * -EINVAL on failure, 0 on success
809 static int rivafb_do_maximize(struct fb_info *info,
810 struct fb_var_screeninfo *var,
826 /* use highest possible virtual resolution */
827 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
828 printk(KERN_WARNING PFX
829 "using maximum available virtual resolution\n");
830 for (i = 0; modes[i].xres != -1; i++) {
831 if (modes[i].xres * nom / den * modes[i].yres <
835 if (modes[i].xres == -1) {
837 "could not find a virtual resolution that fits into video memory!!\n");
838 NVTRACE("EXIT - EINVAL error\n");
841 var->xres_virtual = modes[i].xres;
842 var->yres_virtual = modes[i].yres;
845 "virtual resolution set to maximum of %dx%d\n",
846 var->xres_virtual, var->yres_virtual);
847 } else if (var->xres_virtual == -1) {
848 var->xres_virtual = (info->fix.smem_len * den /
849 (nom * var->yres_virtual)) & ~15;
850 printk(KERN_WARNING PFX
851 "setting virtual X resolution to %d\n", var->xres_virtual);
852 } else if (var->yres_virtual == -1) {
853 var->xres_virtual = (var->xres_virtual + 15) & ~15;
854 var->yres_virtual = info->fix.smem_len * den /
855 (nom * var->xres_virtual);
856 printk(KERN_WARNING PFX
857 "setting virtual Y resolution to %d\n", var->yres_virtual);
859 var->xres_virtual = (var->xres_virtual + 15) & ~15;
860 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
862 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
863 var->xres, var->yres, var->bits_per_pixel);
864 NVTRACE("EXIT - EINVAL error\n");
869 if (var->xres_virtual * nom / den >= 8192) {
870 printk(KERN_WARNING PFX
871 "virtual X resolution (%d) is too high, lowering to %d\n",
872 var->xres_virtual, 8192 * den / nom - 16);
873 var->xres_virtual = 8192 * den / nom - 16;
876 if (var->xres_virtual < var->xres) {
878 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
882 if (var->yres_virtual < var->yres) {
884 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
887 if (var->yres_virtual > 0x7fff/nom)
888 var->yres_virtual = 0x7fff/nom;
889 if (var->xres_virtual > 0x7fff/nom)
890 var->xres_virtual = 0x7fff/nom;
896 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
898 RIVA_FIFO_FREE(par->riva, Patt, 4);
899 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
900 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
901 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
902 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
905 /* acceleration routines */
906 inline void wait_for_idle(struct riva_par *par)
908 while (par->riva.Busy(&par->riva));
912 * Set ROP. Translate X rop into ROP3. Internal routine.
915 riva_set_rop_solid(struct riva_par *par, int rop)
917 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
918 RIVA_FIFO_FREE(par->riva, Rop, 1);
919 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
923 void riva_setup_accel(struct fb_info *info)
925 struct riva_par *par = (struct riva_par *) info->par;
927 RIVA_FIFO_FREE(par->riva, Clip, 2);
928 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
929 NV_WR32(&par->riva.Clip->WidthHeight, 0,
930 (info->var.xres_virtual & 0xffff) |
931 (info->var.yres_virtual << 16));
932 riva_set_rop_solid(par, 0xcc);
937 * riva_get_cmap_len - query current color map length
938 * @var: standard kernel fb changeable data
941 * Get current color map length.
944 * Length of color map
949 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
951 int rc = 256; /* reasonable default */
953 switch (var->green.length) {
955 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
958 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
961 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
964 /* should not occur */
970 /* ------------------------------------------------------------------------- *
972 * Backlight operations
974 * ------------------------------------------------------------------------- */
976 #ifdef CONFIG_PMAC_BACKLIGHT
977 static int riva_set_backlight_enable(int on, int level, void *data)
979 struct riva_par *par = (struct riva_par *)data;
980 U032 tmp_pcrt, tmp_pmc;
982 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
983 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
984 if(on && (level > BACKLIGHT_OFF)) {
986 tmp_pmc |= (1 << 31); // backlight bit
987 tmp_pmc |= riva_backlight_levels[level-1] << 16; // level
989 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
990 par->riva.PMC[0x10F0/4] = tmp_pmc;
994 static int riva_set_backlight_level(int level, void *data)
996 return riva_set_backlight_enable(1, level, data);
998 #endif /* CONFIG_PMAC_BACKLIGHT */
1000 /* ------------------------------------------------------------------------- *
1002 * framebuffer operations
1004 * ------------------------------------------------------------------------- */
1006 static int rivafb_open(struct fb_info *info, int user)
1008 struct riva_par *par = (struct riva_par *) info->par;
1009 int cnt = atomic_read(&par->ref_count);
1014 memset(&par->state, 0, sizeof(struct vgastate));
1015 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1016 /* save the DAC for Riva128 */
1017 if (par->riva.Architecture == NV_ARCH_03)
1018 par->state.flags |= VGA_SAVE_CMAP;
1019 save_vga(&par->state);
1021 /* vgaHWunlock() + riva unlock (0x7F) */
1022 CRTCout(par, 0x11, 0xFF);
1023 par->riva.LockUnlock(&par->riva, 0);
1025 riva_save_state(par, &par->initial_state);
1027 atomic_inc(&par->ref_count);
1032 static int rivafb_release(struct fb_info *info, int user)
1034 struct riva_par *par = (struct riva_par *) info->par;
1035 int cnt = atomic_read(&par->ref_count);
1041 par->riva.LockUnlock(&par->riva, 0);
1042 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1043 riva_load_state(par, &par->initial_state);
1045 restore_vga(&par->state);
1047 par->riva.LockUnlock(&par->riva, 1);
1049 atomic_dec(&par->ref_count);
1054 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1056 struct fb_videomode *mode;
1057 struct riva_par *par = (struct riva_par *) info->par;
1058 int nom, den; /* translating from pixels->bytes */
1062 switch (var->bits_per_pixel) {
1064 var->red.offset = var->green.offset = var->blue.offset = 0;
1065 var->red.length = var->green.length = var->blue.length = 8;
1066 var->bits_per_pixel = 8;
1070 var->green.length = 5;
1073 var->bits_per_pixel = 16;
1074 /* The Riva128 supports RGB555 only */
1075 if (par->riva.Architecture == NV_ARCH_03)
1076 var->green.length = 5;
1077 if (var->green.length == 5) {
1078 /* 0rrrrrgg gggbbbbb */
1079 var->red.offset = 10;
1080 var->green.offset = 5;
1081 var->blue.offset = 0;
1082 var->red.length = 5;
1083 var->green.length = 5;
1084 var->blue.length = 5;
1086 /* rrrrrggg gggbbbbb */
1087 var->red.offset = 11;
1088 var->green.offset = 5;
1089 var->blue.offset = 0;
1090 var->red.length = 5;
1091 var->green.length = 6;
1092 var->blue.length = 5;
1098 var->red.length = var->green.length = var->blue.length = 8;
1099 var->bits_per_pixel = 32;
1100 var->red.offset = 16;
1101 var->green.offset = 8;
1102 var->blue.offset = 0;
1108 "mode %dx%dx%d rejected...color depth not supported.\n",
1109 var->xres, var->yres, var->bits_per_pixel);
1110 NVTRACE("EXIT, returning -EINVAL\n");
1115 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1116 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1120 /* calculate modeline if supported by monitor */
1121 if (!mode_valid && info->monspecs.gtf) {
1122 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1127 mode = fb_find_best_mode(var, &info->modelist);
1129 riva_update_var(var, mode);
1134 if (!mode_valid && info->monspecs.modedb_len)
1137 if (var->xres_virtual < var->xres)
1138 var->xres_virtual = var->xres;
1139 if (var->yres_virtual <= var->yres)
1140 var->yres_virtual = -1;
1141 if (rivafb_do_maximize(info, var, nom, den) < 0)
1144 if (var->xoffset < 0)
1146 if (var->yoffset < 0)
1149 /* truncate xoffset and yoffset to maximum if too high */
1150 if (var->xoffset > var->xres_virtual - var->xres)
1151 var->xoffset = var->xres_virtual - var->xres - 1;
1153 if (var->yoffset > var->yres_virtual - var->yres)
1154 var->yoffset = var->yres_virtual - var->yres - 1;
1156 var->red.msb_right =
1157 var->green.msb_right =
1158 var->blue.msb_right =
1159 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1164 static int rivafb_set_par(struct fb_info *info)
1166 struct riva_par *par = (struct riva_par *) info->par;
1169 /* vgaHWunlock() + riva unlock (0x7F) */
1170 CRTCout(par, 0x11, 0xFF);
1171 par->riva.LockUnlock(&par->riva, 0);
1172 riva_load_video_mode(info);
1173 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1174 riva_setup_accel(info);
1176 par->cursor_reset = 1;
1177 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1178 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1179 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1181 if (info->flags & FBINFO_HWACCEL_DISABLED)
1182 info->pixmap.scan_align = 1;
1184 info->pixmap.scan_align = 4;
1190 * rivafb_pan_display
1191 * @var: standard kernel fb changeable data
1193 * @info: pointer to fb_info object containing info for current riva board
1196 * Pan (or wrap, depending on the `vmode' field) the display using the
1197 * `xoffset' and `yoffset' fields of the `var' structure.
1198 * If the values don't fit, return -EINVAL.
1200 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1202 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1203 struct fb_info *info)
1205 struct riva_par *par = (struct riva_par *)info->par;
1209 if (var->xoffset > (var->xres_virtual - var->xres))
1211 if (var->yoffset > (var->yres_virtual - var->yres))
1214 if (var->vmode & FB_VMODE_YWRAP) {
1215 if (var->yoffset < 0
1216 || var->yoffset >= info->var.yres_virtual
1217 || var->xoffset) return -EINVAL;
1219 if (var->xoffset + info->var.xres > info->var.xres_virtual ||
1220 var->yoffset + info->var.yres > info->var.yres_virtual)
1224 base = var->yoffset * info->fix.line_length + var->xoffset;
1226 par->riva.SetStartAddress(&par->riva, base);
1228 info->var.xoffset = var->xoffset;
1229 info->var.yoffset = var->yoffset;
1231 if (var->vmode & FB_VMODE_YWRAP)
1232 info->var.vmode |= FB_VMODE_YWRAP;
1234 info->var.vmode &= ~FB_VMODE_YWRAP;
1239 static int rivafb_blank(int blank, struct fb_info *info)
1241 struct riva_par *par= (struct riva_par *)info->par;
1242 unsigned char tmp, vesa;
1244 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1245 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1253 case FB_BLANK_UNBLANK:
1254 case FB_BLANK_NORMAL:
1256 case FB_BLANK_VSYNC_SUSPEND:
1259 case FB_BLANK_HSYNC_SUSPEND:
1262 case FB_BLANK_POWERDOWN:
1267 SEQout(par, 0x01, tmp);
1268 CRTCout(par, 0x1a, vesa);
1270 #ifdef CONFIG_PMAC_BACKLIGHT
1271 if ( par->FlatPanel && _machine == _MACH_Pmac) {
1272 set_backlight_enable(!blank);
1283 * @regno: register index
1284 * @red: red component
1285 * @green: green component
1286 * @blue: blue component
1287 * @transp: transparency
1288 * @info: pointer to fb_info object containing info for current riva board
1291 * Set a single color register. The values supplied have a 16 bit
1295 * Return != 0 for invalid regno.
1298 * fbcmap.c:fb_set_cmap()
1300 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1301 unsigned blue, unsigned transp,
1302 struct fb_info *info)
1304 struct riva_par *par = (struct riva_par *)info->par;
1305 RIVA_HW_INST *chip = &par->riva;
1308 if (regno >= riva_get_cmap_len(&info->var))
1311 if (info->var.grayscale) {
1312 /* gray = 0.30*R + 0.59*G + 0.11*B */
1313 red = green = blue =
1314 (red * 77 + green * 151 + blue * 28) >> 8;
1317 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1318 ((u32 *) info->pseudo_palette)[regno] =
1319 (regno << info->var.red.offset) |
1320 (regno << info->var.green.offset) |
1321 (regno << info->var.blue.offset);
1323 * The Riva128 2D engine requires color information in
1324 * TrueColor format even if framebuffer is in DirectColor
1326 if (par->riva.Architecture == NV_ARCH_03) {
1327 switch (info->var.bits_per_pixel) {
1329 par->palette[regno] = ((red & 0xf800) >> 1) |
1330 ((green & 0xf800) >> 6) |
1331 ((blue & 0xf800) >> 11);
1334 par->palette[regno] = ((red & 0xff00) << 8) |
1335 ((green & 0xff00)) |
1336 ((blue & 0xff00) >> 8);
1342 switch (info->var.bits_per_pixel) {
1344 /* "transparent" stuff is completely ignored. */
1345 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1348 if (info->var.green.length == 5) {
1349 for (i = 0; i < 8; i++) {
1350 riva_wclut(chip, regno*8+i, red >> 8,
1351 green >> 8, blue >> 8);
1357 for (i = 0; i < 8; i++) {
1358 riva_wclut(chip, regno*8+i,
1359 red >> 8, green >> 8,
1363 riva_rclut(chip, regno*4, &r, &g, &b);
1364 for (i = 0; i < 4; i++)
1365 riva_wclut(chip, regno*4+i, r,
1370 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1380 * rivafb_fillrect - hardware accelerated color fill function
1381 * @info: pointer to fb_info structure
1382 * @rect: pointer to fb_fillrect structure
1385 * This function fills up a region of framebuffer memory with a solid
1386 * color with a choice of two different ROP's, copy or invert.
1391 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1393 struct riva_par *par = (struct riva_par *) info->par;
1394 u_int color, rop = 0;
1396 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1397 cfb_fillrect(info, rect);
1401 if (info->var.bits_per_pixel == 8)
1402 color = rect->color;
1404 if (par->riva.Architecture != NV_ARCH_03)
1405 color = ((u32 *)info->pseudo_palette)[rect->color];
1407 color = par->palette[rect->color];
1410 switch (rect->rop) {
1420 riva_set_rop_solid(par, rop);
1422 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1423 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1425 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1426 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1427 (rect->dx << 16) | rect->dy);
1429 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1430 (rect->width << 16) | rect->height);
1432 riva_set_rop_solid(par, 0xcc);
1437 * rivafb_copyarea - hardware accelerated blit function
1438 * @info: pointer to fb_info structure
1439 * @region: pointer to fb_copyarea structure
1442 * This copies an area of pixels from one location to another
1447 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1449 struct riva_par *par = (struct riva_par *) info->par;
1451 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1452 cfb_copyarea(info, region);
1456 RIVA_FIFO_FREE(par->riva, Blt, 3);
1457 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1458 (region->sy << 16) | region->sx);
1459 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1460 (region->dy << 16) | region->dx);
1462 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1463 (region->height << 16) | region->width);
1467 static inline void convert_bgcolor_16(u32 *col)
1469 *col = ((*col & 0x0000F800) << 8)
1470 | ((*col & 0x00007E0) << 5)
1471 | ((*col & 0x0000001F) << 3)
1477 * rivafb_imageblit: hardware accelerated color expand function
1478 * @info: pointer to fb_info structure
1479 * @image: pointer to fb_image structure
1482 * If the source is a monochrome bitmap, the function fills up a a region
1483 * of framebuffer memory with pixels whose color is determined by the bit
1484 * setting of the bitmap, 1 - foreground, 0 - background.
1486 * If the source is not a monochrome bitmap, color expansion is not done.
1487 * In this case, it is channeled to a software function.
1492 static void rivafb_imageblit(struct fb_info *info,
1493 const struct fb_image *image)
1495 struct riva_par *par = (struct riva_par *) info->par;
1496 u32 fgx = 0, bgx = 0, width, tmp;
1497 u8 *cdat = (u8 *) image->data;
1498 volatile u32 __iomem *d;
1501 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1502 cfb_imageblit(info, image);
1506 switch (info->var.bits_per_pixel) {
1508 fgx = image->fg_color;
1509 bgx = image->bg_color;
1513 if (par->riva.Architecture != NV_ARCH_03) {
1514 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1515 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1517 fgx = par->palette[image->fg_color];
1518 bgx = par->palette[image->bg_color];
1520 if (info->var.green.length == 6)
1521 convert_bgcolor_16(&bgx);
1525 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1526 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1527 (image->dy << 16) | (image->dx & 0xFFFF));
1528 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1529 (((image->dy + image->height) << 16) |
1530 ((image->dx + image->width) & 0xffff)));
1531 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1532 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1533 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1534 (image->height << 16) | ((image->width + 31) & ~31));
1535 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1536 (image->height << 16) | ((image->width + 31) & ~31));
1537 NV_WR32(&par->riva.Bitmap->PointE, 0,
1538 (image->dy << 16) | (image->dx & 0xFFFF));
1540 d = &par->riva.Bitmap->MonochromeData01E;
1542 width = (image->width + 31)/32;
1543 size = width * image->height;
1544 while (size >= 16) {
1545 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1546 for (i = 0; i < 16; i++) {
1547 tmp = *((u32 *)cdat);
1548 cdat = (u8 *)((u32 *)cdat + 1);
1549 reverse_order(&tmp);
1550 NV_WR32(d, i*4, tmp);
1555 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1556 for (i = 0; i < size; i++) {
1557 tmp = *((u32 *) cdat);
1558 cdat = (u8 *)((u32 *)cdat + 1);
1559 reverse_order(&tmp);
1560 NV_WR32(d, i*4, tmp);
1566 * rivafb_cursor - hardware cursor function
1567 * @info: pointer to info structure
1568 * @cursor: pointer to fbcursor structure
1571 * A cursor function that supports displaying a cursor image via hardware.
1572 * Within the kernel, copy and invert rops are supported. If exported
1573 * to user space, only the copy rop will be supported.
1578 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1580 struct riva_par *par = (struct riva_par *) info->par;
1581 u8 data[MAX_CURS * MAX_CURS/8];
1583 int i, set = cursor->set;
1585 if (cursor->image.width > MAX_CURS ||
1586 cursor->image.height > MAX_CURS)
1587 return soft_cursor(info, cursor);
1589 par->riva.ShowHideCursor(&par->riva, 0);
1591 if (par->cursor_reset) {
1592 set = FB_CUR_SETALL;
1593 par->cursor_reset = 0;
1596 if (set & FB_CUR_SETSIZE)
1597 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1599 if (set & FB_CUR_SETPOS) {
1602 yy = cursor->image.dy - info->var.yoffset;
1603 xx = cursor->image.dx - info->var.xoffset;
1607 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1611 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1612 u32 bg_idx = cursor->image.bg_color;
1613 u32 fg_idx = cursor->image.fg_color;
1614 u32 s_pitch = (cursor->image.width+7) >> 3;
1615 u32 d_pitch = MAX_CURS/8;
1616 u8 *dat = (u8 *) cursor->image.data;
1617 u8 *msk = (u8 *) cursor->mask;
1620 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1623 switch (cursor->rop) {
1625 for (i = 0; i < s_pitch * cursor->image.height;
1627 src[i] = dat[i] ^ msk[i];
1631 for (i = 0; i < s_pitch * cursor->image.height;
1633 src[i] = dat[i] & msk[i];
1637 fb_sysmove_buf_aligned(info, &info->pixmap, data,
1638 d_pitch, src, s_pitch,
1639 cursor->image.height);
1641 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1642 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1643 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1646 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1647 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1648 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1651 par->riva.LockUnlock(&par->riva, 0);
1653 rivafb_load_cursor_image(par, data, bg, fg,
1654 cursor->image.width,
1655 cursor->image.height);
1661 par->riva.ShowHideCursor(&par->riva, 1);
1666 static int rivafb_sync(struct fb_info *info)
1668 struct riva_par *par = (struct riva_par *)info->par;
1674 /* ------------------------------------------------------------------------- *
1676 * initialization helper functions
1678 * ------------------------------------------------------------------------- */
1680 /* kernel interface */
1681 static struct fb_ops riva_fb_ops = {
1682 .owner = THIS_MODULE,
1683 .fb_open = rivafb_open,
1684 .fb_release = rivafb_release,
1685 .fb_check_var = rivafb_check_var,
1686 .fb_set_par = rivafb_set_par,
1687 .fb_setcolreg = rivafb_setcolreg,
1688 .fb_pan_display = rivafb_pan_display,
1689 .fb_blank = rivafb_blank,
1690 .fb_fillrect = rivafb_fillrect,
1691 .fb_copyarea = rivafb_copyarea,
1692 .fb_imageblit = rivafb_imageblit,
1693 .fb_cursor = rivafb_cursor,
1694 .fb_sync = rivafb_sync,
1697 static int __devinit riva_set_fbinfo(struct fb_info *info)
1699 unsigned int cmap_len;
1700 struct riva_par *par = (struct riva_par *) info->par;
1703 info->flags = FBINFO_DEFAULT
1704 | FBINFO_HWACCEL_XPAN
1705 | FBINFO_HWACCEL_YPAN
1706 | FBINFO_HWACCEL_COPYAREA
1707 | FBINFO_HWACCEL_FILLRECT
1708 | FBINFO_HWACCEL_IMAGEBLIT
1709 | FBINFO_MISC_MODESWITCHLATE;
1711 /* Accel seems to not work properly on NV30 yet...*/
1712 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1713 printk(KERN_DEBUG PFX "disabling acceleration\n");
1714 info->flags |= FBINFO_HWACCEL_DISABLED;
1717 info->var = rivafb_default_var;
1718 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1719 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1721 info->pseudo_palette = par->pseudo_palette;
1723 cmap_len = riva_get_cmap_len(&info->var);
1724 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1726 info->pixmap.size = 8 * 1024;
1727 info->pixmap.buf_align = 4;
1728 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1729 info->var.yres_virtual = -1;
1731 return (rivafb_check_var(&info->var, info));
1734 #ifdef CONFIG_PPC_OF
1735 static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1737 struct riva_par *par = (struct riva_par *) info->par;
1738 struct device_node *dp;
1739 unsigned char *pedid = NULL;
1740 unsigned char *disptype = NULL;
1741 static char *propnames[] = {
1742 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1746 dp = pci_device_to_OF_node(pd);
1747 for (; dp != NULL; dp = dp->child) {
1748 disptype = (unsigned char *)get_property(dp, "display-type", NULL);
1749 if (disptype == NULL)
1751 if (strncmp(disptype, "LCD", 3) != 0)
1753 for (i = 0; propnames[i] != NULL; ++i) {
1754 pedid = (unsigned char *)
1755 get_property(dp, propnames[i], NULL);
1756 if (pedid != NULL) {
1758 NVTRACE("LCD found.\n");
1766 #endif /* CONFIG_PPC_OF */
1768 #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1769 static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1771 struct riva_par *par = (struct riva_par *) info->par;
1775 riva_create_i2c_busses(par);
1776 for (i = par->bus; i >= 1; i--) {
1777 riva_probe_i2c_connector(par, i, &par->EDID);
1779 printk(PFX "Found EDID Block from BUS %i\n", i);
1784 return (par->EDID) ? 1 : 0;
1786 #endif /* CONFIG_FB_RIVA_I2C */
1788 static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1789 struct fb_info *info)
1791 struct fb_monspecs *specs = &info->monspecs;
1792 struct fb_videomode modedb;
1795 /* respect mode options */
1797 fb_find_mode(var, info, mode_option,
1798 specs->modedb, specs->modedb_len,
1800 } else if (specs->modedb != NULL) {
1801 /* get preferred timing */
1802 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1805 for (i = 0; i < specs->modedb_len; i++) {
1806 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1807 modedb = specs->modedb[i];
1812 /* otherwise, get first mode in database */
1813 modedb = specs->modedb[0];
1815 var->bits_per_pixel = 8;
1816 riva_update_var(var, &modedb);
1822 static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1825 #ifdef CONFIG_PPC_OF
1826 if (!riva_get_EDID_OF(info, pdev))
1827 printk(PFX "could not retrieve EDID from OF\n");
1828 #elif CONFIG_FB_RIVA_I2C
1829 if (!riva_get_EDID_i2c(info))
1830 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1836 static void __devinit riva_get_edidinfo(struct fb_info *info)
1838 struct fb_var_screeninfo *var = &rivafb_default_var;
1839 struct riva_par *par = (struct riva_par *) info->par;
1841 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1842 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1844 riva_update_default_var(var, info);
1846 /* if user specified flatpanel, we respect that */
1847 if (info->monspecs.input & FB_DISP_DDI)
1851 /* ------------------------------------------------------------------------- *
1855 * ------------------------------------------------------------------------- */
1857 static u32 __devinit riva_get_arch(struct pci_dev *pd)
1861 switch (pd->device & 0x0ff0) {
1862 case 0x0100: /* GeForce 256 */
1863 case 0x0110: /* GeForce2 MX */
1864 case 0x0150: /* GeForce2 */
1865 case 0x0170: /* GeForce4 MX */
1866 case 0x0180: /* GeForce4 MX (8x AGP) */
1867 case 0x01A0: /* nForce */
1868 case 0x01F0: /* nForce2 */
1871 case 0x0200: /* GeForce3 */
1872 case 0x0250: /* GeForce4 Ti */
1873 case 0x0280: /* GeForce4 Ti (8x AGP) */
1876 case 0x0300: /* GeForceFX 5800 */
1877 case 0x0310: /* GeForceFX 5600 */
1878 case 0x0320: /* GeForceFX 5200 */
1879 case 0x0330: /* GeForceFX 5900 */
1880 case 0x0340: /* GeForceFX 5700 */
1883 case 0x0020: /* TNT, TNT2 */
1886 case 0x0010: /* Riva128 */
1889 default: /* unknown architecture */
1895 static int __devinit rivafb_probe(struct pci_dev *pd,
1896 const struct pci_device_id *ent)
1898 struct riva_par *default_par;
1899 struct fb_info *info;
1905 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1907 printk (KERN_ERR PFX "could not allocate memory\n");
1911 default_par = (struct riva_par *) info->par;
1912 default_par->pdev = pd;
1914 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1915 if (info->pixmap.addr == NULL) {
1917 goto err_framebuffer_release;
1919 memset(info->pixmap.addr, 0, 8 * 1024);
1921 ret = pci_enable_device(pd);
1923 printk(KERN_ERR PFX "cannot enable PCI device\n");
1924 goto err_free_pixmap;
1927 ret = pci_request_regions(pd, "rivafb");
1929 printk(KERN_ERR PFX "cannot request PCI regions\n");
1930 goto err_disable_device;
1933 default_par->riva.Architecture = riva_get_arch(pd);
1935 default_par->Chipset = (pd->vendor << 16) | pd->device;
1936 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1938 #ifdef CONFIG_PCI_NAMES
1939 printk(KERN_INFO PFX "%s\n", pd->pretty_name);
1942 if(default_par->riva.Architecture == 0) {
1943 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1945 goto err_release_region;
1947 if(default_par->riva.Architecture == NV_ARCH_10 ||
1948 default_par->riva.Architecture == NV_ARCH_20 ||
1949 default_par->riva.Architecture == NV_ARCH_30) {
1950 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1952 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1955 default_par->FlatPanel = flatpanel;
1957 printk(KERN_INFO PFX "flatpanel support enabled\n");
1958 default_par->forceCRTC = forceCRTC;
1960 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1961 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1964 /* enable IO and mem if not already done */
1967 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1968 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1969 pci_write_config_word(pd, PCI_COMMAND, cmd);
1972 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1973 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1975 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1976 rivafb_fix.mmio_len);
1977 if (!default_par->ctrl_base) {
1978 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1980 goto err_release_region;
1983 switch (default_par->riva.Architecture) {
1985 /* Riva128's PRAMIN is in the "framebuffer" space
1986 * Since these cards were never made with more than 8 megabytes
1987 * we can safely allocate this separately.
1989 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1990 if (!default_par->riva.PRAMIN) {
1991 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1993 goto err_iounmap_ctrl_base;
2000 default_par->riva.PCRTC0 =
2001 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2002 default_par->riva.PRAMIN =
2003 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2006 riva_common_setup(default_par);
2008 if (default_par->riva.Architecture == NV_ARCH_03) {
2009 default_par->riva.PCRTC = default_par->riva.PCRTC0
2010 = default_par->riva.PGRAPH;
2013 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2014 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2015 info->screen_base = ioremap(rivafb_fix.smem_start,
2016 rivafb_fix.smem_len);
2017 if (!info->screen_base) {
2018 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2020 goto err_iounmap_pramin;
2025 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2026 rivafb_fix.smem_len,
2027 MTRR_TYPE_WRCOMB, 1);
2028 if (default_par->mtrr.vram < 0) {
2029 printk(KERN_ERR PFX "unable to setup MTRR\n");
2031 default_par->mtrr.vram_valid = 1;
2032 /* let there be speed */
2033 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2036 #endif /* CONFIG_MTRR */
2038 info->fbops = &riva_fb_ops;
2039 info->fix = rivafb_fix;
2040 riva_get_EDID(info, pd);
2041 riva_get_edidinfo(info);
2043 ret=riva_set_fbinfo(info);
2045 printk(KERN_ERR PFX "error setting initial video mode\n");
2046 goto err_iounmap_screen_base;
2049 fb_destroy_modedb(info->monspecs.modedb);
2050 info->monspecs.modedb = NULL;
2051 ret = register_framebuffer(info);
2054 "error registering riva framebuffer\n");
2055 goto err_iounmap_screen_base;
2058 pci_set_drvdata(pd, info);
2060 printk(KERN_INFO PFX
2061 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2064 info->fix.smem_len / (1024 * 1024),
2065 info->fix.smem_start);
2066 #ifdef CONFIG_PMAC_BACKLIGHT
2067 if (default_par->FlatPanel && _machine == _MACH_Pmac)
2068 register_backlight_controller(&riva_backlight_controller,
2069 default_par, "mnca");
2074 err_iounmap_screen_base:
2075 #ifdef CONFIG_FB_RIVA_I2C
2076 riva_delete_i2c_busses((struct riva_par *) info->par);
2078 iounmap(info->screen_base);
2080 if (default_par->riva.Architecture == NV_ARCH_03)
2081 iounmap(default_par->riva.PRAMIN);
2082 err_iounmap_ctrl_base:
2083 iounmap(default_par->ctrl_base);
2085 pci_release_regions(pd);
2087 pci_disable_device(pd);
2089 kfree(info->pixmap.addr);
2090 err_framebuffer_release:
2091 framebuffer_release(info);
2096 static void __exit rivafb_remove(struct pci_dev *pd)
2098 struct fb_info *info = pci_get_drvdata(pd);
2099 struct riva_par *par = (struct riva_par *) info->par;
2105 #ifdef CONFIG_FB_RIVA_I2C
2106 riva_delete_i2c_busses(par);
2111 unregister_framebuffer(info);
2113 if (par->mtrr.vram_valid)
2114 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2115 info->fix.smem_len);
2116 #endif /* CONFIG_MTRR */
2118 iounmap(par->ctrl_base);
2119 iounmap(info->screen_base);
2120 if (par->riva.Architecture == NV_ARCH_03)
2121 iounmap(par->riva.PRAMIN);
2122 pci_release_regions(pd);
2123 pci_disable_device(pd);
2124 kfree(info->pixmap.addr);
2125 framebuffer_release(info);
2126 pci_set_drvdata(pd, NULL);
2130 /* ------------------------------------------------------------------------- *
2134 * ------------------------------------------------------------------------- */
2137 int __init rivafb_setup(char *options)
2142 if (!options || !*options)
2145 while ((this_opt = strsep(&options, ",")) != NULL) {
2146 if (!strncmp(this_opt, "forceCRTC", 9)) {
2150 if (!*p || !*(++p)) continue;
2151 forceCRTC = *p - '0';
2152 if (forceCRTC < 0 || forceCRTC > 1)
2154 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2157 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2160 } else if (!strncmp(this_opt, "strictmode", 10)) {
2162 } else if (!strncmp(this_opt, "noaccel", 7)) {
2165 mode_option = this_opt;
2170 #endif /* !MODULE */
2172 static struct pci_driver rivafb_driver = {
2174 .id_table = rivafb_pci_tbl,
2175 .probe = rivafb_probe,
2176 .remove = __exit_p(rivafb_remove),
2181 /* ------------------------------------------------------------------------- *
2185 * ------------------------------------------------------------------------- */
2187 int __devinit rivafb_init(void)
2190 char *option = NULL;
2192 if (fb_get_options("rivafb", &option))
2194 rivafb_setup(option);
2196 return pci_register_driver(&rivafb_driver);
2200 module_init(rivafb_init);
2203 static void __exit rivafb_exit(void)
2205 pci_unregister_driver(&rivafb_driver);
2208 module_exit(rivafb_exit);
2211 module_param(noaccel, bool, 0);
2212 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2213 module_param(flatpanel, int, 0);
2214 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2215 module_param(forceCRTC, int, 0);
2216 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2218 module_param(nomtrr, bool, 0);
2219 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2221 module_param(strictmode, bool, 0);
2222 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2224 MODULE_AUTHOR("Ani Joshi, maintainer");
2225 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2226 MODULE_LICENSE("GPL");