2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
6 * Copyright 1999-2000 Jeff Garzik
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
17 * Paul Richards: Bug fixes, updates
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
32 #include <linux/config.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/string.h>
38 #include <linux/tty.h>
39 #include <linux/slab.h>
40 #include <linux/delay.h>
42 #include <linux/init.h>
43 #include <linux/pci.h>
49 #include <asm/pci-bridge.h>
55 #ifndef CONFIG_PCI /* sanity check */
56 #error This driver requires PCI support.
59 /* version number of this driver */
60 #define RIVAFB_VERSION "0.9.5b"
62 /* ------------------------------------------------------------------------- *
64 * various helpful macros and constants
66 * ------------------------------------------------------------------------- */
70 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
72 #define DPRINTK(fmt, args...)
76 #define assert(expr) \
78 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
79 #expr,__FILE__,__FUNCTION__,__LINE__); \
86 #define PFX "rivafb: "
88 /* macro that allows you to set overflow bits */
89 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
90 #define SetBit(n) (1<<(n))
91 #define Set8Bits(value) ((value)&0xff)
93 /* HW cursor parameters */
96 /* ------------------------------------------------------------------------- *
100 * ------------------------------------------------------------------------- */
102 static int rivafb_blank(int blank, struct fb_info *info);
104 /* ------------------------------------------------------------------------- *
106 * card identification
108 * ------------------------------------------------------------------------- */
134 CH_GEFORCE4_420_GO_M32,
136 CH_GEFORCE4_440_GO_M64,
153 /* directly indexed by riva_chips enum, above */
154 static struct riva_chip_info {
157 } riva_chip_info[] __initdata = {
158 { "RIVA-128", NV_ARCH_03 },
159 { "RIVA-TNT", NV_ARCH_04 },
160 { "RIVA-TNT2", NV_ARCH_04 },
161 { "RIVA-UTNT2", NV_ARCH_04 },
162 { "RIVA-VTNT2", NV_ARCH_04 },
163 { "RIVA-UVTNT2", NV_ARCH_04 },
164 { "RIVA-ITNT2", NV_ARCH_04 },
165 { "GeForce-SDR", NV_ARCH_10 },
166 { "GeForce-DDR", NV_ARCH_10 },
167 { "Quadro", NV_ARCH_10 },
168 { "GeForce2-MX", NV_ARCH_10 },
169 { "GeForce2-MX", NV_ARCH_10 },
170 { "GeForce2-GO", NV_ARCH_10 },
171 { "Quadro2-MXR", NV_ARCH_10 },
172 { "GeForce2-GTS", NV_ARCH_10 },
173 { "GeForce2-GTS", NV_ARCH_10 },
174 { "GeForce2-ULTRA", NV_ARCH_10 },
175 { "Quadro2-PRO", NV_ARCH_10 },
176 { "GeForce4-MX-460", NV_ARCH_20 },
177 { "GeForce4-MX-440", NV_ARCH_20 },
178 { "GeForce4-MX-420", NV_ARCH_20 },
179 { "GeForce4-440-GO", NV_ARCH_20 },
180 { "GeForce4-420-GO", NV_ARCH_20 },
181 { "GeForce4-420-GO-M32", NV_ARCH_20 },
182 { "Quadro4-500-XGL", NV_ARCH_20 },
183 { "GeForce4-440-GO-M64", NV_ARCH_20 },
184 { "Quadro4-200", NV_ARCH_20 },
185 { "Quadro4-550-XGL", NV_ARCH_20 },
186 { "Quadro4-500-GOGL", NV_ARCH_20 },
187 { "GeForce2", NV_ARCH_20 },
188 { "GeForce3", NV_ARCH_20 },
189 { "GeForce3 Ti 200", NV_ARCH_20 },
190 { "GeForce3 Ti 500", NV_ARCH_20 },
191 { "Quadro DDC", NV_ARCH_20 },
192 { "GeForce4 Ti 4600", NV_ARCH_20 },
193 { "GeForce4 Ti 4400", NV_ARCH_20 },
194 { "GeForce4 Ti 4200", NV_ARCH_20 },
195 { "Quadro4-900-XGL", NV_ARCH_20 },
196 { "Quadro4-750-XGL", NV_ARCH_20 },
197 { "Quadro4-700-XGL", NV_ARCH_20 }
200 static struct pci_device_id rivafb_pci_tbl[] = {
201 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_128 },
203 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT },
205 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT2 },
207 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_UTNT2 },
209 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 },
211 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 },
213 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_ITNT2 },
215 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_SDR },
217 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_DDR },
219 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO },
221 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX },
223 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX2 },
225 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GO },
227 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_MXR },
229 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS },
231 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS2 },
233 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_ULTRA },
235 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_PRO },
237 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_460 },
239 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_440 },
241 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_420 },
243 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO },
245 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO },
247 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO_M32 },
249 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500XGL },
251 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO_M64 },
253 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_200 },
255 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_550XGL },
257 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500_GOGL },
259 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_IGEFORCE2 },
261 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3 },
263 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_1 },
265 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_2 },
267 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO_DDC },
269 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4600 },
271 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4400 },
273 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4200 },
275 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_900XGL },
277 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_750XGL },
279 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_700XGL },
281 { 0, } /* terminate list */
283 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
285 /* ------------------------------------------------------------------------- *
289 * ------------------------------------------------------------------------- */
291 /* command line data, set in rivafb_setup() */
292 static u32 pseudo_palette[17];
293 static int flatpanel __initdata = -1; /* Autodetect later */
294 static int forceCRTC __initdata = -1;
296 static int nomtrr __initdata = 0;
300 static char *mode_option __initdata = NULL;
303 static struct fb_fix_screeninfo rivafb_fix = {
305 .type = FB_TYPE_PACKED_PIXELS,
310 static struct fb_var_screeninfo rivafb_default_var = {
320 .activate = FB_ACTIVATE_NOW,
323 .accel_flags = FB_ACCELF_TEXT,
331 .vmode = FB_VMODE_NONINTERLACED
335 static const struct riva_regs reg_template = {
336 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
337 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
338 0x41, 0x01, 0x0F, 0x00, 0x00},
339 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
340 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
341 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
342 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
343 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
344 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
345 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
346 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
349 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
351 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
355 /* ------------------------------------------------------------------------- *
359 * ------------------------------------------------------------------------- */
361 static inline void CRTCout(struct riva_par *par, unsigned char index,
364 VGA_WR08(par->riva.PCIO, 0x3d4, index);
365 VGA_WR08(par->riva.PCIO, 0x3d5, val);
368 static inline unsigned char CRTCin(struct riva_par *par,
371 VGA_WR08(par->riva.PCIO, 0x3d4, index);
372 return (VGA_RD08(par->riva.PCIO, 0x3d5));
375 static inline void GRAout(struct riva_par *par, unsigned char index,
378 VGA_WR08(par->riva.PVIO, 0x3ce, index);
379 VGA_WR08(par->riva.PVIO, 0x3cf, val);
382 static inline unsigned char GRAin(struct riva_par *par,
385 VGA_WR08(par->riva.PVIO, 0x3ce, index);
386 return (VGA_RD08(par->riva.PVIO, 0x3cf));
389 static inline void SEQout(struct riva_par *par, unsigned char index,
392 VGA_WR08(par->riva.PVIO, 0x3c4, index);
393 VGA_WR08(par->riva.PVIO, 0x3c5, val);
396 static inline unsigned char SEQin(struct riva_par *par,
399 VGA_WR08(par->riva.PVIO, 0x3c4, index);
400 return (VGA_RD08(par->riva.PVIO, 0x3c5));
403 static inline void ATTRout(struct riva_par *par, unsigned char index,
406 VGA_WR08(par->riva.PCIO, 0x3c0, index);
407 VGA_WR08(par->riva.PCIO, 0x3c0, val);
410 static inline unsigned char ATTRin(struct riva_par *par,
413 VGA_WR08(par->riva.PCIO, 0x3c0, index);
414 return (VGA_RD08(par->riva.PCIO, 0x3c1));
417 static inline void MISCout(struct riva_par *par, unsigned char val)
419 VGA_WR08(par->riva.PVIO, 0x3c2, val);
422 static inline unsigned char MISCin(struct riva_par *par)
424 return (VGA_RD08(par->riva.PVIO, 0x3cc));
427 static u8 byte_rev[256] = {
428 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
429 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
430 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
431 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
432 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
433 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
434 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
435 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
436 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
437 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
438 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
439 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
440 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
441 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
442 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
443 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
444 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
445 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
446 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
447 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
448 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
449 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
450 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
451 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
452 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
453 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
454 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
455 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
456 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
457 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
458 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
459 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
462 static inline void reverse_order(u32 *l)
465 *a = byte_rev[*a], a++;
466 *a = byte_rev[*a], a++;
467 *a = byte_rev[*a], a++;
471 /* ------------------------------------------------------------------------- *
475 * ------------------------------------------------------------------------- */
478 * rivafb_load_cursor_image - load cursor image to hardware
479 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
480 * @par: pointer to private data
481 * @w: width of cursor image in pixels
482 * @h: height of cursor image in scanlines
483 * @bg: background color (ARGB1555) - alpha bit determines opacity
484 * @fg: foreground color (ARGB1555)
487 * Loads cursor image based on a monochrome source and mask bitmap. The
488 * image bits determines the color of the pixel, 0 for background, 1 for
489 * foreground. Only the affected region (as determined by @w and @h
490 * parameters) will be updated.
495 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data,
496 u8 *mask, u16 bg, u16 fg, u32 w, u32 h)
501 for (i = 0; i < h; i++) {
503 b = (u32)((u32 *)b + 1);
505 m = (u32)((u32 *)m + 1);
508 for (j = 0; j < w/2; j++) {
510 #if defined (__BIG_ENDIAN)
515 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
523 tmp |= (b & (1 << 31)) ? fg : bg;
531 tmp = (b & 1) ? fg : bg;
539 tmp |= (b & 1) ? fg << 16 : bg << 16;
543 writel(tmp, par->riva.CURSOR + k++);
545 k += (MAX_CURS - w)/2;
549 /* ------------------------------------------------------------------------- *
551 * general utility functions
553 * ------------------------------------------------------------------------- */
556 * riva_wclut - set CLUT entry
557 * @chip: pointer to RIVA_HW_INST object
558 * @regnum: register number
559 * @red: red component
560 * @green: green component
561 * @blue: blue component
564 * Sets color register @regnum.
569 static void riva_wclut(RIVA_HW_INST *chip,
570 unsigned char regnum, unsigned char red,
571 unsigned char green, unsigned char blue)
573 VGA_WR08(chip->PDIO, 0x3c8, regnum);
574 VGA_WR08(chip->PDIO, 0x3c9, red);
575 VGA_WR08(chip->PDIO, 0x3c9, green);
576 VGA_WR08(chip->PDIO, 0x3c9, blue);
580 * riva_rclut - read fromCLUT register
581 * @chip: pointer to RIVA_HW_INST object
582 * @regnum: register number
583 * @red: red component
584 * @green: green component
585 * @blue: blue component
588 * Reads red, green, and blue from color register @regnum.
593 static void riva_rclut(RIVA_HW_INST *chip,
594 unsigned char regnum, unsigned char *red,
595 unsigned char *green, unsigned char *blue)
598 VGA_WR08(chip->PDIO, 0x3c8, regnum);
599 *red = VGA_RD08(chip->PDIO, 0x3c9);
600 *green = VGA_RD08(chip->PDIO, 0x3c9);
601 *blue = VGA_RD08(chip->PDIO, 0x3c9);
605 * riva_save_state - saves current chip state
606 * @par: pointer to riva_par object containing info for current riva board
607 * @regs: pointer to riva_regs object
610 * Saves current chip state to @regs.
616 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
620 par->riva.LockUnlock(&par->riva, 0);
622 par->riva.UnloadStateExt(&par->riva, ®s->ext);
624 regs->misc_output = MISCin(par);
626 for (i = 0; i < NUM_CRT_REGS; i++)
627 regs->crtc[i] = CRTCin(par, i);
629 for (i = 0; i < NUM_ATC_REGS; i++)
630 regs->attr[i] = ATTRin(par, i);
632 for (i = 0; i < NUM_GRC_REGS; i++)
633 regs->gra[i] = GRAin(par, i);
635 for (i = 0; i < NUM_SEQ_REGS; i++)
636 regs->seq[i] = SEQin(par, i);
640 * riva_load_state - loads current chip state
641 * @par: pointer to riva_par object containing info for current riva board
642 * @regs: pointer to riva_regs object
645 * Loads chip state from @regs.
648 * riva_load_video_mode()
653 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
655 RIVA_HW_STATE *state = ®s->ext;
658 CRTCout(par, 0x11, 0x00);
660 par->riva.LockUnlock(&par->riva, 0);
662 par->riva.LoadStateExt(&par->riva, state);
664 MISCout(par, regs->misc_output);
666 for (i = 0; i < NUM_CRT_REGS; i++) {
672 CRTCout(par, i, regs->crtc[i]);
676 for (i = 0; i < NUM_ATC_REGS; i++)
677 ATTRout(par, i, regs->attr[i]);
679 for (i = 0; i < NUM_GRC_REGS; i++)
680 GRAout(par, i, regs->gra[i]);
682 for (i = 0; i < NUM_SEQ_REGS; i++)
683 SEQout(par, i, regs->seq[i]);
687 * riva_load_video_mode - calculate timings
688 * @info: pointer to fb_info object containing info for current riva board
691 * Calculate some timings and then send em off to riva_load_state().
696 static void riva_load_video_mode(struct fb_info *info)
698 int bpp, width, hDisplaySize, hDisplay, hStart,
699 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
700 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
701 struct riva_par *par = (struct riva_par *) info->par;
702 struct riva_regs newmode;
704 /* time to calculate */
705 rivafb_blank(1, info);
707 bpp = info->var.bits_per_pixel;
708 if (bpp == 16 && info->var.green.length == 5)
710 width = info->var.xres_virtual;
711 hDisplaySize = info->var.xres;
712 hDisplay = (hDisplaySize / 8) - 1;
713 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
714 hEnd = (hDisplaySize + info->var.right_margin +
715 info->var.hsync_len) / 8 - 1;
716 hTotal = (hDisplaySize + info->var.right_margin +
717 info->var.hsync_len + info->var.left_margin) / 8 - 5;
718 hBlankStart = hDisplay;
719 hBlankEnd = hTotal + 4;
721 height = info->var.yres_virtual;
722 vDisplay = info->var.yres - 1;
723 vStart = info->var.yres + info->var.lower_margin - 1;
724 vEnd = info->var.yres + info->var.lower_margin +
725 info->var.vsync_len - 1;
726 vTotal = info->var.yres + info->var.lower_margin +
727 info->var.vsync_len + info->var.upper_margin + 2;
728 vBlankStart = vDisplay;
729 vBlankEnd = vTotal + 1;
730 dotClock = 1000000000 / info->var.pixclock;
732 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
734 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
737 if (par->FlatPanel) {
740 vBlankStart = vStart;
743 hBlankEnd = hTotal + 4;
746 newmode.crtc[0x0] = Set8Bits (hTotal);
747 newmode.crtc[0x1] = Set8Bits (hDisplay);
748 newmode.crtc[0x2] = Set8Bits (hBlankStart);
749 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
750 newmode.crtc[0x4] = Set8Bits (hStart);
751 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
752 | SetBitField (hEnd, 4: 0, 4:0);
753 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
754 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
755 | SetBitField (vDisplay, 8: 8, 1:1)
756 | SetBitField (vStart, 8: 8, 2:2)
757 | SetBitField (vBlankStart, 8: 8, 3:3)
759 | SetBitField (vTotal, 9: 9, 5:5)
760 | SetBitField (vDisplay, 9: 9, 6:6)
761 | SetBitField (vStart, 9: 9, 7:7);
762 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
764 newmode.crtc[0x10] = Set8Bits (vStart);
765 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
767 newmode.crtc[0x12] = Set8Bits (vDisplay);
768 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
769 newmode.crtc[0x15] = Set8Bits (vBlankStart);
770 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
772 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
773 | SetBitField(vBlankStart,10:10,3:3)
774 | SetBitField(vStart,10:10,2:2)
775 | SetBitField(vDisplay,10:10,1:1)
776 | SetBitField(vTotal,10:10,0:0);
777 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
778 | SetBitField(hDisplay,8:8,1:1)
779 | SetBitField(hBlankStart,8:8,2:2)
780 | SetBitField(hStart,8:8,3:3);
781 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
782 | SetBitField(vDisplay,11:11,2:2)
783 | SetBitField(vStart,11:11,4:4)
784 | SetBitField(vBlankStart,11:11,6:6);
786 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
787 int tmp = (hTotal >> 1) & ~1;
788 newmode.ext.interlace = Set8Bits(tmp);
789 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
791 newmode.ext.interlace = 0xff; /* interlace off */
793 if (par->riva.Architecture >= NV_ARCH_10)
794 par->riva.CURSOR = (U032 *)(info->screen_base + par->riva.CursorStart);
796 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
797 newmode.misc_output &= ~0x40;
799 newmode.misc_output |= 0x40;
800 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
801 newmode.misc_output &= ~0x80;
803 newmode.misc_output |= 0x80;
805 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
806 hDisplaySize, height, dotClock);
808 newmode.ext.scale = par->riva.PRAMDAC[0x00000848/4] & 0xfff000ff;
809 if (par->FlatPanel == 1) {
810 newmode.ext.pixel |= (1 << 7);
811 newmode.ext.scale |= (1 << 8);
813 if (par->SecondCRTC) {
814 newmode.ext.head = par->riva.PCRTC0[0x00000860/4] & ~0x00001000;
815 newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] | 0x00001000;
816 newmode.ext.crtcOwner = 3;
817 newmode.ext.pllsel |= 0x20000800;
818 newmode.ext.vpll2 = newmode.ext.vpll;
819 } else if (par->riva.twoHeads) {
820 newmode.ext.head = par->riva.PCRTC0[0x00000860/4] | 0x00001000;
821 newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] & ~0x00001000;
822 newmode.ext.crtcOwner = 0;
823 newmode.ext.vpll2 = par->riva.PRAMDAC0[0x00000520/4];
825 if (par->FlatPanel == 1) {
826 newmode.ext.pixel |= (1 << 7);
827 newmode.ext.scale |= (1 << 8);
829 newmode.ext.cursorConfig = 0x02000100;
830 par->current_state = newmode;
831 riva_load_state(par, &par->current_state);
832 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
833 rivafb_blank(0, info);
837 * rivafb_do_maximize -
838 * @info: pointer to fb_info object containing info for current riva board
847 * -EINVAL on failure, 0 on success
853 static int rivafb_do_maximize(struct fb_info *info,
854 struct fb_var_screeninfo *var,
869 /* use highest possible virtual resolution */
870 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
871 printk(KERN_WARNING PFX
872 "using maximum available virtual resolution\n");
873 for (i = 0; modes[i].xres != -1; i++) {
874 if (modes[i].xres * nom / den * modes[i].yres <
875 info->fix.smem_len / 2)
878 if (modes[i].xres == -1) {
880 "could not find a virtual resolution that fits into video memory!!\n");
881 DPRINTK("EXIT - EINVAL error\n");
884 var->xres_virtual = modes[i].xres;
885 var->yres_virtual = modes[i].yres;
888 "virtual resolution set to maximum of %dx%d\n",
889 var->xres_virtual, var->yres_virtual);
890 } else if (var->xres_virtual == -1) {
891 var->xres_virtual = (info->fix.smem_len * den /
892 (nom * var->yres_virtual * 2)) & ~15;
893 printk(KERN_WARNING PFX
894 "setting virtual X resolution to %d\n", var->xres_virtual);
895 } else if (var->yres_virtual == -1) {
896 var->xres_virtual = (var->xres_virtual + 15) & ~15;
897 var->yres_virtual = info->fix.smem_len * den /
898 (nom * var->xres_virtual * 2);
899 printk(KERN_WARNING PFX
900 "setting virtual Y resolution to %d\n", var->yres_virtual);
902 var->xres_virtual = (var->xres_virtual + 15) & ~15;
903 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
905 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
906 var->xres, var->yres, var->bits_per_pixel);
907 DPRINTK("EXIT - EINVAL error\n");
912 if (var->xres_virtual * nom / den >= 8192) {
913 printk(KERN_WARNING PFX
914 "virtual X resolution (%d) is too high, lowering to %d\n",
915 var->xres_virtual, 8192 * den / nom - 16);
916 var->xres_virtual = 8192 * den / nom - 16;
919 if (var->xres_virtual < var->xres) {
921 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
925 if (var->yres_virtual < var->yres) {
927 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
933 /* acceleration routines */
934 inline void wait_for_idle(struct riva_par *par)
936 while (par->riva.Busy(&par->riva));
939 /* set copy ROP, no mask */
940 static void riva_setup_ROP(struct riva_par *par)
942 RIVA_FIFO_FREE(par->riva, Patt, 5);
943 par->riva.Patt->Shape = 0;
944 par->riva.Patt->Color0 = 0xffffffff;
945 par->riva.Patt->Color1 = 0xffffffff;
946 par->riva.Patt->Monochrome[0] = 0xffffffff;
947 par->riva.Patt->Monochrome[1] = 0xffffffff;
949 RIVA_FIFO_FREE(par->riva, Rop, 1);
950 par->riva.Rop->Rop3 = 0xCC;
953 void riva_setup_accel(struct riva_par *par)
955 RIVA_FIFO_FREE(par->riva, Clip, 2);
956 par->riva.Clip->TopLeft = 0x0;
957 par->riva.Clip->WidthHeight = 0x80008000;
963 * riva_get_cmap_len - query current color map length
964 * @var: standard kernel fb changeable data
967 * Get current color map length.
970 * Length of color map
975 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
977 int rc = 256; /* reasonable default */
979 switch (var->green.length) {
981 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
984 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
987 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
990 /* should not occur */
996 /* ------------------------------------------------------------------------- *
998 * framebuffer operations
1000 * ------------------------------------------------------------------------- */
1002 static int rivafb_open(struct fb_info *info, int user)
1004 struct riva_par *par = (struct riva_par *) info->par;
1005 int cnt = atomic_read(&par->ref_count);
1008 memset(&par->state, 0, sizeof(struct vgastate));
1009 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1010 /* save the DAC for Riva128 */
1011 if (par->riva.Architecture == NV_ARCH_03)
1012 par->state.flags |= VGA_SAVE_CMAP;
1013 save_vga(&par->state);
1015 RivaGetConfig(&par->riva, par->Chipset);
1016 /* vgaHWunlock() + riva unlock (0x7F) */
1017 CRTCout(par, 0x11, 0xFF);
1018 par->riva.LockUnlock(&par->riva, 0);
1020 riva_save_state(par, &par->initial_state);
1022 atomic_inc(&par->ref_count);
1026 static int rivafb_release(struct fb_info *info, int user)
1028 struct riva_par *par = (struct riva_par *) info->par;
1029 int cnt = atomic_read(&par->ref_count);
1034 par->riva.LockUnlock(&par->riva, 0);
1035 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1036 riva_load_state(par, &par->initial_state);
1037 restore_vga(&par->state);
1038 par->riva.LockUnlock(&par->riva, 1);
1040 atomic_dec(&par->ref_count);
1044 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1046 int nom, den; /* translating from pixels->bytes */
1048 switch (var->bits_per_pixel) {
1050 var->red.offset = var->green.offset = var->blue.offset = 0;
1051 var->red.length = var->green.length = var->blue.length = 8;
1052 var->bits_per_pixel = 8;
1056 var->green.length = 5;
1059 var->bits_per_pixel = 16;
1060 if (var->green.length == 5) {
1061 /* 0rrrrrgg gggbbbbb */
1062 var->red.offset = 10;
1063 var->green.offset = 5;
1064 var->blue.offset = 0;
1065 var->red.length = 5;
1066 var->green.length = 5;
1067 var->blue.length = 5;
1069 /* rrrrrggg gggbbbbb */
1070 var->red.offset = 11;
1071 var->green.offset = 5;
1072 var->blue.offset = 0;
1073 var->red.length = 5;
1074 var->green.length = 6;
1075 var->blue.length = 5;
1081 var->red.length = var->green.length = var->blue.length = 8;
1082 var->bits_per_pixel = 32;
1083 var->red.offset = 16;
1084 var->green.offset = 8;
1085 var->blue.offset = 0;
1091 "mode %dx%dx%d rejected...color depth not supported.\n",
1092 var->xres, var->yres, var->bits_per_pixel);
1093 DPRINTK("EXIT, returning -EINVAL\n");
1097 if (rivafb_do_maximize(info, var, nom, den) < 0)
1100 if (var->xoffset < 0)
1102 if (var->yoffset < 0)
1105 /* truncate xoffset and yoffset to maximum if too high */
1106 if (var->xoffset > var->xres_virtual - var->xres)
1107 var->xoffset = var->xres_virtual - var->xres - 1;
1109 if (var->yoffset > var->yres_virtual - var->yres)
1110 var->yoffset = var->yres_virtual - var->yres - 1;
1112 var->red.msb_right =
1113 var->green.msb_right =
1114 var->blue.msb_right =
1115 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1119 static int rivafb_set_par(struct fb_info *info)
1121 struct riva_par *par = (struct riva_par *) info->par;
1123 riva_load_video_mode(info);
1124 riva_setup_accel(par);
1126 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1127 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1128 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1133 * rivafb_pan_display
1134 * @var: standard kernel fb changeable data
1136 * @info: pointer to fb_info object containing info for current riva board
1139 * Pan (or wrap, depending on the `vmode' field) the display using the
1140 * `xoffset' and `yoffset' fields of the `var' structure.
1141 * If the values don't fit, return -EINVAL.
1143 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1145 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1146 struct fb_info *info)
1148 struct riva_par *par = (struct riva_par *)info->par;
1151 if (var->xoffset > (var->xres_virtual - var->xres))
1153 if (var->yoffset > (var->yres_virtual - var->yres))
1156 if (var->vmode & FB_VMODE_YWRAP) {
1157 if (var->yoffset < 0
1158 || var->yoffset >= info->var.yres_virtual
1159 || var->xoffset) return -EINVAL;
1161 if (var->xoffset + info->var.xres > info->var.xres_virtual ||
1162 var->yoffset + info->var.yres > info->var.yres_virtual)
1166 base = var->yoffset * info->fix.line_length + var->xoffset;
1168 par->riva.SetStartAddress(&par->riva, base);
1170 info->var.xoffset = var->xoffset;
1171 info->var.yoffset = var->yoffset;
1173 if (var->vmode & FB_VMODE_YWRAP)
1174 info->var.vmode |= FB_VMODE_YWRAP;
1176 info->var.vmode &= ~FB_VMODE_YWRAP;
1180 static int rivafb_blank(int blank, struct fb_info *info)
1182 struct riva_par *par= (struct riva_par *)info->par;
1183 unsigned char tmp, vesa;
1185 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1186 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1190 switch (blank - 1) {
1191 case VESA_NO_BLANKING:
1193 case VESA_VSYNC_SUSPEND:
1196 case VESA_HSYNC_SUSPEND:
1199 case VESA_POWERDOWN:
1204 SEQout(par, 0x01, tmp);
1205 CRTCout(par, 0x1a, vesa);
1211 * @regno: register index
1212 * @red: red component
1213 * @green: green component
1214 * @blue: blue component
1215 * @transp: transparency
1216 * @info: pointer to fb_info object containing info for current riva board
1219 * Set a single color register. The values supplied have a 16 bit
1223 * Return != 0 for invalid regno.
1226 * fbcmap.c:fb_set_cmap()
1228 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1229 unsigned blue, unsigned transp,
1230 struct fb_info *info)
1232 struct riva_par *par = (struct riva_par *)info->par;
1233 RIVA_HW_INST *chip = &par->riva;
1236 if (regno >= riva_get_cmap_len(&info->var))
1239 if (info->var.grayscale) {
1240 /* gray = 0.30*R + 0.59*G + 0.11*B */
1241 red = green = blue =
1242 (red * 77 + green * 151 + blue * 28) >> 8;
1245 switch (info->var.bits_per_pixel) {
1247 /* "transparent" stuff is completely ignored. */
1248 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1251 if (info->var.green.length == 5) {
1253 /* 0rrrrrgg gggbbbbb */
1254 ((u32 *)info->pseudo_palette)[regno] =
1255 ((red & 0xf800) >> 1) |
1256 ((green & 0xf800) >> 6) |
1257 ((blue & 0xf800) >> 11);
1259 for (i = 0; i < 8; i++)
1260 riva_wclut(chip, regno*8+i, red >> 8,
1261 green >> 8, blue >> 8);
1266 /* rrrrrggg gggbbbbb */
1267 ((u32 *)info->pseudo_palette)[regno] =
1268 ((red & 0xf800) >> 0) |
1269 ((green & 0xf800) >> 5) |
1270 ((blue & 0xf800) >> 11);
1273 for (i = 0; i < 8; i++) {
1274 riva_wclut(chip, regno*8+i, red >> 8,
1275 green >> 8, blue >> 8);
1278 for (i = 0; i < 4; i++) {
1279 riva_rclut(chip, regno*2+i, &r, &g, &b);
1280 riva_wclut(chip, regno*4+i, r, green >> 8, b);
1286 ((u32 *)info->pseudo_palette)[regno] =
1287 ((red & 0xff00) << 8) |
1288 ((green & 0xff00)) | ((blue & 0xff00) >> 8);
1291 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1301 * rivafb_fillrect - hardware accelerated color fill function
1302 * @info: pointer to fb_info structure
1303 * @rect: pointer to fb_fillrect structure
1306 * This function fills up a region of framebuffer memory with a solid
1307 * color with a choice of two different ROP's, copy or invert.
1312 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1314 struct riva_par *par = (struct riva_par *) info->par;
1315 u_int color, rop = 0;
1317 if (info->var.bits_per_pixel == 8)
1318 color = rect->color;
1320 color = ((u32 *)info->pseudo_palette)[rect->color];
1322 switch (rect->rop) {
1332 RIVA_FIFO_FREE(par->riva, Rop, 1);
1333 par->riva.Rop->Rop3 = rop;
1335 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1336 par->riva.Bitmap->Color1A = color;
1338 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1339 par->riva.Bitmap->UnclippedRectangle[0].TopLeft =
1340 (rect->dx << 16) | rect->dy;
1341 par->riva.Bitmap->UnclippedRectangle[0].WidthHeight =
1342 (rect->width << 16) | rect->height;
1343 RIVA_FIFO_FREE(par->riva, Rop, 1);
1344 par->riva.Rop->Rop3 = 0xCC; // back to COPY
1348 * rivafb_copyarea - hardware accelerated blit function
1349 * @info: pointer to fb_info structure
1350 * @region: pointer to fb_copyarea structure
1353 * This copies an area of pixels from one location to another
1358 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1360 struct riva_par *par = (struct riva_par *) info->par;
1362 RIVA_FIFO_FREE(par->riva, Blt, 3);
1363 par->riva.Blt->TopLeftSrc = (region->sy << 16) | region->sx;
1364 par->riva.Blt->TopLeftDst = (region->dy << 16) | region->dx;
1365 par->riva.Blt->WidthHeight = (region->height << 16) | region->width;
1369 static inline void convert_bgcolor_16(u32 *col)
1371 *col = ((*col & 0x00007C00) << 9)
1372 | ((*col & 0x000003E0) << 6)
1373 | ((*col & 0x0000001F) << 3)
1378 * rivafb_imageblit: hardware accelerated color expand function
1379 * @info: pointer to fb_info structure
1380 * @image: pointer to fb_image structure
1383 * If the source is a monochrome bitmap, the function fills up a a region
1384 * of framebuffer memory with pixels whose color is determined by the bit
1385 * setting of the bitmap, 1 - foreground, 0 - background.
1387 * If the source is not a monochrome bitmap, color expansion is not done.
1388 * In this case, it is channeled to a software function.
1393 static void rivafb_imageblit(struct fb_info *info,
1394 const struct fb_image *image)
1396 struct riva_par *par = (struct riva_par *) info->par;
1397 u32 fgx = 0, bgx = 0, width, tmp;
1398 u8 *cdat = (u8 *) image->data;
1402 if (image->depth != 1) {
1403 cfb_imageblit(info, image);
1407 switch (info->var.bits_per_pixel) {
1409 fgx = image->fg_color;
1410 bgx = image->bg_color;
1413 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1414 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1415 if (info->var.green.length == 6)
1416 convert_bgcolor_16(&bgx);
1419 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1420 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1424 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1425 par->riva.Bitmap->ClipE.TopLeft =
1426 (image->dy << 16) | (image->dx & 0xFFFF);
1427 par->riva.Bitmap->ClipE.BottomRight =
1428 (((image->dy + image->height) << 16) |
1429 ((image->dx + image->width) & 0xffff));
1430 par->riva.Bitmap->Color0E = bgx;
1431 par->riva.Bitmap->Color1E = fgx;
1432 par->riva.Bitmap->WidthHeightInE =
1433 (image->height << 16) | ((image->width + 31) & ~31);
1434 par->riva.Bitmap->WidthHeightOutE =
1435 (image->height << 16) | ((image->width + 31) & ~31);
1436 par->riva.Bitmap->PointE =
1437 (image->dy << 16) | (image->dx & 0xFFFF);
1439 d = &par->riva.Bitmap->MonochromeData01E;
1441 width = (image->width + 31)/32;
1442 size = width * image->height;
1443 while (size >= 16) {
1444 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1445 for (i = 0; i < 16; i++) {
1446 tmp = *((u32 *)cdat);
1447 cdat = (u8 *)((u32 *)cdat + 1);
1448 reverse_order(&tmp);
1454 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1455 for (i = 0; i < size; i++) {
1456 tmp = *((u32 *) cdat);
1457 cdat = (u8 *)((u32 *)cdat + 1);
1458 reverse_order(&tmp);
1465 * rivafb_cursor - hardware cursor function
1466 * @info: pointer to info structure
1467 * @cursor: pointer to fbcursor structure
1470 * A cursor function that supports displaying a cursor image via hardware.
1471 * Within the kernel, copy and invert rops are supported. If exported
1472 * to user space, only the copy rop will be supported.
1477 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1479 struct riva_par *par = (struct riva_par *) info->par;
1480 u8 data[MAX_CURS * MAX_CURS/8];
1481 u8 mask[MAX_CURS * MAX_CURS/8];
1485 par->riva.ShowHideCursor(&par->riva, 0);
1487 if (cursor->set & FB_CUR_SETPOS) {
1490 info->cursor.image.dx = cursor->image.dx;
1491 info->cursor.image.dy = cursor->image.dy;
1492 yy = cursor->image.dy - info->var.yoffset;
1493 xx = cursor->image.dx - info->var.xoffset;
1497 par->riva.PRAMDAC[0x0000300/4] = temp;
1500 if (cursor->set & FB_CUR_SETSIZE) {
1501 info->cursor.image.height = cursor->image.height;
1502 info->cursor.image.width = cursor->image.width;
1503 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1506 if (cursor->set & FB_CUR_SETCMAP) {
1507 info->cursor.image.bg_color = cursor->image.bg_color;
1508 info->cursor.image.fg_color = cursor->image.fg_color;
1511 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP)) {
1512 u32 bg_idx = info->cursor.image.bg_color;
1513 u32 fg_idx = info->cursor.image.fg_color;
1514 u32 s_pitch = (info->cursor.image.width+7) >> 3;
1515 u32 d_pitch = MAX_CURS/8;
1516 u8 *dat = (u8 *) cursor->image.data;
1517 u8 *msk = (u8 *) info->cursor.mask;
1520 switch (info->cursor.rop) {
1522 for (i = 0; i < s_pitch * info->cursor.image.height; i++)
1523 src[i] = dat[i] ^ msk[i];
1527 for (i = 0; i < s_pitch * info->cursor.image.height; i++)
1529 src[i] = dat[i] & msk[i];
1533 fb_move_buf_aligned(info, &info->sprite, data, d_pitch, src, s_pitch, info->cursor.image.height);
1535 fb_move_buf_aligned(info, &info->sprite, mask, d_pitch, msk, s_pitch, info->cursor.image.height);
1537 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1538 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1539 ((info->cmap.blue[bg_idx] & 0xf8) >> 3);
1541 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1542 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1543 ((info->cmap.blue[fg_idx] & 0xf8) >> 3);
1545 par->riva.LockUnlock(&par->riva, 0);
1547 rivafb_load_cursor_image(par, data, mask, bg, fg,
1548 info->cursor.image.width,
1549 info->cursor.image.height);
1551 if (info->cursor.enable)
1552 par->riva.ShowHideCursor(&par->riva, 1);
1556 static int rivafb_sync(struct fb_info *info)
1558 struct riva_par *par = (struct riva_par *)info->par;
1564 /* ------------------------------------------------------------------------- *
1566 * initialization helper functions
1568 * ------------------------------------------------------------------------- */
1570 /* kernel interface */
1571 static struct fb_ops riva_fb_ops = {
1572 .owner = THIS_MODULE,
1573 .fb_open = rivafb_open,
1574 .fb_release = rivafb_release,
1575 .fb_check_var = rivafb_check_var,
1576 .fb_set_par = rivafb_set_par,
1577 .fb_setcolreg = rivafb_setcolreg,
1578 .fb_pan_display = rivafb_pan_display,
1579 .fb_blank = rivafb_blank,
1580 .fb_fillrect = rivafb_fillrect,
1581 .fb_copyarea = rivafb_copyarea,
1582 .fb_imageblit = rivafb_imageblit,
1583 .fb_cursor = rivafb_cursor,
1584 .fb_sync = rivafb_sync,
1587 static int __devinit riva_set_fbinfo(struct fb_info *info)
1589 struct riva_par *par = (struct riva_par *) info->par;
1590 unsigned int cmap_len;
1592 info->flags = FBINFO_FLAG_DEFAULT;
1593 info->var = rivafb_default_var;
1594 info->fix = rivafb_fix;
1595 info->fbops = &riva_fb_ops;
1596 info->pseudo_palette = pseudo_palette;
1600 fb_find_mode(&info->var, info, mode_option,
1603 if (par->use_default_var)
1604 /* We will use the modified default var */
1605 info->var = rivafb_default_var;
1607 cmap_len = riva_get_cmap_len(&info->var);
1608 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1610 info->pixmap.size = 64 * 1024;
1611 info->pixmap.buf_align = 4;
1612 info->pixmap.scan_align = 4;
1613 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1617 #ifdef CONFIG_PPC_OF
1618 static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1620 struct riva_par *par = (struct riva_par *) info->par;
1621 struct device_node *dp;
1622 unsigned char *pedid = NULL;
1624 dp = pci_device_to_OF_node(pd);
1625 pedid = (unsigned char *)get_property(dp, "EDID,B", 0);
1633 #endif /* CONFIG_PPC_OF */
1635 static int riva_dfp_parse_EDID(struct riva_par *par)
1637 unsigned char *block = par->EDID;
1642 /* jump to detailed timing block section */
1645 par->clock = (block[0] + (block[1] << 8));
1646 par->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
1647 par->hblank = (block[3] + ((block[4] & 0x0f) << 8));
1648 par->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
1649 par->vblank = (block[6] + ((block[7] & 0x0f) << 8));
1650 par->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
1651 par->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
1652 par->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
1653 par->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
1654 par->interlaced = ((block[17] & 0x80) >> 7);
1655 par->synct = ((block[17] & 0x18) >> 3);
1656 par->misc = ((block[17] & 0x06) >> 1);
1657 par->hAct_high = par->vAct_high = 0;
1658 if (par->synct == 3) {
1665 printk(KERN_INFO PFX
1666 "detected DFP panel size from EDID: %dx%d\n",
1667 par->panel_xres, par->panel_yres);
1668 par->got_dfpinfo = 1;
1672 static void riva_update_default_var(struct fb_info *info)
1674 struct fb_var_screeninfo *var = &rivafb_default_var;
1675 struct riva_par *par = (struct riva_par *) info->par;
1677 var->xres = par->panel_xres;
1678 var->yres = par->panel_yres;
1679 var->xres_virtual = par->panel_xres;
1680 var->yres_virtual = par->panel_yres;
1681 var->xoffset = var->yoffset = 0;
1682 var->bits_per_pixel = 8;
1683 var->pixclock = 100000000 / par->clock;
1684 var->left_margin = (par->hblank - par->hOver_plus - par->hSync_width);
1685 var->right_margin = par->hOver_plus;
1686 var->upper_margin = (par->vblank - par->vOver_plus - par->vSync_width);
1687 var->lower_margin = par->vOver_plus;
1688 var->hsync_len = par->hSync_width;
1689 var->vsync_len = par->vSync_width;
1692 if (par->synct == 3) {
1694 var->sync |= FB_SYNC_HOR_HIGH_ACT;
1696 var->sync |= FB_SYNC_VERT_HIGH_ACT;
1700 if (par->interlaced)
1701 var->vmode |= FB_VMODE_INTERLACED;
1703 var->accel_flags |= FB_ACCELF_TEXT;
1705 par->use_default_var = 1;
1709 static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1711 #ifdef CONFIG_PPC_OF
1712 if (!riva_get_EDID_OF(info, pdev))
1713 printk("rivafb: could not retrieve EDID from OF\n");
1715 /* XXX use other methods later */
1720 static void riva_get_dfpinfo(struct fb_info *info)
1722 struct riva_par *par = (struct riva_par *) info->par;
1724 if (riva_dfp_parse_EDID(par))
1725 riva_update_default_var(info);
1727 /* if user specified flatpanel, we respect that */
1728 if (par->got_dfpinfo == 1)
1732 /* ------------------------------------------------------------------------- *
1736 * ------------------------------------------------------------------------- */
1738 static int __devinit rivafb_probe(struct pci_dev *pd,
1739 const struct pci_device_id *ent)
1741 struct riva_chip_info *rci = &riva_chip_info[ent->driver_data];
1742 struct riva_par *default_par;
1743 struct fb_info *info;
1746 assert(rci != NULL);
1748 info = kmalloc(sizeof(struct fb_info), GFP_KERNEL);
1752 default_par = kmalloc(sizeof(struct riva_par), GFP_KERNEL);
1756 memset(info, 0, sizeof(struct fb_info));
1757 memset(default_par, 0, sizeof(struct riva_par));
1759 info->pixmap.addr = kmalloc(64 * 1024, GFP_KERNEL);
1760 if (info->pixmap.addr == NULL)
1761 goto err_out_kfree1;
1762 memset(info->pixmap.addr, 0, 64 * 1024);
1764 strcat(rivafb_fix.id, rci->name);
1765 default_par->riva.Architecture = rci->arch_rev;
1767 default_par->Chipset = (pd->vendor << 16) | pd->device;
1768 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1770 default_par->FlatPanel = flatpanel;
1772 printk(KERN_INFO PFX "flatpanel support enabled\n");
1773 default_par->forceCRTC = forceCRTC;
1775 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1776 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1779 /* enable IO and mem if not already done */
1782 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1783 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1784 pci_write_config_word(pd, PCI_COMMAND, cmd);
1787 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1788 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1790 if (!request_mem_region(rivafb_fix.mmio_start,
1791 rivafb_fix.mmio_len, "rivafb")) {
1792 printk(KERN_ERR PFX "cannot reserve MMIO region\n");
1793 goto err_out_kfree2;
1796 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1797 rivafb_fix.mmio_len);
1798 if (!default_par->ctrl_base) {
1799 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1800 goto err_out_free_base0;
1803 info->par = default_par;
1805 riva_get_EDID(info, pd);
1807 riva_get_dfpinfo(info);
1809 switch (default_par->riva.Architecture) {
1811 /* Riva128's PRAMIN is in the "framebuffer" space
1812 * Since these cards were never made with more than 8 megabytes
1813 * we can safely allocate this separately.
1815 if (!request_mem_region(rivafb_fix.smem_start + 0x00C00000,
1816 0x00008000, "rivafb")) {
1817 printk(KERN_ERR PFX "cannot reserve PRAMIN region\n");
1818 goto err_out_iounmap_ctrl;
1820 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1821 if (!default_par->riva.PRAMIN) {
1822 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1823 goto err_out_free_nv3_pramin;
1825 rivafb_fix.accel = FB_ACCEL_NV3;
1830 default_par->riva.PCRTC0 = (unsigned *)(default_par->ctrl_base + 0x00600000);
1831 default_par->riva.PRAMIN = (unsigned *)(default_par->ctrl_base + 0x00710000);
1832 rivafb_fix.accel = FB_ACCEL_NV4;
1836 riva_common_setup(default_par);
1838 if (default_par->riva.Architecture == NV_ARCH_03) {
1839 default_par->riva.PCRTC = default_par->riva.PCRTC0 = default_par->riva.PGRAPH;
1842 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
1843 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
1845 if (!request_mem_region(rivafb_fix.smem_start,
1846 rivafb_fix.smem_len, "rivafb")) {
1847 printk(KERN_ERR PFX "cannot reserve FB region\n");
1848 goto err_out_iounmap_nv3_pramin;
1851 info->screen_base = ioremap(rivafb_fix.smem_start,
1852 rivafb_fix.smem_len);
1853 if (!info->screen_base) {
1854 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1855 goto err_out_free_base1;
1860 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
1861 rivafb_fix.smem_len,
1862 MTRR_TYPE_WRCOMB, 1);
1863 if (default_par->mtrr.vram < 0) {
1864 printk(KERN_ERR PFX "unable to setup MTRR\n");
1866 default_par->mtrr.vram_valid = 1;
1867 /* let there be speed */
1868 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
1871 #endif /* CONFIG_MTRR */
1873 if (riva_set_fbinfo(info) < 0) {
1874 printk(KERN_ERR PFX "error setting initial video mode\n");
1875 goto err_out_iounmap_fb;
1878 if (register_framebuffer(info) < 0) {
1880 "error registering riva framebuffer\n");
1881 goto err_out_iounmap_fb;
1884 pci_set_drvdata(pd, info);
1886 printk(KERN_INFO PFX
1887 "PCI nVidia NV%x framebuffer ver %s (%s, %dMB @ 0x%lX)\n",
1888 default_par->riva.Architecture,
1891 info->fix.smem_len / (1024 * 1024),
1892 info->fix.smem_start);
1896 iounmap(info->screen_base);
1898 release_mem_region(rivafb_fix.smem_start, rivafb_fix.smem_len);
1899 err_out_iounmap_nv3_pramin:
1900 if (default_par->riva.Architecture == NV_ARCH_03)
1901 iounmap((caddr_t)default_par->riva.PRAMIN);
1902 err_out_free_nv3_pramin:
1903 if (default_par->riva.Architecture == NV_ARCH_03)
1904 release_mem_region(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1905 err_out_iounmap_ctrl:
1906 iounmap(default_par->ctrl_base);
1908 release_mem_region(rivafb_fix.mmio_start, rivafb_fix.mmio_len);
1910 kfree(info->pixmap.addr);
1919 static void __exit rivafb_remove(struct pci_dev *pd)
1921 struct fb_info *info = pci_get_drvdata(pd);
1922 struct riva_par *par = (struct riva_par *) info->par;
1927 unregister_framebuffer(info);
1929 if (par->mtrr.vram_valid)
1930 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1931 info->fix.smem_len);
1932 #endif /* CONFIG_MTRR */
1934 iounmap(par->ctrl_base);
1935 iounmap(info->screen_base);
1937 release_mem_region(info->fix.mmio_start,
1938 info->fix.mmio_len);
1939 release_mem_region(info->fix.smem_start,
1940 info->fix.smem_len);
1942 if (par->riva.Architecture == NV_ARCH_03) {
1943 iounmap((caddr_t)par->riva.PRAMIN);
1944 release_mem_region(info->fix.smem_start + 0x00C00000, 0x00008000);
1946 kfree(info->pixmap.addr);
1949 pci_set_drvdata(pd, NULL);
1952 /* ------------------------------------------------------------------------- *
1956 * ------------------------------------------------------------------------- */
1959 int __init rivafb_setup(char *options)
1963 if (!options || !*options)
1966 while ((this_opt = strsep(&options, ",")) != NULL) {
1967 if (!strncmp(this_opt, "forceCRTC", 9)) {
1971 if (!*p || !*(++p)) continue;
1972 forceCRTC = *p - '0';
1973 if (forceCRTC < 0 || forceCRTC > 1)
1975 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1978 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1982 mode_option = this_opt;
1986 #endif /* !MODULE */
1988 static struct pci_driver rivafb_driver = {
1990 .id_table = rivafb_pci_tbl,
1991 .probe = rivafb_probe,
1992 .remove = __exit_p(rivafb_remove),
1997 /* ------------------------------------------------------------------------- *
2001 * ------------------------------------------------------------------------- */
2003 int __init rivafb_init(void)
2005 if (pci_register_driver(&rivafb_driver) > 0)
2007 pci_unregister_driver(&rivafb_driver);
2013 static void __exit rivafb_exit(void)
2015 pci_unregister_driver(&rivafb_driver);
2018 module_init(rivafb_init);
2019 module_exit(rivafb_exit);
2021 MODULE_PARM(flatpanel, "i");
2022 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2023 MODULE_PARM(forceCRTC, "i");
2024 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2027 MODULE_PARM(nomtrr, "i");
2028 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2032 MODULE_AUTHOR("Ani Joshi, maintainer");
2033 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2034 MODULE_LICENSE("GPL");