1 /***************************************************************************\
3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
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14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
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17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
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28 |* U.S. Government End Users. This source code is a "commercial *|
29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30 |* consisting of "commercial computer software" and "commercial *|
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35 |* all U.S. Government End Users acquire the source code with only *|
36 |* those rights set forth herein. *|
38 \***************************************************************************/
41 * GPL licensing note -- nVidia is allowing a liberal interpretation of
42 * the documentation restriction above, to merely say that this nVidia's
43 * copyright and disclaimer should be included with all code derived
44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
47 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */
49 #include <linux/kernel.h>
50 #include <linux/pci.h>
51 #include <linux/pci_ids.h>
57 * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT
58 * operate identically (except TNT has more memory and better 3D quality.
65 return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x000006B0/4] & 0x01));
72 return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x00000700/4] & 0x01));
79 return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x00000700/4] & 0x01));
82 static void vgaLockUnlock
89 VGA_WR08(chip->PCIO, 0x3D4, 0x11);
90 cr11 = VGA_RD08(chip->PCIO, 0x3D5);
91 if(Lock) cr11 |= 0x80;
93 VGA_WR08(chip->PCIO, 0x3D5, cr11);
95 static void nv3LockUnlock
101 VGA_WR08(chip->PVIO, 0x3C4, 0x06);
102 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
103 vgaLockUnlock(chip, Lock);
105 static void nv4LockUnlock
111 VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
112 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
113 vgaLockUnlock(chip, Lock);
116 static int ShowHideCursor
123 cursor = chip->CurrentState->cursor1;
124 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
126 VGA_WR08(chip->PCIO, 0x3D4, 0x31);
127 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
128 return (cursor & 0x01);
131 /****************************************************************************\
133 * The video arbitration routines calculate some "magic" numbers. Fixes *
134 * the snow seen when accessing the framebuffer without it. *
135 * It just works (I hope). *
137 \****************************************************************************/
139 #define DEFAULT_GR_LWM 100
140 #define DEFAULT_VID_LWM 100
141 #define DEFAULT_GR_BURST_SIZE 256
142 #define DEFAULT_VID_BURST_SIZE 128
147 #define GFIFO_SIZE 320
148 #define GFIFO_SIZE_128 256
149 #define MFIFO_SIZE 120
150 #define VFIFO_SIZE 256
160 int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm;
178 int graphics_burst_size;
179 int video_burst_size;
180 int graphics_hi_priority;
181 int media_hi_priority;
201 int graphics_burst_size;
202 int video_burst_size;
221 int graphics_burst_size;
222 int video_burst_size;
239 static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
243 int vfsize, mfsize, gfsize;
244 int mburst_size = 32;
245 int mmisses, gmisses, vmisses;
247 int vlwm, glwm, mlwm;
261 if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128;
262 else max_gfsize = GFIFO_SIZE;
263 max_gfsize = GFIFO_SIZE;
268 if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc;
269 if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ;
270 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
271 vfsize = ns * ainfo->vdrain_rate / 1000000;
272 vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize;
274 if (state->enable_mp)
276 if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc;
280 if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ;
281 if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc;
282 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
283 gfsize = (ns * (long) ainfo->gdrain_rate)/1000000;
284 gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize;
287 if (!state->gr_during_vid && ainfo->vid_en)
288 if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once)
290 else if (ainfo->mocc < 0)
292 else if (ainfo->gocc< ainfo->by_gfacc)
295 else switch (ainfo->priority)
298 if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
300 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
302 else if (ainfo->mocc<0)
307 if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
309 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
311 else if (ainfo->mocc<0)
318 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
320 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
331 if (last==cur) misses = 0;
332 else if (ainfo->first_vacc) misses = vmisses;
334 ainfo->first_vacc = 0;
337 ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
338 vlwm = ns * ainfo->vdrain_rate/ 1000000;
339 vlwm = ainfo->vocc - vlwm;
341 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
342 ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000;
343 ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000;
344 ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000;
347 if (last==cur) misses = 0;
348 else if (ainfo->first_gacc) misses = gmisses;
350 ainfo->first_gacc = 0;
353 ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ;
354 glwm = ns * ainfo->gdrain_rate/1000000;
355 glwm = ainfo->gocc - glwm;
357 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
358 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
359 ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000;
360 ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000;
363 if (last==cur) misses = 0;
364 else if (ainfo->first_macc) misses = mmisses;
366 ainfo->first_macc = 0;
367 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
368 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
369 ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000;
370 ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000;
375 ainfo->converged = 0;
378 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
379 tmp = ns * ainfo->gdrain_rate/1000000;
380 if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize)
382 ainfo->converged = 0;
385 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
386 tmp = ns * ainfo->vdrain_rate/1000000;
387 if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE)
389 ainfo->converged = 0;
392 if (abs(ainfo->gocc) > max_gfsize)
394 ainfo->converged = 0;
397 if (abs(ainfo->vocc) > VFIFO_SIZE)
399 ainfo->converged = 0;
402 if (abs(ainfo->mocc) > MFIFO_SIZE)
404 ainfo->converged = 0;
407 if (abs(vfsize) > VFIFO_SIZE)
409 ainfo->converged = 0;
412 if (abs(gfsize) > max_gfsize)
414 ainfo->converged = 0;
417 if (abs(mfsize) > MFIFO_SIZE)
419 ainfo->converged = 0;
424 static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
426 long ens, vns, mns, gns;
427 int mmisses, gmisses, vmisses, eburst_size, mburst_size;
431 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5;
433 if (state->mem_aligned) gmisses = 2;
436 eburst_size = state->memory_width * 1;
438 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
439 ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000;
445 ainfo->engine_en = 1;
446 ainfo->converged = 1;
447 if (ainfo->engine_en)
449 ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
450 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0;
451 ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0;
452 ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0;
454 ainfo->first_vacc = 1;
455 ainfo->first_gacc = 1;
456 ainfo->first_macc = 1;
457 nv3_iterate(res_info, state,ainfo);
459 if (state->enable_mp)
461 mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
462 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000;
463 ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000;
464 ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000;
466 ainfo->first_vacc = 1;
467 ainfo->first_gacc = 1;
468 ainfo->first_macc = 0;
469 nv3_iterate(res_info, state,ainfo);
473 ainfo->first_vacc = 1;
474 ainfo->first_gacc = 0;
475 ainfo->first_macc = 1;
476 gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
477 ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000;
478 ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0;
479 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0;
480 ainfo->cur = GRAPHICS;
481 nv3_iterate(res_info, state,ainfo);
485 ainfo->first_vacc = 0;
486 ainfo->first_gacc = 1;
487 ainfo->first_macc = 1;
488 vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
489 ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000;
490 ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0;
491 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ;
493 nv3_iterate(res_info, state, ainfo);
495 if (ainfo->converged)
497 res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16;
498 res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32;
499 res_info->graphics_burst_size = ainfo->gburst_size;
500 res_info->video_burst_size = ainfo->vburst_size;
501 res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS);
502 res_info->media_hi_priority = (ainfo->priority == MPORT);
503 if (res_info->video_lwm > 160)
505 res_info->graphics_lwm = 256;
506 res_info->video_lwm = 128;
507 res_info->graphics_burst_size = 64;
508 res_info->video_burst_size = 64;
509 res_info->graphics_hi_priority = 0;
510 res_info->media_hi_priority = 0;
511 ainfo->converged = 0;
514 if (res_info->video_lwm > 128)
516 res_info->video_lwm = 128;
522 res_info->graphics_lwm = 256;
523 res_info->video_lwm = 128;
524 res_info->graphics_burst_size = 64;
525 res_info->video_burst_size = 64;
526 res_info->graphics_hi_priority = 0;
527 res_info->media_hi_priority = 0;
531 static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
536 for (p=0; p < 2; p++)
538 for (g=128 ; g > 32; g= g>> 1)
540 for (v=128; v >=32; v = v>> 1)
543 ainfo->gburst_size = g;
544 ainfo->vburst_size = v;
545 done = nv3_arb(res_info, state,ainfo);
546 if (done && (g==128))
547 if ((res_info->graphics_lwm + g) > 256)
558 static void nv3CalcArbitration
560 nv3_fifo_info * res_info,
561 nv3_sim_state * state
564 nv3_fifo_info save_info;
566 char res_gr, res_vid;
569 ainfo.vid_en = state->enable_video;
570 ainfo.vid_only_once = 0;
571 ainfo.gr_only_once = 0;
572 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
573 ainfo.vdrain_rate = (int) state->pclk_khz * 2;
574 if (state->video_scale != 0)
575 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale;
576 ainfo.mdrain_rate = 33000;
577 res_info->rtl_values = 0;
578 if (!state->gr_during_vid && state->enable_video)
580 ainfo.gr_only_once = 1;
582 ainfo.gdrain_rate = 0;
583 res_vid = nv3_get_param(res_info, state, &ainfo);
584 res_vid = ainfo.converged;
585 save_info.video_lwm = res_info->video_lwm;
586 save_info.video_burst_size = res_info->video_burst_size;
588 ainfo.vid_only_once = 1;
590 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
591 ainfo.vdrain_rate = 0;
592 res_gr = nv3_get_param(res_info, state, &ainfo);
593 res_gr = ainfo.converged;
594 res_info->video_lwm = save_info.video_lwm;
595 res_info->video_burst_size = save_info.video_burst_size;
596 res_info->valid = res_gr & res_vid;
600 if (!ainfo.gr_en) ainfo.gdrain_rate = 0;
601 if (!ainfo.vid_en) ainfo.vdrain_rate = 0;
602 res_gr = nv3_get_param(res_info, state, &ainfo);
603 res_info->valid = ainfo.converged;
606 static void nv3UpdateArbitrationSettings
615 nv3_fifo_info fifo_data;
616 nv3_sim_state sim_data;
617 unsigned int M, N, P, pll, MClk;
619 pll = chip->PRAMDAC0[0x00000504/4];
620 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
621 MClk = (N * chip->CrystalFreqKHz / M) >> P;
622 sim_data.pix_bpp = (char)pixelDepth;
623 sim_data.enable_video = 0;
624 sim_data.enable_mp = 0;
625 sim_data.video_scale = 1;
626 sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
627 sim_data.memory_width = 128;
629 sim_data.mem_latency = 9;
630 sim_data.mem_aligned = 1;
631 sim_data.mem_page_miss = 11;
632 sim_data.gr_during_vid = 0;
633 sim_data.pclk_khz = VClk;
634 sim_data.mclk_khz = MClk;
635 nv3CalcArbitration(&fifo_data, &sim_data);
638 int b = fifo_data.graphics_burst_size >> 4;
640 while (b >>= 1) (*burst)++;
641 *lwm = fifo_data.graphics_lwm >> 3;
649 static void nv4CalcArbitration
655 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
656 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
657 int found, mclk_extra, mclk_loop, cbs, m1, p1;
658 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
659 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
660 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
664 pclk_freq = arb->pclk_khz;
665 mclk_freq = arb->mclk_khz;
666 nvclk_freq = arb->nvclk_khz;
667 pagemiss = arb->mem_page_miss;
668 cas = arb->mem_latency;
669 width = arb->memory_width >> 6;
670 video_enable = arb->enable_video;
671 color_key_enable = arb->gr_during_vid;
673 align = arb->mem_aligned;
674 mp_enable = arb->enable_mp;
705 mclk_loop = mclks+mclk_extra;
706 us_m = mclk_loop *1000*1000 / mclk_freq;
707 us_n = nvclks*1000*1000 / nvclk_freq;
708 us_p = nvclks*1000*1000 / pclk_freq;
711 video_drain_rate = pclk_freq * 2;
712 crtc_drain_rate = pclk_freq * bpp/8;
716 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
717 if (nvclk_freq * 2 > mclk_freq * width)
718 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
720 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
721 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
722 vlwm = us_video * video_drain_rate/(1000*1000);
725 if (vlwm > 128) vbs = 64;
726 if (vlwm > (256-64)) vbs = 32;
727 if (nvclk_freq * 2 > mclk_freq * width)
728 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
730 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
731 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
738 clwm = us_crt * crtc_drain_rate/(1000*1000);
743 crtc_drain_rate = pclk_freq * bpp/8;
746 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
747 us_crt = cpm_us + us_m + us_n + us_p ;
748 clwm = us_crt * crtc_drain_rate/(1000*1000);
751 m1 = clwm + cbs - 512;
752 p1 = m1 * pclk_freq / mclk_freq;
754 if ((p1 < m1) && (m1 > 0))
758 if (mclk_extra ==0) found = 1;
761 else if (video_enable)
763 if ((clwm > 511) || (vlwm > 255))
767 if (mclk_extra ==0) found = 1;
777 if (mclk_extra ==0) found = 1;
783 if (clwm < 384) clwm = 384;
784 if (vlwm < 128) vlwm = 128;
786 fifo->graphics_lwm = data;
787 fifo->graphics_burst_size = 128;
788 data = (int)((vlwm+15));
789 fifo->video_lwm = data;
790 fifo->video_burst_size = vbs;
793 static void nv4UpdateArbitrationSettings
802 nv4_fifo_info fifo_data;
803 nv4_sim_state sim_data;
804 unsigned int M, N, P, pll, MClk, NVClk, cfg1;
806 pll = chip->PRAMDAC0[0x00000504/4];
807 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
808 MClk = (N * chip->CrystalFreqKHz / M) >> P;
809 pll = chip->PRAMDAC0[0x00000500/4];
810 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
811 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
812 cfg1 = chip->PFB[0x00000204/4];
813 sim_data.pix_bpp = (char)pixelDepth;
814 sim_data.enable_video = 0;
815 sim_data.enable_mp = 0;
816 sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
817 sim_data.mem_latency = (char)cfg1 & 0x0F;
818 sim_data.mem_aligned = 1;
819 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
820 sim_data.gr_during_vid = 0;
821 sim_data.pclk_khz = VClk;
822 sim_data.mclk_khz = MClk;
823 sim_data.nvclk_khz = NVClk;
824 nv4CalcArbitration(&fifo_data, &sim_data);
827 int b = fifo_data.graphics_burst_size >> 4;
829 while (b >>= 1) (*burst)++;
830 *lwm = fifo_data.graphics_lwm >> 3;
833 static void nv10CalcArbitration
835 nv10_fifo_info *fifo,
839 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
840 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
841 int nvclk_fill, us_extra;
842 int found, mclk_extra, mclk_loop, cbs, m1;
843 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
844 int us_m, us_m_min, us_n, us_p, video_drain_rate, crtc_drain_rate;
845 int vus_m, vus_n, vus_p;
846 int vpm_us, us_video, vlwm, cpm_us, us_crt,clwm;
848 int craw, m2us, us_pipe, us_pipe_min, vus_pipe, p1clk, p2;
849 int pclks_2_top_fifo, min_mclk_extra;
850 int us_min_mclk_extra;
853 pclk_freq = arb->pclk_khz; /* freq in KHz */
854 mclk_freq = arb->mclk_khz;
855 nvclk_freq = arb->nvclk_khz;
856 pagemiss = arb->mem_page_miss;
857 cas = arb->mem_latency;
858 width = arb->memory_width/64;
859 video_enable = arb->enable_video;
860 color_key_enable = arb->gr_during_vid;
862 align = arb->mem_aligned;
863 mp_enable = arb->enable_mp;
870 pclks = 4; /* lwm detect. */
872 nvclks = 3; /* lwm -> sync. */
873 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
875 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */
877 mclks += 1; /* arb_hp_req */
878 mclks += 5; /* ap_hp_req tiling pipeline */
880 mclks += 2; /* tc_req latency fifo */
881 mclks += 2; /* fb_cas_n_ memory request to fbio block */
882 mclks += 7; /* sm_d_rdv data returned from fbio block */
884 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
885 if (arb->memory_type == 0)
886 if (arb->memory_width == 64) /* 64 bit bus */
891 if (arb->memory_width == 64) /* 64 bit bus */
896 if ((!video_enable) && (arb->memory_width == 128))
898 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
903 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
904 /* mclk_extra = 4; */ /* Margin of error */
908 nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */
909 nvclks += 1; /* fbi_d_rdv_n */
910 nvclks += 1; /* Fbi_d_rdata */
911 nvclks += 1; /* crtfifo load */
914 mclks+=4; /* Mp can get in with a burst of 8. */
915 /* Extra clocks determined by heuristics */
923 mclk_loop = mclks+mclk_extra;
924 us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
925 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */
926 us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;
927 us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */
928 us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */
929 us_pipe = us_m + us_n + us_p;
930 us_pipe_min = us_m_min + us_n + us_p;
933 vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
934 vus_n = (4)*1000*1000 / nvclk_freq;/* nvclk latency in us */
935 vus_p = 0*1000*1000 / pclk_freq;/* pclk latency in us */
936 vus_pipe = vus_m + vus_n + vus_p;
939 video_drain_rate = pclk_freq * 4; /* MB/s */
940 crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */
942 vpagemiss = 1; /* self generating page miss */
943 vpagemiss += 1; /* One higher priority before */
945 crtpagemiss = 2; /* self generating page miss */
947 crtpagemiss += 1; /* if MA0 conflict */
949 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
951 us_video = vpm_us + vus_m; /* Video has separate read return path */
953 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
955 us_video /* Wait for video */
956 +cpm_us /* CRT Page miss */
957 +us_m + us_n +us_p /* other latency */
960 clwm = us_crt * crtc_drain_rate/(1000*1000);
961 clwm++; /* fixed point <= float_point - 1. Fixes that */
963 crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */
965 crtpagemiss = 1; /* self generating page miss */
966 crtpagemiss += 1; /* MA0 page miss */
968 crtpagemiss += 1; /* if MA0 conflict */
969 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
970 us_crt = cpm_us + us_m + us_n + us_p ;
971 clwm = us_crt * crtc_drain_rate/(1000*1000);
972 clwm++; /* fixed point <= float_point - 1. Fixes that */
976 // Another concern, only for high pclks so don't do this
978 // What happens if the latency to fetch the cbs is so large that
979 // fifo empties. In that case we need to have an alternate clwm value
980 // based off the total burst fetch
982 us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ;
983 us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq;
984 clwm_mt = us_crt * crtc_drain_rate/(1000*1000);
989 /* Finally, a heuristic check when width == 64 bits */
991 nvclk_fill = nvclk_freq * 8;
992 if(crtc_drain_rate * 100 >= nvclk_fill * 102)
993 clwm = 0xfff; /*Large number to fail */
995 else if(crtc_drain_rate * 100 >= nvclk_fill * 98) {
998 us_extra = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ;
1009 clwm_rnd_down = ((int)clwm/8)*8;
1010 if (clwm_rnd_down < clwm)
1013 m1 = clwm + cbs - 1024; /* Amount of overfill */
1014 m2us = us_pipe_min + us_min_mclk_extra;
1015 pclks_2_top_fifo = (1024-clwm)/(8*width);
1017 /* pclk cycles to drain */
1018 p1clk = m2us * pclk_freq/(1000*1000);
1019 p2 = p1clk * bpp / 8; /* bytes drained. */
1021 if((p2 < m1) && (m1 > 0)) {
1024 if(min_mclk_extra == 0) {
1026 found = 1; /* Can't adjust anymore! */
1028 cbs = cbs/2; /* reduce the burst size */
1034 if (clwm > 1023){ /* Have some margin */
1037 if(min_mclk_extra == 0)
1038 found = 1; /* Can't adjust anymore! */
1045 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;
1047 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */
1048 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs;
1050 /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */
1051 fifo->video_lwm = 1024; fifo->video_burst_size = 512;
1054 static void nv10UpdateArbitrationSettings
1057 unsigned pixelDepth,
1063 nv10_fifo_info fifo_data;
1064 nv10_sim_state sim_data;
1065 unsigned int M, N, P, pll, MClk, NVClk, cfg1;
1067 pll = chip->PRAMDAC0[0x00000504/4];
1068 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1069 MClk = (N * chip->CrystalFreqKHz / M) >> P;
1070 pll = chip->PRAMDAC0[0x00000500/4];
1071 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1072 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1073 cfg1 = chip->PFB[0x00000204/4];
1074 sim_data.pix_bpp = (char)pixelDepth;
1075 sim_data.enable_video = 0;
1076 sim_data.enable_mp = 0;
1077 sim_data.memory_type = (chip->PFB[0x00000200/4] & 0x01) ? 1 : 0;
1078 sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
1079 sim_data.mem_latency = (char)cfg1 & 0x0F;
1080 sim_data.mem_aligned = 1;
1081 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
1082 sim_data.gr_during_vid = 0;
1083 sim_data.pclk_khz = VClk;
1084 sim_data.mclk_khz = MClk;
1085 sim_data.nvclk_khz = NVClk;
1086 nv10CalcArbitration(&fifo_data, &sim_data);
1087 if (fifo_data.valid)
1089 int b = fifo_data.graphics_burst_size >> 4;
1091 while (b >>= 1) (*burst)++;
1092 *lwm = fifo_data.graphics_lwm >> 3;
1096 static void nForceUpdateArbitrationSettings
1099 unsigned pixelDepth,
1105 nv10_fifo_info fifo_data;
1106 nv10_sim_state sim_data;
1107 unsigned int M, N, P, pll, MClk, NVClk;
1108 unsigned int uMClkPostDiv;
1109 struct pci_dev *dev;
1111 dev = pci_find_slot(0, 3);
1112 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
1113 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
1115 if(!uMClkPostDiv) uMClkPostDiv = 4;
1116 MClk = 400000 / uMClkPostDiv;
1118 pll = chip->PRAMDAC0[0x00000500/4];
1119 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1120 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1121 sim_data.pix_bpp = (char)pixelDepth;
1122 sim_data.enable_video = 0;
1123 sim_data.enable_mp = 0;
1125 dev = pci_find_slot(0, 1);
1126 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
1127 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
1129 sim_data.memory_width = 64;
1130 sim_data.mem_latency = 3;
1131 sim_data.mem_aligned = 1;
1132 sim_data.mem_page_miss = 10;
1133 sim_data.gr_during_vid = 0;
1134 sim_data.pclk_khz = VClk;
1135 sim_data.mclk_khz = MClk;
1136 sim_data.nvclk_khz = NVClk;
1137 nv10CalcArbitration(&fifo_data, &sim_data);
1138 if (fifo_data.valid)
1140 int b = fifo_data.graphics_burst_size >> 4;
1142 while (b >>= 1) (*burst)++;
1143 *lwm = fifo_data.graphics_lwm >> 3;
1147 /****************************************************************************\
1149 * RIVA Mode State Routines *
1151 \****************************************************************************/
1154 * Calculate the Video Clock parameters for the PLL.
1156 static int CalcVClock
1166 unsigned lowM, highM, highP;
1167 unsigned DeltaNew, DeltaOld;
1168 unsigned VClk, Freq;
1171 DeltaOld = 0xFFFFFFFF;
1173 VClk = (unsigned)clockIn;
1175 if (chip->CrystalFreqKHz == 13500)
1178 highM = 13 - (chip->Architecture == NV_ARCH_03);
1183 highM = 14 - (chip->Architecture == NV_ARCH_03);
1186 highP = 4 - (chip->Architecture == NV_ARCH_03);
1187 for (P = 0; P <= highP; P ++)
1190 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
1192 for (M = lowM; M <= highM; M++)
1194 N = (VClk << P) * M / chip->CrystalFreqKHz;
1196 Freq = (chip->CrystalFreqKHz * N / M) >> P;
1198 DeltaNew = Freq - VClk;
1200 DeltaNew = VClk - Freq;
1201 if (DeltaNew < DeltaOld)
1207 DeltaOld = DeltaNew;
1213 return (DeltaOld != 0xFFFFFFFF);
1216 * Calculate extended mode parameters (SVGA) and save in a
1217 * mode state structure.
1219 static void CalcStateExt
1222 RIVA_HW_STATE *state,
1230 int pixelDepth, VClk, m, n, p;
1232 * Save mode parameters.
1234 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
1235 state->width = width;
1236 state->height = height;
1238 * Extended RIVA registers.
1240 pixelDepth = (bpp + 1)/8;
1241 CalcVClock(dotClock, &VClk, &m, &n, &p, chip);
1243 switch (chip->Architecture)
1246 nv3UpdateArbitrationSettings(VClk,
1248 &(state->arbitration0),
1249 &(state->arbitration1),
1251 state->cursor0 = 0x00;
1252 state->cursor1 = 0x78;
1253 state->cursor2 = 0x00000000;
1254 state->pllsel = 0x10010100;
1255 state->config = ((width + 31)/32)
1256 | (((pixelDepth > 2) ? 3 : pixelDepth) << 8)
1258 state->general = 0x00100100;
1259 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
1262 nv4UpdateArbitrationSettings(VClk,
1264 &(state->arbitration0),
1265 &(state->arbitration1),
1267 state->cursor0 = 0x00;
1268 state->cursor1 = 0xFC;
1269 state->cursor2 = 0x00000000;
1270 state->pllsel = 0x10000700;
1271 state->config = 0x00001114;
1272 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1273 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1278 if((chip->Chipset == NV_CHIP_IGEFORCE2) ||
1279 (chip->Chipset == NV_CHIP_0x01F0))
1281 nForceUpdateArbitrationSettings(VClk,
1283 &(state->arbitration0),
1284 &(state->arbitration1),
1287 nv10UpdateArbitrationSettings(VClk,
1289 &(state->arbitration0),
1290 &(state->arbitration1),
1293 state->cursor0 = 0x80 | (chip->CursorStart >> 17);
1294 state->cursor1 = (chip->CursorStart >> 11) << 2;
1295 state->cursor2 = chip->CursorStart >> 24;
1296 state->pllsel = 0x10000700;
1297 state->config = chip->PFB[0x00000200/4];
1298 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1299 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1303 /* Paul Richards: below if block borks things in kernel for some reason */
1304 /* Tony: Below is needed to set hardware in DirectColor */
1305 if((bpp != 8) && (chip->Architecture != NV_ARCH_03))
1306 state->general |= 0x00000030;
1308 state->vpll = (p << 16) | (n << 8) | m;
1309 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
1310 state->pixel = pixelDepth > 2 ? 3 : pixelDepth;
1318 state->pitch3 = pixelDepth * width;
1321 * Load fixed function state and pre-calculated/stored state.
1323 #define LOAD_FIXED_STATE(tbl,dev) \
1324 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
1325 chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
1326 #define LOAD_FIXED_STATE_8BPP(tbl,dev) \
1327 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
1328 chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
1329 #define LOAD_FIXED_STATE_15BPP(tbl,dev) \
1330 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
1331 chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
1332 #define LOAD_FIXED_STATE_16BPP(tbl,dev) \
1333 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
1334 chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
1335 #define LOAD_FIXED_STATE_32BPP(tbl,dev) \
1336 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
1337 chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
1338 static void UpdateFifoState
1345 switch (chip->Architecture)
1348 LOAD_FIXED_STATE(nv4,FIFO);
1350 chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
1356 * Initialize state for the RivaTriangle3D05 routines.
1358 LOAD_FIXED_STATE(nv10tri05,PGRAPH);
1359 LOAD_FIXED_STATE(nv10,FIFO);
1361 chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
1365 static void LoadStateExt
1368 RIVA_HW_STATE *state
1374 * Load HW fixed function state.
1376 LOAD_FIXED_STATE(Riva,PMC);
1377 LOAD_FIXED_STATE(Riva,PTIMER);
1378 switch (chip->Architecture)
1382 * Make sure frame buffer config gets set before loading PRAMIN.
1384 chip->PFB[0x00000200/4] = state->config;
1385 LOAD_FIXED_STATE(nv3,PFIFO);
1386 LOAD_FIXED_STATE(nv3,PRAMIN);
1387 LOAD_FIXED_STATE(nv3,PGRAPH);
1392 LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
1393 LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
1394 chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
1398 LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
1399 LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
1404 LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
1405 LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
1409 for (i = 0x00000; i < 0x00800; i++)
1410 chip->PRAMIN[0x00000502 + i] = (i << 12) | 0x03;
1411 chip->PGRAPH[0x00000630/4] = state->offset0;
1412 chip->PGRAPH[0x00000634/4] = state->offset1;
1413 chip->PGRAPH[0x00000638/4] = state->offset2;
1414 chip->PGRAPH[0x0000063C/4] = state->offset3;
1415 chip->PGRAPH[0x00000650/4] = state->pitch0;
1416 chip->PGRAPH[0x00000654/4] = state->pitch1;
1417 chip->PGRAPH[0x00000658/4] = state->pitch2;
1418 chip->PGRAPH[0x0000065C/4] = state->pitch3;
1422 * Make sure frame buffer config gets set before loading PRAMIN.
1424 chip->PFB[0x00000200/4] = state->config;
1425 LOAD_FIXED_STATE(nv4,PFIFO);
1426 LOAD_FIXED_STATE(nv4,PRAMIN);
1427 LOAD_FIXED_STATE(nv4,PGRAPH);
1431 LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
1432 LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
1433 chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
1436 LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
1437 LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
1438 chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
1442 LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
1443 LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
1448 LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
1449 LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
1453 chip->PGRAPH[0x00000640/4] = state->offset0;
1454 chip->PGRAPH[0x00000644/4] = state->offset1;
1455 chip->PGRAPH[0x00000648/4] = state->offset2;
1456 chip->PGRAPH[0x0000064C/4] = state->offset3;
1457 chip->PGRAPH[0x00000670/4] = state->pitch0;
1458 chip->PGRAPH[0x00000674/4] = state->pitch1;
1459 chip->PGRAPH[0x00000678/4] = state->pitch2;
1460 chip->PGRAPH[0x0000067C/4] = state->pitch3;
1465 if(chip->twoHeads) {
1466 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1467 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
1468 chip->LockUnlock(chip, 0);
1471 LOAD_FIXED_STATE(nv10,PFIFO);
1472 LOAD_FIXED_STATE(nv10,PRAMIN);
1473 LOAD_FIXED_STATE(nv10,PGRAPH);
1477 LOAD_FIXED_STATE_15BPP(nv10,PRAMIN);
1478 LOAD_FIXED_STATE_15BPP(nv10,PGRAPH);
1479 chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
1482 LOAD_FIXED_STATE_16BPP(nv10,PRAMIN);
1483 LOAD_FIXED_STATE_16BPP(nv10,PGRAPH);
1484 chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
1488 LOAD_FIXED_STATE_32BPP(nv10,PRAMIN);
1489 LOAD_FIXED_STATE_32BPP(nv10,PGRAPH);
1494 LOAD_FIXED_STATE_8BPP(nv10,PRAMIN);
1495 LOAD_FIXED_STATE_8BPP(nv10,PGRAPH);
1500 if(chip->Architecture == NV_ARCH_10) {
1501 chip->PGRAPH[0x00000640/4] = state->offset0;
1502 chip->PGRAPH[0x00000644/4] = state->offset1;
1503 chip->PGRAPH[0x00000648/4] = state->offset2;
1504 chip->PGRAPH[0x0000064C/4] = state->offset3;
1505 chip->PGRAPH[0x00000670/4] = state->pitch0;
1506 chip->PGRAPH[0x00000674/4] = state->pitch1;
1507 chip->PGRAPH[0x00000678/4] = state->pitch2;
1508 chip->PGRAPH[0x0000067C/4] = state->pitch3;
1509 chip->PGRAPH[0x00000680/4] = state->pitch3;
1511 chip->PGRAPH[0x00000820/4] = state->offset0;
1512 chip->PGRAPH[0x00000824/4] = state->offset1;
1513 chip->PGRAPH[0x00000828/4] = state->offset2;
1514 chip->PGRAPH[0x0000082C/4] = state->offset3;
1515 chip->PGRAPH[0x00000850/4] = state->pitch0;
1516 chip->PGRAPH[0x00000854/4] = state->pitch1;
1517 chip->PGRAPH[0x00000858/4] = state->pitch2;
1518 chip->PGRAPH[0x0000085C/4] = state->pitch3;
1519 chip->PGRAPH[0x00000860/4] = state->pitch3;
1520 chip->PGRAPH[0x00000864/4] = state->pitch3;
1521 chip->PGRAPH[0x000009A4/4] = chip->PFB[0x00000200/4];
1522 chip->PGRAPH[0x000009A8/4] = chip->PFB[0x00000204/4];
1524 if(chip->twoHeads) {
1525 chip->PCRTC0[0x00000860/4] = state->head;
1526 chip->PCRTC0[0x00002860/4] = state->head2;
1528 chip->PRAMDAC[0x00000404/4] |= (1 << 25);
1530 chip->PMC[0x00008704/4] = 1;
1531 chip->PMC[0x00008140/4] = 0;
1532 chip->PMC[0x00008920/4] = 0;
1533 chip->PMC[0x00008924/4] = 0;
1534 chip->PMC[0x00008908/4] = 0x01ffffff;
1535 chip->PMC[0x0000890C/4] = 0x01ffffff;
1536 chip->PMC[0x00001588/4] = 0;
1538 chip->PFB[0x00000240/4] = 0;
1539 chip->PFB[0x00000244/4] = 0;
1540 chip->PFB[0x00000248/4] = 0;
1541 chip->PFB[0x0000024C/4] = 0;
1542 chip->PFB[0x00000250/4] = 0;
1543 chip->PFB[0x00000254/4] = 0;
1544 chip->PFB[0x00000258/4] = 0;
1545 chip->PFB[0x0000025C/4] = 0;
1547 chip->PGRAPH[0x00000B00/4] = chip->PFB[0x00000240/4];
1548 chip->PGRAPH[0x00000B04/4] = chip->PFB[0x00000244/4];
1549 chip->PGRAPH[0x00000B08/4] = chip->PFB[0x00000248/4];
1550 chip->PGRAPH[0x00000B0C/4] = chip->PFB[0x0000024C/4];
1551 chip->PGRAPH[0x00000B10/4] = chip->PFB[0x00000250/4];
1552 chip->PGRAPH[0x00000B14/4] = chip->PFB[0x00000254/4];
1553 chip->PGRAPH[0x00000B18/4] = chip->PFB[0x00000258/4];
1554 chip->PGRAPH[0x00000B1C/4] = chip->PFB[0x0000025C/4];
1555 chip->PGRAPH[0x00000B20/4] = chip->PFB[0x00000260/4];
1556 chip->PGRAPH[0x00000B24/4] = chip->PFB[0x00000264/4];
1557 chip->PGRAPH[0x00000B28/4] = chip->PFB[0x00000268/4];
1558 chip->PGRAPH[0x00000B2C/4] = chip->PFB[0x0000026C/4];
1559 chip->PGRAPH[0x00000B30/4] = chip->PFB[0x00000270/4];
1560 chip->PGRAPH[0x00000B34/4] = chip->PFB[0x00000274/4];
1561 chip->PGRAPH[0x00000B38/4] = chip->PFB[0x00000278/4];
1562 chip->PGRAPH[0x00000B3C/4] = chip->PFB[0x0000027C/4];
1563 chip->PGRAPH[0x00000B40/4] = chip->PFB[0x00000280/4];
1564 chip->PGRAPH[0x00000B44/4] = chip->PFB[0x00000284/4];
1565 chip->PGRAPH[0x00000B48/4] = chip->PFB[0x00000288/4];
1566 chip->PGRAPH[0x00000B4C/4] = chip->PFB[0x0000028C/4];
1567 chip->PGRAPH[0x00000B50/4] = chip->PFB[0x00000290/4];
1568 chip->PGRAPH[0x00000B54/4] = chip->PFB[0x00000294/4];
1569 chip->PGRAPH[0x00000B58/4] = chip->PFB[0x00000298/4];
1570 chip->PGRAPH[0x00000B5C/4] = chip->PFB[0x0000029C/4];
1571 chip->PGRAPH[0x00000B60/4] = chip->PFB[0x000002A0/4];
1572 chip->PGRAPH[0x00000B64/4] = chip->PFB[0x000002A4/4];
1573 chip->PGRAPH[0x00000B68/4] = chip->PFB[0x000002A8/4];
1574 chip->PGRAPH[0x00000B6C/4] = chip->PFB[0x000002AC/4];
1575 chip->PGRAPH[0x00000B70/4] = chip->PFB[0x000002B0/4];
1576 chip->PGRAPH[0x00000B74/4] = chip->PFB[0x000002B4/4];
1577 chip->PGRAPH[0x00000B78/4] = chip->PFB[0x000002B8/4];
1578 chip->PGRAPH[0x00000B7C/4] = chip->PFB[0x000002BC/4];
1579 chip->PGRAPH[0x00000F40/4] = 0x10000000;
1580 chip->PGRAPH[0x00000F44/4] = 0x00000000;
1581 chip->PGRAPH[0x00000F50/4] = 0x00000040;
1582 chip->PGRAPH[0x00000F54/4] = 0x00000008;
1583 chip->PGRAPH[0x00000F50/4] = 0x00000200;
1584 for (i = 0; i < (3*16); i++)
1585 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1586 chip->PGRAPH[0x00000F50/4] = 0x00000040;
1587 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1588 chip->PGRAPH[0x00000F50/4] = 0x00000800;
1589 for (i = 0; i < (16*16); i++)
1590 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1591 chip->PGRAPH[0x00000F40/4] = 0x30000000;
1592 chip->PGRAPH[0x00000F44/4] = 0x00000004;
1593 chip->PGRAPH[0x00000F50/4] = 0x00006400;
1594 for (i = 0; i < (59*4); i++)
1595 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1596 chip->PGRAPH[0x00000F50/4] = 0x00006800;
1597 for (i = 0; i < (47*4); i++)
1598 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1599 chip->PGRAPH[0x00000F50/4] = 0x00006C00;
1600 for (i = 0; i < (3*4); i++)
1601 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1602 chip->PGRAPH[0x00000F50/4] = 0x00007000;
1603 for (i = 0; i < (19*4); i++)
1604 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1605 chip->PGRAPH[0x00000F50/4] = 0x00007400;
1606 for (i = 0; i < (12*4); i++)
1607 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1608 chip->PGRAPH[0x00000F50/4] = 0x00007800;
1609 for (i = 0; i < (12*4); i++)
1610 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1611 chip->PGRAPH[0x00000F50/4] = 0x00004400;
1612 for (i = 0; i < (8*4); i++)
1613 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1614 chip->PGRAPH[0x00000F50/4] = 0x00000000;
1615 for (i = 0; i < 16; i++)
1616 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1617 chip->PGRAPH[0x00000F50/4] = 0x00000040;
1618 for (i = 0; i < 4; i++)
1619 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1621 chip->PCRTC[0x00000810/4] = state->cursorConfig;
1623 if(chip->flatPanel) {
1624 if((chip->Chipset & 0x0ff0) == 0x0110) {
1625 chip->PRAMDAC[0x0528/4] = state->dither;
1627 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1628 chip->PRAMDAC[0x083C/4] = state->dither;
1631 VGA_WR08(chip->PCIO, 0x03D4, 0x53);
1632 VGA_WR08(chip->PCIO, 0x03D5, 0);
1633 VGA_WR08(chip->PCIO, 0x03D4, 0x54);
1634 VGA_WR08(chip->PCIO, 0x03D5, 0);
1635 VGA_WR08(chip->PCIO, 0x03D4, 0x21);
1636 VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
1639 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1640 VGA_WR08(chip->PCIO, 0x03D5, state->extra);
1642 LOAD_FIXED_STATE(Riva,FIFO);
1643 UpdateFifoState(chip);
1645 * Load HW mode state.
1647 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1648 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
1649 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1650 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
1651 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1652 VGA_WR08(chip->PCIO, 0x03D5, state->screen);
1653 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1654 VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
1655 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1656 VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
1657 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1658 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
1659 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1660 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
1661 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1662 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
1663 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1664 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
1665 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1666 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
1667 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1668 VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
1670 if(!chip->flatPanel) {
1671 chip->PRAMDAC0[0x00000508/4] = state->vpll;
1672 chip->PRAMDAC0[0x0000050C/4] = state->pllsel;
1674 chip->PRAMDAC0[0x00000520/4] = state->vpll2;
1676 chip->PRAMDAC[0x00000848/4] = state->scale;
1678 chip->PRAMDAC[0x00000600/4] = state->general;
1681 * Turn off VBlank enable and reset.
1683 chip->PCRTC[0x00000140/4] = 0;
1684 chip->PCRTC[0x00000100/4] = chip->VBlankBit;
1686 * Set interrupt enable.
1688 chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01;
1690 * Set current state pointer.
1692 chip->CurrentState = state;
1694 * Reset FIFO free and empty counts.
1696 chip->FifoFreeCount = 0;
1697 /* Free count from first subchannel */
1698 chip->FifoEmptyCount = chip->Rop->FifoFree;
1700 static void UnloadStateExt
1703 RIVA_HW_STATE *state
1707 * Save current HW state.
1709 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1710 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);
1711 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1712 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);
1713 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1714 state->screen = VGA_RD08(chip->PCIO, 0x03D5);
1715 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1716 state->pixel = VGA_RD08(chip->PCIO, 0x03D5);
1717 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1718 state->horiz = VGA_RD08(chip->PCIO, 0x03D5);
1719 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1720 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
1721 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1722 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
1723 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1724 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
1725 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1726 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
1727 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1728 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
1729 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1730 state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
1731 state->vpll = chip->PRAMDAC0[0x00000508/4];
1732 state->vpll2 = chip->PRAMDAC0[0x00000520/4];
1733 state->pllsel = chip->PRAMDAC0[0x0000050C/4];
1734 state->general = chip->PRAMDAC[0x00000600/4];
1735 state->scale = chip->PRAMDAC[0x00000848/4];
1736 state->config = chip->PFB[0x00000200/4];
1737 switch (chip->Architecture)
1740 state->offset0 = chip->PGRAPH[0x00000630/4];
1741 state->offset1 = chip->PGRAPH[0x00000634/4];
1742 state->offset2 = chip->PGRAPH[0x00000638/4];
1743 state->offset3 = chip->PGRAPH[0x0000063C/4];
1744 state->pitch0 = chip->PGRAPH[0x00000650/4];
1745 state->pitch1 = chip->PGRAPH[0x00000654/4];
1746 state->pitch2 = chip->PGRAPH[0x00000658/4];
1747 state->pitch3 = chip->PGRAPH[0x0000065C/4];
1750 state->offset0 = chip->PGRAPH[0x00000640/4];
1751 state->offset1 = chip->PGRAPH[0x00000644/4];
1752 state->offset2 = chip->PGRAPH[0x00000648/4];
1753 state->offset3 = chip->PGRAPH[0x0000064C/4];
1754 state->pitch0 = chip->PGRAPH[0x00000670/4];
1755 state->pitch1 = chip->PGRAPH[0x00000674/4];
1756 state->pitch2 = chip->PGRAPH[0x00000678/4];
1757 state->pitch3 = chip->PGRAPH[0x0000067C/4];
1762 state->offset0 = chip->PGRAPH[0x00000640/4];
1763 state->offset1 = chip->PGRAPH[0x00000644/4];
1764 state->offset2 = chip->PGRAPH[0x00000648/4];
1765 state->offset3 = chip->PGRAPH[0x0000064C/4];
1766 state->pitch0 = chip->PGRAPH[0x00000670/4];
1767 state->pitch1 = chip->PGRAPH[0x00000674/4];
1768 state->pitch2 = chip->PGRAPH[0x00000678/4];
1769 state->pitch3 = chip->PGRAPH[0x0000067C/4];
1770 if(chip->twoHeads) {
1771 state->head = chip->PCRTC0[0x00000860/4];
1772 state->head2 = chip->PCRTC0[0x00002860/4];
1773 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1774 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
1776 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1777 state->extra = VGA_RD08(chip->PCIO, 0x03D5);
1778 state->cursorConfig = chip->PCRTC[0x00000810/4];
1780 if((chip->Chipset & 0x0ff0) == 0x0110) {
1781 state->dither = chip->PRAMDAC[0x0528/4];
1783 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1784 state->dither = chip->PRAMDAC[0x083C/4];
1789 static void SetStartAddress
1795 chip->PCRTC[0x800/4] = start;
1798 static void SetStartAddress3
1804 int offset = start >> 2;
1805 int pan = (start & 3) << 1;
1809 * Unlock extended registers.
1811 chip->LockUnlock(chip, 0);
1813 * Set start address.
1815 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
1817 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
1819 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1820 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
1821 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1822 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
1824 * 4 pixel pan register.
1826 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
1827 VGA_WR08(chip->PCIO, 0x3C0, 0x13);
1828 VGA_WR08(chip->PCIO, 0x3C0, pan);
1830 static void nv3SetSurfaces2D
1837 RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
1839 RIVA_FIFO_FREE(*chip,Tri03,5);
1840 chip->FIFO[0x00003800] = 0x80000003;
1841 Surface->Offset = surf0;
1842 chip->FIFO[0x00003800] = 0x80000004;
1843 Surface->Offset = surf1;
1844 chip->FIFO[0x00003800] = 0x80000013;
1846 static void nv4SetSurfaces2D
1853 RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
1855 chip->FIFO[0x00003800] = 0x80000003;
1856 Surface->Offset = surf0;
1857 chip->FIFO[0x00003800] = 0x80000004;
1858 Surface->Offset = surf1;
1859 chip->FIFO[0x00003800] = 0x80000014;
1861 static void nv10SetSurfaces2D
1868 RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
1870 chip->FIFO[0x00003800] = 0x80000003;
1871 Surface->Offset = surf0;
1872 chip->FIFO[0x00003800] = 0x80000004;
1873 Surface->Offset = surf1;
1874 chip->FIFO[0x00003800] = 0x80000014;
1876 static void nv3SetSurfaces3D
1883 RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
1885 RIVA_FIFO_FREE(*chip,Tri03,5);
1886 chip->FIFO[0x00003800] = 0x80000005;
1887 Surface->Offset = surf0;
1888 chip->FIFO[0x00003800] = 0x80000006;
1889 Surface->Offset = surf1;
1890 chip->FIFO[0x00003800] = 0x80000013;
1892 static void nv4SetSurfaces3D
1899 RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
1901 chip->FIFO[0x00003800] = 0x80000005;
1902 Surface->Offset = surf0;
1903 chip->FIFO[0x00003800] = 0x80000006;
1904 Surface->Offset = surf1;
1905 chip->FIFO[0x00003800] = 0x80000014;
1907 static void nv10SetSurfaces3D
1914 RivaSurface3D *Surfaces3D = (RivaSurface3D *)&(chip->FIFO[0x0000E000/4]);
1916 RIVA_FIFO_FREE(*chip,Tri03,4);
1917 chip->FIFO[0x00003800] = 0x80000007;
1918 Surfaces3D->RenderBufferOffset = surf0;
1919 Surfaces3D->ZBufferOffset = surf1;
1920 chip->FIFO[0x00003800] = 0x80000014;
1923 /****************************************************************************\
1925 * Probe RIVA Chip Configuration *
1927 \****************************************************************************/
1929 static void nv3GetConfig
1935 * Fill in chip configuration.
1937 if (chip->PFB[0x00000000/4] & 0x00000020)
1939 if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
1940 && ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02))
1945 chip->RamBandwidthKBytesPerSec = 800000;
1946 switch (chip->PFB[0x00000000/4] & 0x03)
1949 chip->RamAmountKBytes = 1024 * 4;
1952 chip->RamAmountKBytes = 1024 * 2;
1955 chip->RamAmountKBytes = 1024 * 8;
1961 chip->RamBandwidthKBytesPerSec = 1000000;
1962 chip->RamAmountKBytes = 1024 * 8;
1970 chip->RamBandwidthKBytesPerSec = 1000000;
1971 switch (chip->PFB[0x00000000/4] & 0x00000003)
1974 chip->RamAmountKBytes = 1024 * 8;
1977 chip->RamAmountKBytes = 1024 * 4;
1980 chip->RamAmountKBytes = 1024 * 2;
1984 chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
1985 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
1986 chip->VBlankBit = 0x00000100;
1987 chip->MaxVClockFreqKHz = 256000;
1989 * Set chip functions.
1991 chip->Busy = nv3Busy;
1992 chip->ShowHideCursor = ShowHideCursor;
1993 chip->CalcStateExt = CalcStateExt;
1994 chip->LoadStateExt = LoadStateExt;
1995 chip->UnloadStateExt = UnloadStateExt;
1996 chip->SetStartAddress = SetStartAddress3;
1997 chip->SetSurfaces2D = nv3SetSurfaces2D;
1998 chip->SetSurfaces3D = nv3SetSurfaces3D;
1999 chip->LockUnlock = nv3LockUnlock;
2001 static void nv4GetConfig
2007 * Fill in chip configuration.
2009 if (chip->PFB[0x00000000/4] & 0x00000100)
2011 chip->RamAmountKBytes = ((chip->PFB[0x00000000/4] >> 12) & 0x0F) * 1024 * 2
2016 switch (chip->PFB[0x00000000/4] & 0x00000003)
2019 chip->RamAmountKBytes = 1024 * 32;
2022 chip->RamAmountKBytes = 1024 * 4;
2025 chip->RamAmountKBytes = 1024 * 8;
2029 chip->RamAmountKBytes = 1024 * 16;
2033 switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003)
2036 chip->RamBandwidthKBytesPerSec = 800000;
2039 chip->RamBandwidthKBytesPerSec = 1000000;
2042 chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
2043 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
2044 chip->VBlankBit = 0x00000001;
2045 chip->MaxVClockFreqKHz = 350000;
2047 * Set chip functions.
2049 chip->Busy = nv4Busy;
2050 chip->ShowHideCursor = ShowHideCursor;
2051 chip->CalcStateExt = CalcStateExt;
2052 chip->LoadStateExt = LoadStateExt;
2053 chip->UnloadStateExt = UnloadStateExt;
2054 chip->SetStartAddress = SetStartAddress;
2055 chip->SetSurfaces2D = nv4SetSurfaces2D;
2056 chip->SetSurfaces3D = nv4SetSurfaces3D;
2057 chip->LockUnlock = nv4LockUnlock;
2059 static void nv10GetConfig
2062 unsigned int chipset
2065 struct pci_dev* dev;
2069 /* turn on big endian register access */
2070 chip->PMC[0x00000004/4] = 0x01000001;
2074 * Fill in chip configuration.
2076 if(chipset == NV_CHIP_IGEFORCE2) {
2077 dev = pci_find_slot(0, 1);
2078 pci_read_config_dword(dev, 0x7C, &amt);
2079 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
2080 } else if(chipset == NV_CHIP_0x01F0) {
2081 dev = pci_find_slot(0, 1);
2082 pci_read_config_dword(dev, 0x84, &amt);
2083 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
2085 switch ((chip->PFB[0x0000020C/4] >> 20) & 0x000000FF)
2088 chip->RamAmountKBytes = 1024 * 2;
2091 chip->RamAmountKBytes = 1024 * 4;
2094 chip->RamAmountKBytes = 1024 * 8;
2097 chip->RamAmountKBytes = 1024 * 16;
2100 chip->RamAmountKBytes = 1024 * 32;
2103 chip->RamAmountKBytes = 1024 * 64;
2106 chip->RamAmountKBytes = 1024 * 128;
2109 chip->RamAmountKBytes = 1024 * 16;
2113 switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003)
2116 chip->RamBandwidthKBytesPerSec = 800000;
2119 chip->RamBandwidthKBytesPerSec = 1000000;
2122 chip->CrystalFreqKHz = (chip->PEXTDEV[0x0000/4] & (1 << 6)) ? 14318 :
2125 switch (chipset & 0x0ff0) {
2131 if(chip->PEXTDEV[0x0000/4] & (1 << 22))
2132 chip->CrystalFreqKHz = 27000;
2138 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;
2139 chip->CURSOR = NULL; /* can't set this here */
2140 chip->VBlankBit = 0x00000001;
2141 chip->MaxVClockFreqKHz = 350000;
2143 * Set chip functions.
2145 chip->Busy = nv10Busy;
2146 chip->ShowHideCursor = ShowHideCursor;
2147 chip->CalcStateExt = CalcStateExt;
2148 chip->LoadStateExt = LoadStateExt;
2149 chip->UnloadStateExt = UnloadStateExt;
2150 chip->SetStartAddress = SetStartAddress;
2151 chip->SetSurfaces2D = nv10SetSurfaces2D;
2152 chip->SetSurfaces3D = nv10SetSurfaces3D;
2153 chip->LockUnlock = nv4LockUnlock;
2155 switch(chipset & 0x0ff0) {
2162 chip->twoHeads = TRUE;
2165 chip->twoHeads = FALSE;
2172 unsigned int chipset
2176 * Save this so future SW know whats it's dealing with.
2178 chip->Version = RIVA_SW_VERSION;
2180 * Chip specific configuration.
2182 switch (chip->Architecture)
2193 nv10GetConfig(chip, chipset);
2198 chip->Chipset = chipset;
2200 * Fill in FIFO pointers.
2202 chip->Rop = (RivaRop *)&(chip->FIFO[0x00000000/4]);
2203 chip->Clip = (RivaClip *)&(chip->FIFO[0x00002000/4]);
2204 chip->Patt = (RivaPattern *)&(chip->FIFO[0x00004000/4]);
2205 chip->Pixmap = (RivaPixmap *)&(chip->FIFO[0x00006000/4]);
2206 chip->Blt = (RivaScreenBlt *)&(chip->FIFO[0x00008000/4]);
2207 chip->Bitmap = (RivaBitmap *)&(chip->FIFO[0x0000A000/4]);
2208 chip->Line = (RivaLine *)&(chip->FIFO[0x0000C000/4]);
2209 chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);