6 * Author: Hannu Mallat <hmallat@cc.hut.fi>
8 * Copyright © 1999 Hannu Mallat
11 * Created : Thu Sep 23 18:17:43 1999, hmallat
12 * Last modified: Tue Nov 2 21:19:47 1999, hmallat
14 * Lots of the information here comes from the Daryll Strauss' Banshee
15 * patches to the XF86 server, and the rest comes from the 3dfx
16 * Banshee specification. I'm very much indebted to Daryll for his
17 * work on the X server.
19 * Voodoo3 support was contributed Harold Oga. Lots of additions
20 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
21 * Kesmarki. Thanks guys!
23 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
24 * behave very differently from the Voodoo3/4/5. For anyone wanting to
25 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
26 * located at http://www.sourceforge.net/projects/sstfb).
28 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
29 * I do wish the next version is a bit more complete. Without the XF86
30 * patches I couldn't have gotten even this far... for instance, the
31 * extensions to the VGA register set go completely unmentioned in the
32 * spec! Also, lots of references are made to the 'SST core', but no
33 * spec is publicly available, AFAIK.
35 * The structure of this driver comes pretty much from the Permedia
36 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
39 * - support for 16/32 bpp needs fixing (funky bootup penguin)
40 * - multihead support (basically need to support an array of fb_infos)
41 * - support other architectures (PPC, Alpha); does the fact that the VGA
42 * core can be accessed only thru I/O (not memory mapped) complicate
47 * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons
49 * 0.1.3 (released 1999-11-02) added Attila's panning support, code
50 * reorg, hwcursor address page size alignment
51 * (for mmaping both frame buffer and regs),
52 * and my changes to get rid of hardcoded
53 * VGA i/o register locations (uses PCI
54 * configuration info now)
55 * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and
57 * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga.
58 * 0.1.0 (released 1999-10-06) initial version
62 #include <linux/config.h>
63 #include <linux/module.h>
64 #include <linux/kernel.h>
65 #include <linux/errno.h>
66 #include <linux/string.h>
68 #include <linux/tty.h>
69 #include <linux/slab.h>
70 #include <linux/delay.h>
71 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/pci.h>
75 #include <linux/nvram.h>
77 #include <linux/timer.h>
78 #include <linux/spinlock.h>
80 #include <video/tdfx.h>
84 #define DPRINTK(a,b...) printk(KERN_DEBUG "fb: %s: " a, __FUNCTION__ , ## b)
86 #define DPRINTK(a,b...)
89 #define BANSHEE_MAX_PIXCLOCK 270000
90 #define VOODOO3_MAX_PIXCLOCK 300000
91 #define VOODOO5_MAX_PIXCLOCK 350000
93 static struct fb_fix_screeninfo tdfx_fix __initdata = {
95 .type = FB_TYPE_PACKED_PIXELS,
96 .visual = FB_VISUAL_PSEUDOCOLOR,
99 .accel = FB_ACCEL_3DFX_BANSHEE
102 static struct fb_var_screeninfo tdfx_var __initdata = {
103 /* "640x480, 8 bpp @ 60 Hz */
107 .yres_virtual = 1024,
112 .activate = FB_ACTIVATE_NOW,
115 .accel_flags = FB_ACCELF_TEXT,
123 .vmode = FB_VMODE_NONINTERLACED
127 * PCI driver prototypes
129 static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id);
130 static void tdfxfb_remove(struct pci_dev *pdev);
132 static struct pci_device_id tdfxfb_id_table[] = {
133 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
134 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
136 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
137 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
139 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
145 static struct pci_driver tdfxfb_driver = {
147 .id_table = tdfxfb_id_table,
148 .probe = tdfxfb_probe,
149 .remove = __devexit_p(tdfxfb_remove),
152 MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
155 * Frame buffer device API
157 int tdfxfb_init(void);
158 void tdfxfb_setup(char *options, int *ints);
160 static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb);
161 static int tdfxfb_set_par(struct fb_info *info);
162 static int tdfxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
163 u_int transp, struct fb_info *info);
164 static int tdfxfb_blank(int blank, struct fb_info *info);
165 static int tdfxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
166 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
167 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
168 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image);
169 #ifdef CONFIG_FB_3DFX_ACCEL
170 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor);
171 #else /* !CONFIG_FB_3DFX_ACCEL */
172 #define tdfxfb_cursor soft_cursor
173 #endif /* CONFIG_FB_3DFX_ACCEL */
174 static int banshee_wait_idle(struct fb_info *info);
176 static struct fb_ops tdfxfb_ops = {
177 .owner = THIS_MODULE,
178 .fb_check_var = tdfxfb_check_var,
179 .fb_set_par = tdfxfb_set_par,
180 .fb_setcolreg = tdfxfb_setcolreg,
181 .fb_blank = tdfxfb_blank,
182 .fb_pan_display = tdfxfb_pan_display,
183 .fb_fillrect = tdfxfb_fillrect,
184 .fb_copyarea = tdfxfb_copyarea,
185 .fb_imageblit = tdfxfb_imageblit,
186 .fb_sync = banshee_wait_idle,
187 .fb_cursor = tdfxfb_cursor,
191 * do_xxx: Hardware-specific functions
193 static u32 do_calc_pll(int freq, int *freq_out);
194 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg);
195 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short);
200 static int nopan = 0;
201 static int nowrap = 1; // not implemented (yet)
202 static int inverse = 0;
203 static char *mode_option __initdata = NULL;
205 /* -------------------------------------------------------------------------
206 * Hardware-specific funcions
207 * ------------------------------------------------------------------------- */
210 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) { return inb(reg); }
211 static inline u16 vga_inw(struct tdfx_par *par, u32 reg) { return inw(reg); }
212 static inline u16 vga_inl(struct tdfx_par *par, u32 reg) { return inl(reg); }
214 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) { outb(val, reg); }
215 static inline void vga_outw(struct tdfx_par *par, u32 reg, u16 val) { outw(val, reg); }
216 static inline void vga_outl(struct tdfx_par *par, u32 reg, u32 val) { outl(val, reg); }
218 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) {
219 return inb(par->iobase + reg - 0x300);
221 static inline u16 vga_inw(struct tdfx_par *par, u32 reg) {
222 return inw(par->iobase + reg - 0x300);
224 static inline u16 vga_inl(struct tdfx_par *par, u32 reg) {
225 return inl(par->iobase + reg - 0x300);
227 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) {
228 outb(val, par->iobase + reg - 0x300);
230 static inline void vga_outw(struct tdfx_par *par, u32 reg, u16 val) {
231 outw(val, par->iobase + reg - 0x300);
233 static inline void vga_outl(struct tdfx_par *par, u32 reg, u32 val) {
234 outl(val, par->iobase + reg - 0x300);
238 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) {
239 vga_outb(par, GRA_I, idx); vga_outb(par, GRA_D, val);
242 static inline u8 gra_inb(struct tdfx_par *par, u32 idx) {
243 vga_outb(par, GRA_I, idx); return vga_inb(par, GRA_D);
246 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) {
247 vga_outb(par, SEQ_I, idx); vga_outb(par, SEQ_D, val);
250 static inline u8 seq_inb(struct tdfx_par *par, u32 idx) {
251 vga_outb(par, SEQ_I, idx); return vga_inb(par, SEQ_D);
254 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) {
255 vga_outb(par, CRT_I, idx); vga_outb(par, CRT_D, val);
258 static inline u8 crt_inb(struct tdfx_par *par, u32 idx) {
259 vga_outb(par, CRT_I, idx); return vga_inb(par, CRT_D);
262 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
266 tmp = vga_inb(par, IS1_R);
267 vga_outb(par, ATT_IW, idx);
268 vga_outb(par, ATT_IW, val);
271 static inline u8 att_inb(struct tdfx_par *par, u32 idx)
275 tmp = vga_inb(par, IS1_R);
276 vga_outb(par, ATT_IW, idx);
277 return vga_inb(par, ATT_IW);
280 static inline void vga_disable_video(struct tdfx_par *par)
284 s = seq_inb(par, 0x01) | 0x20;
285 seq_outb(par, 0x00, 0x01);
286 seq_outb(par, 0x01, s);
287 seq_outb(par, 0x00, 0x03);
290 static inline void vga_enable_video(struct tdfx_par *par)
294 s = seq_inb(par, 0x01) & 0xdf;
295 seq_outb(par, 0x00, 0x01);
296 seq_outb(par, 0x01, s);
297 seq_outb(par, 0x00, 0x03);
300 static inline void vga_disable_palette(struct tdfx_par *par)
303 vga_outb(par, ATT_IW, 0x00);
306 static inline void vga_enable_palette(struct tdfx_par *par)
309 vga_outb(par, ATT_IW, 0x20);
312 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
314 return readl(par->regbase_virt + reg);
317 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
319 writel(val, par->regbase_virt + reg);
322 static inline void banshee_make_room(struct tdfx_par *par, int size)
324 /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
325 * won't quit if you ask for more. */
326 while((tdfx_inl(par, STATUS) & 0x1f) < size-1);
329 static int banshee_wait_idle(struct fb_info *info)
331 struct tdfx_par *par = (struct tdfx_par *) info->par;
334 banshee_make_room(par, 1);
335 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
338 i = (tdfx_inl(par, STATUS) & STATUS_BUSY) ? 0 : i + 1;
345 * Set the color of a palette entry in 8bpp mode
347 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
349 banshee_make_room(par, 2);
350 tdfx_outl(par, DACADDR, regno);
351 tdfx_outl(par, DACDATA, c);
354 static u32 do_calc_pll(int freq, int* freq_out)
356 int m, n, k, best_m, best_n, best_k, f_cur, best_error;
359 /* this really could be done with more intelligence --
360 255*63*4 = 64260 iterations is silly */
362 best_n = best_m = best_k = 0;
363 for (n = 1; n < 256; n++) {
364 for (m = 1; m < 64; m++) {
365 for (k = 0; k < 4; k++) {
366 f_cur = fref*(n + 2)/(m + 2)/(1 << k);
367 if (abs(f_cur - freq) < best_error) {
368 best_error = abs(f_cur-freq);
379 *freq_out = fref*(n + 2)/(m + 2)/(1 << k);
380 return (n << 8) | (m << 2) | k;
383 static void do_write_regs(struct fb_info *info, struct banshee_reg* reg)
385 struct tdfx_par *par = (struct tdfx_par *) info->par;
388 banshee_wait_idle(info);
390 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
392 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
394 banshee_make_room(par, 3);
395 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
396 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
398 tdfx_outl(par, PLLCTRL1, reg->mempll);
399 tdfx_outl(par, PLLCTRL2, reg->gfxpll);
401 tdfx_outl(par, PLLCTRL0, reg->vidpll);
403 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
405 for (i = 0; i < 5; i++)
406 seq_outb(par, i, reg->seq[i]);
408 for (i = 0; i < 25; i++)
409 crt_outb(par, i, reg->crt[i]);
411 for (i = 0; i < 9; i++)
412 gra_outb(par, i, reg->gra[i]);
414 for (i = 0; i < 21; i++)
415 att_outb(par, i, reg->att[i]);
417 crt_outb(par, 0x1a, reg->ext[0]);
418 crt_outb(par, 0x1b, reg->ext[1]);
420 vga_enable_palette(par);
421 vga_enable_video(par);
423 banshee_make_room(par, 11);
424 tdfx_outl(par, VGAINIT0, reg->vgainit0);
425 tdfx_outl(par, DACMODE, reg->dacmode);
426 tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
427 tdfx_outl(par, HWCURPATADDR, 0);
429 tdfx_outl(par, VIDSCREENSIZE,reg->screensize);
430 tdfx_outl(par, VIDDESKSTART, reg->startaddr);
431 tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
432 tdfx_outl(par, VGAINIT1, reg->vgainit1);
433 tdfx_outl(par, MISCINIT0, reg->miscinit0);
435 banshee_make_room(par, 8);
436 tdfx_outl(par, SRCBASE, reg->srcbase);
437 tdfx_outl(par, DSTBASE, reg->dstbase);
438 tdfx_outl(par, COMMANDEXTRA_2D, 0);
439 tdfx_outl(par, CLIP0MIN, 0);
440 tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
441 tdfx_outl(par, CLIP1MIN, 0);
442 tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
443 tdfx_outl(par, SRCXY, 0);
445 banshee_wait_idle(info);
448 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
456 draminit0 = tdfx_inl(par, DRAMINIT0);
457 draminit1 = tdfx_inl(par, DRAMINIT1);
459 if ((dev_id == PCI_DEVICE_ID_3DFX_BANSHEE) ||
460 (dev_id == PCI_DEVICE_ID_3DFX_VOODOO3)) {
461 sgram_p = (draminit1 & DRAMINIT1_MEM_SDRAM) ? 0 : 1;
464 (((draminit0 & DRAMINIT0_SGRAM_NUM) ? 2 : 1) *
465 ((draminit0 & DRAMINIT0_SGRAM_TYPE) ? 8 : 4) * 1024 * 1024) :
469 u32 chips, psize, banks;
471 chips = ((draminit0 & (1 << 26)) == 0) ? 4 : 8;
472 psize = 1 << ((draminit0 & 0x38000000) >> 28);
473 banks = ((draminit0 & (1 << 30)) == 0) ? 2 : 4;
474 lfbsize = chips * psize * banks;
477 /* disable block writes for SDRAM (why?) */
478 miscinit1 = tdfx_inl(par, MISCINIT1);
479 miscinit1 |= sgram_p ? 0 : MISCINIT1_2DBLOCK_DIS;
480 miscinit1 |= MISCINIT1_CLUT_INV;
482 banshee_make_room(par, 1);
483 tdfx_outl(par, MISCINIT1, miscinit1);
487 /* ------------------------------------------------------------------------- */
489 static int tdfxfb_check_var(struct fb_var_screeninfo *var,struct fb_info *info)
491 struct tdfx_par *par = (struct tdfx_par *) info->par;
494 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
495 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
496 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
500 if (var->xres != var->xres_virtual) {
501 DPRINTK("virtual x resolution != physical x resolution not supported\n");
505 if (var->yres > var->yres_virtual) {
506 DPRINTK("virtual y resolution < physical y resolution not possible\n");
511 DPRINTK("xoffset not supported\n");
515 /* fixme: does Voodoo3 support interlace? Banshee doesn't */
516 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
517 DPRINTK("interlace not supported\n");
521 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
522 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
524 if (var->xres < 320 || var->xres > 2048) {
525 DPRINTK("width not supported: %u\n", var->xres);
529 if (var->yres < 200 || var->yres > 2048) {
530 DPRINTK("height not supported: %u\n", var->yres);
534 if (lpitch * var->yres_virtual > info->fix.smem_len) {
535 DPRINTK("no memory for screen (%ux%ux%u)\n",
536 var->xres, var->yres_virtual, var->bits_per_pixel);
540 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
541 DPRINTK("pixclock too high (%ldKHz)\n",PICOS2KHZ(var->pixclock));
545 switch(var->bits_per_pixel) {
547 var->red.length = var->green.length = var->blue.length = 8;
550 var->red.offset = 11;
552 var->green.offset = 5;
553 var->green.length = 6;
554 var->blue.offset = 0;
555 var->blue.length = 5;
561 var->red.length = var->green.length = var->blue.length = 8;
563 var->red.offset = 16;
564 var->green.offset = 8;
565 var->blue.offset = 0;
566 var->red.length = var->green.length = var->blue.length = 8;
569 var->height = var->width = -1;
571 var->accel_flags = FB_ACCELF_TEXT;
573 DPRINTK("Checking graphics mode at %dx%d depth %d\n", var->xres, var->yres, var->bits_per_pixel);
577 static int tdfxfb_set_par(struct fb_info *info)
579 struct tdfx_par *par = (struct tdfx_par *) info->par;
580 u32 hdispend, hsyncsta, hsyncend, htotal;
581 u32 hd, hs, he, ht, hbs, hbe;
582 u32 vd, vs, ve, vt, vbs, vbe;
583 struct banshee_reg reg;
587 info->cmap.len = (info->var.bits_per_pixel == 8) ? 256 : 16;
590 memset(®, 0, sizeof(reg));
591 cpp = (info->var.bits_per_pixel + 7)/8;
593 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | VIDCFG_CURS_X11 | ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
596 freq = PICOS2KHZ(info->var.pixclock);
599 reg.vidcfg &= ~VIDCFG_2X;
601 hdispend = info->var.xres;
602 hsyncsta = hdispend + info->var.right_margin;
603 hsyncend = hsyncsta + info->var.hsync_len;
604 htotal = hsyncend + info->var.left_margin;
606 if (freq > par->max_pixclock/2) {
607 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
608 reg.dacmode |= DACMODE_2X;
609 reg.vidcfg |= VIDCFG_2X;
616 hd = wd = (hdispend >> 3) - 1;
617 hs = (hsyncsta >> 3) - 1;
618 he = (hsyncend >> 3) - 1;
619 ht = (htotal >> 3) - 1;
623 vbs = vd = info->var.yres - 1;
624 vs = vd + info->var.lower_margin;
625 ve = vs + info->var.vsync_len;
626 vbe = vt = ve + info->var.upper_margin - 1;
628 /* this is all pretty standard VGA register stuffing */
629 reg.misc[0x00] = 0x0f |
630 (info->var.xres < 400 ? 0xa0 :
631 info->var.xres < 480 ? 0x60 :
632 info->var.xres < 768 ? 0xe0 : 0x20);
634 reg.gra[0x00] = 0x00;
635 reg.gra[0x01] = 0x00;
636 reg.gra[0x02] = 0x00;
637 reg.gra[0x03] = 0x00;
638 reg.gra[0x04] = 0x00;
639 reg.gra[0x05] = 0x40;
640 reg.gra[0x06] = 0x05;
641 reg.gra[0x07] = 0x0f;
642 reg.gra[0x08] = 0xff;
644 reg.att[0x00] = 0x00;
645 reg.att[0x01] = 0x01;
646 reg.att[0x02] = 0x02;
647 reg.att[0x03] = 0x03;
648 reg.att[0x04] = 0x04;
649 reg.att[0x05] = 0x05;
650 reg.att[0x06] = 0x06;
651 reg.att[0x07] = 0x07;
652 reg.att[0x08] = 0x08;
653 reg.att[0x09] = 0x09;
654 reg.att[0x0a] = 0x0a;
655 reg.att[0x0b] = 0x0b;
656 reg.att[0x0c] = 0x0c;
657 reg.att[0x0d] = 0x0d;
658 reg.att[0x0e] = 0x0e;
659 reg.att[0x0f] = 0x0f;
660 reg.att[0x10] = 0x41;
661 reg.att[0x11] = 0x00;
662 reg.att[0x12] = 0x0f;
663 reg.att[0x13] = 0x00;
664 reg.att[0x14] = 0x00;
666 reg.seq[0x00] = 0x03;
667 reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
668 reg.seq[0x02] = 0x0f;
669 reg.seq[0x03] = 0x00;
670 reg.seq[0x04] = 0x0e;
672 reg.crt[0x00] = ht - 4;
675 reg.crt[0x03] = 0x80 | (hbe & 0x1f);
677 reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
679 reg.crt[0x07] = ((vs & 0x200) >> 2) |
680 ((vd & 0x200) >> 3) |
681 ((vt & 0x200) >> 4) | 0x10 |
682 ((vbs & 0x100) >> 5) |
683 ((vs & 0x100) >> 6) |
684 ((vd & 0x100) >> 7) |
686 reg.crt[0x08] = 0x00;
687 reg.crt[0x09] = 0x40 | ((vbs & 0x200) >> 4);
688 reg.crt[0x0a] = 0x00;
689 reg.crt[0x0b] = 0x00;
690 reg.crt[0x0c] = 0x00;
691 reg.crt[0x0d] = 0x00;
692 reg.crt[0x0e] = 0x00;
693 reg.crt[0x0f] = 0x00;
695 reg.crt[0x11] = (ve & 0x0f) | 0x20;
698 reg.crt[0x14] = 0x00;
700 reg.crt[0x16] = vbe + 1;
701 reg.crt[0x17] = 0xc3;
702 reg.crt[0x18] = 0xff;
704 /* Banshee's nonvga stuff */
705 reg.ext[0x00] = (((ht & 0x100) >> 8) |
706 ((hd & 0x100) >> 6) |
707 ((hbs & 0x100) >> 4) |
708 ((hbe & 0x40) >> 1) |
709 ((hs & 0x100) >> 2) |
711 reg.ext[0x01] = (((vt & 0x400) >> 10) |
712 ((vd & 0x400) >> 8) |
713 ((vbs & 0x400) >> 6) |
714 ((vbe & 0x400) >> 4));
716 reg.vgainit0 = VGAINIT0_8BIT_DAC |
717 VGAINIT0_EXT_ENABLE |
718 VGAINIT0_WAKEUP_3C3 |
719 VGAINIT0_ALT_READBACK |
720 VGAINIT0_EXTSHIFTOUT;
721 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
726 reg.cursc1 = 0xffffff;
728 reg.stride = info->var.xres * cpp;
729 reg.startaddr = par->baseline * reg.stride;
730 reg.srcbase = reg.startaddr;
731 reg.dstbase = reg.startaddr;
734 freq = PICOS2KHZ(info->var.pixclock);
736 reg.dacmode &= ~DACMODE_2X;
737 reg.vidcfg &= ~VIDCFG_2X;
738 if (freq > par->max_pixclock/2) {
739 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
740 reg.dacmode |= DACMODE_2X;
741 reg.vidcfg |= VIDCFG_2X;
743 reg.vidpll = do_calc_pll(freq, &fout);
745 reg.mempll = do_calc_pll(..., &fout);
746 reg.gfxpll = do_calc_pll(..., &fout);
749 reg.screensize = info->var.xres | (info->var.yres << 12);
750 reg.vidcfg &= ~VIDCFG_HALF_MODE;
751 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
753 #if defined(__BIG_ENDIAN)
754 switch (info->var.bits_per_pixel) {
757 reg.miscinit0 &= ~(1 << 30);
758 reg.miscinit0 &= ~(1 << 31);
761 reg.miscinit0 |= (1 << 30);
762 reg.miscinit0 |= (1 << 31);
765 reg.miscinit0 |= (1 << 30);
766 reg.miscinit0 &= ~(1 << 31);
770 do_write_regs(info, ®);
772 /* Now change fb_fix_screeninfo according to changes in par */
773 info->fix.line_length = info->var.xres * ((info->var.bits_per_pixel + 7)>>3);
774 info->fix.visual = (info->var.bits_per_pixel == 8)
775 ? FB_VISUAL_PSEUDOCOLOR
776 : FB_VISUAL_TRUECOLOR;
777 DPRINTK("Graphics mode is now set at %dx%d depth %d\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
781 /* A handy macro shamelessly pinched from matroxfb */
782 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
784 static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
785 unsigned blue,unsigned transp,struct fb_info *info)
787 struct tdfx_par *par = (struct tdfx_par *) info->par;
790 if (regno >= info->cmap.len) return 1;
792 switch (info->fix.visual) {
793 case FB_VISUAL_PSEUDOCOLOR:
794 rgbcol =(((u32)red & 0xff00) << 8) |
795 (((u32)green & 0xff00) << 0) |
796 (((u32)blue & 0xff00) >> 8);
797 do_setpalentry(par, regno, rgbcol);
799 /* Truecolor has no hardware color palettes. */
800 case FB_VISUAL_TRUECOLOR:
801 rgbcol = (CNVT_TOHW( red, info->var.red.length) << info->var.red.offset) |
802 (CNVT_TOHW( green, info->var.green.length) << info->var.green.offset) |
803 (CNVT_TOHW( blue, info->var.blue.length) << info->var.blue.offset) |
804 (CNVT_TOHW( transp, info->var.transp.length) << info->var.transp.offset);
805 ((u32*)(info->pseudo_palette))[regno] = rgbcol;
808 DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
814 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
815 static int tdfxfb_blank(int blank, struct fb_info *info)
817 struct tdfx_par *par = (struct tdfx_par *) info->par;
818 u32 dacmode, state = 0, vgablank = 0;
820 dacmode = tdfx_inl(par, DACMODE);
823 case 0: /* Screen: On; HSync: On, VSync: On */
827 case 1: /* Screen: Off; HSync: On, VSync: On */
831 case 2: /* Screen: Off; HSync: On, VSync: Off */
835 case 3: /* Screen: Off; HSync: Off, VSync: On */
839 case 4: /* Screen: Off; HSync: Off, VSync: Off */
840 state = BIT(1) | BIT(3);
845 dacmode &= ~(BIT(1) | BIT(3));
847 banshee_make_room(par, 1);
848 tdfx_outl(par, DACMODE, dacmode);
850 vga_disable_video(par);
852 vga_enable_video(par);
857 * Set the starting position of the visible screen to var->yoffset
859 static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
860 struct fb_info *info)
862 struct tdfx_par *par = (struct tdfx_par *) info->par;
865 if (nopan || var->xoffset || (var->yoffset > var->yres_virtual))
867 if ((var->yoffset + var->yres > var->yres_virtual && nowrap))
870 addr = var->yoffset * info->fix.line_length;
871 banshee_make_room(par, 1);
872 tdfx_outl(par, VIDDESKSTART, addr);
874 info->var.xoffset = var->xoffset;
875 info->var.yoffset = var->yoffset;
880 * FillRect 2D command (solidfill or invert (via ROP_XOR))
882 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
884 struct tdfx_par *par = (struct tdfx_par *) info->par;
885 u32 bpp = info->var.bits_per_pixel;
886 u32 stride = info->fix.line_length;
887 u32 fmt= stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
890 if (rect->rop == ROP_COPY)
891 tdfx_rop = TDFX_ROP_COPY;
893 tdfx_rop = TDFX_ROP_XOR;
895 banshee_make_room(par, 5);
896 tdfx_outl(par, DSTFORMAT, fmt);
897 tdfx_outl(par, COLORFORE, rect->color);
898 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
899 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
900 tdfx_outl(par, LAUNCH_2D, rect->dx | (rect->dy << 16));
901 banshee_wait_idle(info);
905 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
907 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
909 struct tdfx_par *par = (struct tdfx_par *) info->par;
910 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
911 u32 bpp = info->var.bits_per_pixel;
912 u32 stride = info->fix.line_length;
913 u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
914 u32 fmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
916 if (area->sx <= area->dx) {
919 sx += area->width - 1;
920 dx += area->width - 1;
922 if (area->sy <= area->dy) {
925 sy += area->height - 1;
926 dy += area->height - 1;
929 banshee_make_room(par, 6);
931 tdfx_outl(par, SRCFORMAT, fmt);
932 tdfx_outl(par, DSTFORMAT, fmt);
933 tdfx_outl(par, COMMAND_2D, blitcmd);
934 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
935 tdfx_outl(par, DSTXY, dx | (dy << 16));
936 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
937 banshee_wait_idle(info);
940 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
942 struct tdfx_par *par = (struct tdfx_par *) info->par;
943 int size = image->height * ((image->width * image->depth + 7)>>3);
945 int i, stride = info->fix.line_length;
946 u32 bpp = info->var.bits_per_pixel;
947 u32 dstfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
948 u8 *chardata = (u8 *) image->data;
951 if (image->depth != 1) {
952 //banshee_make_room(par, 6 + ((size + 3) >> 2));
953 //srcfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13) | 0x400000;
954 cfb_imageblit(info, image);
957 banshee_make_room(par, 8);
958 switch (info->fix.visual) {
959 case FB_VISUAL_PSEUDOCOLOR:
960 tdfx_outl(par, COLORFORE, image->fg_color);
961 tdfx_outl(par, COLORBACK, image->bg_color);
963 case FB_VISUAL_TRUECOLOR:
965 tdfx_outl(par, COLORFORE, ((u32*)(info->pseudo_palette))[image->fg_color]);
966 tdfx_outl(par, COLORBACK, ((u32*)(info->pseudo_palette))[image->bg_color]);
969 srcfmt = 0x400000 | BIT(20);
975 tdfx_outl(par, SRCXY, 0);
976 tdfx_outl(par, DSTXY, image->dx | (image->dy << 16));
977 tdfx_outl(par, COMMAND_2D, COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
978 tdfx_outl(par, SRCFORMAT, srcfmt);
979 tdfx_outl(par, DSTFORMAT, dstfmt);
980 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
982 /* A count of how many free FIFO entries we've requested.
983 * When this goes negative, we need to request more. */
986 /* Send four bytes at a time of data */
987 for (i = (size >> 2) ; i > 0; i--) {
988 if(--fifo_free < 0) {
990 banshee_make_room(par,fifo_free);
992 tdfx_outl(par, LAUNCH_2D,*(u32*)chardata);
996 /* Send the leftovers now */
997 banshee_make_room(par,3);
1001 case 1: tdfx_outl(par, LAUNCH_2D,*chardata); break;
1002 case 2: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata); break;
1003 case 3: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata | ((chardata[3]) << 24)); break;
1005 banshee_wait_idle(info);
1008 #ifdef CONFIG_FB_3DFX_ACCEL
1009 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1011 struct tdfx_par *par = (struct tdfx_par *) info->par;
1012 unsigned long flags;
1015 * If the cursor is not be changed this means either we want the
1016 * current cursor state (if enable is set) or we want to query what
1017 * we can do with the cursor (if enable is not set)
1019 if (!cursor->set) return 0;
1021 /* Too large of a cursor :-( */
1022 if (cursor->image.width > 64 || cursor->image.height > 64)
1026 * If we are going to be changing things we should disable
1029 if (info->cursor.enable) {
1030 spin_lock_irqsave(&par->DAClock, flags);
1031 info->cursor.enable = 0;
1032 del_timer(&(par->hwcursor.timer));
1033 tdfx_outl(par, VIDPROCCFG, par->hwcursor.disable);
1034 spin_unlock_irqrestore(&par->DAClock, flags);
1037 /* Disable the Cursor */
1038 if ((cursor->set && FB_CUR_SETCUR) && !cursor->enable)
1041 /* fix cursor color - XFree86 forgets to restore it properly */
1042 if (cursor->set && FB_CUR_SETCMAP) {
1043 struct fb_cmap cmap = cursor->image.cmap;
1044 unsigned long bg_color, fg_color;
1046 cmap.len = 2;/* Voodoo 3+ only support 2 color cursors*/
1047 fg_color = ((cmap.red[cmap.start] << 16) |
1048 (cmap.green[cmap.start] << 8) |
1049 (cmap.blue[cmap.start]));
1050 bg_color = ((cmap.red[cmap.start+1] << 16) |
1051 (cmap.green[cmap.start+1] << 8) |
1052 (cmap.blue[cmap.start+1]));
1053 fb_copy_cmap(&cmap, &info->cursor.image.cmap, 0);
1054 spin_lock_irqsave(&par->DAClock, flags);
1055 banshee_make_room(par, 2);
1056 tdfx_outl(par, HWCURC0, bg_color);
1057 tdfx_outl(par, HWCURC1, fg_color);
1058 spin_unlock_irqrestore(&par->DAClock, flags);
1061 if (cursor->set && FB_CUR_SETPOS) {
1064 x = cursor->image.dx;
1065 y = cursor->image.dy;
1066 y -= info->var.yoffset;
1067 info->cursor.image.dx = x;
1068 info->cursor.image.dy = y;
1071 spin_lock_irqsave(&par->DAClock, flags);
1072 banshee_make_room(par, 1);
1073 tdfx_outl(par, HWCURLOC, (y << 16) + x);
1074 spin_unlock_irqrestore(&par->DAClock, flags);
1077 /* Not supported so we fake it */
1078 if (cursor->set && FB_CUR_SETHOT) {
1079 info->cursor.hot.x = cursor->hot.x;
1080 info->cursor.hot.y = cursor->hot.y;
1083 if (cursor->set && FB_CUR_SETSHAPE) {
1085 * Voodoo 3 and above cards use 2 monochrome cursor patterns.
1086 * The reason is so the card can fetch 8 words at a time
1087 * and are stored on chip for use for the next 8 scanlines.
1088 * This reduces the number of times for access to draw the
1089 * cursor for each screen refresh.
1090 * Each pattern is a bitmap of 64 bit wide and 64 bit high
1091 * (total of 8192 bits or 1024 Kbytes). The two patterns are
1092 * stored in such a way that pattern 0 always resides in the
1093 * lower half (least significant 64 bits) of a 128 bit word
1094 * and pattern 1 the upper half. If you examine the data of
1095 * the cursor image the graphics card uses then from the
1096 * begining you see line one of pattern 0, line one of
1097 * pattern 1, line two of pattern 0, line two of pattern 1,
1098 * etc etc. The linear stride for the cursor is always 16 bytes
1099 * (128 bits) which is the maximum cursor width times two for
1100 * the two monochrome patterns.
1102 u8 *cursorbase = (u8 *) info->cursor.image.data;
1103 char *bitmap = (char *)cursor->image.data;
1104 const char *mask = cursor->mask;
1107 for (i = 0; i < 64; i++) {
1108 if (i < cursor->image.height) {
1109 j = (cursor->image.width + 7) >> 3;
1113 /* Pattern 0. Copy the cursor bitmap to it */
1114 fb_writeb(*bitmap, cursorbase + h);
1116 /* Pattern 1. Copy the cursor mask to it */
1117 fb_writeb(*mask, cursorbase + h + 8);
1122 fb_writeb(0, cursorbase + h);
1123 fb_writeb(~0, cursorbase + h + 8);
1127 fb_writel(0, cursorbase + h);
1128 fb_writel(0, cursorbase + h + 4);
1129 fb_writel(~0, cursorbase + h + 8);
1130 fb_writel(~0, cursorbase + h + 12);
1135 /* Turn the cursor on */
1137 info->cursor = *cursor;
1138 mod_timer(&par->hwcursor.timer, jiffies+HZ/2);
1139 spin_lock_irqsave(&par->DAClock, flags);
1140 banshee_make_room(par, 1);
1141 tdfx_outl(par, VIDPROCCFG, par->hwcursor.enable);
1142 spin_unlock_irqrestore(&par->DAClock, flags);
1145 #endif /* CONFIG_FB_3DFX_ACCEL */
1148 * tdfxfb_probe - Device Initializiation
1150 * @pdev: PCI Device to initialize
1151 * @id: PCI Device ID
1153 * Initializes and allocates resources for PCI device @pdev.
1156 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
1157 const struct pci_device_id *id)
1159 struct tdfx_par *default_par;
1160 struct fb_info *info;
1163 if ((err = pci_enable_device(pdev))) {
1164 printk(KERN_WARNING "tdfxfb: Can't enable pdev: %d\n", err);
1168 size = sizeof(struct fb_info)+sizeof(struct tdfx_par)+16*sizeof(u32);
1170 info = kmalloc(size, GFP_KERNEL);
1172 if (!info) return -ENOMEM;
1174 memset(info, 0, size);
1176 default_par = (struct tdfx_par *) (info + 1);
1178 /* Configure the default fb_fix_screeninfo first */
1179 switch (pdev->device) {
1180 case PCI_DEVICE_ID_3DFX_BANSHEE:
1181 strcat(tdfx_fix.id, " Banshee");
1182 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
1184 case PCI_DEVICE_ID_3DFX_VOODOO3:
1185 strcat(tdfx_fix.id, " Voodoo3");
1186 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
1188 case PCI_DEVICE_ID_3DFX_VOODOO5:
1189 strcat(tdfx_fix.id, " Voodoo5");
1190 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
1194 tdfx_fix.mmio_start = pci_resource_start(pdev, 0);
1195 tdfx_fix.mmio_len = pci_resource_len(pdev, 0);
1196 default_par->regbase_virt = ioremap_nocache(tdfx_fix.mmio_start, tdfx_fix.mmio_len);
1197 if (!default_par->regbase_virt) {
1198 printk("fb: Can't remap %s register area.\n", tdfx_fix.id);
1202 if (!request_mem_region(pci_resource_start(pdev, 0),
1203 pci_resource_len(pdev, 0), "tdfx regbase")) {
1204 printk(KERN_WARNING "tdfxfb: Can't reserve regbase\n");
1208 tdfx_fix.smem_start = pci_resource_start(pdev, 1);
1209 if (!(tdfx_fix.smem_len = do_lfb_size(default_par, pdev->device))) {
1210 printk("fb: Can't count %s memory.\n", tdfx_fix.id);
1211 release_mem_region(pci_resource_start(pdev, 0),
1212 pci_resource_len(pdev, 0));
1216 if (!request_mem_region(pci_resource_start(pdev, 1),
1217 pci_resource_len(pdev, 1), "tdfx smem")) {
1218 printk(KERN_WARNING "tdfxfb: Can't reserve smem\n");
1219 release_mem_region(pci_resource_start(pdev, 0),
1220 pci_resource_len(pdev, 0));
1224 info->screen_base = ioremap_nocache(tdfx_fix.smem_start,
1226 if (!info->screen_base) {
1227 printk("fb: Can't remap %s framebuffer.\n", tdfx_fix.id);
1228 release_mem_region(pci_resource_start(pdev, 1),
1229 pci_resource_len(pdev, 1));
1230 release_mem_region(pci_resource_start(pdev, 0),
1231 pci_resource_len(pdev, 0));
1235 default_par->iobase = pci_resource_start(pdev, 2);
1237 if (!request_region(pci_resource_start(pdev, 2),
1238 pci_resource_len(pdev, 2), "tdfx iobase")) {
1239 printk(KERN_WARNING "tdfxfb: Can't reserve iobase\n");
1240 release_mem_region(pci_resource_start(pdev, 1),
1241 pci_resource_len(pdev, 1));
1242 release_mem_region(pci_resource_start(pdev, 0),
1243 pci_resource_len(pdev, 0));
1247 printk("fb: %s memory = %dK\n", tdfx_fix.id, tdfx_fix.smem_len >> 10);
1249 tdfx_fix.ypanstep = nopan ? 0 : 1;
1250 tdfx_fix.ywrapstep = nowrap ? 0 : 1;
1252 info->fbops = &tdfxfb_ops;
1253 info->fix = tdfx_fix;
1254 info->par = default_par;
1255 info->pseudo_palette = (void *)(default_par + 1);
1256 info->flags = FBINFO_FLAG_DEFAULT;
1260 mode_option = "640x480@60";
1262 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1263 if (!err || err == 4)
1265 info->var = tdfx_var;
1267 size = (info->var.bits_per_pixel == 8) ? 256 : 16;
1268 fb_alloc_cmap(&info->cmap, size, 0);
1270 if (register_framebuffer(info) < 0) {
1271 printk("tdfxfb: can't register framebuffer\n");
1277 pci_set_drvdata(pdev, info);
1282 * Cleanup after anything that was remapped/allocated.
1284 if (default_par->regbase_virt)
1285 iounmap(default_par->regbase_virt);
1286 if (info->screen_base)
1287 iounmap(info->screen_base);
1293 * tdfxfb_remove - Device removal
1295 * @pdev: PCI Device to cleanup
1297 * Releases all resources allocated during the course of the driver's
1298 * lifetime for the PCI device @pdev.
1301 static void __devexit tdfxfb_remove(struct pci_dev *pdev)
1303 struct fb_info *info = pci_get_drvdata(pdev);
1304 struct tdfx_par *par = (struct tdfx_par *) info->par;
1306 unregister_framebuffer(info);
1307 iounmap(par->regbase_virt);
1308 iounmap(info->screen_base);
1310 /* Clean up after reserved regions */
1311 release_region(pci_resource_start(pdev, 2),
1312 pci_resource_len(pdev, 2));
1313 release_mem_region(pci_resource_start(pdev, 1),
1314 pci_resource_len(pdev, 1));
1315 release_mem_region(pci_resource_start(pdev, 0),
1316 pci_resource_len(pdev, 0));
1317 pci_set_drvdata(pdev, NULL);
1321 int __init tdfxfb_init(void)
1323 return pci_module_init(&tdfxfb_driver);
1326 static void __exit tdfxfb_exit(void)
1328 pci_unregister_driver(&tdfxfb_driver);
1331 MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
1332 MODULE_DESCRIPTION("3Dfx framebuffer device driver");
1333 MODULE_LICENSE("GPL");
1336 module_init(tdfxfb_init);
1338 module_exit(tdfxfb_exit);
1342 void tdfxfb_setup(char *options, int *ints)
1346 if (!options || !*options)
1349 while ((this_opt = strsep(&options, ",")) != NULL) {
1352 if (!strcmp(this_opt, "inverse")) {
1355 } else if(!strcmp(this_opt, "nopan")) {
1357 } else if(!strcmp(this_opt, "nowrap")) {
1360 mode_option = this_opt;