6 * Author: Hannu Mallat <hmallat@cc.hut.fi>
8 * Copyright © 1999 Hannu Mallat
11 * Created : Thu Sep 23 18:17:43 1999, hmallat
12 * Last modified: Tue Nov 2 21:19:47 1999, hmallat
14 * Lots of the information here comes from the Daryll Strauss' Banshee
15 * patches to the XF86 server, and the rest comes from the 3dfx
16 * Banshee specification. I'm very much indebted to Daryll for his
17 * work on the X server.
19 * Voodoo3 support was contributed Harold Oga. Lots of additions
20 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
21 * Kesmarki. Thanks guys!
23 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
24 * behave very differently from the Voodoo3/4/5. For anyone wanting to
25 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
26 * located at http://www.sourceforge.net/projects/sstfb).
28 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
29 * I do wish the next version is a bit more complete. Without the XF86
30 * patches I couldn't have gotten even this far... for instance, the
31 * extensions to the VGA register set go completely unmentioned in the
32 * spec! Also, lots of references are made to the 'SST core', but no
33 * spec is publicly available, AFAIK.
35 * The structure of this driver comes pretty much from the Permedia
36 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
39 * - support for 16/32 bpp needs fixing (funky bootup penguin)
40 * - multihead support (basically need to support an array of fb_infos)
41 * - support other architectures (PPC, Alpha); does the fact that the VGA
42 * core can be accessed only thru I/O (not memory mapped) complicate
47 * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons
49 * 0.1.3 (released 1999-11-02) added Attila's panning support, code
50 * reorg, hwcursor address page size alignment
51 * (for mmaping both frame buffer and regs),
52 * and my changes to get rid of hardcoded
53 * VGA i/o register locations (uses PCI
54 * configuration info now)
55 * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and
57 * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga.
58 * 0.1.0 (released 1999-10-06) initial version
62 #include <linux/config.h>
63 #include <linux/module.h>
64 #include <linux/kernel.h>
65 #include <linux/errno.h>
66 #include <linux/string.h>
68 #include <linux/tty.h>
69 #include <linux/slab.h>
70 #include <linux/delay.h>
71 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/pci.h>
75 #include <linux/nvram.h>
77 #include <linux/timer.h>
78 #include <linux/spinlock.h>
80 #include <video/tdfx.h>
84 #define DPRINTK(a,b...) printk(KERN_DEBUG "fb: %s: " a, __FUNCTION__ , ## b)
86 #define DPRINTK(a,b...)
89 #define BANSHEE_MAX_PIXCLOCK 270000
90 #define VOODOO3_MAX_PIXCLOCK 300000
91 #define VOODOO5_MAX_PIXCLOCK 350000
93 static struct fb_fix_screeninfo tdfx_fix __initdata = {
95 .type = FB_TYPE_PACKED_PIXELS,
96 .visual = FB_VISUAL_PSEUDOCOLOR,
99 .accel = FB_ACCEL_3DFX_BANSHEE
102 static struct fb_var_screeninfo tdfx_var __initdata = {
103 /* "640x480, 8 bpp @ 60 Hz */
107 .yres_virtual = 1024,
112 .activate = FB_ACTIVATE_NOW,
115 .accel_flags = FB_ACCELF_TEXT,
123 .vmode = FB_VMODE_NONINTERLACED
127 * PCI driver prototypes
129 static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id);
130 static void tdfxfb_remove(struct pci_dev *pdev);
132 static struct pci_device_id tdfxfb_id_table[] = {
133 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
134 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
136 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
137 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
139 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
145 static struct pci_driver tdfxfb_driver = {
147 .id_table = tdfxfb_id_table,
148 .probe = tdfxfb_probe,
149 .remove = __devexit_p(tdfxfb_remove),
152 MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
155 * Frame buffer device API
157 int tdfxfb_init(void);
158 void tdfxfb_setup(char *options, int *ints);
160 static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb);
161 static int tdfxfb_set_par(struct fb_info *info);
162 static int tdfxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
163 u_int transp, struct fb_info *info);
164 static int tdfxfb_blank(int blank, struct fb_info *info);
165 static int tdfxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
166 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
167 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
168 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image);
169 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor);
170 static int banshee_wait_idle(struct fb_info *info);
172 static struct fb_ops tdfxfb_ops = {
173 .owner = THIS_MODULE,
174 .fb_check_var = tdfxfb_check_var,
175 .fb_set_par = tdfxfb_set_par,
176 .fb_setcolreg = tdfxfb_setcolreg,
177 .fb_blank = tdfxfb_blank,
178 .fb_pan_display = tdfxfb_pan_display,
179 .fb_fillrect = tdfxfb_fillrect,
180 .fb_copyarea = tdfxfb_copyarea,
181 .fb_imageblit = tdfxfb_imageblit,
182 .fb_sync = banshee_wait_idle,
183 .fb_cursor = soft_cursor,
187 * do_xxx: Hardware-specific functions
189 static u32 do_calc_pll(int freq, int *freq_out);
190 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg);
191 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short);
196 static int nopan = 0;
197 static int nowrap = 1; // not implemented (yet)
198 static int inverse = 0;
199 static char *mode_option __initdata = NULL;
201 /* -------------------------------------------------------------------------
202 * Hardware-specific funcions
203 * ------------------------------------------------------------------------- */
206 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) { return inb(reg); }
207 static inline u16 vga_inw(struct tdfx_par *par, u32 reg) { return inw(reg); }
208 static inline u16 vga_inl(struct tdfx_par *par, u32 reg) { return inl(reg); }
210 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) { outb(val, reg); }
211 static inline void vga_outw(struct tdfx_par *par, u32 reg, u16 val) { outw(val, reg); }
212 static inline void vga_outl(struct tdfx_par *par, u32 reg, u32 val) { outl(val, reg); }
214 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) {
215 return inb(par->iobase + reg - 0x300);
217 static inline u16 vga_inw(struct tdfx_par *par, u32 reg) {
218 return inw(par->iobase + reg - 0x300);
220 static inline u16 vga_inl(struct tdfx_par *par, u32 reg) {
221 return inl(par->iobase + reg - 0x300);
223 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) {
224 outb(val, par->iobase + reg - 0x300);
226 static inline void vga_outw(struct tdfx_par *par, u32 reg, u16 val) {
227 outw(val, par->iobase + reg - 0x300);
229 static inline void vga_outl(struct tdfx_par *par, u32 reg, u32 val) {
230 outl(val, par->iobase + reg - 0x300);
234 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) {
235 vga_outb(par, GRA_I, idx); vga_outb(par, GRA_D, val);
238 static inline u8 gra_inb(struct tdfx_par *par, u32 idx) {
239 vga_outb(par, GRA_I, idx); return vga_inb(par, GRA_D);
242 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) {
243 vga_outb(par, SEQ_I, idx); vga_outb(par, SEQ_D, val);
246 static inline u8 seq_inb(struct tdfx_par *par, u32 idx) {
247 vga_outb(par, SEQ_I, idx); return vga_inb(par, SEQ_D);
250 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) {
251 vga_outb(par, CRT_I, idx); vga_outb(par, CRT_D, val);
254 static inline u8 crt_inb(struct tdfx_par *par, u32 idx) {
255 vga_outb(par, CRT_I, idx); return vga_inb(par, CRT_D);
258 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
262 tmp = vga_inb(par, IS1_R);
263 vga_outb(par, ATT_IW, idx);
264 vga_outb(par, ATT_IW, val);
267 static inline u8 att_inb(struct tdfx_par *par, u32 idx)
271 tmp = vga_inb(par, IS1_R);
272 vga_outb(par, ATT_IW, idx);
273 return vga_inb(par, ATT_IW);
276 static inline void vga_disable_video(struct tdfx_par *par)
280 s = seq_inb(par, 0x01) | 0x20;
281 seq_outb(par, 0x00, 0x01);
282 seq_outb(par, 0x01, s);
283 seq_outb(par, 0x00, 0x03);
286 static inline void vga_enable_video(struct tdfx_par *par)
290 s = seq_inb(par, 0x01) & 0xdf;
291 seq_outb(par, 0x00, 0x01);
292 seq_outb(par, 0x01, s);
293 seq_outb(par, 0x00, 0x03);
296 static inline void vga_disable_palette(struct tdfx_par *par)
299 vga_outb(par, ATT_IW, 0x00);
302 static inline void vga_enable_palette(struct tdfx_par *par)
305 vga_outb(par, ATT_IW, 0x20);
308 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
310 return readl(par->regbase_virt + reg);
313 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
315 writel(val, par->regbase_virt + reg);
318 static inline void banshee_make_room(struct tdfx_par *par, int size)
320 /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
321 * won't quit if you ask for more. */
322 while((tdfx_inl(par, STATUS) & 0x1f) < size-1);
325 static int banshee_wait_idle(struct fb_info *info)
327 struct tdfx_par *par = (struct tdfx_par *) info->par;
330 banshee_make_room(par, 1);
331 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
334 i = (tdfx_inl(par, STATUS) & STATUS_BUSY) ? 0 : i + 1;
341 * Set the color of a palette entry in 8bpp mode
343 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
345 banshee_make_room(par, 2);
346 tdfx_outl(par, DACADDR, regno);
347 tdfx_outl(par, DACDATA, c);
350 static u32 do_calc_pll(int freq, int* freq_out)
352 int m, n, k, best_m, best_n, best_k, f_cur, best_error;
355 /* this really could be done with more intelligence --
356 255*63*4 = 64260 iterations is silly */
358 best_n = best_m = best_k = 0;
359 for (n = 1; n < 256; n++) {
360 for (m = 1; m < 64; m++) {
361 for (k = 0; k < 4; k++) {
362 f_cur = fref*(n + 2)/(m + 2)/(1 << k);
363 if (abs(f_cur - freq) < best_error) {
364 best_error = abs(f_cur-freq);
375 *freq_out = fref*(n + 2)/(m + 2)/(1 << k);
376 return (n << 8) | (m << 2) | k;
379 static void do_write_regs(struct fb_info *info, struct banshee_reg* reg)
381 struct tdfx_par *par = (struct tdfx_par *) info->par;
384 banshee_wait_idle(info);
386 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
388 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
390 banshee_make_room(par, 3);
391 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
392 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
394 tdfx_outl(par, PLLCTRL1, reg->mempll);
395 tdfx_outl(par, PLLCTRL2, reg->gfxpll);
397 tdfx_outl(par, PLLCTRL0, reg->vidpll);
399 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
401 for (i = 0; i < 5; i++)
402 seq_outb(par, i, reg->seq[i]);
404 for (i = 0; i < 25; i++)
405 crt_outb(par, i, reg->crt[i]);
407 for (i = 0; i < 9; i++)
408 gra_outb(par, i, reg->gra[i]);
410 for (i = 0; i < 21; i++)
411 att_outb(par, i, reg->att[i]);
413 crt_outb(par, 0x1a, reg->ext[0]);
414 crt_outb(par, 0x1b, reg->ext[1]);
416 vga_enable_palette(par);
417 vga_enable_video(par);
419 banshee_make_room(par, 11);
420 tdfx_outl(par, VGAINIT0, reg->vgainit0);
421 tdfx_outl(par, DACMODE, reg->dacmode);
422 tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
423 tdfx_outl(par, HWCURPATADDR, 0);
425 tdfx_outl(par, VIDSCREENSIZE,reg->screensize);
426 tdfx_outl(par, VIDDESKSTART, reg->startaddr);
427 tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
428 tdfx_outl(par, VGAINIT1, reg->vgainit1);
429 tdfx_outl(par, MISCINIT0, reg->miscinit0);
431 banshee_make_room(par, 8);
432 tdfx_outl(par, SRCBASE, reg->srcbase);
433 tdfx_outl(par, DSTBASE, reg->dstbase);
434 tdfx_outl(par, COMMANDEXTRA_2D, 0);
435 tdfx_outl(par, CLIP0MIN, 0);
436 tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
437 tdfx_outl(par, CLIP1MIN, 0);
438 tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
439 tdfx_outl(par, SRCXY, 0);
441 banshee_wait_idle(info);
444 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
452 draminit0 = tdfx_inl(par, DRAMINIT0);
453 draminit1 = tdfx_inl(par, DRAMINIT1);
455 if ((dev_id == PCI_DEVICE_ID_3DFX_BANSHEE) ||
456 (dev_id == PCI_DEVICE_ID_3DFX_VOODOO3)) {
457 sgram_p = (draminit1 & DRAMINIT1_MEM_SDRAM) ? 0 : 1;
460 (((draminit0 & DRAMINIT0_SGRAM_NUM) ? 2 : 1) *
461 ((draminit0 & DRAMINIT0_SGRAM_TYPE) ? 8 : 4) * 1024 * 1024) :
465 u32 chips, psize, banks;
467 chips = ((draminit0 & (1 << 26)) == 0) ? 4 : 8;
468 psize = 1 << ((draminit0 & 0x38000000) >> 28);
469 banks = ((draminit0 & (1 << 30)) == 0) ? 2 : 4;
470 lfbsize = chips * psize * banks;
473 /* disable block writes for SDRAM (why?) */
474 miscinit1 = tdfx_inl(par, MISCINIT1);
475 miscinit1 |= sgram_p ? 0 : MISCINIT1_2DBLOCK_DIS;
476 miscinit1 |= MISCINIT1_CLUT_INV;
478 banshee_make_room(par, 1);
479 tdfx_outl(par, MISCINIT1, miscinit1);
483 /* ------------------------------------------------------------------------- */
485 static int tdfxfb_check_var(struct fb_var_screeninfo *var,struct fb_info *info)
487 struct tdfx_par *par = (struct tdfx_par *) info->par;
490 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
491 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
492 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
496 if (var->xres != var->xres_virtual) {
497 DPRINTK("virtual x resolution != physical x resolution not supported\n");
501 if (var->yres > var->yres_virtual) {
502 DPRINTK("virtual y resolution < physical y resolution not possible\n");
507 DPRINTK("xoffset not supported\n");
511 /* fixme: does Voodoo3 support interlace? Banshee doesn't */
512 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
513 DPRINTK("interlace not supported\n");
517 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
518 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
520 if (var->xres < 320 || var->xres > 2048) {
521 DPRINTK("width not supported: %u\n", var->xres);
525 if (var->yres < 200 || var->yres > 2048) {
526 DPRINTK("height not supported: %u\n", var->yres);
530 if (lpitch * var->yres_virtual > info->fix.smem_len) {
531 DPRINTK("no memory for screen (%ux%ux%u)\n",
532 var->xres, var->yres_virtual, var->bits_per_pixel);
536 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
537 DPRINTK("pixclock too high (%ldKHz)\n",PICOS2KHZ(var->pixclock));
541 switch(var->bits_per_pixel) {
543 var->red.length = var->green.length = var->blue.length = 8;
546 var->red.offset = 11;
548 var->green.offset = 5;
549 var->green.length = 6;
550 var->blue.offset = 0;
551 var->blue.length = 5;
557 var->red.length = var->green.length = var->blue.length = 8;
559 var->red.offset = 16;
560 var->green.offset = 8;
561 var->blue.offset = 0;
562 var->red.length = var->green.length = var->blue.length = 8;
565 var->height = var->width = -1;
567 var->accel_flags = FB_ACCELF_TEXT;
569 DPRINTK("Checking graphics mode at %dx%d depth %d\n", var->xres, var->yres, var->bits_per_pixel);
573 static int tdfxfb_set_par(struct fb_info *info)
575 struct tdfx_par *par = (struct tdfx_par *) info->par;
576 u32 hdispend, hsyncsta, hsyncend, htotal;
577 u32 hd, hs, he, ht, hbs, hbe;
578 u32 vd, vs, ve, vt, vbs, vbe;
579 struct banshee_reg reg;
583 info->cmap.len = (info->var.bits_per_pixel == 8) ? 256 : 16;
586 memset(®, 0, sizeof(reg));
587 cpp = (info->var.bits_per_pixel + 7)/8;
589 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | VIDCFG_CURS_X11 | ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
592 freq = PICOS2KHZ(info->var.pixclock);
595 reg.vidcfg &= ~VIDCFG_2X;
597 hdispend = info->var.xres;
598 hsyncsta = hdispend + info->var.right_margin;
599 hsyncend = hsyncsta + info->var.hsync_len;
600 htotal = hsyncend + info->var.left_margin;
602 if (freq > par->max_pixclock/2) {
603 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
604 reg.dacmode |= DACMODE_2X;
605 reg.vidcfg |= VIDCFG_2X;
612 hd = wd = (hdispend >> 3) - 1;
613 hs = (hsyncsta >> 3) - 1;
614 he = (hsyncend >> 3) - 1;
615 ht = (htotal >> 3) - 1;
619 vbs = vd = info->var.yres - 1;
620 vs = vd + info->var.lower_margin;
621 ve = vs + info->var.vsync_len;
622 vbe = vt = ve + info->var.upper_margin - 1;
624 /* this is all pretty standard VGA register stuffing */
625 reg.misc[0x00] = 0x0f |
626 (info->var.xres < 400 ? 0xa0 :
627 info->var.xres < 480 ? 0x60 :
628 info->var.xres < 768 ? 0xe0 : 0x20);
630 reg.gra[0x00] = 0x00;
631 reg.gra[0x01] = 0x00;
632 reg.gra[0x02] = 0x00;
633 reg.gra[0x03] = 0x00;
634 reg.gra[0x04] = 0x00;
635 reg.gra[0x05] = 0x40;
636 reg.gra[0x06] = 0x05;
637 reg.gra[0x07] = 0x0f;
638 reg.gra[0x08] = 0xff;
640 reg.att[0x00] = 0x00;
641 reg.att[0x01] = 0x01;
642 reg.att[0x02] = 0x02;
643 reg.att[0x03] = 0x03;
644 reg.att[0x04] = 0x04;
645 reg.att[0x05] = 0x05;
646 reg.att[0x06] = 0x06;
647 reg.att[0x07] = 0x07;
648 reg.att[0x08] = 0x08;
649 reg.att[0x09] = 0x09;
650 reg.att[0x0a] = 0x0a;
651 reg.att[0x0b] = 0x0b;
652 reg.att[0x0c] = 0x0c;
653 reg.att[0x0d] = 0x0d;
654 reg.att[0x0e] = 0x0e;
655 reg.att[0x0f] = 0x0f;
656 reg.att[0x10] = 0x41;
657 reg.att[0x11] = 0x00;
658 reg.att[0x12] = 0x0f;
659 reg.att[0x13] = 0x00;
660 reg.att[0x14] = 0x00;
662 reg.seq[0x00] = 0x03;
663 reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
664 reg.seq[0x02] = 0x0f;
665 reg.seq[0x03] = 0x00;
666 reg.seq[0x04] = 0x0e;
668 reg.crt[0x00] = ht - 4;
671 reg.crt[0x03] = 0x80 | (hbe & 0x1f);
673 reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
675 reg.crt[0x07] = ((vs & 0x200) >> 2) |
676 ((vd & 0x200) >> 3) |
677 ((vt & 0x200) >> 4) | 0x10 |
678 ((vbs & 0x100) >> 5) |
679 ((vs & 0x100) >> 6) |
680 ((vd & 0x100) >> 7) |
682 reg.crt[0x08] = 0x00;
683 reg.crt[0x09] = 0x40 | ((vbs & 0x200) >> 4);
684 reg.crt[0x0a] = 0x00;
685 reg.crt[0x0b] = 0x00;
686 reg.crt[0x0c] = 0x00;
687 reg.crt[0x0d] = 0x00;
688 reg.crt[0x0e] = 0x00;
689 reg.crt[0x0f] = 0x00;
691 reg.crt[0x11] = (ve & 0x0f) | 0x20;
694 reg.crt[0x14] = 0x00;
696 reg.crt[0x16] = vbe + 1;
697 reg.crt[0x17] = 0xc3;
698 reg.crt[0x18] = 0xff;
700 /* Banshee's nonvga stuff */
701 reg.ext[0x00] = (((ht & 0x100) >> 8) |
702 ((hd & 0x100) >> 6) |
703 ((hbs & 0x100) >> 4) |
704 ((hbe & 0x40) >> 1) |
705 ((hs & 0x100) >> 2) |
707 reg.ext[0x01] = (((vt & 0x400) >> 10) |
708 ((vd & 0x400) >> 8) |
709 ((vbs & 0x400) >> 6) |
710 ((vbe & 0x400) >> 4));
712 reg.vgainit0 = VGAINIT0_8BIT_DAC |
713 VGAINIT0_EXT_ENABLE |
714 VGAINIT0_WAKEUP_3C3 |
715 VGAINIT0_ALT_READBACK |
716 VGAINIT0_EXTSHIFTOUT;
717 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
722 reg.cursc1 = 0xffffff;
724 reg.stride = info->var.xres * cpp;
725 reg.startaddr = par->baseline * reg.stride;
726 reg.srcbase = reg.startaddr;
727 reg.dstbase = reg.startaddr;
730 freq = PICOS2KHZ(info->var.pixclock);
732 reg.dacmode &= ~DACMODE_2X;
733 reg.vidcfg &= ~VIDCFG_2X;
734 if (freq > par->max_pixclock/2) {
735 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
736 reg.dacmode |= DACMODE_2X;
737 reg.vidcfg |= VIDCFG_2X;
739 reg.vidpll = do_calc_pll(freq, &fout);
741 reg.mempll = do_calc_pll(..., &fout);
742 reg.gfxpll = do_calc_pll(..., &fout);
745 reg.screensize = info->var.xres | (info->var.yres << 12);
746 reg.vidcfg &= ~VIDCFG_HALF_MODE;
747 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
749 #if defined(__BIG_ENDIAN)
750 switch (info->var.bits_per_pixel) {
753 reg.miscinit0 &= ~(1 << 30);
754 reg.miscinit0 &= ~(1 << 31);
757 reg.miscinit0 |= (1 << 30);
758 reg.miscinit0 |= (1 << 31);
761 reg.miscinit0 |= (1 << 30);
762 reg.miscinit0 &= ~(1 << 31);
766 do_write_regs(info, ®);
768 /* Now change fb_fix_screeninfo according to changes in par */
769 info->fix.line_length = info->var.xres * ((info->var.bits_per_pixel + 7)>>3);
770 info->fix.visual = (info->var.bits_per_pixel == 8)
771 ? FB_VISUAL_PSEUDOCOLOR
772 : FB_VISUAL_TRUECOLOR;
773 DPRINTK("Graphics mode is now set at %dx%d depth %d\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
777 /* A handy macro shamelessly pinched from matroxfb */
778 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
780 static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
781 unsigned blue,unsigned transp,struct fb_info *info)
783 struct tdfx_par *par = (struct tdfx_par *) info->par;
786 if (regno >= info->cmap.len) return 1;
788 switch (info->fix.visual) {
789 case FB_VISUAL_PSEUDOCOLOR:
790 rgbcol =(((u32)red & 0xff00) << 8) |
791 (((u32)green & 0xff00) << 0) |
792 (((u32)blue & 0xff00) >> 8);
793 do_setpalentry(par, regno, rgbcol);
795 /* Truecolor has no hardware color palettes. */
796 case FB_VISUAL_TRUECOLOR:
797 rgbcol = (CNVT_TOHW( red, info->var.red.length) << info->var.red.offset) |
798 (CNVT_TOHW( green, info->var.green.length) << info->var.green.offset) |
799 (CNVT_TOHW( blue, info->var.blue.length) << info->var.blue.offset) |
800 (CNVT_TOHW( transp, info->var.transp.length) << info->var.transp.offset);
801 ((u32*)(info->pseudo_palette))[regno] = rgbcol;
804 DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
810 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
811 static int tdfxfb_blank(int blank, struct fb_info *info)
813 struct tdfx_par *par = (struct tdfx_par *) info->par;
814 u32 dacmode, state = 0, vgablank = 0;
816 dacmode = tdfx_inl(par, DACMODE);
819 case 0: /* Screen: On; HSync: On, VSync: On */
823 case 1: /* Screen: Off; HSync: On, VSync: On */
827 case 2: /* Screen: Off; HSync: On, VSync: Off */
831 case 3: /* Screen: Off; HSync: Off, VSync: On */
835 case 4: /* Screen: Off; HSync: Off, VSync: Off */
836 state = BIT(1) | BIT(3);
841 dacmode &= ~(BIT(1) | BIT(3));
843 banshee_make_room(par, 1);
844 tdfx_outl(par, DACMODE, dacmode);
846 vga_disable_video(par);
848 vga_enable_video(par);
853 * Set the starting position of the visible screen to var->yoffset
855 static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
856 struct fb_info *info)
858 struct tdfx_par *par = (struct tdfx_par *) info->par;
861 if (nopan || var->xoffset || (var->yoffset > var->yres_virtual))
863 if ((var->yoffset + var->yres > var->yres_virtual && nowrap))
866 addr = var->yoffset * info->fix.line_length;
867 banshee_make_room(par, 1);
868 tdfx_outl(par, VIDDESKSTART, addr);
870 info->var.xoffset = var->xoffset;
871 info->var.yoffset = var->yoffset;
876 * FillRect 2D command (solidfill or invert (via ROP_XOR))
878 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
880 struct tdfx_par *par = (struct tdfx_par *) info->par;
881 u32 bpp = info->var.bits_per_pixel;
882 u32 stride = info->fix.line_length;
883 u32 fmt= stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
886 if (rect->rop == ROP_COPY)
887 tdfx_rop = TDFX_ROP_COPY;
889 tdfx_rop = TDFX_ROP_XOR;
891 banshee_make_room(par, 5);
892 tdfx_outl(par, DSTFORMAT, fmt);
893 tdfx_outl(par, COLORFORE, rect->color);
894 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
895 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
896 tdfx_outl(par, LAUNCH_2D, rect->dx | (rect->dy << 16));
897 banshee_wait_idle(info);
901 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
903 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
905 struct tdfx_par *par = (struct tdfx_par *) info->par;
906 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
907 u32 bpp = info->var.bits_per_pixel;
908 u32 stride = info->fix.line_length;
909 u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
910 u32 fmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
912 if (area->sx <= area->dx) {
915 sx += area->width - 1;
916 dx += area->width - 1;
918 if (area->sy <= area->dy) {
921 sy += area->height - 1;
922 dy += area->height - 1;
925 banshee_make_room(par, 6);
927 tdfx_outl(par, SRCFORMAT, fmt);
928 tdfx_outl(par, DSTFORMAT, fmt);
929 tdfx_outl(par, COMMAND_2D, blitcmd);
930 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
931 tdfx_outl(par, DSTXY, dx | (dy << 16));
932 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
933 banshee_wait_idle(info);
936 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
938 struct tdfx_par *par = (struct tdfx_par *) info->par;
939 int size = image->height * ((image->width * image->depth + 7)>>3);
941 int i, stride = info->fix.line_length;
942 u32 bpp = info->var.bits_per_pixel;
943 u32 dstfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
944 u8 *chardata = (u8 *) image->data;
947 if (image->depth != 1) {
948 //banshee_make_room(par, 6 + ((size + 3) >> 2));
949 //srcfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13) | 0x400000;
950 cfb_imageblit(info, image);
953 banshee_make_room(par, 8);
954 switch (info->fix.visual) {
955 case FB_VISUAL_PSEUDOCOLOR:
956 tdfx_outl(par, COLORFORE, image->fg_color);
957 tdfx_outl(par, COLORBACK, image->bg_color);
959 case FB_VISUAL_TRUECOLOR:
961 tdfx_outl(par, COLORFORE, ((u32*)(info->pseudo_palette))[image->fg_color]);
962 tdfx_outl(par, COLORBACK, ((u32*)(info->pseudo_palette))[image->bg_color]);
965 srcfmt = 0x400000 | BIT(20);
971 tdfx_outl(par, SRCXY, 0);
972 tdfx_outl(par, DSTXY, image->dx | (image->dy << 16));
973 tdfx_outl(par, COMMAND_2D, COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
974 tdfx_outl(par, SRCFORMAT, srcfmt);
975 tdfx_outl(par, DSTFORMAT, dstfmt);
976 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
978 /* A count of how many free FIFO entries we've requested.
979 * When this goes negative, we need to request more. */
982 /* Send four bytes at a time of data */
983 for (i = (size >> 2) ; i > 0; i--) {
984 if(--fifo_free < 0) {
986 banshee_make_room(par,fifo_free);
988 tdfx_outl(par, LAUNCH_2D,*(u32*)chardata);
992 /* Send the leftovers now */
993 banshee_make_room(par,3);
997 case 1: tdfx_outl(par, LAUNCH_2D,*chardata); break;
998 case 2: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata); break;
999 case 3: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata | ((chardata[3]) << 24)); break;
1001 banshee_wait_idle(info);
1004 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1006 struct tdfx_par *par = (struct tdfx_par *) info->par;
1007 unsigned long flags;
1010 * If the cursor is not be changed this means either we want the
1011 * current cursor state (if enable is set) or we want to query what
1012 * we can do with the cursor (if enable is not set)
1014 if (!cursor->set) return 0;
1016 /* Too large of a cursor :-( */
1017 if (cursor->image.width > 64 || cursor->image.height > 64)
1021 * If we are going to be changing things we should disable
1024 if (info->cursor.enable) {
1025 spin_lock_irqsave(&par->DAClock, flags);
1026 info->cursor.enable = 0;
1027 del_timer(&(par->hwcursor.timer));
1028 tdfx_outl(par, VIDPROCCFG, par->hwcursor.disable);
1029 spin_unlock_irqrestore(&par->DAClock, flags);
1032 /* Disable the Cursor */
1033 if ((cursor->set && FB_CUR_SETCUR) && !cursor->enable)
1036 /* fix cursor color - XFree86 forgets to restore it properly */
1037 if (cursor->set && FB_CUR_SETCMAP) {
1038 struct fb_cmap cmap = cursor->image.cmap;
1039 unsigned long bg_color, fg_color;
1041 cmap.len = 2;/* Voodoo 3+ only support 2 color cursors*/
1042 fg_color = ((cmap.red[cmap.start] << 16) |
1043 (cmap.green[cmap.start] << 8) |
1044 (cmap.blue[cmap.start]));
1045 bg_color = ((cmap.red[cmap.start+1] << 16) |
1046 (cmap.green[cmap.start+1] << 8) |
1047 (cmap.blue[cmap.start+1]));
1048 fb_copy_cmap(&cmap, &info->cursor.image.cmap, 0);
1049 spin_lock_irqsave(&par->DAClock, flags);
1050 banshee_make_room(par, 2);
1051 tdfx_outl(par, HWCURC0, bg_color);
1052 tdfx_outl(par, HWCURC1, fg_color);
1053 spin_unlock_irqrestore(&par->DAClock, flags);
1056 if (cursor->set && FB_CUR_SETPOS) {
1059 x = cursor->image.dx;
1060 y = cursor->image.dy;
1061 y -= info->var.yoffset;
1062 info->cursor.image.dx = x;
1063 info->cursor.image.dy = y;
1066 spin_lock_irqsave(&par->DAClock, flags);
1067 banshee_make_room(par, 1);
1068 tdfx_outl(par, HWCURLOC, (y << 16) + x);
1069 spin_unlock_irqrestore(&par->DAClock, flags);
1072 /* Not supported so we fake it */
1073 if (cursor->set && FB_CUR_SETHOT) {
1074 info->cursor.hot.x = cursor->hot.x;
1075 info->cursor.hot.y = cursor->hot.y;
1078 if (cursor->set && FB_CUR_SETSHAPE) {
1080 * Voodoo 3 and above cards use 2 monochrome cursor patterns.
1081 * The reason is so the card can fetch 8 words at a time
1082 * and are stored on chip for use for the next 8 scanlines.
1083 * This reduces the number of times for access to draw the
1084 * cursor for each screen refresh.
1085 * Each pattern is a bitmap of 64 bit wide and 64 bit high
1086 * (total of 8192 bits or 1024 Kbytes). The two patterns are
1087 * stored in such a way that pattern 0 always resides in the
1088 * lower half (least significant 64 bits) of a 128 bit word
1089 * and pattern 1 the upper half. If you examine the data of
1090 * the cursor image the graphics card uses then from the
1091 * begining you see line one of pattern 0, line one of
1092 * pattern 1, line two of pattern 0, line two of pattern 1,
1093 * etc etc. The linear stride for the cursor is always 16 bytes
1094 * (128 bits) which is the maximum cursor width times two for
1095 * the two monochrome patterns.
1097 u8 *cursorbase = (u8 *) info->cursor.image.data;
1098 char *bitmap = (char *)cursor->image.data;
1099 char *mask = cursor->mask;
1102 for (i = 0; i < 64; i++) {
1103 if (i < cursor->image.height) {
1104 j = (cursor->image.width + 7) >> 3;
1108 /* Pattern 0. Copy the cursor bitmap to it */
1109 fb_writeb(*bitmap, cursorbase + h);
1111 /* Pattern 1. Copy the cursor mask to it */
1112 fb_writeb(*mask, cursorbase + h + 8);
1117 fb_writeb(0, cursorbase + h);
1118 fb_writeb(~0, cursorbase + h + 8);
1122 fb_writel(0, cursorbase + h);
1123 fb_writel(0, cursorbase + h + 4);
1124 fb_writel(~0, cursorbase + h + 8);
1125 fb_writel(~0, cursorbase + h + 12);
1130 /* Turn the cursor on */
1132 info->cursor = *cursor;
1133 mod_timer(&par->hwcursor.timer, jiffies+HZ/2);
1134 spin_lock_irqsave(&par->DAClock, flags);
1135 banshee_make_room(par, 1);
1136 tdfx_outl(par, VIDPROCCFG, par->hwcursor.enable);
1137 spin_unlock_irqrestore(&par->DAClock, flags);
1142 * tdfxfb_probe - Device Initializiation
1144 * @pdev: PCI Device to initialize
1145 * @id: PCI Device ID
1147 * Initializes and allocates resources for PCI device @pdev.
1150 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
1151 const struct pci_device_id *id)
1153 struct tdfx_par *default_par;
1154 struct fb_info *info;
1157 if ((err = pci_enable_device(pdev))) {
1158 printk(KERN_WARNING "tdfxfb: Can't enable pdev: %d\n", err);
1162 size = sizeof(struct fb_info)+sizeof(struct tdfx_par)+16*sizeof(u32);
1164 info = kmalloc(size, GFP_KERNEL);
1166 if (!info) return -ENOMEM;
1168 memset(info, 0, size);
1170 default_par = (struct tdfx_par *) (info + 1);
1172 /* Configure the default fb_fix_screeninfo first */
1173 switch (pdev->device) {
1174 case PCI_DEVICE_ID_3DFX_BANSHEE:
1175 strcat(tdfx_fix.id, " Banshee");
1176 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
1178 case PCI_DEVICE_ID_3DFX_VOODOO3:
1179 strcat(tdfx_fix.id, " Voodoo3");
1180 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
1182 case PCI_DEVICE_ID_3DFX_VOODOO5:
1183 strcat(tdfx_fix.id, " Voodoo5");
1184 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
1188 tdfx_fix.mmio_start = pci_resource_start(pdev, 0);
1189 tdfx_fix.mmio_len = pci_resource_len(pdev, 0);
1190 default_par->regbase_virt = ioremap_nocache(tdfx_fix.mmio_start, tdfx_fix.mmio_len);
1191 if (!default_par->regbase_virt) {
1192 printk("fb: Can't remap %s register area.\n", tdfx_fix.id);
1196 if (!request_mem_region(pci_resource_start(pdev, 0),
1197 pci_resource_len(pdev, 0), "tdfx regbase")) {
1198 printk(KERN_WARNING "tdfxfb: Can't reserve regbase\n");
1202 tdfx_fix.smem_start = pci_resource_start(pdev, 1);
1203 if (!(tdfx_fix.smem_len = do_lfb_size(default_par, pdev->device))) {
1204 printk("fb: Can't count %s memory.\n", tdfx_fix.id);
1205 release_mem_region(pci_resource_start(pdev, 0),
1206 pci_resource_len(pdev, 0));
1210 if (!request_mem_region(pci_resource_start(pdev, 1),
1211 pci_resource_len(pdev, 1), "tdfx smem")) {
1212 printk(KERN_WARNING "tdfxfb: Can't reserve smem\n");
1213 release_mem_region(pci_resource_start(pdev, 0),
1214 pci_resource_len(pdev, 0));
1218 info->screen_base = ioremap_nocache(tdfx_fix.smem_start,
1220 if (!info->screen_base) {
1221 printk("fb: Can't remap %s framebuffer.\n", tdfx_fix.id);
1222 release_mem_region(pci_resource_start(pdev, 1),
1223 pci_resource_len(pdev, 1));
1224 release_mem_region(pci_resource_start(pdev, 0),
1225 pci_resource_len(pdev, 0));
1229 default_par->iobase = pci_resource_start(pdev, 2);
1231 if (!request_region(pci_resource_start(pdev, 2),
1232 pci_resource_len(pdev, 2), "tdfx iobase")) {
1233 printk(KERN_WARNING "tdfxfb: Can't reserve iobase\n");
1234 release_mem_region(pci_resource_start(pdev, 1),
1235 pci_resource_len(pdev, 1));
1236 release_mem_region(pci_resource_start(pdev, 0),
1237 pci_resource_len(pdev, 0));
1241 printk("fb: %s memory = %dK\n", tdfx_fix.id, tdfx_fix.smem_len >> 10);
1243 tdfx_fix.ypanstep = nopan ? 0 : 1;
1244 tdfx_fix.ywrapstep = nowrap ? 0 : 1;
1246 info->fbops = &tdfxfb_ops;
1247 info->fix = tdfx_fix;
1248 info->par = default_par;
1249 info->pseudo_palette = (void *)(default_par + 1);
1250 info->flags = FBINFO_FLAG_DEFAULT;
1254 mode_option = "640x480@60";
1256 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1257 if (!err || err == 4)
1259 info->var = tdfx_var;
1261 size = (info->var.bits_per_pixel == 8) ? 256 : 16;
1262 fb_alloc_cmap(&info->cmap, size, 0);
1264 if (register_framebuffer(info) < 0) {
1265 printk("tdfxfb: can't register framebuffer\n");
1271 pci_set_drvdata(pdev, info);
1276 * Cleanup after anything that was remapped/allocated.
1278 if (default_par->regbase_virt)
1279 iounmap(default_par->regbase_virt);
1280 if (info->screen_base)
1281 iounmap(info->screen_base);
1287 * tdfxfb_remove - Device removal
1289 * @pdev: PCI Device to cleanup
1291 * Releases all resources allocated during the course of the driver's
1292 * lifetime for the PCI device @pdev.
1295 static void __devexit tdfxfb_remove(struct pci_dev *pdev)
1297 struct fb_info *info = pci_get_drvdata(pdev);
1298 struct tdfx_par *par = (struct tdfx_par *) info->par;
1300 unregister_framebuffer(info);
1301 iounmap(par->regbase_virt);
1302 iounmap(info->screen_base);
1304 /* Clean up after reserved regions */
1305 release_region(pci_resource_start(pdev, 2),
1306 pci_resource_len(pdev, 2));
1307 release_mem_region(pci_resource_start(pdev, 1),
1308 pci_resource_len(pdev, 1));
1309 release_mem_region(pci_resource_start(pdev, 0),
1310 pci_resource_len(pdev, 0));
1311 pci_set_drvdata(pdev, NULL);
1315 int __init tdfxfb_init(void)
1317 return pci_module_init(&tdfxfb_driver);
1320 static void __exit tdfxfb_exit(void)
1322 pci_unregister_driver(&tdfxfb_driver);
1325 MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
1326 MODULE_DESCRIPTION("3Dfx framebuffer device driver");
1327 MODULE_LICENSE("GPL");
1330 module_init(tdfxfb_init);
1332 module_exit(tdfxfb_exit);
1336 void tdfxfb_setup(char *options, int *ints)
1340 if (!options || !*options)
1343 while ((this_opt = strsep(&options, ",")) != NULL) {
1346 if (!strcmp(this_opt, "inverse")) {
1349 } else if(!strcmp(this_opt, "nopan")) {
1351 } else if(!strcmp(this_opt, "nowrap")) {
1354 mode_option = this_opt;