2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
25 #include <linux/pci.h>
27 #include <video/tgafb.h>
28 #include <linux/selection.h>
34 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
35 static int tgafb_set_par(struct fb_info *);
36 static void tgafb_set_pll(struct tga_par *, int);
37 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
38 unsigned, struct fb_info *);
39 static int tgafb_blank(int, struct fb_info *);
40 static void tgafb_init_fix(struct fb_info *);
42 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
43 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
44 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
46 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
48 static void tgafb_pci_unregister(struct pci_dev *);
51 static const char *mode_option = "640x480@60";
55 * Frame buffer operations
58 static struct fb_ops tgafb_ops = {
60 .fb_check_var = tgafb_check_var,
61 .fb_set_par = tgafb_set_par,
62 .fb_setcolreg = tgafb_setcolreg,
63 .fb_blank = tgafb_blank,
64 .fb_fillrect = tgafb_fillrect,
65 .fb_copyarea = tgafb_copyarea,
66 .fb_imageblit = tgafb_imageblit,
67 .fb_cursor = soft_cursor,
72 * PCI registration operations
75 static struct pci_device_id const tgafb_pci_table[] = {
76 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, PCI_ANY_ID, PCI_ANY_ID,
80 static struct pci_driver tgafb_driver = {
82 .id_table = tgafb_pci_table,
83 .probe = tgafb_pci_register,
84 .remove = __devexit_p(tgafb_pci_unregister),
89 * tgafb_check_var - Optional function. Validates a var passed in.
90 * @var: frame buffer variable screen structure
91 * @info: frame buffer structure that represents a single frame buffer
94 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
96 struct tga_par *par = (struct tga_par *)info->par;
98 if (par->tga_type == TGA_TYPE_8PLANE) {
99 if (var->bits_per_pixel != 8)
102 if (var->bits_per_pixel != 32)
106 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
110 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
112 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
115 /* Some of the acceleration routines assume the line width is
116 a multiple of 64 bytes. */
117 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
124 * tgafb_set_par - Optional function. Alters the hardware state.
125 * @info: frame buffer structure that represents a single frame buffer
128 tgafb_set_par(struct fb_info *info)
130 static unsigned int const deep_presets[4] = {
136 static unsigned int const rasterop_presets[4] = {
142 static unsigned int const mode_presets[4] = {
148 static unsigned int const base_addr_presets[4] = {
155 struct tga_par *par = (struct tga_par *) info->par;
156 u32 htimings, vtimings, pll_freq;
160 /* Encode video timings. */
161 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
162 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
163 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
164 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
165 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
166 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
167 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
168 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
169 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
171 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
172 htimings |= TGA_HORIZ_POLARITY;
173 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
174 vtimings |= TGA_VERT_POLARITY;
176 par->htimings = htimings;
177 par->vtimings = vtimings;
179 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
181 /* Store other useful values in par. */
182 par->xres = info->var.xres;
183 par->yres = info->var.yres;
184 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
185 par->bits_per_pixel = info->var.bits_per_pixel;
187 tga_type = par->tga_type;
189 /* First, disable video. */
190 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
192 /* Write the DEEP register. */
193 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
196 TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
197 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
201 /* Write some more registers. */
202 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
203 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
204 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
206 /* Calculate & write the PLL. */
207 tgafb_set_pll(par, pll_freq);
209 /* Write some more registers. */
210 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
211 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
213 /* Init video timing regs. */
214 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
215 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
217 /* Initalise RAMDAC. */
218 if (tga_type == TGA_TYPE_8PLANE) {
220 /* Init BT485 RAMDAC registers. */
221 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
223 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
224 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
225 BT485_WRITE(par, 0x40, BT485_CMD_1);
226 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
227 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
229 /* Fill palette registers. */
230 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
231 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
233 for (i = 0; i < 16; i++) {
235 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
237 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
239 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
242 for (i = 0; i < 240*3; i += 4) {
243 TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
245 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
247 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
249 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
253 } else { /* 24-plane or 24plusZ */
255 /* Init BT463 registers. */
256 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
257 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
258 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
259 (par->sync_on_green ? 0x80 : 0x40));
261 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
262 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
263 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
264 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
266 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
267 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
268 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
269 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
271 /* Fill the palette. */
272 BT463_LOAD_ADDR(par, 0x0000);
273 TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
275 for (i = 0; i < 16; i++) {
277 TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
279 TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
281 TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
284 for (i = 0; i < 512*3; i += 4) {
285 TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
287 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
289 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
291 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
295 /* Fill window type table after start of vertical retrace. */
296 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
298 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
300 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
302 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
304 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
305 TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG);
307 for (i = 0; i < 16; i++) {
308 TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10),
310 TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10),
312 TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10),
318 /* Finally, enable video scan (and pray for the monitor... :-) */
319 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
324 #define DIFFCHECK(X) \
327 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
330 if (delta < min_diff) \
331 min_diff = delta, vm = m, va = a, vr = r; \
336 tgafb_set_pll(struct tga_par *par, int f)
338 int n, shift, base, min_diff, target;
339 int r,a,m,vm = 34, va = 1, vr = 30;
341 for (r = 0 ; r < 12 ; r++)
342 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
344 if (f > TGA_PLL_MAX_FREQ)
345 f = TGA_PLL_MAX_FREQ;
347 if (f >= TGA_PLL_MAX_FREQ / 2)
349 else if (f >= TGA_PLL_MAX_FREQ / 4)
354 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
355 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
357 for (r = 0 ; r < 10 ; r++)
358 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
361 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
362 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
364 else if (f <= 200000) {
365 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
366 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
369 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
370 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
373 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
374 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
375 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
376 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
377 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
378 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
380 target = (f << shift) / TGA_PLL_BASE_FREQ;
381 min_diff = TGA_PLL_MAX_FREQ;
388 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
389 m = ((n + 3) / 7) - 1;
391 DIFFCHECK((m + 1) * 7);
393 DIFFCHECK((m + 1) * 7);
404 for (r = 0; r < 8; r++)
405 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
406 for (r = 0; r < 8 ; r++)
407 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
408 for (r = 0; r < 7 ; r++)
409 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
410 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
415 * tgafb_setcolreg - Optional function. Sets a color register.
416 * @regno: boolean, 0 copy local, 1 get_user() function
417 * @red: frame buffer colormap structure
418 * @green: The green value which can be up to 16 bits wide
419 * @blue: The blue value which can be up to 16 bits wide.
420 * @transp: If supported the alpha value which can be up to 16 bits wide.
421 * @info: frame buffer info structure
424 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
425 unsigned transp, struct fb_info *info)
427 struct tga_par *par = (struct tga_par *) info->par;
435 if (par->tga_type == TGA_TYPE_8PLANE) {
436 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
437 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
438 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
439 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
440 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
441 } else if (regno < 16) {
442 u32 value = (red << 16) | (green << 8) | blue;
443 ((u32 *)info->pseudo_palette)[regno] = value;
451 * tgafb_blank - Optional function. Blanks the display.
452 * @blank_mode: the blank mode we want.
453 * @info: frame buffer structure that represents a single frame buffer
456 tgafb_blank(int blank, struct fb_info *info)
458 struct tga_par *par = (struct tga_par *) info->par;
459 u32 vhcr, vvcr, vvvr;
462 local_irq_save(flags);
464 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
465 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
466 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
467 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
470 case 0: /* Unblanking */
471 if (par->vesa_blanked) {
472 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
473 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
474 par->vesa_blanked = 0;
476 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
479 case 1: /* Normal blanking */
480 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
484 case 2: /* VESA blank (vsync off) */
485 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
486 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
487 par->vesa_blanked = 1;
490 case 3: /* VESA blank (hsync off) */
491 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
492 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
493 par->vesa_blanked = 1;
496 case 4: /* Poweroff */
497 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
498 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
499 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
500 par->vesa_blanked = 1;
504 local_irq_restore(flags);
514 * tgafb_imageblit - REQUIRED function. Can use generic routines if
515 * non acclerated hardware and packed pixel based.
516 * Copies a image from system memory to the screen.
518 * @info: frame buffer structure that represents a single frame buffer
519 * @image: structure defining the image.
522 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
524 static unsigned char const bitrev[256] = {
525 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
526 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
527 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
528 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
529 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
530 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
531 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
532 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
533 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
534 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
535 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
536 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
537 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
538 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
539 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
540 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
541 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
542 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
543 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
544 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
545 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
546 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
547 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
548 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
549 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
550 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
551 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
552 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
553 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
554 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
555 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
556 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
559 struct tga_par *par = (struct tga_par *) info->par;
560 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
561 unsigned long rincr, line_length, shift, pos, is8bpp;
563 const unsigned char *data;
564 void *regs_base, *fb_base;
568 width = image->width;
569 height = image->height;
570 vxres = info->var.xres_virtual;
571 vyres = info->var.yres_virtual;
572 line_length = info->fix.line_length;
573 rincr = (width + 7) / 8;
575 /* Crop the image to the screen. */
576 if (dx > vxres || dy > vyres)
578 if (dx + width > vxres)
580 if (dy + height > vyres)
583 /* For copies that aren't pixel expansion, there's little we
584 can do better than the generic code. */
585 /* ??? There is a DMA write mode; I wonder if that could be
586 made to pull the data from the image buffer... */
587 if (image->depth > 1) {
588 cfb_imageblit(info, image);
592 regs_base = par->tga_regs_base;
593 fb_base = par->tga_fb_base;
594 is8bpp = info->var.bits_per_pixel == 8;
596 /* Expand the color values to fill 32-bits. */
597 /* ??? Would be nice to notice colour changes elsewhere, so
598 that we can do this only when necessary. */
599 fgcolor = image->fg_color;
600 bgcolor = image->bg_color;
602 fgcolor |= fgcolor << 8;
603 fgcolor |= fgcolor << 16;
604 bgcolor |= bgcolor << 8;
605 bgcolor |= bgcolor << 16;
608 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
610 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
612 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
613 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
615 /* Acquire proper alignment; set up the PIXELMASK register
616 so that we only write the proper character cell. */
617 pos = dy * line_length;
624 shift = (pos & 7) >> 2;
628 data = (const unsigned char *) image->data;
630 /* Enable opaque stipple mode. */
632 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
633 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
634 regs_base + TGA_MODE_REG);
636 if (width + shift <= 32) {
637 unsigned long bwidth;
639 /* Handle common case of imaging a single character, in
640 a font less than 32 pixels wide. */
642 pixelmask = (1 << width) - 1;
644 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
647 bwidth = (width + 7) / 8;
649 for (i = 0; i < height; ++i) {
652 /* The image data is bit big endian; we need
654 for (j = 0; j < bwidth; ++j)
655 mask |= bitrev[data[j]] << (j * 8);
657 __raw_writel(mask << shift, fb_base + pos);
663 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
664 } else if (shift == 0) {
665 unsigned long pos0 = pos;
666 const unsigned char *data0 = data;
667 unsigned long bincr = (is8bpp ? 8 : 8*4);
668 unsigned long bwidth;
670 /* Handle another common case in which accel_putcs
671 generates a large bitmap, which happens to be aligned.
672 Allow the tail to be misaligned. This case is
673 interesting because we've not got to hold partial
674 bytes across the words being written. */
678 bwidth = (width / 8) & -4;
679 for (i = 0; i < height; ++i) {
680 for (j = 0; j < bwidth; j += 4) {
682 mask |= bitrev[data[j+0]] << (0 * 8);
683 mask |= bitrev[data[j+1]] << (1 * 8);
684 mask |= bitrev[data[j+2]] << (2 * 8);
685 mask |= bitrev[data[j+3]] << (3 * 8);
686 __raw_writel(mask, fb_base + pos + j*bincr);
693 pixelmask = (1ul << (width & 31)) - 1;
695 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
698 pos = pos0 + bwidth*bincr;
699 data = data0 + bwidth;
700 bwidth = ((width & 31) + 7) / 8;
702 for (i = 0; i < height; ++i) {
704 for (j = 0; j < bwidth; ++j)
705 mask |= bitrev[data[j]] << (j * 8);
706 __raw_writel(mask, fb_base + pos);
711 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
714 unsigned long pos0 = pos;
715 const unsigned char *data0 = data;
716 unsigned long bincr = (is8bpp ? 8 : 8*4);
717 unsigned long bwidth;
719 /* Finally, handle the generic case of misaligned start.
720 Here we split the write into 16-bit spans. This allows
721 us to use only one pixel mask, instead of four as would
722 be required by writing 24-bit spans. */
724 pixelmask = 0xffff << shift;
725 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
728 bwidth = (width / 8) & -2;
729 for (i = 0; i < height; ++i) {
730 for (j = 0; j < bwidth; j += 2) {
732 mask |= bitrev[data[j+0]] << (0 * 8);
733 mask |= bitrev[data[j+1]] << (1 * 8);
735 __raw_writel(mask, fb_base + pos + j*bincr);
742 pixelmask = ((1ul << (width & 15)) - 1) << shift;
744 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
747 pos = pos0 + bwidth*bincr;
748 data = data0 + bwidth;
749 bwidth = (width & 15) > 8;
751 for (i = 0; i < height; ++i) {
752 u32 mask = bitrev[data[0]];
754 mask |= bitrev[data[1]] << 8;
756 __raw_writel(mask, fb_base + pos);
762 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
765 /* Disable opaque stipple mode. */
767 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
768 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
769 regs_base + TGA_MODE_REG);
773 * tgafb_fillrect - REQUIRED function. Can use generic routines if
774 * non acclerated hardware and packed pixel based.
775 * Draws a rectangle on the screen.
777 * @info: frame buffer structure that represents a single frame buffer
778 * @rect: structure defining the rectagle and operation.
781 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
783 struct tga_par *par = (struct tga_par *) info->par;
784 int is8bpp = info->var.bits_per_pixel == 8;
785 u32 dx, dy, width, height, vxres, vyres, color;
786 unsigned long pos, align, line_length, i, j;
787 void *regs_base, *fb_base;
792 height = rect->height;
793 vxres = info->var.xres_virtual;
794 vyres = info->var.yres_virtual;
795 line_length = info->fix.line_length;
796 regs_base = par->tga_regs_base;
797 fb_base = par->tga_fb_base;
799 /* Crop the rectangle to the screen. */
800 if (dx > vxres || dy > vyres || !width || !height)
802 if (dx + width > vxres)
804 if (dy + height > vyres)
807 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
809 /* ??? We could implement ROP_XOR with opaque fill mode
810 and a RasterOp setting of GXxor, but as far as I can
811 tell, this mode is not actually used in the kernel.
812 Thus I am ignoring it for now. */
813 if (rect->rop != ROP_COPY) {
814 cfb_fillrect(info, rect);
818 /* Expand the color value to fill 8 pixels. */
822 color |= color << 16;
823 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
824 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
827 color = ((u32 *)info->pseudo_palette)[color];
828 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
829 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
830 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
831 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
832 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
833 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
834 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
835 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
838 /* The DATA register holds the fill mask for block fill mode.
839 Since we're not stippling, this is all ones. */
840 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
842 /* Enable block fill mode. */
844 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
845 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
846 regs_base + TGA_MODE_REG);
849 /* We can fill 2k pixels per operation. Notice blocks that fit
850 the width of the screen so that we can take advantage of this
851 and fill more than one line per write. */
852 if (width == line_length)
853 width *= height, height = 1;
855 /* The write into the frame buffer must be aligned to 4 bytes,
856 but we are allowed to encode the offset within the word in
857 the data word written. */
858 align = (pos & 3) << 16;
864 data = (width - 1) | align;
866 for (i = 0; i < height; ++i) {
867 __raw_writel(data, fb_base + pos);
871 unsigned long Bpp = (is8bpp ? 1 : 4);
872 unsigned long nwidth = width & -2048;
875 fdata = (2048 - 1) | align;
876 ldata = ((width & 2047) - 1) | align;
878 for (i = 0; i < height; ++i) {
879 for (j = 0; j < nwidth; j += 2048)
880 __raw_writel(fdata, fb_base + pos + j*Bpp);
882 __raw_writel(ldata, fb_base + pos + j*Bpp);
888 /* Disable block fill mode. */
890 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
891 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
892 regs_base + TGA_MODE_REG);
896 * tgafb_copyarea - REQUIRED function. Can use generic routines if
897 * non acclerated hardware and packed pixel based.
898 * Copies on area of the screen to another area.
900 * @info: frame buffer structure that represents a single frame buffer
901 * @area: structure defining the source and destination.
904 /* Handle the special case of copying entire lines, e.g. during scrolling.
905 We can avoid a lot of needless computation in this case. In the 8bpp
906 case we need to use the COPY64 registers instead of mask writes into
907 the frame buffer to achieve maximum performance. */
910 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
911 u32 height, u32 width)
913 struct tga_par *par = (struct tga_par *) info->par;
914 void *tga_regs = par->tga_regs_base;
915 unsigned long dpos, spos, i, n64;
917 /* Set up the MODE and PIXELSHIFT registers. */
918 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
919 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
922 n64 = (height * width) / 64;
925 spos = (sy + height) * width;
926 dpos = (dy + height) * width;
928 for (i = 0; i < n64; ++i) {
931 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
933 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
940 for (i = 0; i < n64; ++i) {
941 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
943 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
950 /* Reset the MODE register to normal. */
951 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
955 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
956 u32 height, u32 width)
958 struct tga_par *par = (struct tga_par *) info->par;
959 void *tga_regs = par->tga_regs_base;
960 void *tga_fb = par->tga_fb_base;
962 unsigned long i, n16;
964 /* Set up the MODE and PIXELSHIFT registers. */
965 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
966 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
969 n16 = (height * width) / 16;
972 src = tga_fb + (sy + height) * width * 4;
973 dst = tga_fb + (dy + height) * width * 4;
975 for (i = 0; i < n16; ++i) {
978 __raw_writel(0xffff, src);
980 __raw_writel(0xffff, dst);
984 src = tga_fb + sy * width * 4;
985 dst = tga_fb + dy * width * 4;
987 for (i = 0; i < n16; ++i) {
988 __raw_writel(0xffff, src);
990 __raw_writel(0xffff, dst);
997 /* Reset the MODE register to normal. */
998 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1001 /* The general case of forward copy in 8bpp mode. */
1003 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1004 u32 height, u32 width, u32 line_length)
1006 struct tga_par *par = (struct tga_par *) info->par;
1007 unsigned long i, copied, left;
1008 unsigned long dpos, spos, dalign, salign, yincr;
1009 u32 smask_first, dmask_first, dmask_last;
1010 int pixel_shift, need_prime, need_second;
1011 unsigned long n64, n32, xincr_first;
1012 void *tga_regs, *tga_fb;
1014 yincr = line_length;
1021 /* Compute the offsets and alignments in the frame buffer.
1022 More than anything else, these control how we do copies. */
1023 dpos = dy * line_length + dx;
1024 spos = sy * line_length + sx;
1030 /* Compute the value for the PIXELSHIFT register. This controls
1031 both non-co-aligned source and destination and copy direction. */
1032 if (dalign >= salign)
1033 pixel_shift = dalign - salign;
1035 pixel_shift = 8 - (salign - dalign);
1037 /* Figure out if we need an additional priming step for the
1038 residue register. */
1039 need_prime = (salign > dalign);
1043 /* Begin by copying the leading unaligned destination. Copy enough
1044 to make the next destination address 32-byte aligned. */
1045 copied = 32 - (dalign + (dpos & 31));
1048 xincr_first = (copied + 7) & -8;
1049 smask_first = dmask_first = (1ul << copied) - 1;
1050 smask_first <<= salign;
1051 dmask_first <<= dalign + need_prime*8;
1052 if (need_prime && copied > 24)
1054 left = width - copied;
1056 /* Care for small copies. */
1057 if (copied > width) {
1059 t = (1ul << width) - 1;
1060 t <<= dalign + need_prime*8;
1065 /* Attempt to use 64-byte copies. This is only possible if the
1066 source and destination are co-aligned at 64 bytes. */
1067 n64 = need_second = 0;
1068 if ((dpos & 63) == (spos & 63)
1069 && (height == 1 || line_length % 64 == 0)) {
1070 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1071 need_second = (dpos + xincr_first) & 63;
1072 if ((need_second & 32) != need_second)
1073 printk(KERN_ERR "tgafb: need_second wrong\n");
1074 if (left >= need_second + 64) {
1075 left -= need_second;
1082 /* Copy trailing full 32-byte sections. This will be the main
1083 loop if the 64 byte loop can't be used. */
1087 /* Copy the trailing unaligned destination. */
1088 dmask_last = (1ul << left) - 1;
1090 tga_regs = par->tga_regs_base;
1091 tga_fb = par->tga_fb_base;
1093 /* Set up the MODE and PIXELSHIFT registers. */
1094 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1095 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1098 for (i = 0; i < height; ++i) {
1102 sfb = tga_fb + spos;
1103 dfb = tga_fb + dpos;
1105 __raw_writel(smask_first, sfb);
1107 __raw_writel(dmask_first, dfb);
1114 __raw_writel(0xffffffff, sfb);
1116 __raw_writel(0xffffffff, dfb);
1122 if (n64 && (((long)sfb | (long)dfb) & 63))
1124 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1127 for (j = 0; j < n64; ++j) {
1128 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1130 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1136 for (j = 0; j < n32; ++j) {
1137 __raw_writel(0xffffffff, sfb);
1139 __raw_writel(0xffffffff, dfb);
1146 __raw_writel(0xffffffff, sfb);
1148 __raw_writel(dmask_last, dfb);
1156 /* Reset the MODE register to normal. */
1157 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1160 /* The (almost) general case of backward copy in 8bpp mode. */
1162 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1163 u32 height, u32 width, u32 line_length,
1164 const struct fb_copyarea *area)
1166 struct tga_par *par = (struct tga_par *) info->par;
1167 unsigned long i, left, yincr;
1168 unsigned long depos, sepos, dealign, sealign;
1169 u32 mask_first, mask_last;
1171 void *tga_regs, *tga_fb;
1173 yincr = line_length;
1180 /* Compute the offsets and alignments in the frame buffer.
1181 More than anything else, these control how we do copies. */
1182 depos = dy * line_length + dx + width;
1183 sepos = sy * line_length + sx + width;
1184 dealign = depos & 7;
1185 sealign = sepos & 7;
1187 /* ??? The documentation appears to be incorrect (or very
1188 misleading) wrt how pixel shifting works in backward copy
1189 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1190 Do handle the common case of co-aligned backward copies,
1191 but frob everything else back on generic code. */
1192 if (dealign != sealign) {
1193 cfb_copyarea(info, area);
1197 /* We begin the copy with the trailing pixels of the
1198 unaligned destination. */
1199 mask_first = (1ul << dealign) - 1;
1200 left = width - dealign;
1202 /* Care for small copies. */
1203 if (dealign > width) {
1204 mask_first ^= (1ul << (dealign - width)) - 1;
1208 /* Next copy full words at a time. */
1212 /* Finally copy the unaligned head of the span. */
1213 mask_last = -1 << (32 - left);
1215 tga_regs = par->tga_regs_base;
1216 tga_fb = par->tga_fb_base;
1218 /* Set up the MODE and PIXELSHIFT registers. */
1219 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1220 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1223 for (i = 0; i < height; ++i) {
1227 sfb = tga_fb + sepos;
1228 dfb = tga_fb + depos;
1230 __raw_writel(mask_first, sfb);
1232 __raw_writel(mask_first, dfb);
1236 for (j = 0; j < n32; ++j) {
1239 __raw_writel(0xffffffff, sfb);
1241 __raw_writel(0xffffffff, dfb);
1248 __raw_writel(mask_last, sfb);
1250 __raw_writel(mask_last, dfb);
1258 /* Reset the MODE register to normal. */
1259 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1263 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1265 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1266 unsigned long line_length, bpp;
1270 width = area->width;
1271 height = area->height;
1274 vxres = info->var.xres_virtual;
1275 vyres = info->var.yres_virtual;
1276 line_length = info->fix.line_length;
1278 /* The top left corners must be in the virtual screen. */
1279 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1282 /* Clip the destination. */
1283 if (dx + width > vxres)
1285 if (dy + height > vyres)
1286 height = vyres - dy;
1288 /* The source must be completely inside the virtual screen. */
1289 if (sx + width > vxres || sy + height > vyres)
1292 bpp = info->var.bits_per_pixel;
1294 /* Detect copies of the entire line. */
1295 if (width * (bpp >> 3) == line_length) {
1297 copyarea_line_8bpp(info, dy, sy, height, width);
1299 copyarea_line_32bpp(info, dy, sy, height, width);
1302 /* ??? The documentation is unclear to me exactly how the pixelshift
1303 register works in 32bpp mode. Since I don't have hardware to test,
1304 give up for now and fall back on the generic routines. */
1306 cfb_copyarea(info, area);
1308 /* Detect overlapping source and destination that requires
1310 else if (dy == sy && dx > sx && dx < sx + width)
1311 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1312 width, line_length, area);
1314 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1315 width, line_length);
1324 tgafb_init_fix(struct fb_info *info)
1326 struct tga_par *par = (struct tga_par *)info->par;
1327 u8 tga_type = par->tga_type;
1328 const char *tga_type_name;
1331 case TGA_TYPE_8PLANE:
1332 tga_type_name = "Digital ZLXp-E1";
1334 case TGA_TYPE_24PLANE:
1335 tga_type_name = "Digital ZLXp-E2";
1337 case TGA_TYPE_24PLUSZ:
1338 tga_type_name = "Digital ZLXp-E3";
1341 tga_type_name = "Unknown";
1345 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1347 info->fix.type = FB_TYPE_PACKED_PIXELS;
1348 info->fix.type_aux = 0;
1349 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1350 ? FB_VISUAL_PSEUDOCOLOR
1351 : FB_VISUAL_TRUECOLOR);
1353 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1354 info->fix.smem_start = (size_t) par->tga_fb_base;
1355 info->fix.smem_len = info->fix.line_length * par->yres;
1356 info->fix.mmio_start = (size_t) par->tga_regs_base;
1357 info->fix.mmio_len = 512;
1359 info->fix.xpanstep = 0;
1360 info->fix.ypanstep = 0;
1361 info->fix.ywrapstep = 0;
1363 info->fix.accel = FB_ACCEL_DEC_TGA;
1366 static __devinit int
1367 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
1369 static unsigned int const fb_offset_presets[4] = {
1370 TGA_8PLANE_FB_OFFSET,
1371 TGA_24PLANE_FB_OFFSET,
1373 TGA_24PLUSZ_FB_OFFSET
1377 struct fb_info info;
1379 u32 pseudo_palette[16];
1383 unsigned long bar0_start, bar0_len;
1387 /* Enable device in PCI config. */
1388 if (pci_enable_device(pdev)) {
1389 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1393 /* Allocate the fb and par structures. */
1394 all = kmalloc(sizeof(*all), GFP_KERNEL);
1396 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1399 memset(all, 0, sizeof(*all));
1400 pci_set_drvdata(pdev, all);
1402 /* Request the mem regions. */
1403 bar0_start = pci_resource_start(pdev, 0);
1404 bar0_len = pci_resource_len(pdev, 0);
1406 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1407 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1411 /* Map the framebuffer. */
1412 mem_base = ioremap(bar0_start, bar0_len);
1414 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1418 /* Grab info about the card. */
1419 tga_type = (readl(mem_base) >> 12) & 0x0f;
1420 all->par.pdev = pdev;
1421 all->par.tga_mem_base = mem_base;
1422 all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type];
1423 all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET;
1424 all->par.tga_type = tga_type;
1425 pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev);
1427 /* Setup framebuffer. */
1428 all->info.flags = FBINFO_FLAG_DEFAULT;
1429 all->info.fbops = &tgafb_ops;
1430 all->info.screen_base = (char *) all->par.tga_fb_base;
1431 all->info.currcon = -1;
1432 all->info.par = &all->par;
1433 all->info.pseudo_palette = all->pseudo_palette;
1435 /* This should give a reasonable default video mode. */
1437 ret = fb_find_mode(&all->info.var, &all->info, mode_option,
1439 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1440 if (ret == 0 || ret == 4) {
1441 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1446 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
1447 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1452 tgafb_set_par(&all->info);
1453 tgafb_init_fix(&all->info);
1455 if (register_framebuffer(&all->info) < 0) {
1456 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1461 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1462 all->par.tga_chip_rev);
1463 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
1464 pdev->bus->number, PCI_SLOT(pdev->devfn),
1465 PCI_FUNC(pdev->devfn));
1466 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
1467 all->info.node, all->info.fix.id, bar0_start);
1472 release_mem_region(bar0_start, bar0_len);
1481 return pci_module_init(&tgafb_driver);
1486 tgafb_pci_unregister(struct pci_dev *pdev)
1488 struct fb_info *info = pci_get_drvdata(pdev);
1489 struct tga_par *par = info->par;
1493 unregister_framebuffer(info);
1494 iounmap(par->tga_mem_base);
1495 release_mem_region(pci_resource_start(pdev, 0),
1496 pci_resource_len(pdev, 0));
1503 pci_unregister_driver(&tgafb_driver);
1509 tgafb_setup(char *arg)
1514 while ((this_opt = strsep(&arg, ","))) {
1517 if (!strncmp(this_opt, "mode:", 5))
1518 mode_option = this_opt+5;
1521 "tgafb: unknown parameter %s\n",
1528 #endif /* !MODULE */
1535 module_init(tgafb_init);
1536 module_exit(tgafb_exit);
1539 MODULE_DESCRIPTION("framebuffer driver for TGA chipset");
1540 MODULE_LICENSE("GPL");