1 #ifndef __ALPHA_IRONGATE__H__
2 #define __ALPHA_IRONGATE__H__
4 #include <linux/types.h>
5 #include <asm/compiler.h>
8 * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
9 * which provides memory controller and PCI access for NAUTILUS-based
10 * EV6 (21264) systems.
12 * This file is based on:
14 * IronGate management library, (c) 1999 Alpha Processor, Inc.
15 * Copyright (C) 1999 Alpha Processor, Inc.,
16 * (David Daniel, Stig Telfer, Soohoon Lee)
20 * The 21264 supports, and internally recognizes, a 44-bit physical
21 * address space that is divided equally between memory address space
22 * and I/O address space. Memory address space resides in the lower
23 * half of the physical address space (PA[43]=0) and I/O address space
24 * resides in the upper half of the physical address space (PA[43]=1).
28 * Irongate CSR map. Some of the CSRs are 8 or 16 bits, but all access
29 * through the routines given is 32-bit.
31 * The first 0x40 bytes are standard as per the PCI spec.
34 typedef volatile __u32 igcsr32;
37 igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */
38 igcsr32 stat_cmd; /* 0x04 - status, command */
39 igcsr32 class; /* 0x08 - class code, rev ID */
40 igcsr32 latency; /* 0x0C - header type, PCI latency */
41 igcsr32 bar0; /* 0x10 - BAR0 - AGP */
42 igcsr32 bar1; /* 0x14 - BAR1 - GART */
43 igcsr32 bar2; /* 0x18 - Power Management reg block */
45 igcsr32 rsrvd0[6]; /* 0x1C-0x33 reserved */
47 igcsr32 capptr; /* 0x34 - Capabilities pointer */
49 igcsr32 rsrvd1[2]; /* 0x38-0x3F reserved */
51 igcsr32 bacsr10; /* 0x40 - base address chip selects */
52 igcsr32 bacsr32; /* 0x44 - base address chip selects */
53 igcsr32 bacsr54_eccms761; /* 0x48 - 751: base addr. chip selects
54 761: ECC, mode/status */
56 igcsr32 rsrvd2[1]; /* 0x4C-0x4F reserved */
58 igcsr32 drammap; /* 0x50 - address mapping control */
59 igcsr32 dramtm; /* 0x54 - timing, driver strength */
60 igcsr32 dramms; /* 0x58 - DRAM mode/status */
62 igcsr32 rsrvd3[1]; /* 0x5C-0x5F reserved */
64 igcsr32 biu0; /* 0x60 - bus interface unit */
65 igcsr32 biusip; /* 0x64 - Serial initialisation pkt */
67 igcsr32 rsrvd4[2]; /* 0x68-0x6F reserved */
69 igcsr32 mro; /* 0x70 - memory request optimiser */
71 igcsr32 rsrvd5[3]; /* 0x74-0x7F reserved */
73 igcsr32 whami; /* 0x80 - who am I */
74 igcsr32 pciarb; /* 0x84 - PCI arbitration control */
75 igcsr32 pcicfg; /* 0x88 - PCI config status */
77 igcsr32 rsrvd6[4]; /* 0x8C-0x9B reserved */
79 igcsr32 pci_mem; /* 0x9C - PCI top of memory,
82 /* AGP (bus 1) control registers */
83 igcsr32 agpcap; /* 0xA0 - AGP Capability Identifier */
84 igcsr32 agpstat; /* 0xA4 - AGP status register */
85 igcsr32 agpcmd; /* 0xA8 - AGP control register */
86 igcsr32 agpva; /* 0xAC - AGP Virtual Address Space */
87 igcsr32 agpmode; /* 0xB0 - AGP/GART mode control */
93 igcsr32 dev_vendor; /* 0x00 - Device and Vendor IDs */
94 igcsr32 stat_cmd; /* 0x04 - Status and Command regs */
95 igcsr32 class; /* 0x08 - subclass, baseclass etc */
96 igcsr32 htype; /* 0x0C - header type (at 0x0E) */
97 igcsr32 rsrvd0[2]; /* 0x10-0x17 reserved */
98 igcsr32 busnos; /* 0x18 - Primary, secondary bus nos */
99 igcsr32 io_baselim_regs; /* 0x1C - IO base, IO lim, AGP status */
100 igcsr32 mem_baselim; /* 0x20 - memory base, memory lim */
101 igcsr32 pfmem_baselim; /* 0x24 - prefetchable base, lim */
102 igcsr32 rsrvd1[2]; /* 0x28-0x2F reserved */
103 igcsr32 io_baselim; /* 0x30 - IO base, IO limit */
104 igcsr32 rsrvd2[2]; /* 0x34-0x3B - reserved */
105 igcsr32 interrupt; /* 0x3C - interrupt, PCI bridge ctrl */
109 extern igcsr32 *IronECC;
115 /* Irongate is consistent with a subset of the Tsunami memory map */
116 #ifdef USE_48_BIT_KSEG
117 #define IRONGATE_BIAS 0x80000000000UL
119 #define IRONGATE_BIAS 0x10000000000UL
123 #define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
124 #define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
125 #define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
126 #define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
129 * PCI Configuration space accesses are formed like so:
131 * 0x1FE << 24 | : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 :
132 * : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 :
133 * ---bus numer--- -device-- -fun- ---register----
136 #define IGCSR(dev,fun,reg) ( IRONGATE_CONF | \
141 #define IRONGATE0 ((Irongate0 *) IGCSR(0, 0, 0))
142 #define IRONGATE1 ((Irongate1 *) IGCSR(1, 0, 0))
145 * Data structure for handling IRONGATE machine checks:
146 * This is the standard OSF logout frame
149 #define SCB_Q_SYSERR 0x620 /* OSF definitions */
150 #define SCB_Q_PROCERR 0x630
151 #define SCB_Q_SYSMCHK 0x660
152 #define SCB_Q_PROCMCHK 0x670
154 struct el_IRONGATE_sysdata_mcheck {
155 __u32 FrameSize; /* Bytes, including this field */
156 __u32 FrameFlags; /* <31> = Retry, <30> = Second Error */
157 __u32 CpuOffset; /* Offset to CPU-specific into */
158 __u32 SystemOffset; /* Offset to system-specific info */
160 __u32 MCHK_Frame_Rev;
181 #ifndef __EXTERN_INLINE
182 #define __EXTERN_INLINE extern inline
183 #define __IO_EXTERN_INLINE
189 * IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and
190 * K7 can only use linear accesses to get at PCI memory and I/O spaces.
193 #define vucp volatile unsigned char *
194 #define vusp volatile unsigned short *
195 #define vuip volatile unsigned int *
196 #define vulp volatile unsigned long *
198 __EXTERN_INLINE u8 irongate_inb(unsigned long addr)
200 return __kernel_ldbu(*(vucp)(addr + IRONGATE_IO));
203 __EXTERN_INLINE void irongate_outb(u8 b, unsigned long addr)
205 __kernel_stb(b, *(vucp)(addr + IRONGATE_IO));
209 __EXTERN_INLINE u16 irongate_inw(unsigned long addr)
211 return __kernel_ldwu(*(vusp)(addr + IRONGATE_IO));
214 __EXTERN_INLINE void irongate_outw(u16 b, unsigned long addr)
216 __kernel_stw(b, *(vusp)(addr + IRONGATE_IO));
220 __EXTERN_INLINE u32 irongate_inl(unsigned long addr)
222 return *(vuip)(addr + IRONGATE_IO);
225 __EXTERN_INLINE void irongate_outl(u32 b, unsigned long addr)
227 *(vuip)(addr + IRONGATE_IO) = b;
232 * Memory functions. All accesses are done through linear space.
235 __EXTERN_INLINE u8 irongate_readb(unsigned long addr)
237 return __kernel_ldbu(*(vucp)addr);
240 __EXTERN_INLINE u16 irongate_readw(unsigned long addr)
242 return __kernel_ldwu(*(vusp)addr);
245 __EXTERN_INLINE u32 irongate_readl(unsigned long addr)
247 return (*(vuip)addr) & 0xffffffff;
250 __EXTERN_INLINE u64 irongate_readq(unsigned long addr)
255 __EXTERN_INLINE void irongate_writeb(u8 b, unsigned long addr)
257 __kernel_stb(b, *(vucp)addr);
260 __EXTERN_INLINE void irongate_writew(u16 b, unsigned long addr)
262 __kernel_stw(b, *(vusp)addr);
265 __EXTERN_INLINE void irongate_writel(u32 b, unsigned long addr)
270 __EXTERN_INLINE void irongate_writeq(u64 b, unsigned long addr)
275 extern unsigned long irongate_ioremap(unsigned long addr, unsigned long size);
276 extern void irongate_iounmap(unsigned long addr);
278 __EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr)
280 return addr >= IRONGATE_MEM;
290 #define __inb(p) irongate_inb((unsigned long)(p))
291 #define __inw(p) irongate_inw((unsigned long)(p))
292 #define __inl(p) irongate_inl((unsigned long)(p))
293 #define __outb(x,p) irongate_outb((x),(unsigned long)(p))
294 #define __outw(x,p) irongate_outw((x),(unsigned long)(p))
295 #define __outl(x,p) irongate_outl((x),(unsigned long)(p))
296 #define __readb(a) irongate_readb((unsigned long)(a))
297 #define __readw(a) irongate_readw((unsigned long)(a))
298 #define __readl(a) irongate_readl((unsigned long)(a))
299 #define __readq(a) irongate_readq((unsigned long)(a))
300 #define __writeb(x,a) irongate_writeb((x),(unsigned long)(a))
301 #define __writew(x,a) irongate_writew((x),(unsigned long)(a))
302 #define __writel(x,a) irongate_writel((x),(unsigned long)(a))
303 #define __writeq(x,a) irongate_writeq((x),(unsigned long)(a))
304 #define __ioremap(a,s) irongate_ioremap((unsigned long)(a),(s))
305 #define __iounmap(a) irongate_iounmap((unsigned long)(a))
306 #define __is_ioaddr(a) irongate_is_ioaddr((unsigned long)(a))
308 #define inb(p) __inb(p)
309 #define inw(p) __inw(p)
310 #define inl(p) __inl(p)
311 #define outb(x,p) __outb((x),(p))
312 #define outw(x,p) __outw((x),(p))
313 #define outl(x,p) __outl((x),(p))
314 #define __raw_readb(a) __readb(a)
315 #define __raw_readw(a) __readw(a)
316 #define __raw_readl(a) __readl(a)
317 #define __raw_readq(a) __readq(a)
318 #define __raw_writeb(v,a) __writeb((v),(a))
319 #define __raw_writew(v,a) __writew((v),(a))
320 #define __raw_writel(v,a) __writel((v),(a))
321 #define __raw_writeq(v,a) __writeq((v),(a))
323 #endif /* __WANT_IO_DEF */
325 #ifdef __IO_EXTERN_INLINE
326 #undef __EXTERN_INLINE
327 #undef __IO_EXTERN_INLINE
330 #endif /* __KERNEL__ */
332 #endif /* __ALPHA_IRONGATE__H__ */