2 * Marvel systems use the IO7 I/O chip provides PCI/PCIX/AGP access
4 * This file is based on:
6 * Marvel / EV7 System Programmer's Manual
11 #ifndef __ALPHA_MARVEL__H__
12 #define __ALPHA_MARVEL__H__
14 #include <linux/types.h>
15 #include <linux/pci.h>
16 #include <linux/spinlock.h>
18 #include <asm/compiler.h>
20 #define MARVEL_MAX_PIDS 32 /* as long as we rely on 43-bit superpage */
21 #define MARVEL_IRQ_VEC_PE_SHIFT (10)
22 #define MARVEL_IRQ_VEC_IRQ_MASK ((1 << MARVEL_IRQ_VEC_PE_SHIFT) - 1)
23 #define MARVEL_NR_IRQS \
24 (16 + (MARVEL_MAX_PIDS * (1 << MARVEL_IRQ_VEC_PE_SHIFT)))
30 volatile unsigned long csr __attribute__((aligned(16)));
34 ev7_csr RBOX_CFG; /* 0x0000 */
38 ev7_csr RBOX_TCTL; /* 0x0040 */
42 ev7_csr RBOX_INTQ; /* 0x0080 */
45 ev7_csr RBOX_SCRATCH1;
46 ev7_csr RBOX_SCRATCH2; /* 0x00c0 */
51 * EV7 CSR addressing macros
53 #define EV7_MASK40(addr) ((addr) & ((1UL << 41) - 1))
54 #define EV7_KERN_ADDR(addr) ((void *)(IDENT_ADDR | EV7_MASK40(addr)))
56 #define EV7_PE_MASK 0x1ffUL /* 9 bits ( 256 + mem/io ) */
57 #define EV7_IPE(pe) ((~((long)(pe)) & EV7_PE_MASK) << 35)
59 #define EV7_CSR_PHYS(pe, off) (EV7_IPE(pe) | (0x7FFCUL << 20) | (off))
60 #define EV7_CSRS_PHYS(pe) (EV7_CSR_PHYS(pe, 0UL))
62 #define EV7_CSR_KERN(pe, off) (EV7_KERN_ADDR(EV7_CSR_PHYS(pe, off)))
63 #define EV7_CSRS_KERN(pe) (EV7_KERN_ADDR(EV7_CSRS_PHYS(pe)))
65 #define EV7_CSR_OFFSET(name) ((unsigned long)&((ev7_csrs *)NULL)->name.csr)
71 volatile unsigned long csr __attribute__((aligned(64)));
75 /* I/O Port Control Registers */
76 io7_csr POx_CTRL; /* 0x0000 */
77 io7_csr POx_CACHE_CTL;
79 io7_csr POx_IO_ADR_EXT;
80 io7_csr POx_MEM_ADR_EXT; /* 0x0100 */
81 io7_csr POx_XCAL_CTRL;
82 io7_csr rsvd1[2]; /* ?? spec doesn't show 0x180 */
83 io7_csr POx_DM_SOURCE; /* 0x0200 */
87 io7_csr rsvd2[4]; /* 0x0300 */
89 /* AGP Control Registers -- port 3 only */
90 io7_csr AGP_CAP_ID; /* 0x0400 */
95 /* I/O Port Monitor Registers */
96 io7_csr POx_MONCTL; /* 0x0500 */
100 io7_csr POx_SCRATCH; /* 0x0600 */
104 io7_csr rsvd4; /* 0x0700 */
109 /* System Address Space Window Control Registers */
111 io7_csr POx_WBASE[4]; /* 0x1000 */
112 io7_csr POx_WMASK[4];
113 io7_csr POx_TBASE[4];
115 io7_csr POx_MSI_WBASE;
118 /* I/O Port Error Registers */
120 io7_csr POx_FIRST_ERR;
123 io7_csr POx_SPL_COMPLT;
124 io7_csr POx_TRANS_SUM;
125 io7_csr POx_FRC_PCI_ERR;
126 io7_csr POx_MULT_ERR;
129 /* I/O Port End of Interrupt Registers */
132 io7_csr POx_IACK_SPECIAL;
137 io7_csr IO_ASIC_REV; /* 0x30.0000 */
141 io7_csr PO7_RST2; /* 0x30.0100 */
146 io7_csr IO7_ACC_CLUMP; /* 0x30.0300 */
150 io7_csr IO7_UPH_TO; /* 0x30.0400 */
151 io7_csr RBX_IREQ_OFF;
152 io7_csr RBX_INTA_OFF;
154 io7_csr PO7_MONCTL; /* 0x30.0500 */
158 io7_csr PO7_SCRATCH; /* 0x30.0600 */
162 io7_csr PO7_PMASK; /* 0x30.0700 */
166 io7_csr PO7_ERROR_SUM; /* 0x30.2000 */
167 io7_csr PO7_BHOLE_MASK;
170 io7_csr PO7_UNCRR_SYM; /* 0x30.2100 */
171 io7_csr PO7_CRRCT_SYM;
172 io7_csr PO7_ERR_PKT[2];
173 io7_csr PO7_UGBGE_SYM; /* 0x30.2200 */
175 io7_csr PO7_LSI_CTL[128]; /* 0x31.0000 */
177 io7_csr HLT_CTL; /* 0x31.3ec0 */
178 io7_csr HPI_CTL; /* 0x31.3f00 */
182 io7_csr PO7_MSI_CTL[16]; /* 0x31.4000 */
186 * Interrupt Diagnostic / Test
194 io7_csr rsvd5[125]; /* 0x31.a000 */
195 io7_csr MISC_PND; /* 0x31.b800 */
197 io7_csr MSI_PND[16]; /* 0x31.c000 */
199 io7_csr MSI_CLR[16]; /* 0x31.c800 */
203 * IO7 DMA Window Base register (POx_WBASEx)
205 #define wbase_m_ena 0x1
206 #define wbase_m_sg 0x2
207 #define wbase_m_dac 0x4
208 #define wbase_m_addr 0xFFF00000
209 union IO7_POx_WBASE {
211 unsigned ena : 1; /* <0> */
212 unsigned sg : 1; /* <1> */
213 unsigned dac : 1; /* <2> -- window 3 only */
215 unsigned addr : 12; /* <31:20> */
223 * IO7 IID (Interrupt IDentifier) format
225 * For level-sensative interrupts, int_num is encoded as:
227 * bus/port slot/device INTx
232 unsigned int_num : 9; /* <8:0> */
233 unsigned tpu_mask : 4; /* <12:9> rsvd */
234 unsigned msi : 1; /* 13 */
235 unsigned ipe : 10; /* <23:14> */
236 unsigned long rsvd : 40;
238 unsigned int as_long[2];
239 unsigned long as_quad;
243 * IO7 addressing macros
245 #define IO7_KERN_ADDR(addr) (EV7_KERN_ADDR(addr))
247 #define IO7_PORT_MASK 0x07UL /* 3 bits of port */
249 #define IO7_IPE(pe) (EV7_IPE(pe))
250 #define IO7_IPORT(port) ((~((long)(port)) & IO7_PORT_MASK) << 32)
252 #define IO7_HOSE(pe, port) (IO7_IPE(pe) | IO7_IPORT(port))
254 #define IO7_MEM_PHYS(pe, port) (IO7_HOSE(pe, port) | 0x00000000UL)
255 #define IO7_CONF_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFE000000UL)
256 #define IO7_IO_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFF000000UL)
257 #define IO7_CSR_PHYS(pe, port, off) \
258 (IO7_HOSE(pe, port) | 0xFF800000UL | (off))
259 #define IO7_CSRS_PHYS(pe, port) (IO7_CSR_PHYS(pe, port, 0UL))
260 #define IO7_PORT7_CSRS_PHYS(pe) (IO7_CSR_PHYS(pe, 7, 0x300000UL))
262 #define IO7_MEM_KERN(pe, port) (IO7_KERN_ADDR(IO7_MEM_PHYS(pe, port)))
263 #define IO7_CONF_KERN(pe, port) (IO7_KERN_ADDR(IO7_CONF_PHYS(pe, port)))
264 #define IO7_IO_KERN(pe, port) (IO7_KERN_ADDR(IO7_IO_PHYS(pe, port)))
265 #define IO7_CSR_KERN(pe, port, off) (IO7_KERN_ADDR(IO7_CSR_PHYS(pe,port,off)))
266 #define IO7_CSRS_KERN(pe, port) (IO7_KERN_ADDR(IO7_CSRS_PHYS(pe, port)))
267 #define IO7_PORT7_CSRS_KERN(pe) (IO7_KERN_ADDR(IO7_PORT7_CSRS_PHYS(pe)))
269 #define IO7_PLL_RNGA(pll) (((pll) >> 3) & 0x7)
270 #define IO7_PLL_RNGB(pll) (((pll) >> 6) & 0x7)
272 #define IO7_MEM_SPACE (2UL * 1024 * 1024 * 1024) /* 2GB MEM */
273 #define IO7_IO_SPACE (8UL * 1024 * 1024) /* 8MB I/O */
277 * Offset between ram physical addresses and pci64 DAC addresses
279 #define IO7_DAC_OFFSET (1UL << 49)
282 * This is needed to satisify the IO() macro used in initializing the machvec
284 #define MARVEL_IACK_SC \
286 (&(((io7_ioport_csrs *)IO7_CSRS_KERN(0, 0))->POx_IACK_SPECIAL)))
293 #define IO7_NUM_PORTS 4
294 #define IO7_AGP_PORT 3
298 struct pci_controller *hose;
302 io7_ioport_csrs *csrs;
304 unsigned long saved_wbase[4];
305 unsigned long saved_wmask[4];
306 unsigned long saved_tbase[4];
313 io7_port7_csrs *csrs;
314 struct io7_port ports[IO7_NUM_PORTS];
319 #ifndef __EXTERN_INLINE
320 # define __EXTERN_INLINE extern inline
321 # define __IO_EXTERN_INLINE
325 * I/O functions. All access through linear space.
328 #define vucp volatile unsigned char *
329 #define vusp volatile unsigned short *
330 #define vuip volatile unsigned int *
331 #define vulp volatile unsigned long *
333 #ifdef CONFIG_VGA_HOSE
334 extern struct pci_controller *pci_vga_hose;
336 # define __marvel_is_port_vga(a) \
337 (((a) >= 0x3b0) && ((a) < 0x3e0) && ((a) != 0x3b3) && ((a) != 0x3d3))
338 # define __marvel_is_mem_vga(a) (((a) >= 0xa0000) && ((a) <= 0xc0000))
339 # define FIXUP_IOADDR_VGA(a) do { \
340 if (pci_vga_hose && __marvel_is_port_vga(a)) \
341 a += pci_vga_hose->io_space->start; \
344 # define FIXUP_IOADDR_VGA(a)
347 #define __marvel_is_port_kbd(a) (((a) == 0x60) || ((a) == 0x64))
348 #define __marvel_is_port_rtc(a) (((a) == 0x70) || ((a) == 0x71))
350 #define FIXUP_IOADDR_LEGACY(a)
352 #define FIXUP_IOADDR(a) do { \
353 FIXUP_IOADDR_VGA(a); \
354 FIXUP_IOADDR_LEGACY(a); \
358 # define IOBUG(x) printk x
359 # define IOBUG_FILTER_IOADDR(a, x) \
360 if (!__marvel_is_port_kbd(a) && !__marvel_is_port_rtc(a)) IOBUG(x)
363 # define IOBUG_FILTER_IOADDR(a, x)
366 extern u8 __marvel_rtc_io(int write, u8 b, unsigned long addr);
367 #define __marvel_rtc_inb(a) __marvel_rtc_io(0, 0, (a))
368 #define __marvel_rtc_outb(b, a) __marvel_rtc_io(1, (b), (a))
370 __EXTERN_INLINE int marvel_is_ioaddr(unsigned long addr)
372 return (addr & (1UL << 40)) != 0; /*FIXME - hardwire*/
375 __EXTERN_INLINE u8 marvel_inb(unsigned long addr)
378 if (!marvel_is_ioaddr(addr)) {
379 if (__marvel_is_port_kbd(addr))
381 if (__marvel_is_port_rtc(addr))
382 return __marvel_rtc_inb(addr);
383 IOBUG_FILTER_IOADDR(addr,
384 ("Bad IO addr %lx - reading -1\n", addr));
387 return __kernel_ldbu(*(vucp)addr);
390 __EXTERN_INLINE void marvel_outb(u8 b, unsigned long addr)
393 if (!marvel_is_ioaddr(addr)) {
394 if (__marvel_is_port_rtc(addr))
395 return (void)__marvel_rtc_outb(b, addr);
396 IOBUG_FILTER_IOADDR(addr,
397 ("Bad IO addr %lx - reading -1\n", addr));
400 __kernel_stb(b, *(vucp)addr);
404 __EXTERN_INLINE u16 marvel_inw(unsigned long addr)
407 if (!marvel_is_ioaddr(addr)) {
408 IOBUG_FILTER_IOADDR(addr,
409 ("Bad IO addr %lx - reading -1\n", addr));
412 return __kernel_ldwu(*(vusp)addr);
415 __EXTERN_INLINE void marvel_outw(u16 w, unsigned long addr)
418 if (!marvel_is_ioaddr(addr)) {
419 IOBUG_FILTER_IOADDR(addr,
420 ("Bad IO addr %lx - reading -1\n", addr));
423 __kernel_stw(w, *(vusp)addr);
427 __EXTERN_INLINE u32 marvel_inl(unsigned long addr)
430 if (!marvel_is_ioaddr(addr)) {
431 IOBUG_FILTER_IOADDR(addr,
432 ("Bad IO addr %lx - reading -1\n", addr));
438 __EXTERN_INLINE void marvel_outl(u32 l, unsigned long addr)
441 if (!marvel_is_ioaddr(addr)) {
442 IOBUG_FILTER_IOADDR(addr,
443 ("Bad IO addr %lx - reading -1\n", addr));
451 * Memory functions. All accesses through linear space.
454 extern unsigned long marvel_ioremap(unsigned long addr, unsigned long size);
455 extern void marvel_iounmap(unsigned long addr);
457 __EXTERN_INLINE u8 marvel_readb(unsigned long addr)
459 if (!marvel_is_ioaddr(addr)) {
460 IOBUG(("Bad MEM addr %lx - reading -1\n", addr));
463 return __kernel_ldbu(*(vucp)addr);
466 __EXTERN_INLINE u16 marvel_readw(unsigned long addr)
468 if (!marvel_is_ioaddr(addr)) {
469 IOBUG(("Bad MEM addr %lx - reading -1\n", addr));
472 return __kernel_ldwu(*(vusp)addr);
475 __EXTERN_INLINE u32 marvel_readl(unsigned long addr)
477 if (!marvel_is_ioaddr(addr)) {
478 IOBUG(("Bad MEM addr %lx - reading -1\n", addr));
484 __EXTERN_INLINE u64 marvel_readq(unsigned long addr)
486 if (!marvel_is_ioaddr(addr)) {
487 IOBUG(("Bad MEM addr %lx - reading -1\n", addr));
493 __EXTERN_INLINE void marvel_writeb(u8 b, unsigned long addr)
495 if (!marvel_is_ioaddr(addr)) {
496 IOBUG(("Bad MEM addr %lx - dropping store\n", addr));
499 __kernel_stb(b, *(vucp)addr);
502 __EXTERN_INLINE void marvel_writew(u16 w, unsigned long addr)
504 if (!marvel_is_ioaddr(addr)) {
505 IOBUG(("Bad MEM addr %lx - dropping store\n", addr));
508 __kernel_stw(w, *(vusp)addr);
511 __EXTERN_INLINE void marvel_writel(u32 l, unsigned long addr)
513 if (!marvel_is_ioaddr(addr)) {
514 IOBUG(("Bad MEM addr %lx - dropping store\n", addr));
520 __EXTERN_INLINE void marvel_writeq(u64 q, unsigned long addr)
522 if (!marvel_is_ioaddr(addr)) {
523 IOBUG(("Bad MEM addr %lx - dropping store\n", addr));
530 #undef FIXUP_IOADDR_LEGACY
531 #undef FIXUP_IOADDR_VGA
540 #define __inb(p) marvel_inb((unsigned long)(p))
541 #define __inw(p) marvel_inw((unsigned long)(p))
542 #define __inl(p) marvel_inl((unsigned long)(p))
543 #define __outb(x,p) marvel_outb((x),(unsigned long)(p))
544 #define __outw(x,p) marvel_outw((x),(unsigned long)(p))
545 #define __outl(x,p) marvel_outl((x),(unsigned long)(p))
546 #define __readb(a) marvel_readb((unsigned long)(a))
547 #define __readw(a) marvel_readw((unsigned long)(a))
548 #define __readl(a) marvel_readl((unsigned long)(a))
549 #define __readq(a) marvel_readq((unsigned long)(a))
550 #define __writeb(x,a) marvel_writeb((x),(unsigned long)(a))
551 #define __writew(x,a) marvel_writew((x),(unsigned long)(a))
552 #define __writel(x,a) marvel_writel((x),(unsigned long)(a))
553 #define __writeq(x,a) marvel_writeq((x),(unsigned long)(a))
554 #define __ioremap(a,s) marvel_ioremap((unsigned long)(a),(s))
555 #define __iounmap(a) marvel_iounmap((unsigned long)(a))
556 #define __is_ioaddr(a) marvel_is_ioaddr((unsigned long)(a))
558 /* Disable direct inlining of these calls with the debug checks present. */
560 #define __raw_readb(a) __readb(a)
561 #define __raw_readw(a) __readw(a)
562 #define __raw_readl(a) __readl(a)
563 #define __raw_readq(a) __readq(a)
564 #define __raw_writeb(v,a) __writeb(v,a)
565 #define __raw_writew(v,a) __writew(v,a)
566 #define __raw_writel(v,a) __writel(v,a)
567 #define __raw_writeq(v,a) __writeq(v,a)
570 #endif /* __WANT_IO_DEF */
572 #ifdef __IO_EXTERN_INLINE
573 # undef __EXTERN_INLINE
574 # undef __IO_EXTERN_INLINE
577 #endif /* __KERNEL__ */
579 #endif /* __ALPHA_MARVEL__H__ */