2 * include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
4 * Register definitions for IXP4xx chipset. This file contains
5 * register location and bit definitions only. Platform specific
6 * definitions and helper function declarations are in platform.h
9 * Copyright (C) 2002 Intel Corporation.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #ifndef __ASM_ARCH_HARDWARE_H__
19 #error "Do not include this directly, instead #include <asm/hardware.h>"
22 #ifndef _ASM_ARM_IXP4XX_H_
23 #define _ASM_ARM_IXP4XX_H_
26 * IXP4xx Linux Memory Map:
28 * Phy Size Virt Description
29 * =========================================================================
31 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
33 * 0x48000000 0x04000000 ioremap'd PCI Memory Space
35 * 0x50000000 0x10000000 ioremap'd EXP BUS
37 * 0x6000000 0x00004000 ioremap'd QMgr
39 * 0xC0000000 0x00001000 0xffbfe000 PCI CFG
41 * 0xC4000000 0x00001000 0xffbfd000 EXP CFG
43 * 0xC8000000 0x0000C000 0xffbf2000 On-Chip Peripherals
48 * Expansion BUS Configuration registers
50 #define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
51 #define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFD000)
52 #define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
55 * PCI Config registers
57 #define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
58 #define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFD000)
59 #define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
64 #define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
65 #define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBF2000)
66 #define IXP4XX_PERIPHERAL_REGION_SIZE (0x0000C000)
68 #define IXP4XX_EXP_CS0_OFFSET 0x00
69 #define IXP4XX_EXP_CS1_OFFSET 0x04
70 #define IXP4XX_EXP_CS2_OFFSET 0x08
71 #define IXP4XX_EXP_CS3_OFFSET 0x0C
72 #define IXP4XX_EXP_CS4_OFFSET 0x10
73 #define IXP4XX_EXP_CS5_OFFSET 0x14
74 #define IXP4XX_EXP_CS6_OFFSET 0x18
75 #define IXP4XX_EXP_CS7_OFFSET 0x1C
76 #define IXP4XX_EXP_CFG0_OFFSET 0x20
77 #define IXP4XX_EXP_CFG1_OFFSET 0x24
78 #define IXP4XX_EXP_CFG2_OFFSET 0x28
79 #define IXP4XX_EXP_CFG3_OFFSET 0x2C
82 * Expansion Bus Controller registers.
84 #define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
86 #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
87 #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
88 #define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
89 #define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
90 #define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
91 #define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
92 #define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
93 #define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
95 #define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
96 #define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
97 #define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
98 #define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
102 * Peripheral Space Register Region Base Addresses
104 #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
105 #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
106 #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
107 #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
108 #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
109 #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
110 #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
112 #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
113 #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
114 #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
115 #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
116 #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
117 #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
118 #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
121 * Constants to make it easy to access Interrupt Controller registers
123 #define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */
124 #define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */
125 #define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
126 #define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */
127 #define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */
128 #define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */
129 #define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
130 #define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
133 * Interrupt Controller Register Definitions.
136 #define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
138 #define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
139 #define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
140 #define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
141 #define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
142 #define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
143 #define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
144 #define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)
145 #define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
148 * Constants to make it easy to access GPIO registers
150 #define IXP4XX_GPIO_GPOUTR_OFFSET 0x00
151 #define IXP4XX_GPIO_GPOER_OFFSET 0x04
152 #define IXP4XX_GPIO_GPINR_OFFSET 0x08
153 #define IXP4XX_GPIO_GPISR_OFFSET 0x0C
154 #define IXP4XX_GPIO_GPIT1R_OFFSET 0x10
155 #define IXP4XX_GPIO_GPIT2R_OFFSET 0x14
156 #define IXP4XX_GPIO_GPCLKR_OFFSET 0x18
157 #define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C
160 * GPIO Register Definitions.
161 * [Only perform 32bit reads/writes]
163 #define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
165 #define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
166 #define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
167 #define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
168 #define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
169 #define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
170 #define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
171 #define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
172 #define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
175 * GPIO register bit definitions
180 #define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
181 #define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
182 #define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
183 #define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
184 #define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
187 * Mask used to clear interrupt styles
189 #define IXP4XX_GPIO_STYLE_CLEAR 0x7
190 #define IXP4XX_GPIO_STYLE_SIZE 3
193 * Constants to make it easy to access Timer Control/Status registers
195 #define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
196 #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
197 #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
198 #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
199 #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
200 #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
201 #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
202 #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
203 #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
206 * Operating System Timer Register Definitions.
209 #define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
211 #define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
212 #define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
213 #define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
214 #define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
215 #define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
216 #define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
217 #define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
218 #define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
219 #define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
222 * Timer register values and bit definitions
224 #define IXP4XX_OST_ENABLE 0x00000001
225 #define IXP4XX_OST_ONE_SHOT 0x00000002
226 /* Low order bits of reload value ignored */
227 #define IXP4XX_OST_RELOAD_MASK 0x00000003
228 #define IXP4XX_OST_DISABLED 0x00000000
229 #define IXP4XX_OSST_TIMER_1_PEND 0x00000001
230 #define IXP4XX_OSST_TIMER_2_PEND 0x00000002
231 #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
232 #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
233 #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
235 #define IXP4XX_WDT_KEY 0x0000482E
237 #define IXP4XX_WDT_RESET_ENABLE 0x00000001
238 #define IXP4XX_WDT_IRQ_ENABLE 0x00000002
239 #define IXP4XX_WDT_COUNT_ENABLE 0x00000004
243 * Constants to make it easy to access PCI Control/Status registers
245 #define PCI_NP_AD_OFFSET 0x00
246 #define PCI_NP_CBE_OFFSET 0x04
247 #define PCI_NP_WDATA_OFFSET 0x08
248 #define PCI_NP_RDATA_OFFSET 0x0c
249 #define PCI_CRP_AD_CBE_OFFSET 0x10
250 #define PCI_CRP_WDATA_OFFSET 0x14
251 #define PCI_CRP_RDATA_OFFSET 0x18
252 #define PCI_CSR_OFFSET 0x1c
253 #define PCI_ISR_OFFSET 0x20
254 #define PCI_INTEN_OFFSET 0x24
255 #define PCI_DMACTRL_OFFSET 0x28
256 #define PCI_AHBMEMBASE_OFFSET 0x2c
257 #define PCI_AHBIOBASE_OFFSET 0x30
258 #define PCI_PCIMEMBASE_OFFSET 0x34
259 #define PCI_AHBDOORBELL_OFFSET 0x38
260 #define PCI_PCIDOORBELL_OFFSET 0x3C
261 #define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
262 #define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
263 #define PCI_ATPDMA0_LENADDR_OFFSET 0x48
264 #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
265 #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
266 #define PCI_ATPDMA1_LENADDR_OFFSET 0x54
269 * PCI Control/Status Registers
271 #define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
273 #define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
274 #define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
275 #define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
276 #define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
277 #define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
278 #define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
279 #define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
280 #define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
281 #define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
282 #define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
283 #define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
284 #define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
285 #define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
286 #define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
287 #define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
288 #define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
289 #define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
290 #define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
291 #define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
292 #define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
293 #define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
294 #define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
297 * PCI register values and bit definitions
300 /* CSR bit definitions */
301 #define PCI_CSR_HOST 0x00000001
302 #define PCI_CSR_ARBEN 0x00000002
303 #define PCI_CSR_ADS 0x00000004
304 #define PCI_CSR_PDS 0x00000008
305 #define PCI_CSR_ABE 0x00000010
306 #define PCI_CSR_DBT 0x00000020
307 #define PCI_CSR_ASE 0x00000100
308 #define PCI_CSR_IC 0x00008000
310 /* ISR (Interrupt status) Register bit definitions */
311 #define PCI_ISR_PSE 0x00000001
312 #define PCI_ISR_PFE 0x00000002
313 #define PCI_ISR_PPE 0x00000004
314 #define PCI_ISR_AHBE 0x00000008
315 #define PCI_ISR_APDC 0x00000010
316 #define PCI_ISR_PADC 0x00000020
317 #define PCI_ISR_ADB 0x00000040
318 #define PCI_ISR_PDB 0x00000080
320 /* INTEN (Interrupt Enable) Register bit definitions */
321 #define PCI_INTEN_PSE 0x00000001
322 #define PCI_INTEN_PFE 0x00000002
323 #define PCI_INTEN_PPE 0x00000004
324 #define PCI_INTEN_AHBE 0x00000008
325 #define PCI_INTEN_APDC 0x00000010
326 #define PCI_INTEN_PADC 0x00000020
327 #define PCI_INTEN_ADB 0x00000040
328 #define PCI_INTEN_PDB 0x00000080
331 * Shift value for byte enable on NP cmd/byte enable register
333 #define IXP4XX_PCI_NP_CBE_BESL 4
336 * PCI commands supported by NP access unit
338 #define NP_CMD_IOREAD 0x2
339 #define NP_CMD_IOWRITE 0x3
340 #define NP_CMD_CONFIGREAD 0xa
341 #define NP_CMD_CONFIGWRITE 0xb
342 #define NP_CMD_MEMREAD 0x6
343 #define NP_CMD_MEMWRITE 0x7
346 * Constants for CRP access into local config space
348 #define CRP_AD_CBE_BESL 20
349 #define CRP_AD_CBE_WRITE 0x00010000
353 * USB Device Controller
355 * These are used by the USB gadget driver, so they don't follow the
356 * IXP4XX_ naming convetions.
359 # define IXP4XX_USB_REG(x) (*((volatile u32 *)(x)))
361 /* UDC Undocumented - Reserved1 */
362 #define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)
363 /* UDC Undocumented - Reserved2 */
364 #define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)
365 /* UDC Undocumented - Reserved3 */
366 #define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)
367 /* UDC Control Register */
368 #define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
369 /* UDC Endpoint 0 Control/Status Register */
370 #define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)
371 /* UDC Endpoint 1 (IN) Control/Status Register */
372 #define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)
373 /* UDC Endpoint 2 (OUT) Control/Status Register */
374 #define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)
375 /* UDC Endpoint 3 (IN) Control/Status Register */
376 #define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)
377 /* UDC Endpoint 4 (OUT) Control/Status Register */
378 #define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)
379 /* UDC Endpoint 5 (Interrupt) Control/Status Register */
380 #define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)
381 /* UDC Endpoint 6 (IN) Control/Status Register */
382 #define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)
383 /* UDC Endpoint 7 (OUT) Control/Status Register */
384 #define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)
385 /* UDC Endpoint 8 (IN) Control/Status Register */
386 #define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)
387 /* UDC Endpoint 9 (OUT) Control/Status Register */
388 #define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)
389 /* UDC Endpoint 10 (Interrupt) Control/Status Register */
390 #define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)
391 /* UDC Endpoint 11 (IN) Control/Status Register */
392 #define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)
393 /* UDC Endpoint 12 (OUT) Control/Status Register */
394 #define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)
395 /* UDC Endpoint 13 (IN) Control/Status Register */
396 #define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)
397 /* UDC Endpoint 14 (OUT) Control/Status Register */
398 #define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)
399 /* UDC Endpoint 15 (Interrupt) Control/Status Register */
400 #define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)
401 /* UDC Frame Number Register High */
402 #define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)
403 /* UDC Frame Number Register Low */
404 #define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)
405 /* UDC Byte Count Reg 2 */
406 #define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)
407 /* UDC Byte Count Reg 4 */
408 #define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)
409 /* UDC Byte Count Reg 7 */
410 #define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)
411 /* UDC Byte Count Reg 9 */
412 #define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)
413 /* UDC Byte Count Reg 12 */
414 #define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)
415 /* UDC Byte Count Reg 14 */
416 #define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)
417 /* UDC Endpoint 0 Data Register */
418 #define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)
419 /* UDC Endpoint 1 Data Register */
420 #define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)
421 /* UDC Endpoint 2 Data Register */
422 #define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)
423 /* UDC Endpoint 3 Data Register */
424 #define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)
425 /* UDC Endpoint 4 Data Register */
426 #define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)
427 /* UDC Endpoint 5 Data Register */
428 #define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)
429 /* UDC Endpoint 6 Data Register */
430 #define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)
431 /* UDC Endpoint 7 Data Register */
432 #define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)
433 /* UDC Endpoint 8 Data Register */
434 #define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)
435 /* UDC Endpoint 9 Data Register */
436 #define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)
437 /* UDC Endpoint 10 Data Register */
438 #define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)
439 /* UDC Endpoint 11 Data Register */
440 #define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)
441 /* UDC Endpoint 12 Data Register */
442 #define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)
443 /* UDC Endpoint 13 Data Register */
444 #define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)
445 /* UDC Endpoint 14 Data Register */
446 #define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)
447 /* UDC Endpoint 15 Data Register */
448 #define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)
449 /* UDC Interrupt Control Register 0 */
450 #define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)
451 /* UDC Interrupt Control Register 1 */
452 #define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)
453 /* UDC Status Interrupt Register 0 */
454 #define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)
455 /* UDC Status Interrupt Register 1 */
456 #define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)
458 #define UDCCR_UDE (1 << 0) /* UDC enable */
459 #define UDCCR_UDA (1 << 1) /* UDC active */
460 #define UDCCR_RSM (1 << 2) /* Device resume */
461 #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
462 #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
463 #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
464 #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
465 #define UDCCR_REM (1 << 7) /* Reset interrupt mask */
467 #define UDCCS0_OPR (1 << 0) /* OUT packet ready */
468 #define UDCCS0_IPR (1 << 1) /* IN packet ready */
469 #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
470 #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
471 #define UDCCS0_SST (1 << 4) /* Sent stall */
472 #define UDCCS0_FST (1 << 5) /* Force stall */
473 #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
474 #define UDCCS0_SA (1 << 7) /* Setup active */
476 #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
477 #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
478 #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
479 #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
480 #define UDCCS_BI_SST (1 << 4) /* Sent stall */
481 #define UDCCS_BI_FST (1 << 5) /* Force stall */
482 #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
484 #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
485 #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
486 #define UDCCS_BO_DME (1 << 3) /* DMA enable */
487 #define UDCCS_BO_SST (1 << 4) /* Sent stall */
488 #define UDCCS_BO_FST (1 << 5) /* Force stall */
489 #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
490 #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
492 #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
493 #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
494 #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
495 #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
496 #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
498 #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
499 #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
500 #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
501 #define UDCCS_IO_DME (1 << 3) /* DMA enable */
502 #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
503 #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
505 #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
506 #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
507 #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
508 #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
509 #define UDCCS_INT_SST (1 << 4) /* Sent stall */
510 #define UDCCS_INT_FST (1 << 5) /* Force stall */
511 #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
513 #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
514 #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
515 #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
516 #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
517 #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
518 #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
519 #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
520 #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
522 #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
523 #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
524 #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
525 #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
526 #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
527 #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
528 #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
529 #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
531 #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
532 #define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
533 #define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
534 #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
535 #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
536 #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
537 #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
538 #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
540 #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
541 #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
542 #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
543 #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
544 #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
545 #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
546 #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
547 #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
549 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */