2 * linux/include/asm-arm/arch-omap/hardware.h
4 * Hardware definitions for TI OMAP processors and boards
6 * NOTE: Please put device driver specific defines into a separate header
7 * file for each driver.
9 * Copyright (C) 2001 RidgeRun, Inc.
10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
13 * and Dirk Behme <dirk.behme@de.bosch.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 #ifndef __ASM_ARCH_OMAP_HARDWARE_H
37 #define __ASM_ARCH_OMAP_HARDWARE_H
39 #include <asm/sizes.h>
40 #include <linux/config.h>
42 #include <asm/types.h>
43 #include <asm/arch/cpu.h>
45 #include <asm/arch/io.h>
48 * ---------------------------------------------------------------------------
49 * Common definitions for all OMAP processors
50 * NOTE: Put all processor or board specific parts to the special header
52 * ---------------------------------------------------------------------------
56 * ----------------------------------------------------------------------------
58 * ----------------------------------------------------------------------------
60 #define CLKGEN_REG_BASE (0xfffece00)
61 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
62 #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
63 #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
64 #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
65 #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
66 #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
67 #define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
68 #define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
74 #define SETARM_IDLE_SHIFT
76 /* DPLL control registers */
77 #define DPLL_CTL (0xfffecf00)
79 /* DSP clock control */
80 #define DSP_CONFIG_REG_BASE (0xe1008000)
81 #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
82 #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
85 * ---------------------------------------------------------------------------
87 * ---------------------------------------------------------------------------
89 #define ULPD_REG_BASE (0xfffe0800)
90 #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
91 #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
92 #define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
93 #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
94 #define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
95 #define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
96 #define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
97 #define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
100 * ---------------------------------------------------------------------------
102 * ---------------------------------------------------------------------------
104 #define OMAP_32kHz_TIMER_BASE 0xfffb9000
106 /* 32k Timer Registers */
107 #define TIMER32k_CR 0x08
108 #define TIMER32k_TVR 0x00
109 #define TIMER32k_TCR 0x04
111 /* 32k Timer Control Register definition */
112 #define TIMER32k_TSS (1<<0)
113 #define TIMER32k_TRB (1<<1)
114 #define TIMER32k_INT (1<<2)
115 #define TIMER32k_ARL (1<<3)
117 /* MPU Timer base addresses */
118 #define OMAP_TIMER1_BASE (0xfffec500)
119 #define OMAP_TIMER2_BASE (0xfffec600)
120 #define OMAP_TIMER3_BASE (0xfffec700)
121 #define OMAP_MPUTIMER_BASE OMAP_TIMER1_BASE
122 #define OMAP_MPUTIMER_OFFSET 0x100
124 /* MPU Timer Registers */
125 #define OMAP_TIMER1_CNTL (OMAP_TIMER_BASE1 + 0x0)
126 #define OMAP_TIMER1_LOAD_TIM (OMAP_TIMER_BASE1 + 0x4)
127 #define OMAP_TIMER1_READ_TIM (OMAP_TIMER_BASE1 + 0x8)
129 #define OMAP_TIMER2_CNTL (OMAP_TIMER_BASE2 + 0x0)
130 #define OMAP_TIMER2_LOAD_TIM (OMAP_TIMER_BASE2 + 0x4)
131 #define OMAP_TIMER2_READ_TIM (OMAP_TIMER_BASE2 + 0x8)
133 #define OMAP_TIMER3_CNTL (OMAP_TIMER_BASE3 + 0x0)
134 #define OMAP_TIMER3_LOAD_TIM (OMAP_TIMER_BASE3 + 0x4)
135 #define OMAP_TIMER3_READ_TIM (OMAP_TIMER_BASE3 + 0x8)
137 /* CNTL_TIMER register bits */
138 #define MPUTIM_FREE (1<<6)
139 #define MPUTIM_CLOCK_ENABLE (1<<5)
140 #define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT)
141 #define MPUTIM_PTV_BIT 2
142 #define MPUTIM_AR (1<<1)
143 #define MPUTIM_ST (1<<0)
145 /* Watchdog timer within the OMAP3.2 gigacell */
146 #define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
147 #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
148 #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
149 #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
150 #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
153 * ---------------------------------------------------------------------------
155 * ---------------------------------------------------------------------------
157 #define OMAP_IH1_BASE 0xfffecb00
158 #define OMAP_IH2_BASE 0xfffe0000
160 #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
161 #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
162 #define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
163 #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
164 #define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
165 #define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
166 #define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
168 #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
169 #define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
170 #define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
171 #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
172 #define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
173 #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
174 #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
176 #define IRQ_ITR_REG_OFFSET 0x00
177 #define IRQ_MIR_REG_OFFSET 0x04
178 #define IRQ_SIR_IRQ_REG_OFFSET 0x10
179 #define IRQ_SIR_FIQ_REG_OFFSET 0x14
180 #define IRQ_CONTROL_REG_OFFSET 0x18
181 #define IRQ_ISR_REG_OFFSET 0x9c
182 #define IRQ_ILR0_REG_OFFSET 0x1c
183 #define IRQ_GMR_REG_OFFSET 0xa0
186 * ---------------------------------------------------------------------------
187 * Traffic controller memory interface
188 * ---------------------------------------------------------------------------
190 #define TCMIF_BASE 0xfffecc00
191 #define IMIF_PRIO (TCMIF_BASE + 0x00)
192 #define EMIFS_PRIO (TCMIF_BASE + 0x04)
193 #define EMIFF_PRIO (TCMIF_BASE + 0x08)
194 #define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
195 #define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
196 #define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
197 #define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
198 #define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
199 #define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
200 #define EMIFF_MRS (TCMIF_BASE + 0x24)
201 #define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
202 #define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
203 #define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
204 #define TC_ENDIANISM (TCMIF_BASE + 0x34)
205 #define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
206 #define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
209 * ----------------------------------------------------------------------------
210 * System control registers
211 * ----------------------------------------------------------------------------
213 #define MOD_CONF_CTRL_0 0xfffe1080
214 #define MOD_CONF_CTRL_1 0xfffe1110
217 * ----------------------------------------------------------------------------
218 * Pin multiplexing registers
219 * ----------------------------------------------------------------------------
221 #define FUNC_MUX_CTRL_0 0xfffe1000
222 #define FUNC_MUX_CTRL_1 0xfffe1004
223 #define FUNC_MUX_CTRL_2 0xfffe1008
224 #define COMP_MODE_CTRL_0 0xfffe100c
225 #define FUNC_MUX_CTRL_3 0xfffe1010
226 #define FUNC_MUX_CTRL_4 0xfffe1014
227 #define FUNC_MUX_CTRL_5 0xfffe1018
228 #define FUNC_MUX_CTRL_6 0xfffe101C
229 #define FUNC_MUX_CTRL_7 0xfffe1020
230 #define FUNC_MUX_CTRL_8 0xfffe1024
231 #define FUNC_MUX_CTRL_9 0xfffe1028
232 #define FUNC_MUX_CTRL_A 0xfffe102C
233 #define FUNC_MUX_CTRL_B 0xfffe1030
234 #define FUNC_MUX_CTRL_C 0xfffe1034
235 #define FUNC_MUX_CTRL_D 0xfffe1038
236 #define PULL_DWN_CTRL_0 0xfffe1040
237 #define PULL_DWN_CTRL_1 0xfffe1044
238 #define PULL_DWN_CTRL_2 0xfffe1048
239 #define PULL_DWN_CTRL_3 0xfffe104c
240 #define PULL_DWN_CTRL_4 0xfffe10ac
242 /* OMAP-1610 specific multiplexing registers */
243 #define FUNC_MUX_CTRL_E 0xfffe1090
244 #define FUNC_MUX_CTRL_F 0xfffe1094
245 #define FUNC_MUX_CTRL_10 0xfffe1098
246 #define FUNC_MUX_CTRL_11 0xfffe109c
247 #define FUNC_MUX_CTRL_12 0xfffe10a0
248 #define PU_PD_SEL_0 0xfffe10b4
249 #define PU_PD_SEL_1 0xfffe10b8
250 #define PU_PD_SEL_2 0xfffe10bc
251 #define PU_PD_SEL_3 0xfffe10c0
252 #define PU_PD_SEL_4 0xfffe10c4
254 /* Timer32K for 1610 and 1710*/
255 #define OMAP_TIMER32K_BASE 0xFFFBC400
258 * ---------------------------------------------------------------------------
260 * ---------------------------------------------------------------------------
262 #define TIPB_PUBLIC_CNTL_BASE 0xfffed300
263 #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
264 #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
265 #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
268 * ----------------------------------------------------------------------------
270 * ----------------------------------------------------------------------------
272 #define MPUI_BASE (0xfffec900)
273 #define MPUI_CTRL (MPUI_BASE + 0x0)
274 #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
275 #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
276 #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
277 #define MPUI_STATUS_REG (MPUI_BASE + 0x10)
278 #define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
279 #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
280 #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
282 #ifndef __ASSEMBLER__
285 * ---------------------------------------------------------------------------
287 * ---------------------------------------------------------------------------
289 #define OMAP_UART1_BASE (unsigned char *)0xfffb0000
290 #define OMAP_UART2_BASE (unsigned char *)0xfffb0800
291 #define OMAP_UART3_BASE (unsigned char *)0xfffb9800
292 #define OMAP_MAX_NR_PORTS 3
293 #define OMAP1510_BASE_BAUD (12000000/16)
294 #define OMAP16XX_BASE_BAUD (48000000/16)
296 #define is_omap_port(p) ({int __ret = 0; \
297 if (p == (char*)IO_ADDRESS(OMAP_UART1_BASE) || \
298 p == (char*)IO_ADDRESS(OMAP_UART2_BASE) || \
299 p == (char*)IO_ADDRESS(OMAP_UART3_BASE)) \
305 * ---------------------------------------------------------------------------
306 * Processor specific defines
307 * ---------------------------------------------------------------------------
309 #ifdef CONFIG_ARCH_OMAP730
313 #ifdef CONFIG_ARCH_OMAP1510
314 #include "omap1510.h"
317 #ifdef CONFIG_ARCH_OMAP16XX
318 #include "omap16xx.h"
322 * ---------------------------------------------------------------------------
323 * Board specific defines
324 * ---------------------------------------------------------------------------
327 #ifdef CONFIG_MACH_OMAP_INNOVATOR
328 #include "board-innovator.h"
331 #ifdef CONFIG_MACH_OMAP_H2
332 #include "board-h2.h"
335 #ifdef CONFIG_MACH_OMAP_PERSEUS2
336 #include "board-perseus2.h"
339 #ifdef CONFIG_MACH_OMAP_H3
340 #include "board-h3.h"
343 #ifdef CONFIG_MACH_OMAP_H4
344 #include "board-h4.h"
345 #error "Support for H4 board not yet implemented."
348 #ifdef CONFIG_MACH_OMAP_OSK
349 #include "board-osk.h"
352 #endif /* !__ASSEMBLER__ */
354 #endif /* __ASM_ARCH_OMAP_HARDWARE_H */