2 * linux/include/asm-arm/arch-omap/time.h
4 * 32kHz timer definition
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 #if !defined(__ASM_ARCH_OMAP_TIME_H)
30 #define __ASM_ARCH_OMAP_TIME_H
32 #include <linux/config.h>
33 #include <linux/delay.h>
34 #include <asm/system.h>
35 #include <asm/hardware.h>
39 #include <asm/mach/irq.h>
40 #include <asm/arch/clocks.h>
44 #define __noinstrument __attribute__ ((no_instrument_function))
48 u32 cntl; /* CNTL_TIMER, R/W */
49 u32 load_tim; /* LOAD_TIM, W */
50 u32 read_tim; /* READ_TIM, R */
53 #define mputimer_base(n) \
54 ((volatile mputimer_regs_t*)IO_ADDRESS(OMAP_MPUTIMER_BASE + \
55 (n)*OMAP_MPUTIMER_OFFSET))
57 static inline unsigned long timer32k_read(int reg) {
59 val = omap_readw(reg + OMAP_32kHz_TIMER_BASE);
62 static inline void timer32k_write(int reg,int val) {
63 omap_writew(val, reg + OMAP_32kHz_TIMER_BASE);
67 * How long is the timer interval? 100 HZ, right...
68 * IRQ rate = (TVR + 1) / 32768 seconds
69 * TVR = 32768 * IRQ_RATE -1
73 #define TIMER32k_PERIOD 326
74 //#define TIMER32k_PERIOD 0x7ff
76 static inline void start_timer32k(void) {
77 timer32k_write(TIMER32k_CR,
78 TIMER32k_TSS | TIMER32k_TRB |
79 TIMER32k_INT | TIMER32k_ARL);
82 #ifdef CONFIG_MACH_OMAP_PERSEUS2
84 * After programming PTV with 0 and setting the MPUTIM_CLOCK_ENABLE
85 * (external clock enable) bit, the timer count rate is 6.5 MHz (13
86 * MHZ input/2). !! The divider by 2 is undocumented !!
88 #define MPUTICKS_PER_SEC (13000000/2)
91 * After programming PTV with 0, the timer count rate is 6 MHz.
92 * WARNING! this must be an even number, or machinecycles_to_usecs
95 #define MPUTICKS_PER_SEC (12000000/2)
98 static int mputimer_started[3] = {0,0,0};
100 static inline void __noinstrument start_mputimer(int n,
101 unsigned long load_val)
103 volatile mputimer_regs_t* timer = mputimer_base(n);
105 mputimer_started[n] = 0;
106 timer->cntl = MPUTIM_CLOCK_ENABLE;
109 timer->load_tim = load_val;
111 timer->cntl = (MPUTIM_CLOCK_ENABLE | MPUTIM_AR | MPUTIM_ST);
112 mputimer_started[n] = 1;
115 static inline unsigned long __noinstrument
118 volatile mputimer_regs_t* timer = mputimer_base(n);
119 return (mputimer_started[n] ? timer->read_tim : 0);
122 void __noinstrument start_mputimer1(unsigned long load_val)
124 start_mputimer(0, load_val);
126 void __noinstrument start_mputimer2(unsigned long load_val)
128 start_mputimer(1, load_val);
130 void __noinstrument start_mputimer3(unsigned long load_val)
132 start_mputimer(2, load_val);
135 unsigned long __noinstrument read_mputimer1(void)
137 return read_mputimer(0);
139 unsigned long __noinstrument read_mputimer2(void)
141 return read_mputimer(1);
143 unsigned long __noinstrument read_mputimer3(void)
145 return read_mputimer(2);
148 unsigned long __noinstrument do_getmachinecycles(void)
150 return 0 - read_mputimer(0);
153 unsigned long __noinstrument machinecycles_to_usecs(unsigned long mputicks)
155 /* Round up to nearest usec */
156 return ((mputicks * 1000) / (MPUTICKS_PER_SEC / 2 / 1000) + 1) >> 1;
160 * This marks the time of the last system timer interrupt
161 * that was *processed by the ISR* (timer 2).
163 static unsigned long systimer_mark;
165 static unsigned long omap1510_gettimeoffset(void)
167 /* Return elapsed usecs since last system timer ISR */
168 return machinecycles_to_usecs(do_getmachinecycles() - systimer_mark);
172 omap1510_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
174 unsigned long now, ilatency;
177 * Mark the time at which the timer interrupt ocurred using
178 * timer1. We need to remove interrupt latency, which we can
179 * retrieve from the current system timer2 counter. Both the
180 * offset timer1 and the system timer2 are counting at 6MHz,
183 now = 0 - read_mputimer1();
184 ilatency = MPUTICKS_PER_SEC / 100 - read_mputimer2();
185 systimer_mark = now - ilatency;
194 void __init time_init(void)
196 /* Since we don't call request_irq, we must init the structure */
197 gettimeoffset = omap1510_gettimeoffset;
199 timer_irq.handler = omap1510_timer_interrupt;
200 timer_irq.flags = SA_INTERRUPT;
201 #ifdef OMAP1510_USE_32KHZ_TIMER
202 timer32k_write(TIMER32k_CR, 0x0);
203 timer32k_write(TIMER32k_TVR,TIMER32k_PERIOD);
204 setup_irq(INT_OS_32kHz_TIMER, &timer_irq);
207 setup_irq(INT_TIMER2, &timer_irq);
208 start_mputimer2(MPUTICKS_PER_SEC / 100 - 1);