1 /* linux/include/asm-arm/arch-bast/dma.h
3 * Copyright (C) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * Samsung S3C2410X DMA support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * ??-May-2003 BJD Created file
14 * ??-Jun-2003 BJD Added more dma functionality to go with arch
18 #ifndef __ASM_ARCH_DMA_H
19 #define __ASM_ARCH_DMA_H
21 #include <linux/config.h>
26 * This is the maximum DMA address(physical address) that can be DMAd to.
29 #define MAX_DMA_ADDRESS 0x20000000
30 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
33 /* according to the samsung port, we cannot use the regular
34 * dma channels... we must therefore provide our own interface
35 * for DMA, and allow our drivers to use that.
38 #define MAX_DMA_CHANNELS 0
41 /* we have 4 dma channels */
42 #define S3C2410_DMA_CHANNELS (4)
47 typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t;
49 struct s3c2410_dma_buf_s {
50 s3c2410_dma_buf_t *next;
51 int magic; /* magic */
52 int size; /* buffer size in bytes */
53 dma_addr_t data; /* start of DMA data */
54 dma_addr_t ptr; /* where the DMA got to [1] */
56 void *id; /* client's id */
57 unsigned char no_callback; /* disable callback for buffer */
60 /* [1] is this updated for both recv/send modes? */
62 typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t;
64 typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size);
65 typedef void (*s3c2410_dma_enfn_t)(s3c2410_dma_chan_t *, int on);
66 typedef void (*s3c2410_dma_pausefn_t)(s3c2410_dma_chan_t *, int on);
68 struct s3c2410_dma_chan_s {
69 /* channel state flags */
70 unsigned char number; /* number of this dma channel */
71 unsigned char in_use; /* channel allocated */
72 unsigned char started; /* channel has been started */
73 unsigned char stopped; /* channel stopped */
74 unsigned char sleeping;
75 unsigned char xfer_unit; /* size of an transfer */
76 unsigned char irq_claimed;
78 /* channel's hardware position and configuration */
79 unsigned long regs; /* channels registers */
80 unsigned int irq; /* channel irq */
81 unsigned long addr_reg; /* data address register for buffs */
82 unsigned long dcon; /* default value of DCON */
84 /* driver handlers for channel */
85 s3c2410_dma_cbfn_t callback_fn; /* callback function for buf-done */
86 s3c2410_dma_enfn_t enable_fn; /* channel enable function */
87 s3c2410_dma_pausefn_t pause_fn; /* channel pause function */
89 /* buffer list and information */
90 s3c2410_dma_buf_t *curr; /* current dma buffer */
91 s3c2410_dma_buf_t *next; /* next buffer to load */
92 s3c2410_dma_buf_t *end; /* end of queue */
94 int queue_count; /* number of items in queue */
95 int loaded_count; /* number of loaded buffers */
98 /* note, we don't really use dma_deivce_t at the moment */
99 typedef unsigned long dma_device_t;
101 typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t;
103 /* these two defines control the source for the dma channel,
104 * wether it is from memory or an device
107 enum s3c2410_dmasrc_e {
108 S3C2410_DMASRC_HW, /* source is memory */
109 S3C2410_DMASRC_MEM /* source is hardware */
112 /* dma control routines */
114 extern int s3c2410_request_dma(dmach_t channel, const char *devid, void *dev);
115 extern int s3c2410_free_dma(dmach_t channel);
116 extern int s3c2410_dma_flush_all(dmach_t channel);
118 extern int s3c2410_dma_stop(dmach_t channel);
119 extern int s3c2410_dma_resume(dmach_t channel);
121 extern int s3c2410_dma_queue(dmach_t channel, void *id,
122 dma_addr_t data, int size);
124 #define s3c2410_dma_queue_buffer s3c2410_dma_queue
126 /* channel configuration */
128 extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
130 extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source,
131 int hwcfg, unsigned long devaddr);
133 extern int s3c2410_dma_set_enablefn(dmach_t, s3c2410_dma_enfn_t rtn);
134 extern int s3c2410_dma_set_pausefn(dmach_t, s3c2410_dma_pausefn_t rtn);
135 extern int s3c2410_dma_set_callbackfn(dmach_t, s3c2410_dma_cbfn_t rtn);
137 #define s3c2410_dma_set_callback s3c2410_dma_set_callbackfn
139 #define S3C2410_DMA_DISRC (0x00)
140 #define S3C2410_DMA_DISRCC (0x04)
141 #define S3C2410_DMA_DIDST (0x08)
142 #define S3C2410_DMA_DIDSTC (0x0C)
143 #define S3C2410_DMA_DCON (0x10)
144 #define S3C2410_DMA_DSTAT (0x14)
145 #define S3C2410_DMA_DCSRC (0x18)
146 #define S3C2410_DMA_DCDST (0x1C)
147 #define S3C2410_DMA_DMASKTRIG (0x20)
149 #define S3C2410_DMASKTRIG_STOP (1<<2)
150 #define S3C2410_DMASKTRIG_ON (1<<1)
151 #define S3C2410_DMASKTRIG_SWTRIG (1<<0)
153 #define S3C2410_DCOM_DEMAND (0<<31)
154 #define S3C2410_DCON_HANDSHAKE (1<<31)
155 #define S3C2410_DCON_SYNC_PCLK (0<<30)
156 #define S3C2410_DCON_SYNC_HCLK (1<<30)
158 #define S3C2410_DCON_INTREQ (1<<29)
160 #define S3C2410_DCON_SRCSHIFT (24)
162 #define S3C2410_DCON_BYTE (0<<20)
163 #define S3C2410_DCON_HALFWORD (1<<20)
164 #define S3C2410_DCON_WORD (2<<20)
166 #define S3C2410_DCON_AUTORELOAD (0<<22)
167 #define S3C2410_DCON_HWTRIG (1<<23)
169 #endif /* __ASM_ARCH_DMA_H */