1 /* linux/include/asm-arm/arch-s3c2410/map.h
3 * (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 - Memory map definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * 12-May-2003 BJD Created file
14 * 06-Jan-2003 BJD Linux 2.6.0 version, moved bast specifics out
15 * 10-Feb-2005 BJD Added CAMIF definition from guillaume.gourat@nexvision.tv
16 * 10-Mar-2005 LCVR Added support to S3C2400, changed {VA,SZ} names
17 * 15-Jan-2006 LCVR Added S3C24XX_PA macros for common S3C24XX resources
20 #ifndef __ASM_ARCH_MAP_H
21 #define __ASM_ARCH_MAP_H
23 /* we have a bit of a tight squeeze to fit all our registers from
24 * 0xF00000000 upwards, since we use all of the nGCS space in some
25 * capacity, and also need to fit the S3C2410 registers in as well...
27 * we try to ensure stuff like the IRQ registers are available for
28 * an single MOVS instruction (ie, only 8 bits of set data)
30 * Note, we are trying to remove some of these from the implementation
31 * as they are only useful to certain drivers...
35 #define S3C2410_ADDR(x) ((void __iomem *)0xF0000000 + (x))
37 #define S3C2410_ADDR(x) (0xF0000000 + (x))
40 #define S3C2400_ADDR(x) S3C2410_ADDR(x)
42 /* interrupt controller is the first thing we put in, to make
43 * the assembly code for the irq detection easier
45 #define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000)
46 #define S3C2400_PA_IRQ (0x14400000)
47 #define S3C2410_PA_IRQ (0x4A000000)
48 #define S3C24XX_SZ_IRQ SZ_1M
50 /* memory controller registers */
51 #define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
52 #define S3C2400_PA_MEMCTRL (0x14000000)
53 #define S3C2410_PA_MEMCTRL (0x48000000)
54 #define S3C24XX_SZ_MEMCTRL SZ_1M
56 /* USB host controller */
57 #define S3C24XX_VA_USBHOST S3C2410_ADDR(0x00200000)
58 #define S3C2400_PA_USBHOST (0x14200000)
59 #define S3C2410_PA_USBHOST (0x49000000)
60 #define S3C24XX_SZ_USBHOST SZ_1M
63 #define S3C24XX_VA_DMA S3C2410_ADDR(0x00300000)
64 #define S3C2400_PA_DMA (0x14600000)
65 #define S3C2410_PA_DMA (0x4B000000)
66 #define S3C24XX_SZ_DMA SZ_1M
68 /* Clock and Power management */
69 #define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00400000)
70 #define S3C2400_PA_CLKPWR (0x14800000)
71 #define S3C2410_PA_CLKPWR (0x4C000000)
72 #define S3C24XX_SZ_CLKPWR SZ_1M
75 #define S3C24XX_VA_LCD S3C2410_ADDR(0x00600000)
76 #define S3C2400_PA_LCD (0x14A00000)
77 #define S3C2410_PA_LCD (0x4D000000)
78 #define S3C24XX_SZ_LCD SZ_1M
80 /* NAND flash controller */
81 #define S3C24XX_VA_NAND S3C2410_ADDR(0x00700000)
82 #define S3C2410_PA_NAND (0x4E000000)
83 #define S3C24XX_SZ_NAND SZ_1M
85 /* MMC controller - available on the S3C2400 */
86 #define S3C2400_VA_MMC S3C2400_ADDR(0x00700000)
87 #define S3C2400_PA_MMC (0x15A00000)
88 #define S3C2400_SZ_MMC SZ_1M
91 #define S3C24XX_VA_UART S3C2410_ADDR(0x00800000)
92 #define S3C2400_PA_UART (0x15000000)
93 #define S3C2410_PA_UART (0x50000000)
94 #define S3C24XX_SZ_UART SZ_1M
97 #define S3C24XX_VA_TIMER S3C2410_ADDR(0x00900000)
98 #define S3C2400_PA_TIMER (0x15100000)
99 #define S3C2410_PA_TIMER (0x51000000)
100 #define S3C24XX_SZ_TIMER SZ_1M
102 /* USB Device port */
103 #define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00A00000)
104 #define S3C2400_PA_USBDEV (0x15200140)
105 #define S3C2410_PA_USBDEV (0x52000000)
106 #define S3C24XX_SZ_USBDEV SZ_1M
109 #define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00B00000)
110 #define S3C2400_PA_WATCHDOG (0x15300000)
111 #define S3C2410_PA_WATCHDOG (0x53000000)
112 #define S3C24XX_SZ_WATCHDOG SZ_1M
114 /* IIC hardware controller */
115 #define S3C24XX_VA_IIC S3C2410_ADDR(0x00C00000)
116 #define S3C2400_PA_IIC (0x15400000)
117 #define S3C2410_PA_IIC (0x54000000)
118 #define S3C24XX_SZ_IIC SZ_1M
120 #define VA_IIC_BASE (S3C24XX_VA_IIC)
123 #define S3C24XX_VA_IIS S3C2410_ADDR(0x00D00000)
124 #define S3C2400_PA_IIS (0x15508000)
125 #define S3C2410_PA_IIS (0x55000000)
126 #define S3C24XX_SZ_IIS SZ_1M
129 #define S3C24XX_VA_GPIO S3C2410_ADDR(0x00E00000)
130 #define S3C2400_PA_GPIO (0x15600000)
131 #define S3C2410_PA_GPIO (0x56000000)
132 #define S3C24XX_SZ_GPIO SZ_1M
135 #define S3C24XX_VA_RTC S3C2410_ADDR(0x00F00000)
136 #define S3C2400_PA_RTC (0x15700040)
137 #define S3C2410_PA_RTC (0x57000000)
138 #define S3C24XX_SZ_RTC SZ_1M
141 #define S3C24XX_VA_ADC S3C2410_ADDR(0x01000000)
142 #define S3C2400_PA_ADC (0x15800000)
143 #define S3C2410_PA_ADC (0x58000000)
144 #define S3C24XX_SZ_ADC SZ_1M
147 #define S3C24XX_VA_SPI S3C2410_ADDR(0x01100000)
148 #define S3C2400_PA_SPI (0x15900000)
149 #define S3C2410_PA_SPI (0x59000000)
150 #define S3C24XX_SZ_SPI SZ_1M
153 #define S3C24XX_VA_SDI S3C2410_ADDR(0x01200000)
154 #define S3C2410_PA_SDI (0x5A000000)
155 #define S3C24XX_SZ_SDI SZ_1M
158 #define S3C2440_PA_CAMIF (0x4F000000)
159 #define S3C2440_SZ_CAMIF SZ_1M
161 /* ISA style IO, for each machine to sort out mappings for, if it
162 * implements it. We reserve two 16M regions for ISA.
165 #define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
166 #define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
168 /* physical addresses of all the chip-select areas */
170 #define S3C2410_CS0 (0x00000000)
171 #define S3C2410_CS1 (0x08000000)
172 #define S3C2410_CS2 (0x10000000)
173 #define S3C2410_CS3 (0x18000000)
174 #define S3C2410_CS4 (0x20000000)
175 #define S3C2410_CS5 (0x28000000)
176 #define S3C2410_CS6 (0x30000000)
177 #define S3C2410_CS7 (0x38000000)
179 #define S3C2410_SDRAM_PA (S3C2410_CS6)
181 #define S3C2400_CS0 (0x00000000)
182 #define S3C2400_CS1 (0x02000000)
183 #define S3C2400_CS2 (0x04000000)
184 #define S3C2400_CS3 (0x06000000)
185 #define S3C2400_CS4 (0x08000000)
186 #define S3C2400_CS5 (0x0A000000)
187 #define S3C2400_CS6 (0x0C000000)
188 #define S3C2400_CS7 (0x0E000000)
190 #define S3C2400_SDRAM_PA (S3C2400_CS6)
192 /* Use a single interface for common resources between S3C24XX cpus */
194 #ifdef CONFIG_CPU_S3C2400
195 #define S3C24XX_PA_IRQ S3C2400_PA_IRQ
196 #define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
197 #define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
198 #define S3C24XX_PA_DMA S3C2400_PA_DMA
199 #define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
200 #define S3C24XX_PA_LCD S3C2400_PA_LCD
201 #define S3C24XX_PA_UART S3C2400_PA_UART
202 #define S3C24XX_PA_TIMER S3C2400_PA_TIMER
203 #define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
204 #define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
205 #define S3C24XX_PA_IIC S3C2400_PA_IIC
206 #define S3C24XX_PA_IIS S3C2400_PA_IIS
207 #define S3C24XX_PA_GPIO S3C2400_PA_GPIO
208 #define S3C24XX_PA_RTC S3C2400_PA_RTC
209 #define S3C24XX_PA_ADC S3C2400_PA_ADC
210 #define S3C24XX_PA_SPI S3C2400_PA_SPI
212 #define S3C24XX_PA_IRQ S3C2410_PA_IRQ
213 #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
214 #define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
215 #define S3C24XX_PA_DMA S3C2410_PA_DMA
216 #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
217 #define S3C24XX_PA_LCD S3C2410_PA_LCD
218 #define S3C24XX_PA_UART S3C2410_PA_UART
219 #define S3C24XX_PA_TIMER S3C2410_PA_TIMER
220 #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
221 #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
222 #define S3C24XX_PA_IIC S3C2410_PA_IIC
223 #define S3C24XX_PA_IIS S3C2410_PA_IIS
224 #define S3C24XX_PA_GPIO S3C2410_PA_GPIO
225 #define S3C24XX_PA_RTC S3C2410_PA_RTC
226 #define S3C24XX_PA_ADC S3C2410_PA_ADC
227 #define S3C24XX_PA_SPI S3C2410_PA_SPI
230 #endif /* __ASM_ARCH_MAP_H */