1 /* linux/include/asm/arch-s3c2410/regs-clock.h
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * S3C2410 clock register definitions
13 * 19-06-2003 BJD Created file
14 * 12-03-2004 BJD Updated include protection
19 #ifndef __ASM_ARM_REGS_CLOCK
20 #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
22 #define S3C2410_CLKREG(x) ((x) + S3C2410_VA_CLKPWR)
24 #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
26 #define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
27 #define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
28 #define S3C2410_UPLLCON S3C2410_CLKREG(0x08)
29 #define S3C2410_CLKCON S3C2410_CLKREG(0x0C)
30 #define S3C2410_CLKSLOW S3C2410_CLKREG(0x10)
31 #define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
33 #define S3C2410_PLLCON_MDIVSHIFT 12
34 #define S3C2410_PLLCON_PDIVSHIFT 4
35 #define S3C2410_PLLCON_SDIVSHIFT 0
36 #define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
37 #define S3C2410_PLLCON_PDIVMASK ((1<<5)-1)
38 #define S3C2410_PLLCON_SDIVMASK 3
40 /* DCLKCON register addresses in gpio.h */
42 #define S3C2410_DCLKCON_DCLK0EN (1<<0)
43 #define S3C2410_DCLKCON_DCLK0_PCLK (0<<1)
44 #define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
45 #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
46 #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
48 #define S3C2410_DCLKCON_DCLK1EN (1<<16)
49 #define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
50 #define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
51 #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
53 #define S3C2410_CLKDIVN_PDIVN (1<<0)
54 #define S3C2410_CLKDIVN_HDIVN (1<<1)
56 static inline unsigned int
57 s3c2410_get_pll(int pllval, int baseclk)
61 mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
62 pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
63 sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
65 mdiv &= S3C2410_PLLCON_MDIVMASK;
66 pdiv &= S3C2410_PLLCON_PDIVMASK;
67 sdiv &= S3C2410_PLLCON_SDIVMASK;
69 return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
72 #endif /* __ASM_ARM_REGS_CLOCK */