1 /* linux/include/asm/hardware/s3c2410/
3 * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * S3C2410 GPIO register definitions
13 * 19-06-2003 BJD Created file
14 * 23-06-2003 BJD Updated GSTATUS registers
15 * 12-03-2004 BJD Updated include protection
16 * 20-07-2004 BJD Added GPIO pin numbers, added Port A definitions
17 * 04-10-2004 BJD Fixed number of bugs, added EXT IRQ filter defs
21 #ifndef __ASM_ARCH_REGS_GPIO_H
22 #define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
24 #define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
26 #define S3C2410_GPIO_BANKA (32*0)
27 #define S3C2410_GPIO_BANKB (32*1)
28 #define S3C2410_GPIO_BANKC (32*2)
29 #define S3C2410_GPIO_BANKD (32*3)
30 #define S3C2410_GPIO_BANKE (32*4)
31 #define S3C2410_GPIO_BANKF (32*5)
32 #define S3C2410_GPIO_BANKG (32*6)
33 #define S3C2410_GPIO_BANKH (32*7)
35 #define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C2410_VA_GPIO)
36 #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
38 /* general configuration options */
40 #define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
42 /* configure GPIO ports A..G */
44 #define S3C2410_GPIOREG(x) ((x) + S3C2410_VA_GPIO)
46 /* port A - 22bits, zero in bit X makes pin X output
47 * 1 makes port special function, this is default
49 #define S3C2410_GPACON S3C2410_GPIOREG(0x00)
50 #define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
52 #define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
53 #define S3C2410_GPA0_OUT (0<<0)
54 #define S3C2410_GPA0_ADDR0 (1<<0)
56 #define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
57 #define S3C2410_GPA1_OUT (0<<1)
58 #define S3C2410_GPA1_ADDR16 (1<<1)
60 #define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
61 #define S3C2410_GPA2_OUT (0<<2)
62 #define S3C2410_GPA2_ADDR17 (1<<2)
64 #define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
65 #define S3C2410_GPA3_OUT (0<<3)
66 #define S3C2410_GPA3_ADDR18 (1<<3)
68 #define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
69 #define S3C2410_GPA4_OUT (0<<4)
70 #define S3C2410_GPA4_ADDR19 (1<<4)
72 #define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
73 #define S3C2410_GPA5_OUT (0<<5)
74 #define S3C2410_GPA5_ADDR20 (1<<5)
76 #define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
77 #define S3C2410_GPA6_OUT (0<<6)
78 #define S3C2410_GPA6_ADDR21 (1<<6)
80 #define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
81 #define S3C2410_GPA7_OUT (0<<7)
82 #define S3C2410_GPA7_ADDR22 (1<<7)
84 #define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
85 #define S3C2410_GPA8_OUT (0<<8)
86 #define S3C2410_GPA8_ADDR23 (1<<8)
88 #define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
89 #define S3C2410_GPA9_OUT (0<<9)
90 #define S3C2410_GPA9_ADDR24 (1<<9)
92 #define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
93 #define S3C2410_GPA10_OUT (0<<10)
94 #define S3C2410_GPA10_ADDR25 (1<<10)
96 #define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
97 #define S3C2410_GPA11_OUT (0<<11)
98 #define S3C2410_GPA11_ADDR26 (1<<11)
100 #define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
101 #define S3C2410_GPA12_OUT (0<<12)
102 #define S3C2410_GPA12_nGCS1 (1<<12)
104 #define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
105 #define S3C2410_GPA13_OUT (0<<13)
106 #define S3C2410_GPA13_nGCS2 (1<<13)
108 #define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
109 #define S3C2410_GPA14_OUT (0<<14)
110 #define S3C2410_GPA14_nGCS3 (1<<14)
112 #define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
113 #define S3C2410_GPA15_OUT (0<<15)
114 #define S3C2410_GPA15_nGCS4 (1<<15)
116 #define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
117 #define S3C2410_GPA16_OUT (0<<16)
118 #define S3C2410_GPA16_nGCS5 (1<<16)
120 #define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
121 #define S3C2410_GPA17_OUT (0<<17)
122 #define S3C2410_GPA17_CLE (1<<17)
124 #define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
125 #define S3C2410_GPA18_OUT (0<<18)
126 #define S3C2410_GPA18_ALE (1<<18)
128 #define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
129 #define S3C2410_GPA19_OUT (0<<19)
130 #define S3C2410_GPA19_nFWE (1<<19)
132 #define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
133 #define S3C2410_GPA20_OUT (0<<20)
134 #define S3C2410_GPA20_nFRE (1<<20)
136 #define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
137 #define S3C2410_GPA21_OUT (0<<21)
138 #define S3C2410_GPA21_nRSTOUT (1<<21)
140 #define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
141 #define S3C2410_GPA22_OUT (0<<22)
142 #define S3C2410_GPA22_nFCE (1<<22)
144 /* 0x08 and 0x0c are reserved */
146 /* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
147 * 00 = input, 01 = output, 10=special function, 11=reserved
148 * bit 0,1 = pin 0, 2,3= pin 1...
150 * CPBUP = pull up resistor control, 1=disabled, 0=enabled
153 #define S3C2410_GPBCON S3C2410_GPIOREG(0x10)
154 #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
155 #define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
157 /* no i/o pin in port b can have value 3! */
159 #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
160 #define S3C2410_GPB0_INP (0x00 << 0)
161 #define S3C2410_GPB0_OUTP (0x01 << 0)
162 #define S3C2410_GPB0_TOUT0 (0x02 << 0)
164 #define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
165 #define S3C2410_GPB1_INP (0x00 << 2)
166 #define S3C2410_GPB1_OUTP (0x01 << 2)
167 #define S3C2410_GPB1_TOUT1 (0x02 << 2)
169 #define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
170 #define S3C2410_GPB2_INP (0x00 << 4)
171 #define S3C2410_GPB2_OUTP (0x01 << 4)
172 #define S3C2410_GPB2_TOUT2 (0x02 << 4)
174 #define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
175 #define S3C2410_GPB3_INP (0x00 << 6)
176 #define S3C2410_GPB3_OUTP (0x01 << 6)
177 #define S3C2410_GPB3_TOUT3 (0x02 << 6)
179 #define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
180 #define S3C2410_GPB4_INP (0x00 << 8)
181 #define S3C2410_GPB4_OUTP (0x01 << 8)
182 #define S3C2410_GPB4_TCLK0 (0x02 << 8)
183 #define S3C2410_GPB4_MASK (0x03 << 8)
185 #define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
186 #define S3C2410_GPB5_INP (0x00 << 10)
187 #define S3C2410_GPB5_OUTP (0x01 << 10)
188 #define S3C2410_GPB5_nXBACK (0x02 << 10)
190 #define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
191 #define S3C2410_GPB6_INP (0x00 << 12)
192 #define S3C2410_GPB6_OUTP (0x01 << 12)
193 #define S3C2410_GPB6_nXBREQ (0x02 << 12)
195 #define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
196 #define S3C2410_GPB7_INP (0x00 << 14)
197 #define S3C2410_GPB7_OUTP (0x01 << 14)
198 #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
200 #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
201 #define S3C2410_GPB8_INP (0x00 << 16)
202 #define S3C2410_GPB8_OUTP (0x01 << 16)
203 #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
205 #define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
206 #define S3C2410_GPB9_INP (0x00 << 18)
207 #define S3C2410_GPB9_OUTP (0x01 << 18)
208 #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
210 #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
211 #define S3C2410_GPB10_INP (0x00 << 18)
212 #define S3C2410_GPB10_OUTP (0x01 << 18)
213 #define S3C2410_GPB10_nXDRE0 (0x02 << 18)
215 /* Port C consits of 16 GPIO/Special function
217 * almost identical setup to port b, but the special functions are mostly
218 * to do with the video system's sync/etc.
221 #define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
222 #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
223 #define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
225 #define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
226 #define S3C2410_GPC0_INP (0x00 << 0)
227 #define S3C2410_GPC0_OUTP (0x01 << 0)
228 #define S3C2410_GPC0_LEND (0x02 << 0)
230 #define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
231 #define S3C2410_GPC1_INP (0x00 << 2)
232 #define S3C2410_GPC1_OUTP (0x01 << 2)
233 #define S3C2410_GPC1_VCLK (0x02 << 2)
235 #define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
236 #define S3C2410_GPC2_INP (0x00 << 4)
237 #define S3C2410_GPC2_OUTP (0x01 << 4)
238 #define S3C2410_GPC2_VLINE (0x02 << 4)
240 #define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
241 #define S3C2410_GPC3_INP (0x00 << 6)
242 #define S3C2410_GPC3_OUTP (0x01 << 6)
243 #define S3C2410_GPC3_VFRAME (0x02 << 6)
245 #define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
246 #define S3C2410_GPC4_INP (0x00 << 8)
247 #define S3C2410_GPC4_OUTP (0x01 << 8)
248 #define S3C2410_GPC4_VM (0x02 << 8)
250 #define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
251 #define S3C2410_GPC5_INP (0x00 << 10)
252 #define S3C2410_GPC5_OUTP (0x01 << 10)
253 #define S3C2410_GPC5_LCDVF0 (0x02 << 10)
255 #define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
256 #define S3C2410_GPC6_INP (0x00 << 12)
257 #define S3C2410_GPC6_OUTP (0x01 << 12)
258 #define S3C2410_GPC6_LCDVF1 (0x02 << 12)
260 #define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
261 #define S3C2410_GPC7_INP (0x00 << 14)
262 #define S3C2410_GPC7_OUTP (0x01 << 14)
263 #define S3C2410_GPC7_LCDVF2 (0x02 << 14)
265 #define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
266 #define S3C2410_GPC8_INP (0x00 << 16)
267 #define S3C2410_GPC8_OUTP (0x01 << 16)
268 #define S3C2410_GPC8_VD0 (0x02 << 16)
270 #define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
271 #define S3C2410_GPC9_INP (0x00 << 18)
272 #define S3C2410_GPC9_OUTP (0x01 << 18)
273 #define S3C2410_GPC9_VD1 (0x02 << 18)
275 #define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
276 #define S3C2410_GPC10_INP (0x00 << 20)
277 #define S3C2410_GPC10_OUTP (0x01 << 20)
278 #define S3C2410_GPC10_VD2 (0x02 << 20)
280 #define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
281 #define S3C2410_GPC11_INP (0x00 << 22)
282 #define S3C2410_GPC11_OUTP (0x01 << 22)
283 #define S3C2410_GPC11_VD3 (0x02 << 22)
285 #define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
286 #define S3C2410_GPC12_INP (0x00 << 24)
287 #define S3C2410_GPC12_OUTP (0x01 << 24)
288 #define S3C2410_GPC12_VD4 (0x02 << 24)
290 #define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
291 #define S3C2410_GPC13_INP (0x00 << 26)
292 #define S3C2410_GPC13_OUTP (0x01 << 26)
293 #define S3C2410_GPC13_VD5 (0x02 << 26)
295 #define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
296 #define S3C2410_GPC14_INP (0x00 << 28)
297 #define S3C2410_GPC14_OUTP (0x01 << 28)
298 #define S3C2410_GPC14_VD6 (0x02 << 28)
300 #define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
301 #define S3C2410_GPC15_INP (0x00 << 30)
302 #define S3C2410_GPC15_OUTP (0x01 << 30)
303 #define S3C2410_GPC15_VD7 (0x02 << 30)
305 /* Port D consists of 16 GPIO/Special function
307 * almost identical setup to port b, but the special functions are mostly
308 * to do with the video system's data.
311 #define S3C2410_GPDCON S3C2410_GPIOREG(0x30)
312 #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
313 #define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
315 #define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
316 #define S3C2410_GPD0_INP (0x00 << 0)
317 #define S3C2410_GPD0_OUTP (0x01 << 0)
318 #define S3C2410_GPD0_VD8 (0x02 << 0)
320 #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
321 #define S3C2410_GPD1_INP (0x00 << 2)
322 #define S3C2410_GPD1_OUTP (0x01 << 2)
323 #define S3C2410_GPD1_VD9 (0x02 << 2)
325 #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
326 #define S3C2410_GPD2_INP (0x00 << 4)
327 #define S3C2410_GPD2_OUTP (0x01 << 4)
328 #define S3C2410_GPD2_VD10 (0x02 << 4)
330 #define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
331 #define S3C2410_GPD3_INP (0x00 << 6)
332 #define S3C2410_GPD3_OUTP (0x01 << 6)
333 #define S3C2410_GPD3_VD11 (0x02 << 6)
335 #define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
336 #define S3C2410_GPD4_INP (0x00 << 8)
337 #define S3C2410_GPD4_OUTP (0x01 << 8)
338 #define S3C2410_GPD4_VD12 (0x02 << 8)
340 #define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
341 #define S3C2410_GPD5_INP (0x00 << 10)
342 #define S3C2410_GPD5_OUTP (0x01 << 10)
343 #define S3C2410_GPD5_VD13 (0x02 << 10)
345 #define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
346 #define S3C2410_GPD6_INP (0x00 << 12)
347 #define S3C2410_GPD6_OUTP (0x01 << 12)
348 #define S3C2410_GPD6_VD14 (0x02 << 12)
350 #define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
351 #define S3C2410_GPD7_INP (0x00 << 14)
352 #define S3C2410_GPD7_OUTP (0x01 << 14)
353 #define S3C2410_GPD7_VD15 (0x02 << 14)
355 #define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
356 #define S3C2410_GPD8_INP (0x00 << 16)
357 #define S3C2410_GPD8_OUTP (0x01 << 16)
358 #define S3C2410_GPD8_VD16 (0x02 << 16)
360 #define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
361 #define S3C2410_GPD9_INP (0x00 << 18)
362 #define S3C2410_GPD9_OUTP (0x01 << 18)
363 #define S3C2410_GPD9_VD17 (0x02 << 18)
365 #define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
366 #define S3C2410_GPD10_INP (0x00 << 20)
367 #define S3C2410_GPD10_OUTP (0x01 << 20)
368 #define S3C2410_GPD10_VD18 (0x02 << 20)
370 #define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
371 #define S3C2410_GPD11_INP (0x00 << 22)
372 #define S3C2410_GPD11_OUTP (0x01 << 22)
373 #define S3C2410_GPD11_VD19 (0x02 << 22)
375 #define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
376 #define S3C2410_GPD12_INP (0x00 << 24)
377 #define S3C2410_GPD12_OUTP (0x01 << 24)
378 #define S3C2410_GPD12_VD20 (0x02 << 24)
380 #define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
381 #define S3C2410_GPD13_INP (0x00 << 26)
382 #define S3C2410_GPD13_OUTP (0x01 << 26)
383 #define S3C2410_GPD13_VD21 (0x02 << 26)
385 #define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
386 #define S3C2410_GPD14_INP (0x00 << 28)
387 #define S3C2410_GPD14_OUTP (0x01 << 28)
388 #define S3C2410_GPD14_VD22 (0x02 << 28)
390 #define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
391 #define S3C2410_GPD15_INP (0x00 << 30)
392 #define S3C2410_GPD15_OUTP (0x01 << 30)
393 #define S3C2410_GPD15_VD23 (0x02 << 30)
395 /* Port E consists of 16 GPIO/Special function
397 * again, the same as port B, but dealing with I2S, SDI, and
398 * more miscellaneous functions
401 #define S3C2410_GPECON S3C2410_GPIOREG(0x40)
402 #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
403 #define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
405 #define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
406 #define S3C2410_GPE0_INP (0x00 << 0)
407 #define S3C2410_GPE0_OUTP (0x01 << 0)
408 #define S3C2410_GPE0_I2SLRCK (0x02 << 0)
409 #define S3C2410_GPE0_MASK (0x03 << 0)
411 #define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
412 #define S3C2410_GPE1_INP (0x00 << 2)
413 #define S3C2410_GPE1_OUTP (0x01 << 2)
414 #define S3C2410_GPE1_I2SSCLK (0x02 << 2)
415 #define S3C2410_GPE1_MASK (0x03 << 2)
417 #define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
418 #define S3C2410_GPE2_INP (0x00 << 4)
419 #define S3C2410_GPE2_OUTP (0x01 << 4)
420 #define S3C2410_GPE2_CDCLK (0x02 << 4)
422 #define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
423 #define S3C2410_GPE3_INP (0x00 << 6)
424 #define S3C2410_GPE3_OUTP (0x01 << 6)
425 #define S3C2410_GPE3_I2SSDI (0x02 << 6)
426 #define S3C2410_GPE3_MASK (0x03 << 6)
428 #define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
429 #define S3C2410_GPE4_INP (0x00 << 8)
430 #define S3C2410_GPE4_OUTP (0x01 << 8)
431 #define S3C2410_GPE4_I2SSDO (0x02 << 8)
432 #define S3C2410_GPE4_MASK (0x03 << 8)
434 #define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
435 #define S3C2410_GPE5_INP (0x00 << 10)
436 #define S3C2410_GPE5_OUTP (0x01 << 10)
437 #define S3C2410_GPE5_SDCLK (0x02 << 10)
439 #define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
440 #define S3C2410_GPE6_INP (0x00 << 12)
441 #define S3C2410_GPE6_OUTP (0x01 << 12)
442 #define S3C2410_GPE6_SDCLK (0x02 << 12)
444 #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
445 #define S3C2410_GPE7_INP (0x00 << 14)
446 #define S3C2410_GPE7_OUTP (0x01 << 14)
447 #define S3C2410_GPE7_SDCMD (0x02 << 14)
449 #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
450 #define S3C2410_GPE8_INP (0x00 << 16)
451 #define S3C2410_GPE8_OUTP (0x01 << 16)
452 #define S3C2410_GPE8_SDDAT1 (0x02 << 16)
454 #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
455 #define S3C2410_GPE9_INP (0x00 << 18)
456 #define S3C2410_GPE9_OUTP (0x01 << 18)
457 #define S3C2410_GPE9_SDDAT2 (0x02 << 18)
459 #define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
460 #define S3C2410_GPE10_INP (0x00 << 20)
461 #define S3C2410_GPE10_OUTP (0x01 << 20)
462 #define S3C2410_GPE10_SDDAT3 (0x02 << 20)
464 #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
465 #define S3C2410_GPE11_INP (0x00 << 22)
466 #define S3C2410_GPE11_OUTP (0x01 << 22)
467 #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
469 #define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
470 #define S3C2410_GPE12_INP (0x00 << 24)
471 #define S3C2410_GPE12_OUTP (0x01 << 24)
472 #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
474 #define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
475 #define S3C2410_GPE13_INP (0x00 << 26)
476 #define S3C2410_GPE13_OUTP (0x01 << 26)
477 #define S3C2410_GPE13_SPICLK0 (0x02 << 26)
479 #define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
480 #define S3C2410_GPE14_INP (0x00 << 28)
481 #define S3C2410_GPE14_OUTP (0x01 << 28)
482 #define S3C2410_GPE14_IICSCL (0x02 << 28)
483 #define S3C2410_GPE14_MASK (0x03 << 28)
485 #define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
486 #define S3C2410_GPE15_INP (0x00 << 30)
487 #define S3C2410_GPE15_OUTP (0x01 << 30)
488 #define S3C2410_GPE15_IICSDA (0x02 << 30)
489 #define S3C2410_GPE15_MASK (0x03 << 30)
491 #define S3C2410_GPE_PUPDIS(x) (1<<(x))
493 /* Port F consists of 8 GPIO/Special function
495 * GPIO / interrupt inputs
497 * GPFCON has 2 bits for each of the input pins on port F
498 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
500 * pull up works like all other ports.
503 #define S3C2410_GPFCON S3C2410_GPIOREG(0x50)
504 #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
505 #define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
507 #define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
508 #define S3C2410_GPF0_INP (0x00 << 0)
509 #define S3C2410_GPF0_OUTP (0x01 << 0)
510 #define S3C2410_GPF0_EINT0 (0x02 << 0)
512 #define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
513 #define S3C2410_GPF1_INP (0x00 << 2)
514 #define S3C2410_GPF1_OUTP (0x01 << 2)
515 #define S3C2410_GPF1_EINT1 (0x02 << 2)
517 #define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
518 #define S3C2410_GPF2_INP (0x00 << 4)
519 #define S3C2410_GPF2_OUTP (0x01 << 4)
520 #define S3C2410_GPF2_EINT2 (0x02 << 4)
522 #define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
523 #define S3C2410_GPF3_INP (0x00 << 6)
524 #define S3C2410_GPF3_OUTP (0x01 << 6)
525 #define S3C2410_GPF3_EINT3 (0x02 << 6)
527 #define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
528 #define S3C2410_GPF4_INP (0x00 << 8)
529 #define S3C2410_GPF4_OUTP (0x01 << 8)
530 #define S3C2410_GPF4_EINT4 (0x02 << 8)
532 #define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
533 #define S3C2410_GPF5_INP (0x00 << 10)
534 #define S3C2410_GPF5_OUTP (0x01 << 10)
535 #define S3C2410_GPF5_EINT5 (0x02 << 10)
537 #define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
538 #define S3C2410_GPF6_INP (0x00 << 12)
539 #define S3C2410_GPF6_OUTP (0x01 << 12)
540 #define S3C2410_GPF6_EINT6 (0x02 << 12)
542 #define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
543 #define S3C2410_GPF7_INP (0x00 << 14)
544 #define S3C2410_GPF7_OUTP (0x01 << 14)
545 #define S3C2410_GPF7_EINT7 (0x02 << 14)
547 /* Port G consists of 8 GPIO/IRQ/Special function
549 * GPGCON has 2 bits for each of the input pins on port F
550 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
552 * pull up works like all other ports.
555 #define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
556 #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
557 #define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
559 #define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
560 #define S3C2410_GPG0_INP (0x00 << 0)
561 #define S3C2410_GPG0_OUTP (0x01 << 0)
562 #define S3C2410_GPG0_EINT8 (0x02 << 0)
564 #define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
565 #define S3C2410_GPG1_INP (0x00 << 2)
566 #define S3C2410_GPG1_OUTP (0x01 << 2)
567 #define S3C2410_GPG1_EINT9 (0x02 << 2)
569 #define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
570 #define S3C2410_GPG2_INP (0x00 << 4)
571 #define S3C2410_GPG2_OUTP (0x01 << 4)
572 #define S3C2410_GPG2_EINT10 (0x02 << 4)
574 #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
575 #define S3C2410_GPG3_INP (0x00 << 6)
576 #define S3C2410_GPG3_OUTP (0x01 << 6)
577 #define S3C2410_GPG3_EINT11 (0x02 << 6)
579 #define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
580 #define S3C2410_GPG4_INP (0x00 << 8)
581 #define S3C2410_GPG4_OUTP (0x01 << 8)
582 #define S3C2410_GPG4_EINT12 (0x02 << 8)
583 #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
585 #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
586 #define S3C2410_GPG5_INP (0x00 << 10)
587 #define S3C2410_GPG5_OUTP (0x01 << 10)
588 #define S3C2410_GPG5_EINT13 (0x02 << 10)
589 #define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
591 #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
592 #define S3C2410_GPG6_INP (0x00 << 12)
593 #define S3C2410_GPG6_OUTP (0x01 << 12)
594 #define S3C2410_GPG6_EINT14 (0x02 << 12)
595 #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
597 #define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
598 #define S3C2410_GPG7_INP (0x00 << 14)
599 #define S3C2410_GPG7_OUTP (0x01 << 14)
600 #define S3C2410_GPG7_EINT15 (0x02 << 14)
601 #define S3C2410_GPG7_SPICLK1 (0x03 << 14)
603 #define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
604 #define S3C2410_GPG8_INP (0x00 << 16)
605 #define S3C2410_GPG8_OUTP (0x01 << 16)
606 #define S3C2410_GPG8_EINT16 (0x02 << 16)
608 #define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
609 #define S3C2410_GPG9_INP (0x00 << 18)
610 #define S3C2410_GPG9_OUTP (0x01 << 18)
611 #define S3C2410_GPG9_EINT17 (0x02 << 18)
613 #define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
614 #define S3C2410_GPG10_INP (0x00 << 20)
615 #define S3C2410_GPG10_OUTP (0x01 << 20)
616 #define S3C2410_GPG10_EINT18 (0x02 << 20)
618 #define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
619 #define S3C2410_GPG11_INP (0x00 << 22)
620 #define S3C2410_GPG11_OUTP (0x01 << 22)
621 #define S3C2410_GPG11_EINT19 (0x02 << 22)
622 #define S3C2410_GPG11_TCLK1 (0x03 << 22)
624 #define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
625 #define S3C2410_GPG12_INP (0x00 << 24)
626 #define S3C2410_GPG12_OUTP (0x01 << 24)
627 #define S3C2410_GPG12_EINT20 (0x02 << 24)
628 #define S3C2410_GPG12_XMON (0x03 << 24)
630 #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
631 #define S3C2410_GPG13_INP (0x00 << 26)
632 #define S3C2410_GPG13_OUTP (0x01 << 26)
633 #define S3C2410_GPG13_EINT21 (0x02 << 26)
634 #define S3C2410_GPG13_nXPON (0x03 << 26)
636 #define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
637 #define S3C2410_GPG14_INP (0x00 << 28)
638 #define S3C2410_GPG14_OUTP (0x01 << 28)
639 #define S3C2410_GPG14_EINT22 (0x02 << 28)
640 #define S3C2410_GPG14_YMON (0x03 << 28)
642 #define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
643 #define S3C2410_GPG15_INP (0x00 << 30)
644 #define S3C2410_GPG15_OUTP (0x01 << 30)
645 #define S3C2410_GPG15_EINT23 (0x02 << 30)
646 #define S3C2410_GPG15_nYPON (0x03 << 30)
649 #define S3C2410_GPG_PUPDIS(x) (1<<(x))
651 /* Port H consists of11 GPIO/serial/Misc pins
653 * GPGCON has 2 bits for each of the input pins on port F
654 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
656 * pull up works like all other ports.
659 #define S3C2410_GPHCON S3C2410_GPIOREG(0x70)
660 #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
661 #define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
663 #define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
664 #define S3C2410_GPH0_INP (0x00 << 0)
665 #define S3C2410_GPH0_OUTP (0x01 << 0)
666 #define S3C2410_GPH0_nCTS0 (0x02 << 0)
668 #define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
669 #define S3C2410_GPH1_INP (0x00 << 2)
670 #define S3C2410_GPH1_OUTP (0x01 << 2)
671 #define S3C2410_GPH1_nRTS0 (0x02 << 2)
673 #define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
674 #define S3C2410_GPH2_INP (0x00 << 4)
675 #define S3C2410_GPH2_OUTP (0x01 << 4)
676 #define S3C2410_GPH2_TXD0 (0x02 << 4)
678 #define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
679 #define S3C2410_GPH3_INP (0x00 << 6)
680 #define S3C2410_GPH3_OUTP (0x01 << 6)
681 #define S3C2410_GPH3_RXD0 (0x02 << 6)
683 #define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
684 #define S3C2410_GPH4_INP (0x00 << 8)
685 #define S3C2410_GPH4_OUTP (0x01 << 8)
686 #define S3C2410_GPH4_TXD1 (0x02 << 8)
688 #define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
689 #define S3C2410_GPH5_INP (0x00 << 10)
690 #define S3C2410_GPH5_OUTP (0x01 << 10)
691 #define S3C2410_GPH5_RXD1 (0x02 << 10)
693 #define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
694 #define S3C2410_GPH6_INP (0x00 << 12)
695 #define S3C2410_GPH6_OUTP (0x01 << 12)
696 #define S3C2410_GPH6_TXD2 (0x02 << 12)
697 #define S3C2410_GPH6_nRTS1 (0x03 << 12)
699 #define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
700 #define S3C2410_GPH7_INP (0x00 << 14)
701 #define S3C2410_GPH7_OUTP (0x01 << 14)
702 #define S3C2410_GPH7_RXD2 (0x02 << 14)
703 #define S3C2410_GPH7_nCTS1 (0x03 << 14)
705 #define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
706 #define S3C2410_GPH8_INP (0x00 << 16)
707 #define S3C2410_GPH8_OUTP (0x01 << 16)
708 #define S3C2410_GPH8_UCLK (0x02 << 16)
710 #define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
711 #define S3C2410_GPH9_INP (0x00 << 18)
712 #define S3C2410_GPH9_OUTP (0x01 << 18)
713 #define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
715 #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
716 #define S3C2410_GPH10_INP (0x00 << 20)
717 #define S3C2410_GPH10_OUTP (0x01 << 20)
718 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
720 /* miscellaneous control */
722 #define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
723 #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
725 /* see clock.h for dclk definitions */
727 /* pullup control on databus */
728 #define S3C2410_MISCCR_SPUCR_HEN (0)
729 #define S3C2410_MISCCR_SPUCR_HDIS (1<<0)
730 #define S3C2410_MISCCR_SPUCR_LEN (0)
731 #define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
733 #define S3C2410_MISCCR_USBDEV (0)
734 #define S3C2410_MISCCR_USBHOST (1<<3)
736 #define S3C2410_MISCCR_CLK0_MPLL (0<<4)
737 #define S3C2410_MISCCR_CLK0_UPLL (1<<4)
738 #define S3C2410_MISCCR_CLK0_FCLK (2<<4)
739 #define S3C2410_MISCCR_CLK0_HCLK (3<<4)
740 #define S3C2410_MISCCR_CLK0_PCLK (4<<4)
741 #define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
743 #define S3C2410_MISCCR_CLK1_MPLL (0<<8)
744 #define S3C2410_MISCCR_CLK1_UPLL (1<<8)
745 #define S3C2410_MISCCR_CLK1_FCLK (2<<8)
746 #define S3C2410_MISCCR_CLK1_HCLK (3<<8)
747 #define S3C2410_MISCCR_CLK1_PCLK (4<<8)
748 #define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
750 #define S3C2410_MISCCR_USBSUSPND0 (1<<12)
751 #define S3C2410_MISCCR_USBSUSPND1 (1<<13)
753 #define S3C2410_MISCCR_nRSTCON (1<<16)
755 #define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
756 #define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
757 #define S3C2410_MISCCR_nEN_SCLKE (1<<19)
758 #define S3C2410_MISCCR_SDSLEEP (7<<17)
760 /* external interrupt control... */
761 /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
762 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
763 * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
765 * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
767 * Samsung datasheet p9-25
770 #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
771 #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
772 #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
774 /* values for S3C2410_EXTINT0/1/2 */
775 #define S3C2410_EXTINT_LOWLEV (0x00)
776 #define S3C2410_EXTINT_HILEV (0x01)
777 #define S3C2410_EXTINT_FALLEDGE (0x02)
778 #define S3C2410_EXTINT_RISEEDGE (0x04)
779 #define S3C2410_EXTINT_BOTHEDGE (0x06)
781 /* interrupt filtering conrrol for EINT16..EINT23 */
782 #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
783 #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
784 #define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
785 #define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
787 /* values for interrupt filtering */
788 #define S3C2410_EINTFLT_PCLK (0x00)
789 #define S3C2410_EINTFLT_EXTCLK (1<<7)
790 #define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f)
792 /* removed EINTxxxx defs from here, not meant for this */
794 /* GSTATUS have miscellaneous information in them
798 #define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
799 #define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)
800 #define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)
801 #define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
802 #define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
804 #define S3C2410_GSTATUS0_nWAIT (1<<3)
805 #define S3C2410_GSTATUS0_NCON (1<<2)
806 #define S3C2410_GSTATUS0_RnB (1<<1)
807 #define S3C2410_GSTATUS0_nBATTFLT (1<<0)
809 #define S3C2410_GSTATUS2_WTRESET (1<<2)
810 #define S3C2410_GSTATUs2_OFFRESET (1<<1)
811 #define S3C2410_GSTATUS2_PONRESET (1<<0)
813 #endif /* __ASM_ARCH_REGS_GPIO_H */