1 /* linux/include/asm-arm/arch-s3c2410/regs-serial.h
3 * From linux/include/asm-arm/hardware/serial_s3c2410.h
5 * Internal header file for Samsung S3C2410 serial ports (UART0-2)
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
9 * Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
13 * Internal header file for MX1ADS serial ports (UART1 & 2)
15 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 #ifndef __ASM_ARM_REGS_SERIAL_H
33 #define __ASM_ARM_REGS_SERIAL_H
35 #define S3C2410_VA_UART0 (S3C2410_VA_UART)
36 #define S3C2410_VA_UART1 (S3C2410_VA_UART + 0x4000 )
37 #define S3C2410_VA_UART2 (S3C2410_VA_UART + 0x8000 )
39 #define S3C2410_PA_UART0 (S3C2410_PA_UART)
40 #define S3C2410_PA_UART1 (S3C2410_PA_UART + 0x4000 )
41 #define S3C2410_PA_UART2 (S3C2410_PA_UART + 0x8000 )
43 #define S3C2410_URXH (0x24)
44 #define S3C2410_UTXH (0x20)
45 #define S3C2410_ULCON (0x00)
46 #define S3C2410_UCON (0x04)
47 #define S3C2410_UFCON (0x08)
48 #define S3C2410_UMCON (0x0C)
49 #define S3C2410_UBRDIV (0x28)
50 #define S3C2410_UTRSTAT (0x10)
51 #define S3C2410_UERSTAT (0x14)
52 #define S3C2410_UFSTAT (0x18)
53 #define S3C2410_UMSTAT (0x1C)
55 #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
57 #define S3C2410_LCON_CS5 (0x0)
58 #define S3C2410_LCON_CS6 (0x1)
59 #define S3C2410_LCON_CS7 (0x2)
60 #define S3C2410_LCON_CS8 (0x3)
61 #define S3C2410_LCON_CSMASK (0x3)
63 #define S3C2410_LCON_PNONE (0x0)
64 #define S3C2410_LCON_PEVEN (0x5 << 3)
65 #define S3C2410_LCON_PODD (0x4 << 3)
66 #define S3C2410_LCON_PMASK (0x7 << 3)
68 #define S3C2410_LCON_STOPB (1<<2)
69 #define S3C2410_LCON_IRM (1<<6)
71 #define S3C2440_UCON_CLKMASK (3<<10)
72 #define S3C2440_UCON_PCLK (0<<10)
73 #define S3C2440_UCON_UCLK (1<<10)
74 #define S3C2440_UCON_PCLK2 (2<<10)
75 #define S3C2440_UCON_FCLK (3<<10)
77 #define S3C2410_UCON_UCLK (1<<10)
78 #define S3C2410_UCON_SBREAK (1<<4)
80 #define S3C2410_UCON_TXILEVEL (1<<9)
81 #define S3C2410_UCON_RXILEVEL (1<<8)
82 #define S3C2410_UCON_TXIRQMODE (1<<2)
83 #define S3C2410_UCON_RXIRQMODE (1<<0)
84 #define S3C2410_UCON_RXFIFO_TOI (1<<7)
86 #define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
87 S3C2410_UCON_RXILEVEL | \
88 S3C2410_UCON_TXIRQMODE | \
89 S3C2410_UCON_RXIRQMODE | \
90 S3C2410_UCON_RXFIFO_TOI)
92 #define S3C2410_UFCON_FIFOMODE (1<<0)
93 #define S3C2410_UFCON_TXTRIG0 (0<<6)
94 #define S3C2410_UFCON_RXTRIG8 (1<<4)
95 #define S3C2410_UFCON_RXTRIG12 (2<<4)
97 /* S3C2440 FIFO trigger levels */
98 #define S3C2440_UFCON_RXTRIG1 (0<<4)
99 #define S3C2440_UFCON_RXTRIG8 (1<<4)
100 #define S3C2440_UFCON_RXTRIG16 (2<<4)
101 #define S3C2440_UFCON_RXTRIG32 (3<<4)
103 #define S3C2440_UFCON_TXTRIG0 (0<<6)
104 #define S3C2440_UFCON_TXTRIG16 (1<<6)
105 #define S3C2440_UFCON_TXTRIG32 (2<<6)
106 #define S3C2440_UFCON_TXTRIG48 (3<<6)
108 #define S3C2410_UFCON_RESETBOTH (3<<1)
109 #define S3C2410_UFCON_RESETTX (1<<2)
110 #define S3C2410_UFCON_RESETRX (1<<1)
112 #define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
113 S3C2410_UFCON_TXTRIG0 | \
114 S3C2410_UFCON_RXTRIG8 )
116 #define S3C2410_UMCOM_AFC (1<<4)
117 #define S3C2410_UMCOM_RTS_LOW (1<<0)
119 #define S3C2410_UFSTAT_TXFULL (1<<9)
120 #define S3C2410_UFSTAT_RXFULL (1<<8)
121 #define S3C2410_UFSTAT_TXMASK (15<<4)
122 #define S3C2410_UFSTAT_TXSHIFT (4)
123 #define S3C2410_UFSTAT_RXMASK (15<<0)
124 #define S3C2410_UFSTAT_RXSHIFT (0)
126 #define S3C2440_UFSTAT_TXFULL (1<<14)
127 #define S3C2440_UFSTAT_RXFULL (1<<6)
128 #define S3C2440_UFSTAT_TXSHIFT (8)
129 #define S3C2440_UFSTAT_RXSHIFT (0)
130 #define S3C2440_UFSTAT_TXMASK (63<<8)
131 #define S3C2440_UFSTAT_RXMASK (63)
133 #define S3C2410_UTRSTAT_TXE (1<<2)
134 #define S3C2410_UTRSTAT_TXFE (1<<1)
135 #define S3C2410_UTRSTAT_RXDR (1<<0)
137 #define S3C2410_UERSTAT_OVERRUN (1<<0)
138 #define S3C2410_UERSTAT_FRAME (1<<2)
139 #define S3C2410_UERSTAT_BREAK (1<<3)
140 #define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
141 S3C2410_UERSTAT_FRAME | \
142 S3C2410_UERSTAT_BREAK)
144 #define S3C2410_UMSTAT_CTS (1<<0)
145 #define S3C2410_UMSTAT_DeltaCTS (1<<2)
149 /* struct s3c24xx_uart_clksrc
151 * this structure defines a named clock source that can be used for the
152 * uart, so that the best clock can be selected for the requested baud
155 * min_baud and max_baud define the range of baud-rates this clock is
156 * acceptable for, if they are both zero, it is assumed any baud rate that
157 * can be generated from this clock will be used.
159 * divisor gives the divisor from the clock to the one seen by the uart
162 struct s3c24xx_uart_clksrc {
164 unsigned int divisor;
165 unsigned int min_baud;
166 unsigned int max_baud;
169 /* configuration structure for per-machine configurations for the
172 * the pointer is setup by the machine specific initialisation from the
173 * arch/arm/mach-s3c2410/ directory.
176 struct s3c2410_uartcfg {
177 unsigned char hwport; /* hardware port number */
178 unsigned char unused;
179 unsigned short flags;
180 unsigned long uart_flags; /* default uart flags */
182 unsigned long ucon; /* value of ucon for port */
183 unsigned long ulcon; /* value of ulcon for port */
184 unsigned long ufcon; /* value of ufcon for port */
186 struct s3c24xx_uart_clksrc *clocks;
187 unsigned int clocks_size;
192 * this is exported from the core as we cannot use driver_register(),
193 * or platform_add_device() before the console_initcall()
196 extern struct platform_device *s3c24xx_uart_devs[3];
198 #endif /* __ASSEMBLY__ */
200 #endif /* __ASM_ARM_REGS_SERIAL_H */