1 #ifndef _ARCH_ARM_MFTB2_h_
2 #define _ARCH_ARM_MFTB2_h_
4 // Defines for arch/arm/mm/mm-sa1100.h
5 #define TRIZEPS_PHYS_VIRT_MAP_SIZE 0x00800000l
7 // physical address (only for mm-sa1100.h)
8 #define TRIZEPS_PHYS_IO_BASE 0x30000000l
9 #define TRIZEPS_PHYS_MEM_BASE 0x38000000l
12 #define TRIZEPS_IO_BASE 0xF0000000l
13 #define TRIZEPS_MEM_BASE 0xF2000000l
15 // Offsets for phys and virtual
16 #define TRIZEPS_OFFSET_REG0 0x00300000l
17 #define TRIZEPS_OFFSET_REG1 0x00380000l
18 #define TRIZEPS_OFFSET_IDE_CS0 0x00000000l
19 #define TRIZEPS_OFFSET_IDE_CS1 0x00080000l
20 #define TRIZEPS_OFFSET_UART5 0x00100000l
21 #define TRIZEPS_OFFSET_UART6 0x00180000l
22 #define TRIZEPS_PHYS_REG0 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_REG0)
23 #define TRIZEPS_PHYS_REG1 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_REG1)
24 #define TRIZEPS_PHYS_IDE_CS0 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_IDE_CS0)
25 #define TRIZEPS_PHYS_IDE_CS1 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_IDE_CS1)
26 #define TRIZEPS_PHYS_UART5 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_UART5)
27 #define TRIZEPS_PHYS_UART6 (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_UART6)
29 // Use follow defines in devices
31 #define TRIZEPS_REG0 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_REG0)
32 #define TRIZEPS_REG1 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_REG1)
33 #define TRIZEPS_IDE_CS0 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_IDE_CS0)
34 #define TRIZEPS_IDE_CS1 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_IDE_CS1)
35 #define TRIZEPS_UART5 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_UART5)
36 #define TRIZEPS_UART6 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_UART6)
38 #define TRIZEPS_BAUD_BASE 1500000
40 //#if 0 //temporarily disabled
42 struct tri_uart_cts_data_t {
45 struct uart_info *info;
46 struct uart_port *port;
49 #endif /* __ASSEMBLY__ */
51 /* Defines for MFTB2 serial_sa1100.c hardware handshaking lines */
53 #define NOT_CONNECTED 0
55 #define TRIZEPS_GPIO_UART1_RTS GPIO_GPIO14
56 #define TRIZEPS_GPIO_UART1_DTR NOT_CONNECTED //GPIO_GPIO9
57 #define TRIZEPS_GPIO_UART1_CTS GPIO_GPIO15
58 #define TRIZEPS_GPIO_UART1_DCD NOT_CONNECTED //GPIO_GPIO2
59 #define TRIZEPS_GPIO_UART1_DSR NOT_CONNECTED //GPIO_GPIO3
60 #define TRIZEPS_GPIO_UART3_RTS NOT_CONNECTED //GPIO_GPIO7
61 #define TRIZEPS_GPIO_UART3_DTR NOT_CONNECTED //GPIO_GPIO8
62 #define TRIZEPS_GPIO_UART3_CTS NOT_CONNECTED //GPIO_GPIO4
63 #define TRIZEPS_GPIO_UART3_DCD NOT_CONNECTED //GPIO_GPIO5
64 #define TRIZEPS_GPIO_UART3_DSR NOT_CONNECTED //GPIO_GPIO6
66 #define TRIZEPS_GPIO_UART2_RTS NOT_CONNECTED //GPIO_GPIO7
67 #define TRIZEPS_GPIO_UART2_DTR NOT_CONNECTED //GPIO_GPIO8
68 #define TRIZEPS_GPIO_UART2_CTS NOT_CONNECTED //GPIO_GPIO4
69 #define TRIZEPS_GPIO_UART2_DCD NOT_CONNECTED //GPIO_GPIO5
70 #define TRIZEPS_GPIO_UART2_DSR NOT_CONNECTED //GPIO_GPIO6
72 #define TRIZEPS_IRQ_UART1_CTS IRQ_GPIO15
73 #define TRIZEPS_IRQ_UART1_DCD NO_IRQ //IRQ_GPIO2
74 #define TRIZEPS_IRQ_UART1_DSR NO_IRQ //IRQ_GPIO3
75 #define TRIZEPS_IRQ_UART3_CTS NO_IRQ //IRQ_GPIO4
76 #define TRIZEPS_IRQ_UART3_DCD NO_IRQ //IRQ_GPIO5
77 #define TRIZEPS_IRQ_UART3_DSR NO_IRQ //IRQ_GPIO6
79 #define TRIZEPS_IRQ_UART2_CTS NO_IRQ //IRQ_GPIO4
80 #define TRIZEPS_IRQ_UART2_DCD NO_IRQ //IRQ_GPIO5
81 #define TRIZEPS_IRQ_UART2_DSR NO_IRQ //IRQ_GPIO6
83 #endif /* SERIAL_FULL */
87 * This section contains the defines for the MFTB2 implementation
88 * of drivers/ide/hd.c. HD_IOBASE_0 and HD_IOBASE_1 have to be
89 * adjusted if hardware changes.
91 #define TRIZEPS_IRQ_IDE 10 /* MFTB2 specific */
94 #define TRIZEPS_GPIO_ROOT_NFS 0
95 #define TRIZEPS_GPIO_ROOT_HD 21
97 #define TRIZEPS_GPIO_PCMCIA_IRQ0 1
98 #define TRIZEPS_GPIO_PCMCIA_CD0 24
99 #define TRIZEPS_IRQ_PCMCIA_IRQ0 TRIZEPS_GPIO_PCMCIA_IRQ0
100 #define TRIZEPS_IRQ_PCMCIA_CD0 TRIZEPS_GPIO_PCMCIA_CD0 + 32 - 11
102 // REGISTER 0 -> 0x0XXXX (16bit access)
104 #define TRIZEPS_A_STAT 0x8000l
105 #define TRIZEPS_F_STAT 0x4000l
106 #define TRIZEPS_BATT_FAULT_EN 0x2000l
107 #define TRIZEPS_nDQ 0x1000l
108 #define TRIZEPS_MFT_OFF 0x0800l
109 #define TRIZEPS_D_APWOFF 0x0400l
110 #define TRIZEPS_F_CTRL 0x0200l
111 #define TRIZEPS_F_STOP 0x0100l
114 #define TRIZEPS_KP_IR_EN 0x0080l
115 #define TRIZEPS_FIR 0x0040l
116 #define TRIZEPS_BAR_ON 0x0020l
117 #define TRIZEPS_VCI_ON 0x0010l
118 #define TRIZEPS_LED4 0x0008l
119 #define TRIZEPS_LED3 0x0004l
120 #define TRIZEPS_LED2 0x0002l
121 #define TRIZEPS_LED1 0x0001l
123 // REGISTER 1 -> 0x1XXXX (16bit access)
125 #define TRIZEPS_nVCI2 0x8000l
126 #define TRIZEPS_nAB_LOW 0x4000l
127 #define TRIZEPS_nMB_DEAD 0x2000l
128 #define TRIZEPS_nMB_LOW 0x1000l
129 #define TRIZEPS_nPCM_VS2 0x0800l
130 #define TRIZEPS_nPCM_VS1 0x0400l
131 #define TRIZEPS_PCM_BVD2 0x0200l
132 #define TRIZEPS_PCM_BVD1 0x0100l
135 #define TRIZEPS_nROOT_NFS 0x0080l
136 #define TRIZEPS_nROOT_HD 0x0040l
137 #define TRIZEPS_nPCM_ENA_REG 0x0020l
138 #define TRIZEPS_nPCM_RESET_DISABLE 0x0010l
139 #define TRIZEPS_PCM_EN0_REG 0x0008l
140 #define TRIZEPS_PCM_EN1_REG 0x0004l
141 #define TRIZEPS_PCM_V3_EN_REG 0x0002l
142 #define TRIZEPS_PCM_V5_EN_REG 0x0001l
144 /* Access to Board Control Register */
145 #define TRIZEPS_BCR0 (*(volatile unsigned short *)(TRIZEPS_REG0))
146 #define TRIZEPS_BCR1 (*(volatile unsigned short *)(TRIZEPS_REG1))
148 #define TRIZEPS_BCR_set( reg, x ) do { \
149 unsigned long flags; \
150 local_irq_save(flags); \
152 local_irq_restore(flags); \
155 #define TRIZEPS_BCR_clear( reg, x ) do { \
156 unsigned long flags; \
157 local_irq_save(flags); \
159 local_irq_restore(flags); \
162 #define TRIZEPS_OFFSET_KP_REG 0x00200000l
163 #define TRIZEPS_OFFSET_VCI2 0x00280000l
164 #define TRIZEPS_OFFSET_VCI4 0x00400000l
166 #define TRIZEPS_OFFSET_VCI2_1_DPR (TRIZEPS_OFFSET_VCI2 + 0x00010000l)
167 #define TRIZEPS_OFFSET_VCI2_2_DPR (TRIZEPS_OFFSET_VCI2 + 0x00018000l)
168 #define TRIZEPS_OFFSET_VCI2_1_SEMA (TRIZEPS_OFFSET_VCI2 + 0x00020000l)
169 #define TRIZEPS_OFFSET_VCI2_2_SEMA (TRIZEPS_OFFSET_VCI2 + 0x00028000l)
171 #define TRIZEPS_OFFSET_VCI4_1_DPR (TRIZEPS_OFFSET_VCI4 + 0x00000000l)
172 #define TRIZEPS_OFFSET_VCI4_2_DPR (TRIZEPS_OFFSET_VCI4 + 0x00008000l)
173 #define TRIZEPS_OFFSET_VCI4_1_SEMA (TRIZEPS_OFFSET_VCI4 + 0x00000380l)
174 #define TRIZEPS_OFFSET_VCI4_2_SEMA (TRIZEPS_OFFSET_VCI4 + 0x00000388l)
175 #define TRIZEPS_OFFSET_VCI4_1_CNTR (TRIZEPS_OFFSET_VCI4 + 0x00000390l)
176 #define TRIZEPS_OFFSET_VCI4_2_CNTR (TRIZEPS_OFFSET_VCI4 + 0x00000392l)
178 #define TRIZEPS_PHYS_KP_REG (PHYS_TRIZEPS_IO_BASE + TRIZEPS_OFFSET_KP_REG)
181 #define TRIZEPS_PHYS_VCI2_1_DPR (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_DPR)
182 #define TRIZEPS_PHYS_VCI2_2_DPR (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_DPR)
183 #define TRIZEPS_PHYS_VCI2_1_SEMA (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_SEMA)
184 #define TRIZEPS_PHYS_VCI2_2_SEMA (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_SEMA)
187 #define TRIZEPS_PHYS_VCI4_1_DPR (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI4_1_DPR)
188 #define TRIZEPS_PHYS_VCI4_2_DPR (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI4_2_DPR)
189 #define TRIZEPS_PHYS_VCI4_1_SEMA (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_VCI4_1_SEMA)
190 #define TRIZEPS_PHYS_VCI4_2_SEMA (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_VCI4_2_SEMA)
191 #define TRIZEPS_PHYS_VCI4_1_CNTR (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_VCI4_1_CNTR)
192 #define TRIZEPS_PHYS_VCI4_2_CNTR (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_VCI4_2_CNTR)
194 #define TRIZEPS_KP_REG (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_KP_REG)
197 #define TRIZEPS_VCI2_1_DPR (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_DPR)
198 #define TRIZEPS_VCI2_2_DPR (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_DPR)
199 #define TRIZEPS_VCI2_1_SEMA (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_SEMA)
200 #define TRIZEPS_VCI2_2_SEMA (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_SEMA)
203 #define TRIZEPS_VCI4_1_DPR (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI4_1_DPR)
204 #define TRIZEPS_VCI4_2_DPR (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI4_2_DPR)
205 #define TRIZEPS_VCI4_1_SEMA (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_VCI4_1_SEMA)
206 #define TRIZEPS_VCI4_2_SEMA (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_VCI4_2_SEMA)
207 #define TRIZEPS_VCI4_1_CNTR (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_VCI4_1_CNTR)
208 #define TRIZEPS_VCI4_2_CNTR (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_VCI4_2_CNTR)