2 * linux/include/asm-arm/arch-versatile/platform.h
4 * Copyright (c) ARM Limited 2003. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #define VERSATILE_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
28 #define VERSATILE_BOOT_ROM_HI 0x30000000
29 #define VERSATILE_BOOT_ROM_BASE VERSATILE_BOOT_ROM_HI /* Normal position */
30 #define VERSATILE_BOOT_ROM_SIZE SZ_64M
32 #define VERSATILE_SSRAM_BASE /* VERSATILE_SSMC_BASE ? */
33 #define VERSATILE_SSRAM_SIZE SZ_2M
35 #define VERSATILE_FLASH_BASE 0x34000000
36 #define VERSATILE_FLASH_SIZE SZ_64M
41 #define VERSATILE_SDRAM_BASE 0x00000000
44 * Logic expansion modules
49 /* ------------------------------------------------------------------------
50 * Versatile PB Registers
51 * ------------------------------------------------------------------------
54 #define VERSATILE_SYS_ID_OFFSET 0x00
55 #define VERSATILE_SYS_SW_OFFSET 0x04
56 #define VERSATILE_SYS_LED_OFFSET 0x08
57 #define VERSATILE_SYS_OSC0_OFFSET 0x0C
58 #define VERSATILE_SYS_OSC1_OFFSET 0x10
59 #define VERSATILE_SYS_OSC2_OFFSET 0x14
60 #define VERSATILE_SYS_OSC3_OFFSET 0x18
61 #define VERSATILE_SYS_OSC4_OFFSET 0x1C
62 #define VERSATILE_SYS_LOCK_OFFSET 0x20
63 #define VERSATILE_SYS_100HZ_OFFSET 0x24
64 #define VERSATILE_SYS_CFGDATA1_OFFSET 0x28
65 #define VERSATILE_SYS_CFGDATA2_OFFSET 0x2C
66 #define VERSATILE_SYS_FLAGS_OFFSET 0x30
67 #define VERSATILE_SYS_FLAGSSET_OFFSET 0x30
68 #define VERSATILE_SYS_FLAGSCLR_OFFSET 0x34
69 #define VERSATILE_SYS_NVFLAGS_OFFSET 0x38
70 #define VERSATILE_SYS_NVFLAGSSET_OFFSET 0x38
71 #define VERSATILE_SYS_NVFLAGSCLR_OFFSET 0x3C
72 #define VERSATILE_SYS_RESETCTL_OFFSET 0x40
73 #define VERSATILE_SYS_PICCTL_OFFSET 0x44
74 #define VERSATILE_SYS_MCI_OFFSET 0x48
75 #define VERSATILE_SYS_FLASH_OFFSET 0x4C
76 #define VERSATILE_SYS_CLCD_OFFSET 0x50
77 #define VERSATILE_SYS_CLCDSER_OFFSET 0x54
78 #define VERSATILE_SYS_BOOTCS_OFFSET 0x58
79 #define VERSATILE_SYS_24MHz_OFFSET 0x5C
80 #define VERSATILE_SYS_MISC_OFFSET 0x60
81 #define VERSATILE_SYS_TEST_OSC0_OFFSET 0x80
82 #define VERSATILE_SYS_TEST_OSC1_OFFSET 0x84
83 #define VERSATILE_SYS_TEST_OSC2_OFFSET 0x88
84 #define VERSATILE_SYS_TEST_OSC3_OFFSET 0x8C
85 #define VERSATILE_SYS_TEST_OSC4_OFFSET 0x90
87 #define VERSATILE_SYS_BASE 0x10000000
88 #define VERSATILE_SYS_ID (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET)
89 #define VERSATILE_SYS_SW (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET)
90 #define VERSATILE_SYS_LED (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET)
91 #define VERSATILE_SYS_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET)
92 #define VERSATILE_SYS_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET)
93 #define VERSATILE_SYS_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET)
94 #define VERSATILE_SYS_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET)
95 #define VERSATILE_SYS_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET)
96 #define VERSATILE_SYS_LOCK (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET)
97 #define VERSATILE_SYS_100HZ (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET)
98 #define VERSATILE_SYS_CFGDATA1 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET)
99 #define VERSATILE_SYS_CFGDATA2 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET)
100 #define VERSATILE_SYS_FLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET)
101 #define VERSATILE_SYS_FLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET)
102 #define VERSATILE_SYS_FLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET)
103 #define VERSATILE_SYS_NVFLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET)
104 #define VERSATILE_SYS_NVFLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
105 #define VERSATILE_SYS_NVFLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
106 #define VERSATILE_SYS_RESETCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
107 #define VERSATILE_SYS_PICCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PICCTL_OFFSET)
108 #define VERSATILE_SYS_MCI (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
109 #define VERSATILE_SYS_FLASH (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
110 #define VERSATILE_SYS_CLCD (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
111 #define VERSATILE_SYS_CLCDSER (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET)
112 #define VERSATILE_SYS_BOOTCS (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET)
113 #define VERSATILE_SYS_24MHz (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET)
114 #define VERSATILE_SYS_MISC (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET)
115 #define VERSATILE_SYS_TEST_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET)
116 #define VERSATILE_SYS_TEST_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET)
117 #define VERSATILE_SYS_TEST_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET)
118 #define VERSATILE_SYS_TEST_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET)
119 #define VERSATILE_SYS_TEST_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET)
122 * Values for VERSATILE_SYS_RESET_CTRL
124 #define VERSATILE_SYS_CTRL_RESET_CONFIGCLR 0x01
125 #define VERSATILE_SYS_CTRL_RESET_CONFIGINIT 0x02
126 #define VERSATILE_SYS_CTRL_RESET_DLLRESET 0x03
127 #define VERSATILE_SYS_CTRL_RESET_PLLRESET 0x04
128 #define VERSATILE_SYS_CTRL_RESET_POR 0x05
129 #define VERSATILE_SYS_CTRL_RESET_DoC 0x06
131 #define VERSATILE_SYS_CTRL_LED (1 << 0)
134 /* ------------------------------------------------------------------------
135 * Versatile PB control registers
136 * ------------------------------------------------------------------------
142 * 31:24 = manufacturer (0x41 = ARM)
143 * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
144 * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
146 * 3:0 = revision number (0x1 = rev B (AHB))
151 * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
152 * SYS_CLD, SYS_BOOTCS
154 #define VERSATILE_SYS_LOCK_LOCKED (1 << 16)
155 #define VERSATILE_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
158 * VERSATILE_SYS_FLASH
160 #define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
164 * - used to acknowledge and control MMCI and UART interrupts
166 #define VERSATILE_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
167 #define VERSATILE_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
168 #define VERSATILE_INTREG_CARDIN 0x08 /* MMCI card in detect */
169 /* write 1 to acknowledge and clear */
170 #define VERSATILE_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
171 #define VERSATILE_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
174 * VERSATILE peripheral addresses
176 #define VERSATILE_PCI_CORE_BASE 0x10001000 /* PCI core control */
177 #define VERSATILE_I2C_BASE 0x10002000 /* I2C control */
178 #define VERSATILE_SIC_BASE 0x10003000 /* Secondary interrupt controller */
179 #define VERSATILE_AACI_BASE 0x10004000 /* Audio */
180 #define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
181 #define VERSATILE_KMI0_BASE 0x10006000 /* KMI interface */
182 #define VERSATILE_KMI1_BASE 0x10007000 /* KMI 2nd interface */
183 #define VERSATILE_CHAR_LCD_BASE 0x10008000 /* Character LCD */
184 #define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */
185 #define VERSATILE_SCI1_BASE 0x1000A000
186 #define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
187 /* 0x1000C000 - 0x1000CFFF = reserved */
188 #define VERSATILE_ETH_BASE 0x10010000 /* Ethernet */
189 #define VERSATILE_USB_BASE 0x10020000 /* USB */
190 /* 0x10030000 - 0x100FFFFF = reserved */
191 #define VERSATILE_SMC_BASE 0x10100000 /* SMC */
192 #define VERSATILE_MPMC_BASE 0x10110000 /* MPMC */
193 #define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */
194 #define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */
195 #define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */
196 #define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */
197 /* 0x10000000 - 0x100FFFFF */
198 #define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */
199 #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
200 #define VERSATILE_WATCHDOG_BASE 0x101E1000 /* Watchdog */
201 #define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */
202 #define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */
203 #define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */
204 #define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */
205 #define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */
206 #define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */
207 #define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */
208 /* 0x101E9000 - reserved */
209 #define VERSATILE_SCI_BASE 0x101F0000 /* Smart card controller */
210 #define VERSATILE_UART0_BASE 0x101F1000 /* Uart 0 */
211 #define VERSATILE_UART1_BASE 0x101F2000 /* Uart 1 */
212 #define VERSATILE_UART2_BASE 0x101F3000 /* Uart 2 */
213 #define VERSATILE_SSP_BASE 0x101F4000 /* Synchronous Serial Port */
215 #define VERSATILE_SSMC_BASE 0x20000000 /* SSMC */
216 #define VERSATILE_MBX_BASE 0x40000000 /* MBX */
217 #define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */
218 #define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
219 #define VERSATILE_LT_BASE 0x80000000 /* Logic Tile expansion */
224 #define VERSATILE_DOC_BASE 0x2C000000
225 #define VERSATILE_DOC_SIZE (16 << 20)
226 #define VERSATILE_DOC_PAGE_SIZE 512
227 #define VERSATILE_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
229 #define ERASE_UNIT_PAGES 32
230 #define START_PAGE 0x80
233 * LED settings, bits [7:0]
235 #define VERSATILE_SYS_LED0 (1 << 0)
236 #define VERSATILE_SYS_LED1 (1 << 1)
237 #define VERSATILE_SYS_LED2 (1 << 2)
238 #define VERSATILE_SYS_LED3 (1 << 3)
239 #define VERSATILE_SYS_LED4 (1 << 4)
240 #define VERSATILE_SYS_LED5 (1 << 5)
241 #define VERSATILE_SYS_LED6 (1 << 6)
242 #define VERSATILE_SYS_LED7 (1 << 7)
244 #define ALL_LEDS 0xFF
246 #define LED_BANK VERSATILE_SYS_LED
251 #define VERSATILE_IDFIELD_OFFSET 0x0 /* Versatile build information */
252 #define VERSATILE_FLASHPROG_OFFSET 0x4 /* Flash devices */
253 #define VERSATILE_INTREG_OFFSET 0x8 /* Interrupt control */
254 #define VERSATILE_DECODE_OFFSET 0xC /* Fitted logic modules */
257 /* ------------------------------------------------------------------------
258 * Versatile PB Interrupt Controller - control registers
259 * ------------------------------------------------------------------------
261 * Offsets from interrupt controller base
263 * System Controller interrupt controller base is
267 * Core Module interrupt controller base is
272 #define VIC_IRQ_STATUS 0
273 #define VIC_FIQ_STATUS 0x04
274 #define VIC_IRQ_RAW_STATUS 0x08
275 #define VIC_INT_SELECT 0x0C /* 1 = FIQ, 0 = IRQ */
276 #define VIC_IRQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
277 #define VIC_IRQ_ENABLE_CLEAR 0x14
278 #define VIC_IRQ_SOFT 0x18
279 #define VIC_IRQ_SOFT_CLEAR 0x1C
280 #define VIC_PROTECT 0x20
281 #define VIC_VECT_ADDR 0x30
282 #define VIC_DEF_VECT_ADDR 0x34
283 #define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
284 #define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
285 #define VIC_ITCR 0x300 /* VIC test control register */
287 #define VIC_FIQ_RAW_STATUS 0x08
288 #define VIC_FIQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
289 #define VIC_FIQ_ENABLE_CLEAR 0x14
290 #define VIC_FIQ_SOFT 0x18
291 #define VIC_FIQ_SOFT_CLEAR 0x1C
293 #define SIC_IRQ_STATUS 0
294 #define SIC_IRQ_RAW_STATUS 0x04
295 #define SIC_IRQ_ENABLE 0x08
296 #define SIC_IRQ_ENABLE_SET 0x08
297 #define SIC_IRQ_ENABLE_CLEAR 0x0C
298 #define SIC_INT_SOFT_SET 0x10
299 #define SIC_INT_SOFT_CLEAR 0x14
300 #define SIC_INT_PIC_ENABLE 0x20 /* read status of pass through mask */
301 #define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */
302 #define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */
304 #define VICVectCntl_Enable (1 << 5)
306 /* ------------------------------------------------------------------------
307 * Interrupts - bit assignment (primary)
308 * ------------------------------------------------------------------------
311 #define INT_WDOGINT 0 /* Watchdog timer */
312 #define INT_SOFTINT 1 /* Software interrupt */
313 #define INT_COMMRx 2 /* Debug Comm Rx interrupt */
314 #define INT_COMMTx 3 /* Debug Comm Tx interrupt */
315 #define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
316 #define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
317 #define INT_GPIOINT0 6 /* GPIO 0 */
318 #define INT_GPIOINT1 7 /* GPIO 1 */
319 #define INT_GPIOINT2 8 /* GPIO 2 */
320 #define INT_GPIOINT3 9 /* GPIO 3 */
321 #define INT_RTCINT 10 /* Real Time Clock */
322 #define INT_SSPINT 11 /* Synchronous Serial Port */
323 #define INT_UARTINT0 12 /* UART 0 on development chip */
324 #define INT_UARTINT1 13 /* UART 1 on development chip */
325 #define INT_UARTINT2 14 /* UART 2 on development chip */
326 #define INT_SCIINT 15 /* Smart Card Interface */
327 #define INT_CLCDINT 16 /* CLCD controller */
328 #define INT_DMAINT 17 /* DMA controller */
329 #define INT_PWRFAILINT 18 /* Power failure */
330 #define INT_MBXINT 19 /* Graphics processor */
331 #define INT_GNDINT 20 /* Reserved */
332 /* External interrupt signals from logic tiles or secondary controller */
333 #define INT_VICSOURCE21 21 /* Disk on Chip */
334 #define INT_VICSOURCE22 22 /* MCI0A */
335 #define INT_VICSOURCE23 23 /* MCI1A */
336 #define INT_VICSOURCE24 24 /* AACI */
337 #define INT_VICSOURCE25 25 /* Ethernet */
338 #define INT_VICSOURCE26 26 /* USB */
339 #define INT_VICSOURCE27 27 /* PCI 0 */
340 #define INT_VICSOURCE28 28 /* PCI 1 */
341 #define INT_VICSOURCE29 29 /* PCI 2 */
342 #define INT_VICSOURCE30 30 /* PCI 3 */
343 #define INT_VICSOURCE31 31 /* SIC source */
346 * Interrupt bit positions
349 #define INTMASK_WDOGINT (1 << INT_WDOGINT)
350 #define INTMASK_SOFTINT (1 << INT_SOFTINT)
351 #define INTMASK_COMMRx (1 << INT_COMMRx)
352 #define INTMASK_COMMTx (1 << INT_COMMTx)
353 #define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
354 #define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
355 #define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
356 #define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
357 #define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
358 #define INTMASK_GPIOINT3 (1 << INT_GPIOINT3)
359 #define INTMASK_RTCINT (1 << INT_RTCINT)
360 #define INTMASK_SSPINT (1 << INT_SSPINT)
361 #define INTMASK_UARTINT0 (1 << INT_UARTINT0)
362 #define INTMASK_UARTINT1 (1 << INT_UARTINT1)
363 #define INTMASK_UARTINT2 (1 << INT_UARTINT2)
364 #define INTMASK_SCIINT (1 << INT_SCIINT)
365 #define INTMASK_CLCDINT (1 << INT_CLCDINT)
366 #define INTMASK_DMAINT (1 << INT_DMAINT)
367 #define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
368 #define INTMASK_MBXINT (1 << INT_MBXINT)
369 #define INTMASK_GNDINT (1 << INT_GNDINT)
370 #define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21)
371 #define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22)
372 #define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23)
373 #define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24)
374 #define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25)
375 #define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26)
376 #define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27)
377 #define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28)
378 #define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29)
379 #define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30)
380 #define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31)
383 #define VERSATILE_SC_VALID_INT 0x003FFFFF
389 /* ------------------------------------------------------------------------
390 * Interrupts - bit assignment (secondary)
391 * ------------------------------------------------------------------------
393 #define SIC_INT_MMCI0B 1 /* Multimedia Card 0B */
394 #define SIC_INT_MMCI1B 2 /* Multimedia Card 1B */
395 #define SIC_INT_KMI0 3 /* Keyboard/Mouse port 0 */
396 #define SIC_INT_KMI1 4 /* Keyboard/Mouse port 1 */
397 #define SIC_INT_SCI3 5 /* Smart Card interface */
398 #define SIC_INT_UART3 6 /* UART 3 empty or data available */
399 #define SIC_INT_CLCD 7 /* Character LCD */
400 #define SIC_INT_TOUCH 8 /* Touchscreen */
401 #define SIC_INT_KEYPAD 9 /* Key pressed on display keypad */
402 /* 10:20 - reserved */
403 #define SIC_INT_DoC 21 /* Disk on Chip memory controller */
404 #define SIC_INT_MMCI0A 22 /* MMC 0A */
405 #define SIC_INT_MMCI1A 23 /* MMC 1A */
406 #define SIC_INT_AACI 24 /* Audio Codec */
407 #define SIC_INT_ETH 25 /* Ethernet controller */
408 #define SIC_INT_USB 26 /* USB controller */
409 #define SIC_INT_PCI0 27
410 #define SIC_INT_PCI1 28
411 #define SIC_INT_PCI2 29
412 #define SIC_INT_PCI3 30
415 #define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B)
416 #define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B)
417 #define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0)
418 #define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1)
419 #define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3)
420 #define SIC_INTMASK_UART3 (1 << SIC_INT_UART3)
421 #define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD)
422 #define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH)
423 #define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD)
424 #define SIC_INTMASK_DoC (1 << SIC_INT_DoC)
425 #define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A)
426 #define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A)
427 #define SIC_INTMASK_AACI (1 << SIC_INT_AACI)
428 #define SIC_INTMASK_ETH (1 << SIC_INT_ETH)
429 #define SIC_INTMASK_USB (1 << SIC_INT_USB)
430 #define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0)
431 #define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1)
432 #define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2)
433 #define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3)
438 #define FLASH_BASE VERSATILE_FLASH_BASE
439 #define FLASH_SIZE VERSATILE_FLASH_SIZE
440 #define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
441 #define FLASH_BLOCK_SIZE SZ_128K
447 #define EPROM_BASE VERSATILE_BOOT_ROM_HI
448 #define EPROM_SIZE VERSATILE_BOOT_ROM_SIZE
449 #define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
455 #define CLEAN_BASE EPROM_BASE
458 * System controller bit assignment
460 #define VERSATILE_REFCLK 0
461 #define VERSATILE_TIMCLK 1
463 #define VERSATILE_TIMER1_EnSel 15
464 #define VERSATILE_TIMER2_EnSel 17
465 #define VERSATILE_TIMER3_EnSel 19
466 #define VERSATILE_TIMER4_EnSel 21
470 #define MAX_PERIOD 699050
471 #define TICKS_PER_uSEC 1
474 * These are useconds NOT ticks.
478 #define mSEC_5 (mSEC_1 * 5)
479 #define mSEC_10 (mSEC_1 * 10)
480 #define mSEC_25 (mSEC_1 * 25)
481 #define SEC_1 (mSEC_1 * 1000)
483 #define VERSATILE_CSR_BASE 0x10000000
484 #define VERSATILE_CSR_SIZE 0x10000000