2 * linux/include/asm-arm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __ASM_ARM_ATOMIC_H
12 #define __ASM_ARM_ATOMIC_H
14 #include <linux/config.h>
16 typedef struct { volatile int counter; } atomic_t;
18 #define ATOMIC_INIT(i) { (i) }
22 #define atomic_read(v) ((v)->counter)
24 #if __LINUX_ARM_ARCH__ >= 6
27 * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
28 * store exclusive to ensure that these are atomic. We may loop
29 * to ensure that the update happens. Writing to 'v->counter'
30 * without using the following operations WILL break the atomic
31 * nature of these ops.
33 static inline void atomic_set(atomic_t *v, int i)
37 __asm__ __volatile__("@ atomic_set\n"
39 " strex %0, %2, [%1]\n"
43 : "r" (&v->counter), "r" (i)
47 static inline void atomic_add(int i, atomic_t *v)
49 unsigned long tmp, tmp2;
51 __asm__ __volatile__("@ atomic_add\n"
54 " strex %1, %0, [%2]\n"
57 : "=&r" (tmp), "=&r" (tmp2)
58 : "r" (&v->counter), "Ir" (i)
62 static inline int atomic_add_return(int i, atomic_t *v)
67 __asm__ __volatile__("@ atomic_add_return\n"
70 " strex %1, %0, [%2]\n"
73 : "=&r" (result), "=&r" (tmp)
74 : "r" (&v->counter), "Ir" (i)
80 static inline void atomic_sub(int i, atomic_t *v)
82 unsigned long tmp, tmp2;
84 __asm__ __volatile__("@ atomic_sub\n"
87 " strex %1, %0, [%2]\n"
90 : "=&r" (tmp), "=&r" (tmp2)
91 : "r" (&v->counter), "Ir" (i)
95 static inline int atomic_sub_return(int i, atomic_t *v)
100 __asm__ __volatile__("@ atomic_sub_return\n"
101 "1: ldrex %0, [%2]\n"
103 " strex %1, %0, [%2]\n"
106 : "=&r" (result), "=&r" (tmp)
107 : "r" (&v->counter), "Ir" (i)
113 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
115 unsigned long tmp, tmp2;
117 __asm__ __volatile__("@ atomic_clear_mask\n"
120 " strex %1, %0, %2\n"
123 : "=&r" (tmp), "=&r" (tmp2)
124 : "r" (addr), "Ir" (mask)
128 #else /* ARM_ARCH_6 */
130 #include <asm/system.h>
133 #error SMP not supported on pre-ARMv6 CPUs
136 #define atomic_set(v,i) (((v)->counter) = (i))
138 static inline void atomic_add(int i, atomic_t *v)
142 local_irq_save(flags);
144 local_irq_restore(flags);
147 static inline int atomic_add_return(int i, atomic_t *v)
152 local_irq_save(flags);
154 v->counter = val += i;
155 local_irq_restore(flags);
160 static inline void atomic_sub(int i, atomic_t *v)
164 local_irq_save(flags);
166 local_irq_restore(flags);
169 static inline int atomic_sub_return(int i, atomic_t *v)
174 local_irq_save(flags);
176 v->counter = val -= i;
177 local_irq_restore(flags);
182 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
186 local_irq_save(flags);
188 local_irq_restore(flags);
191 #endif /* __LINUX_ARM_ARCH__ */
193 #define atomic_inc(v) atomic_add(1, v)
194 #define atomic_dec(v) atomic_sub(1, v)
196 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
197 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
199 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
201 /* Atomic operations are already serializing on ARM */
202 #define smp_mb__before_atomic_dec() barrier()
203 #define smp_mb__after_atomic_dec() barrier()
204 #define smp_mb__before_atomic_inc() barrier()
205 #define smp_mb__after_atomic_inc() barrier()