2 * linux/include/asm-arm/cacheflush.h
4 * Copyright (C) 1999-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef _ASMARM_CACHEFLUSH_H
11 #define _ASMARM_CACHEFLUSH_H
13 #include <linux/config.h>
14 #include <linux/sched.h>
27 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
29 # define MULTI_CACHE 1
35 #if defined(CONFIG_CPU_ARM720T)
37 # define MULTI_CACHE 1
43 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
44 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
45 # define MULTI_CACHE 1
48 #if defined(CONFIG_CPU_ARM926T)
50 # define MULTI_CACHE 1
52 # define _CACHE arm926
56 #if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
58 # define MULTI_CACHE 1
64 #if defined(CONFIG_CPU_XSCALE)
66 # define MULTI_CACHE 1
68 # define _CACHE xscale
72 #if defined(CONFIG_CPU_V6)
74 # define MULTI_CACHE 1
80 #if !defined(_CACHE) && !defined(MULTI_CACHE)
81 #error Unknown cache maintainence model
85 * This flag is used to indicate that the page pointed to by a pte
86 * is dirty and requires cleaning before returning it to the user.
88 #define PG_dcache_dirty PG_arch_1
94 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
95 * implement these methods.
97 * Start addresses are inclusive and end addresses are exclusive;
98 * start addresses should be rounded down, end addresses up.
100 * See linux/Documentation/cachetlb.txt for more information.
101 * Please note that the implementation of these, and the required
102 * effects are cache-type (VIVT/VIPT/PIPT) specific.
104 * flush_cache_kern_all()
106 * Unconditionally clean and invalidate the entire cache.
108 * flush_cache_user_mm(mm)
110 * Clean and invalidate all user space cache entries
111 * before a change of page tables.
113 * flush_cache_user_range(start, end, flags)
115 * Clean and invalidate a range of cache entries in the
116 * specified address space before a change of page tables.
117 * - start - user start address (inclusive, page aligned)
118 * - end - user end address (exclusive, page aligned)
119 * - flags - vma->vm_flags field
121 * coherent_kern_range(start, end)
123 * Ensure coherency between the Icache and the Dcache in the
124 * region described by start, end. If you have non-snooping
125 * Harvard caches, you need to implement this function.
126 * - start - virtual start address
127 * - end - virtual end address
129 * DMA Cache Coherency
130 * ===================
132 * dma_inv_range(start, end)
134 * Invalidate (discard) the specified virtual address range.
135 * May not write back any entries. If 'start' or 'end'
136 * are not cache line aligned, those lines must be written
138 * - start - virtual start address
139 * - end - virtual end address
141 * dma_clean_range(start, end)
143 * Clean (write back) the specified virtual address range.
144 * - start - virtual start address
145 * - end - virtual end address
147 * dma_flush_range(start, end)
149 * Clean and invalidate the specified virtual address range.
150 * - start - virtual start address
151 * - end - virtual end address
154 struct cpu_cache_fns {
155 void (*flush_kern_all)(void);
156 void (*flush_user_all)(void);
157 void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
159 void (*coherent_kern_range)(unsigned long, unsigned long);
160 void (*flush_kern_dcache_page)(void *);
162 void (*dma_inv_range)(unsigned long, unsigned long);
163 void (*dma_clean_range)(unsigned long, unsigned long);
164 void (*dma_flush_range)(unsigned long, unsigned long);
168 * Select the calling method
172 extern struct cpu_cache_fns cpu_cache;
174 #define __cpuc_flush_kern_all cpu_cache.flush_kern_all
175 #define __cpuc_flush_user_all cpu_cache.flush_user_all
176 #define __cpuc_flush_user_range cpu_cache.flush_user_range
177 #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
178 #define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page
181 * These are private to the dma-mapping API. Do not use directly.
182 * Their sole purpose is to ensure that data held in the cache
183 * is visible to DMA, or data written by DMA to system memory is
184 * visible to the CPU.
186 #define dmac_inv_range cpu_cache.dma_inv_range
187 #define dmac_clean_range cpu_cache.dma_clean_range
188 #define dmac_flush_range cpu_cache.dma_flush_range
192 #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
193 #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
194 #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
195 #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
196 #define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page)
198 extern void __cpuc_flush_kern_all(void);
199 extern void __cpuc_flush_user_all(void);
200 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
201 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
202 extern void __cpuc_flush_dcache_page(void *);
205 * These are private to the dma-mapping API. Do not use directly.
206 * Their sole purpose is to ensure that data held in the cache
207 * is visible to DMA, or data written by DMA to system memory is
208 * visible to the CPU.
210 #define dmac_inv_range __glue(_CACHE,_dma_inv_range)
211 #define dmac_clean_range __glue(_CACHE,_dma_clean_range)
212 #define dmac_flush_range __glue(_CACHE,_dma_flush_range)
214 extern void dmac_inv_range(unsigned long, unsigned long);
215 extern void dmac_clean_range(unsigned long, unsigned long);
216 extern void dmac_flush_range(unsigned long, unsigned long);
221 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
222 * vmalloc, ioremap etc) in kernel space for pages. Since the
223 * direct-mappings of these pages may contain cached data, we need
224 * to do a full cache flush to ensure that writebacks don't corrupt
225 * data placed into these pages via the new mappings.
227 #define flush_cache_vmap(start, end) flush_cache_all()
228 #define flush_cache_vunmap(start, end) flush_cache_all()
231 * Copy user data from/to a page which is mapped into a different
232 * processes address space. Really, we want to allow our "user
233 * space" model to handle this.
235 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
236 do { memcpy(dst, src, len); \
237 flush_icache_user_range(vma, page, vaddr, len); \
239 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
240 memcpy(dst, src, len)
243 * Convert calls to our calling convention.
245 #define flush_cache_all() __cpuc_flush_kern_all()
247 static inline void flush_cache_mm(struct mm_struct *mm)
249 if (current->active_mm == mm)
250 __cpuc_flush_user_all();
254 flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
256 if (current->active_mm == vma->vm_mm)
257 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
262 flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr)
264 if (current->active_mm == vma->vm_mm) {
265 unsigned long addr = user_addr & PAGE_MASK;
266 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
271 * Perform necessary cache operations to ensure that data previously
272 * stored within this range of addresses can be executed by the CPU.
274 #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
277 * Perform necessary cache operations to ensure that the TLB will
278 * see data written in the specified area.
280 #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
283 * flush_dcache_page is used when the kernel has written to the page
284 * cache page at virtual address page->virtual.
286 * If this page isn't mapped (ie, page_mapping == NULL), or it might
287 * have userspace mappings, then we _must_ always clean + invalidate
288 * the dcache entries associated with the kernel mapping.
290 * Otherwise we can defer the operation, and clean the cache when we are
291 * about to change to user space. This is the same method as used on SPARC64.
292 * See update_mmu_cache for the user space part.
294 extern void flush_dcache_page(struct page *);
296 #define flush_dcache_mmap_lock(mapping) \
297 spin_lock_irq(&(mapping)->tree_lock)
298 #define flush_dcache_mmap_unlock(mapping) \
299 spin_unlock_irq(&(mapping)->tree_lock)
301 #define flush_icache_user_range(vma,page,addr,len) \
302 flush_dcache_page(page)
305 * We don't appear to need to do anything here. In fact, if we did, we'd
306 * duplicate cache flushing elsewhere performed by flush_dcache_page().
308 #define flush_icache_page(vma,page) do { } while (0)