1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
6 #include <linux/config.h>
8 #define CPU_ARCH_UNKNOWN 0
9 #define CPU_ARCH_ARMv3 1
10 #define CPU_ARCH_ARMv4 2
11 #define CPU_ARCH_ARMv4T 3
12 #define CPU_ARCH_ARMv5 4
13 #define CPU_ARCH_ARMv5T 5
14 #define CPU_ARCH_ARMv5TE 6
15 #define CPU_ARCH_ARMv5TEJ 7
16 #define CPU_ARCH_ARMv6 8
19 * CR1 bits (CP#15 CR1)
21 #define CR_M (1 << 0) /* MMU enable */
22 #define CR_A (1 << 1) /* Alignment abort enable */
23 #define CR_C (1 << 2) /* Dcache enable */
24 #define CR_W (1 << 3) /* Write buffer enable */
25 #define CR_P (1 << 4) /* 32-bit exception handler */
26 #define CR_D (1 << 5) /* 32-bit data address range */
27 #define CR_L (1 << 6) /* Implementation defined */
28 #define CR_B (1 << 7) /* Big endian */
29 #define CR_S (1 << 8) /* System MMU protection */
30 #define CR_R (1 << 9) /* ROM MMU protection */
31 #define CR_F (1 << 10) /* Implementation defined */
32 #define CR_Z (1 << 11) /* Implementation defined */
33 #define CR_I (1 << 12) /* Icache enable */
34 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
35 #define CR_RR (1 << 14) /* Round Robin cache replacement */
36 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
37 #define CR_DT (1 << 16)
38 #define CR_IT (1 << 18)
39 #define CR_ST (1 << 19)
40 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
41 #define CR_U (1 << 22) /* Unaligned access operation */
42 #define CR_XP (1 << 23) /* Extended page tables */
43 #define CR_VE (1 << 24) /* Vectored interrupts */
46 #define CPUID_CACHETYPE 1
48 #define CPUID_TLBTYPE 3
50 #define read_cpuid(reg) \
53 asm("mrc%? p15, 0, %0, c0, c0, " __stringify(reg) \
59 * This is used to ensure the compiler did actually allocate the register we
60 * asked it for some inline assembly sequences. Apparently we can't trust
61 * the compiler from one version to another so a bit of paranoia won't hurt.
62 * This string is meant to be concatenated with the inline asm string and
63 * will cause compilation to stop on mismatch.
65 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
69 #include <linux/kernel.h>
73 /* information about the system we're running on */
74 extern unsigned int system_rev;
75 extern unsigned int system_serial_low;
76 extern unsigned int system_serial_high;
77 extern unsigned int mem_fclk_21285;
81 void die(const char *msg, struct pt_regs *regs, int err)
82 __attribute__((noreturn));
84 void die_if_kernel(const char *str, struct pt_regs *regs, int err);
86 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
88 int sig, const char *name);
90 #include <asm/proc-fns.h>
93 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
95 #define tas(ptr) (xchg((ptr),1))
97 extern asmlinkage void __backtrace(void);
99 extern int cpu_architecture(void);
102 __asm__ __volatile__( \
103 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \
108 unsigned int __val; \
109 __asm__ __volatile__( \
110 "mrc p15, 0, %0, c1, c0, 0 @ get CR" \
111 : "=r" (__val) : : "cc"); \
115 extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
116 extern unsigned long cr_alignment; /* defined in entry-armv.S */
118 #define UDBG_UNDEFINED (1 << 0)
119 #define UDBG_SYSCALL (1 << 1)
120 #define UDBG_BADABORT (1 << 2)
121 #define UDBG_SEGV (1 << 3)
122 #define UDBG_BUS (1 << 4)
124 extern unsigned int user_debug;
126 #if __LINUX_ARM_ARCH__ >= 4
127 #define vectors_base() ((cr_alignment & CR_V) ? 0xffff0000 : 0)
129 #define vectors_base() (0)
132 #define mb() __asm__ __volatile__ ("" : : : "memory")
135 #define read_barrier_depends() do { } while(0)
136 #define set_mb(var, value) do { var = value; mb(); } while (0)
137 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
138 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
140 #define prepare_to_switch() do { } while(0)
143 * switch_to(prev, next) should switch from task `prev' to `next'
144 * `prev' will never be the same as `next'.
145 * The `mb' is to tell GCC not to cache `current' across this call.
149 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
151 #define switch_to(prev,next,last) \
153 last = __switch_to(prev,prev->thread_info,next->thread_info); \
158 * CPU interrupt mask handling.
160 #if __LINUX_ARM_ARCH__ >= 6
162 #define local_irq_save(x) \
164 __asm__ __volatile__( \
165 "mrs %0, cpsr @ local_irq_save\n" \
167 : "=r" (x) : : "memory", "cc"); \
170 #define local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc")
171 #define local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc")
172 #define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc")
173 #define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc")
178 * Save the current interrupt enable state & disable IRQs
180 #define local_irq_save(x) \
182 unsigned long temp; \
183 (void) (&temp == &x); \
184 __asm__ __volatile__( \
185 "mrs %0, cpsr @ local_irq_save\n" \
186 " orr %1, %0, #128\n" \
188 : "=r" (x), "=r" (temp) \
196 #define local_irq_enable() \
198 unsigned long temp; \
199 __asm__ __volatile__( \
200 "mrs %0, cpsr @ local_irq_enable\n" \
201 " bic %0, %0, #128\n" \
211 #define local_irq_disable() \
213 unsigned long temp; \
214 __asm__ __volatile__( \
215 "mrs %0, cpsr @ local_irq_disable\n" \
216 " orr %0, %0, #128\n" \
228 unsigned long temp; \
229 __asm__ __volatile__( \
230 "mrs %0, cpsr @ stf\n" \
231 " bic %0, %0, #64\n" \
243 unsigned long temp; \
244 __asm__ __volatile__( \
245 "mrs %0, cpsr @ clf\n" \
246 " orr %0, %0, #64\n" \
256 * Save the current interrupt enable state.
258 #define local_save_flags(x) \
260 __asm__ __volatile__( \
261 "mrs %0, cpsr @ local_save_flags" \
262 : "=r" (x) : : "memory", "cc"); \
266 * restore saved IRQ & FIQ state
268 #define local_irq_restore(x) \
269 __asm__ __volatile__( \
270 "msr cpsr_c, %0 @ local_irq_restore\n" \
276 #error SMP not supported
278 #define smp_mb() mb()
279 #define smp_rmb() rmb()
280 #define smp_wmb() wmb()
281 #define smp_read_barrier_depends() read_barrier_depends()
285 #define smp_mb() barrier()
286 #define smp_rmb() barrier()
287 #define smp_wmb() barrier()
288 #define smp_read_barrier_depends() do { } while(0)
290 #define clf() __clf()
291 #define stf() __stf()
293 #define irqs_disabled() \
295 unsigned long flags; \
296 local_save_flags(flags); \
300 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
302 * On the StrongARM, "swp" is terminally broken since it bypasses the
303 * cache totally. This means that the cache becomes inconsistent, and,
304 * since we use normal loads/stores as well, this is really bad.
305 * Typically, this causes oopsen in filp_close, but could have other,
306 * more disasterous effects. There are two work-arounds:
307 * 1. Disable interrupts and emulate the atomic swap
308 * 2. Clean the cache, perform atomic swap, flush the cache
310 * We choose (1) since its the "easiest" to achieve here and is not
311 * dependent on the processor type.
316 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
318 extern void __bad_xchg(volatile void *, int);
327 local_irq_save(flags);
328 ret = *(volatile unsigned char *)ptr;
329 *(volatile unsigned char *)ptr = x;
330 local_irq_restore(flags);
334 local_irq_save(flags);
335 ret = *(volatile unsigned long *)ptr;
336 *(volatile unsigned long *)ptr = x;
337 local_irq_restore(flags);
340 case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]"
345 case 4: __asm__ __volatile__ ("swp %0, %1, [%2]"
351 default: __bad_xchg(ptr, size), ret = 0;
357 #endif /* CONFIG_SMP */
359 #endif /* __ASSEMBLY__ */
361 #endif /* __KERNEL__ */