2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/threads.h>
21 #include <asm/percpu.h>
22 #include <linux/cpumask.h>
23 #include <xen/interface/physdev.h>
25 /* flag for disabling the tsc */
26 extern int tsc_disable;
32 #define desc_empty(desc) \
33 (!((desc)->a | (desc)->b))
35 #define desc_equal(desc1, desc2) \
36 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
38 * Default implementation of macro that returns current
39 * instruction pointer ("program counter").
41 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
44 * CPU type and hardware bug flags. Kept separately for each CPU.
45 * Members of this structure are referenced in head.S, so think twice
46 * before touching them. [mj]
50 __u8 x86; /* CPU family */
51 __u8 x86_vendor; /* CPU vendor */
54 char wp_works_ok; /* It doesn't on 386's */
55 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
58 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
59 unsigned long x86_capability[NCAPINTS];
60 char x86_vendor_id[16];
61 char x86_model_id[64];
62 int x86_cache_size; /* in KB - valid for CPUS which support this
64 int x86_cache_alignment; /* In bytes */
70 unsigned long loops_per_jiffy;
72 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
74 unsigned char x86_max_cores; /* cpuid returned max cores value */
77 unsigned char booted_cores; /* number of cores as seen by OS */
78 __u8 phys_proc_id; /* Physical processor id. */
79 __u8 cpu_core_id; /* Core id */
81 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
83 #define X86_VENDOR_INTEL 0
84 #define X86_VENDOR_CYRIX 1
85 #define X86_VENDOR_AMD 2
86 #define X86_VENDOR_UMC 3
87 #define X86_VENDOR_NEXGEN 4
88 #define X86_VENDOR_CENTAUR 5
89 #define X86_VENDOR_RISE 6
90 #define X86_VENDOR_TRANSMETA 7
91 #define X86_VENDOR_NSC 8
92 #define X86_VENDOR_NUM 9
93 #define X86_VENDOR_UNKNOWN 0xff
96 * capabilities of CPUs
99 extern struct cpuinfo_x86 boot_cpu_data;
100 extern struct cpuinfo_x86 new_cpu_data;
101 #ifndef CONFIG_X86_NO_TSS
102 extern struct tss_struct doublefault_tss;
103 DECLARE_PER_CPU(struct tss_struct, init_tss);
107 extern struct cpuinfo_x86 cpu_data[];
108 #define current_cpu_data cpu_data[smp_processor_id()]
110 #define cpu_data (&boot_cpu_data)
111 #define current_cpu_data boot_cpu_data
114 extern int cpu_llc_id[NR_CPUS];
115 extern char ignore_fpu_irq;
117 extern void identify_cpu(struct cpuinfo_x86 *);
118 extern void print_cpu_info(struct cpuinfo_x86 *);
119 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
120 extern unsigned short num_cache_leaves;
123 extern void detect_ht(struct cpuinfo_x86 *c);
125 static inline void detect_ht(struct cpuinfo_x86 *c) {}
131 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
132 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
133 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
134 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
135 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
136 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
137 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
138 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
139 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
140 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
141 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
142 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
143 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
144 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
145 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
146 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
147 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
150 * Generic CPUID function
151 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
152 * resulting in stale register contents being returned.
154 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
164 /* Some CPUID calls want 'count' to be placed in ecx */
165 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
173 : "0" (op), "c" (count));
177 * CPUID functions returning a single datum
179 static inline unsigned int cpuid_eax(unsigned int op)
189 static inline unsigned int cpuid_ebx(unsigned int op)
191 unsigned int eax, ebx;
194 : "=a" (eax), "=b" (ebx)
199 static inline unsigned int cpuid_ecx(unsigned int op)
201 unsigned int eax, ecx;
204 : "=a" (eax), "=c" (ecx)
209 static inline unsigned int cpuid_edx(unsigned int op)
211 unsigned int eax, edx;
214 : "=a" (eax), "=d" (edx)
220 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
223 * Intel CPU features in CR4
225 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
226 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
227 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
228 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
229 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
230 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
231 #define X86_CR4_MCE 0x0040 /* Machine check enable */
232 #define X86_CR4_PGE 0x0080 /* enable global pages */
233 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
234 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
235 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
238 * Save the cr4 feature set we're using (ie
239 * Pentium 4MB enable and PPro Global page
240 * enable), so that any CPU's that boot up
241 * after us can get the correct flags.
243 extern unsigned long mmu_cr4_features;
245 static inline void set_in_cr4 (unsigned long mask)
248 mmu_cr4_features |= mask;
254 static inline void clear_in_cr4 (unsigned long mask)
257 mmu_cr4_features &= ~mask;
264 * NSC/Cyrix CPU configuration register indexes
267 #define CX86_PCR0 0x20
268 #define CX86_GCR 0xb8
269 #define CX86_CCR0 0xc0
270 #define CX86_CCR1 0xc1
271 #define CX86_CCR2 0xc2
272 #define CX86_CCR3 0xc3
273 #define CX86_CCR4 0xe8
274 #define CX86_CCR5 0xe9
275 #define CX86_CCR6 0xea
276 #define CX86_CCR7 0xeb
277 #define CX86_PCR1 0xf0
278 #define CX86_DIR0 0xfe
279 #define CX86_DIR1 0xff
280 #define CX86_ARR_BASE 0xc4
281 #define CX86_RCR_BASE 0xdc
284 * NSC/Cyrix CPU indexed register access macros
287 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
289 #define setCx86(reg, data) do { \
291 outb((data), 0x23); \
294 /* Stop speculative execution */
295 static inline void sync_core(void)
298 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
301 static inline void __monitor(const void *eax, unsigned long ecx,
304 /* "monitor %eax,%ecx,%edx;" */
306 ".byte 0x0f,0x01,0xc8;"
307 : :"a" (eax), "c" (ecx), "d"(edx));
310 static inline void __mwait(unsigned long eax, unsigned long ecx)
312 /* "mwait %eax,%ecx;" */
314 ".byte 0x0f,0x01,0xc9;"
315 : :"a" (eax), "c" (ecx));
318 /* from system description table in BIOS. Mostly for MCA use, but
319 others may find it useful. */
320 extern unsigned int machine_id;
321 extern unsigned int machine_submodel_id;
322 extern unsigned int BIOS_revision;
323 extern unsigned int mca_pentium_flag;
325 /* Boot loader type from the setup header */
326 extern int bootloader_type;
329 * User space process size: 3GB (default).
331 #define TASK_SIZE (PAGE_OFFSET)
333 /* This decides where the kernel will search for a free chunk of vm
334 * space during mmap's.
336 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE/3)
338 #define __HAVE_ARCH_ALIGN_STACK
339 extern unsigned long arch_align_stack(unsigned long sp);
341 #define HAVE_ARCH_PICK_MMAP_LAYOUT
346 #define IO_BITMAP_BITS 65536
347 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
348 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
349 #ifndef CONFIG_X86_NO_TSS
350 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
352 #define INVALID_IO_BITMAP_OFFSET 0x8000
353 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
355 struct i387_fsave_struct {
363 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
364 long status; /* software status information */
367 struct i387_fxsave_struct {
378 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
379 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
381 } __attribute__ ((aligned (16)));
383 struct i387_soft_struct {
391 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
392 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
394 unsigned long entry_eip;
398 struct i387_fsave_struct fsave;
399 struct i387_fxsave_struct fxsave;
400 struct i387_soft_struct soft;
407 struct thread_struct;
409 #ifndef CONFIG_X86_NO_TSS
411 unsigned short back_link,__blh;
413 unsigned short ss0,__ss0h;
415 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
417 unsigned short ss2,__ss2h;
420 unsigned long eflags;
421 unsigned long eax,ecx,edx,ebx;
426 unsigned short es, __esh;
427 unsigned short cs, __csh;
428 unsigned short ss, __ssh;
429 unsigned short ds, __dsh;
430 unsigned short fs, __fsh;
431 unsigned short gs, __gsh;
432 unsigned short ldt, __ldth;
433 unsigned short trace, io_bitmap_base;
435 * The extra 1 is there because the CPU will access an
436 * additional byte beyond the end of the IO permission
437 * bitmap. The extra byte must be all 1 bits, and must
438 * be within the limit.
440 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
442 * Cache the current maximum and the last task that used the bitmap:
444 unsigned long io_bitmap_max;
445 struct thread_struct *io_bitmap_owner;
447 * pads the TSS to be cacheline-aligned (size is 0x100)
449 unsigned long __cacheline_filler[35];
451 * .. and then another 0x100 bytes for emergency kernel stack
453 unsigned long stack[64];
454 } __attribute__((packed));
457 #define ARCH_MIN_TASKALIGN 16
459 struct thread_struct {
460 /* cached TLS descriptors. */
461 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
463 unsigned long sysenter_cs;
468 /* Hardware debugging registers */
469 unsigned long debugreg[8]; /* %%db0-7 debug registers */
471 unsigned long cr2, trap_no, error_code;
472 /* floating point info */
473 union i387_union i387;
474 /* virtual 86 mode info */
475 struct vm86_struct __user * vm86_info;
476 unsigned long screen_bitmap;
477 unsigned long v86flags, v86mask, saved_esp0;
478 unsigned int saved_fs, saved_gs;
480 unsigned long *io_bitmap_ptr;
482 /* max allowed port in the bitmap, in bytes: */
483 unsigned long io_bitmap_max;
486 #define INIT_THREAD { \
488 .sysenter_cs = __KERNEL_CS, \
489 .io_bitmap_ptr = NULL, \
492 #ifndef CONFIG_X86_NO_TSS
494 * Note that the .io_bitmap member must be extra-big. This is because
495 * the CPU will access an additional byte beyond the end of the IO
496 * permission bitmap. The extra byte must be all 1 bits, and must
497 * be within the limit.
500 .esp0 = sizeof(init_stack) + (long)&init_stack, \
501 .ss0 = __KERNEL_DS, \
502 .ss1 = __KERNEL_CS, \
503 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
504 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
507 static inline void __load_esp0(struct tss_struct *tss, struct thread_struct *thread)
509 tss->esp0 = thread->esp0;
510 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
511 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
512 tss->ss1 = thread->sysenter_cs;
513 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
516 #define load_esp0(tss, thread) \
517 __load_esp0(tss, thread)
519 #define load_esp0(tss, thread) \
520 HYPERVISOR_stack_switch(__KERNEL_DS, (thread)->esp0)
523 #define start_thread(regs, new_eip, new_esp) do { \
524 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
526 regs->xds = __USER_DS; \
527 regs->xes = __USER_DS; \
528 regs->xss = __USER_DS; \
529 regs->xcs = __USER_CS; \
530 regs->eip = new_eip; \
531 regs->esp = new_esp; \
533 load_user_cs_desc(smp_processor_id(), current->mm); \
538 * These special macros can be used to get or set a debugging register
540 #define get_debugreg(var, register) \
541 (var) = HYPERVISOR_get_debugreg((register))
542 #define set_debugreg(value, register) \
543 HYPERVISOR_set_debugreg((register), (value))
546 * Set IOPL bits in EFLAGS from given mask
548 static inline void set_iopl_mask(unsigned mask)
550 struct physdev_set_iopl set_iopl;
552 /* Force the change at ring 0. */
553 set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3;
554 HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
557 /* Forward declaration, a strange C thing */
561 /* Free all resources held by a thread. */
562 extern void release_thread(struct task_struct *);
564 /* Prepare to copy thread state - unlazy all lazy status */
565 extern void prepare_to_copy(struct task_struct *tsk);
568 * create a kernel thread without removing it from tasklists
570 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
572 extern unsigned long thread_saved_pc(struct task_struct *tsk);
573 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
575 unsigned long get_wchan(struct task_struct *p);
577 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
578 #define KSTK_TOP(info) \
580 unsigned long *__ptr = (unsigned long *)(info); \
581 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
585 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
586 * This is necessary to guarantee that the entire "struct pt_regs"
587 * is accessable even if the CPU haven't stored the SS/ESP registers
588 * on the stack (interrupt gate does not save these registers
589 * when switching to the same priv ring).
590 * Therefore beware: accessing the xss/esp fields of the
591 * "struct pt_regs" is possible, but they may contain the
592 * completely wrong values.
594 #define task_pt_regs(task) \
596 struct pt_regs *__regs__; \
597 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
601 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
602 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
605 struct microcode_header {
613 unsigned int datasize;
614 unsigned int totalsize;
615 unsigned int reserved[3];
619 struct microcode_header hdr;
620 unsigned int bits[0];
623 typedef struct microcode microcode_t;
624 typedef struct microcode_header microcode_header_t;
626 /* microcode format is extended from prescott processors */
627 struct extended_signature {
633 struct extended_sigtable {
636 unsigned int reserved[3];
637 struct extended_signature sigs[0];
640 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
641 static inline void rep_nop(void)
643 __asm__ __volatile__("rep;nop": : :"memory");
646 #define cpu_relax() rep_nop()
648 /* generic versions from gas */
649 #define GENERIC_NOP1 ".byte 0x90\n"
650 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
651 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
652 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
653 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
654 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
655 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
656 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
659 #define K8_NOP1 GENERIC_NOP1
660 #define K8_NOP2 ".byte 0x66,0x90\n"
661 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
662 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
663 #define K8_NOP5 K8_NOP3 K8_NOP2
664 #define K8_NOP6 K8_NOP3 K8_NOP3
665 #define K8_NOP7 K8_NOP4 K8_NOP3
666 #define K8_NOP8 K8_NOP4 K8_NOP4
669 /* uses eax dependencies (arbitary choice) */
670 #define K7_NOP1 GENERIC_NOP1
671 #define K7_NOP2 ".byte 0x8b,0xc0\n"
672 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
673 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
674 #define K7_NOP5 K7_NOP4 ASM_NOP1
675 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
676 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
677 #define K7_NOP8 K7_NOP7 ASM_NOP1
680 #define ASM_NOP1 K8_NOP1
681 #define ASM_NOP2 K8_NOP2
682 #define ASM_NOP3 K8_NOP3
683 #define ASM_NOP4 K8_NOP4
684 #define ASM_NOP5 K8_NOP5
685 #define ASM_NOP6 K8_NOP6
686 #define ASM_NOP7 K8_NOP7
687 #define ASM_NOP8 K8_NOP8
688 #elif defined(CONFIG_MK7)
689 #define ASM_NOP1 K7_NOP1
690 #define ASM_NOP2 K7_NOP2
691 #define ASM_NOP3 K7_NOP3
692 #define ASM_NOP4 K7_NOP4
693 #define ASM_NOP5 K7_NOP5
694 #define ASM_NOP6 K7_NOP6
695 #define ASM_NOP7 K7_NOP7
696 #define ASM_NOP8 K7_NOP8
698 #define ASM_NOP1 GENERIC_NOP1
699 #define ASM_NOP2 GENERIC_NOP2
700 #define ASM_NOP3 GENERIC_NOP3
701 #define ASM_NOP4 GENERIC_NOP4
702 #define ASM_NOP5 GENERIC_NOP5
703 #define ASM_NOP6 GENERIC_NOP6
704 #define ASM_NOP7 GENERIC_NOP7
705 #define ASM_NOP8 GENERIC_NOP8
708 #define ASM_NOP_MAX 8
710 /* Prefetch instructions for Pentium III and AMD Athlon */
711 /* It's not worth to care about 3dnow! prefetches for the K6
712 because they are microcoded there and very slow.
713 However we don't do prefetches for pre XP Athlons currently
714 That should be fixed. */
715 #define ARCH_HAS_PREFETCH
716 static inline void prefetch(const void *x)
718 alternative_input(ASM_NOP4,
724 #define ARCH_HAS_PREFETCH
725 #define ARCH_HAS_PREFETCHW
726 #define ARCH_HAS_SPINLOCK_PREFETCH
728 /* 3dnow! prefetch to get an exclusive cache line. Useful for
729 spinlocks to avoid one state transition in the cache coherency protocol. */
730 static inline void prefetchw(const void *x)
732 alternative_input(ASM_NOP4,
737 #define spin_lock_prefetch(x) prefetchw(x)
739 extern void select_idle_routine(const struct cpuinfo_x86 *c);
741 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
743 extern unsigned long boot_option_idle_override;
744 extern void enable_sep_cpu(void);
745 extern int sysenter_setup(void);
747 #endif /* __ASM_I386_PROCESSOR_H */