1 #ifndef _I386_PGTABLE_H
2 #define _I386_PGTABLE_H
4 #include <linux/config.h>
7 * The Linux memory management assumes a three-level page table setup. On
8 * the i386, we use that, but "fold" the mid level into the top-level page
9 * table, so that we physically have the same two-level page table as the
12 * This file contains the functions and defines necessary to modify and use
13 * the i386 page table tree.
16 #include <asm/processor.h>
17 #include <asm/fixmap.h>
18 #include <linux/threads.h>
19 #include <linux/slab.h>
21 #ifndef _I386_BITOPS_H
22 #include <asm/bitops.h>
25 extern pgd_t swapper_pg_dir[1024];
26 extern kmem_cache_t *pgd_cache, *pmd_cache, *kpmd_cache;
27 extern spinlock_t pgd_lock;
28 extern struct page *pgd_list;
29 void pmd_ctor(void *, kmem_cache_t *, unsigned long);
30 void kpmd_ctor(void *, kmem_cache_t *, unsigned long);
31 void pgd_ctor(void *, kmem_cache_t *, unsigned long);
32 void pgd_dtor(void *, kmem_cache_t *, unsigned long);
33 void pgtable_cache_init(void);
34 extern void paging_init(void);
35 void setup_identity_mappings(pgd_t *pgd_base, unsigned long start, unsigned long end);
38 * ZERO_PAGE is a global shared page that is always zero: used
39 * for zero-mapped memory areas etc..
41 extern unsigned long empty_zero_page[1024];
42 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
45 * The Linux x86 paging architecture is 'compile-time dual-mode', it
46 * implements both the traditional 2-level x86 page tables and the
47 * newer 3-level PAE-mode page tables.
50 extern void set_system_gate(unsigned int n, void *addr);
51 extern void init_entry_mappings(void);
52 extern void entry_trampoline_setup(void);
55 # include <asm/pgtable-3level-defs.h>
57 # include <asm/pgtable-2level-defs.h>
60 #define PMD_SIZE (1UL << PMD_SHIFT)
61 #define PMD_MASK (~(PMD_SIZE-1))
62 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
63 #define PGDIR_MASK (~(PGDIR_SIZE-1))
65 #if defined(CONFIG_X86_PAE) && defined(CONFIG_X86_4G_VM_LAYOUT)
66 # define USER_PTRS_PER_PGD 4
68 # define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) + ((TASK_SIZE % PGDIR_SIZE) + PGDIR_SIZE-1)/PGDIR_SIZE)
71 #define FIRST_USER_PGD_NR 0
73 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
74 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
76 #define TWOLEVEL_PGDIR_SHIFT 22
77 #define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
78 #define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS)
80 /* Just any arbitrary offset to the start of the vmalloc VM area: the
81 * current 8MB value just means that there will be a 8MB "hole" after the
82 * physical memory until the kernel virtual memory starts. That means that
83 * any out-of-bounds memory accesses will hopefully be caught.
84 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
85 * area for the same reason. ;)
87 #define VMALLOC_OFFSET (8*1024*1024)
88 #define VMALLOC_START (((unsigned long) high_memory + vmalloc_earlyreserve + \
89 2*VMALLOC_OFFSET-1) & ~(VMALLOC_OFFSET-1))
91 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
93 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
97 * The 4MB page is guessing.. Detailed in the infamous "Chapter H"
98 * of the Pentium details, but assuming intel did the straightforward
99 * thing, this bit set in the page directory entry just means that
100 * the page directory entry points directly to a 4MB-aligned block of
103 #define _PAGE_BIT_PRESENT 0
104 #define _PAGE_BIT_RW 1
105 #define _PAGE_BIT_USER 2
106 #define _PAGE_BIT_PWT 3
107 #define _PAGE_BIT_PCD 4
108 #define _PAGE_BIT_ACCESSED 5
109 #define _PAGE_BIT_DIRTY 6
110 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page, Pentium+, if present.. */
111 #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
112 #define _PAGE_BIT_UNUSED1 9 /* available for programmer */
113 #define _PAGE_BIT_UNUSED2 10
114 #define _PAGE_BIT_UNUSED3 11
115 #define _PAGE_BIT_NX 63
117 #define _PAGE_PRESENT 0x001
118 #define _PAGE_RW 0x002
119 #define _PAGE_USER 0x004
120 #define _PAGE_PWT 0x008
121 #define _PAGE_PCD 0x010
122 #define _PAGE_ACCESSED 0x020
123 #define _PAGE_DIRTY 0x040
124 #define _PAGE_PSE 0x080 /* 4 MB (or 2MB) page, Pentium+, if present.. */
125 #define _PAGE_GLOBAL 0x100 /* Global TLB entry PPro+ */
126 #define _PAGE_UNUSED1 0x200 /* available for programmer */
127 #define _PAGE_UNUSED2 0x400
128 #define _PAGE_UNUSED3 0x800
130 #define _PAGE_FILE 0x040 /* set:pagecache unset:swap */
131 #define _PAGE_PROTNONE 0x080 /* If not present */
132 #ifdef CONFIG_X86_PAE
133 #define _PAGE_NX (1ULL<<_PAGE_BIT_NX)
138 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
139 #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
140 #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
143 __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
144 #define PAGE_SHARED \
145 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
147 #define PAGE_SHARED_EXEC \
148 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
149 #define PAGE_COPY_NOEXEC \
150 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
151 #define PAGE_COPY_EXEC \
152 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
155 #define PAGE_READONLY \
156 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
157 #define PAGE_READONLY_EXEC \
158 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
160 #define _PAGE_KERNEL \
161 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX)
162 #define _PAGE_KERNEL_EXEC \
163 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
165 extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
166 #define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
167 #define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_PCD)
168 #define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
169 #define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
171 #define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
172 #define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
173 #define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC)
174 #define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
175 #define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
176 #define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
179 * The i386 can't do page protection for execute, and considers that
180 * the same are read. Also, write permissions imply read permissions.
181 * This is the closest we can get..
183 #define __P000 PAGE_NONE
184 #define __P001 PAGE_READONLY
185 #define __P010 PAGE_COPY
186 #define __P011 PAGE_COPY
187 #define __P100 PAGE_READONLY_EXEC
188 #define __P101 PAGE_READONLY_EXEC
189 #define __P110 PAGE_COPY_EXEC
190 #define __P111 PAGE_COPY_EXEC
192 #define __S000 PAGE_NONE
193 #define __S001 PAGE_READONLY
194 #define __S010 PAGE_SHARED
195 #define __S011 PAGE_SHARED
196 #define __S100 PAGE_READONLY_EXEC
197 #define __S101 PAGE_READONLY_EXEC
198 #define __S110 PAGE_SHARED_EXEC
199 #define __S111 PAGE_SHARED_EXEC
202 * Define this if things work differently on an i386 and an i486:
203 * it will (on an i486) warn about kernel memory accesses that are
204 * done without a 'verify_area(VERIFY_WRITE,..)'
206 #undef TEST_VERIFY_AREA
208 /* The boot page tables (all created as a single array) */
209 extern unsigned long pg0[];
211 #define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
212 #define pte_clear(xp) do { set_pte(xp, __pte(0)); } while (0)
214 #define pmd_none(x) (!pmd_val(x))
215 #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
216 #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
217 #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
220 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
223 * The following only work if pte_present() is true.
224 * Undefined behaviour if not..
226 static inline int pte_user(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
227 static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
228 static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_DIRTY; }
229 static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; }
230 static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_RW; }
233 * The following only works if pte_present() is not true.
235 static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; }
237 static inline pte_t pte_rdprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
238 static inline pte_t pte_exprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
239 static inline pte_t pte_mkclean(pte_t pte) { (pte).pte_low &= ~_PAGE_DIRTY; return pte; }
240 static inline pte_t pte_mkold(pte_t pte) { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; }
241 static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_RW; return pte; }
242 static inline pte_t pte_mkread(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
243 static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
244 static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; }
245 static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
246 static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; }
248 #ifdef CONFIG_X86_PAE
249 # include <asm/pgtable-3level.h>
251 # include <asm/pgtable-2level.h>
254 static inline int ptep_test_and_clear_dirty(pte_t *ptep)
256 if (!pte_dirty(*ptep))
258 return test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte_low);
261 static inline int ptep_test_and_clear_young(pte_t *ptep)
263 if (!pte_young(*ptep))
265 return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte_low);
268 static inline void ptep_set_wrprotect(pte_t *ptep) { clear_bit(_PAGE_BIT_RW, &ptep->pte_low); }
269 static inline void ptep_mkdirty(pte_t *ptep) { set_bit(_PAGE_BIT_DIRTY, &ptep->pte_low); }
272 * Macro to mark a page protection value as "uncacheable". On processors which do not support
273 * it, this is a no-op.
275 #define pgprot_noncached(prot) ((boot_cpu_data.x86 > 3) \
276 ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) : (prot))
279 * Conversion functions: convert a page and protection to a page entry,
280 * and a page entry and page directory to the page they refer to.
283 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
284 #define mk_pte_huge(entry) ((entry).pte_low |= _PAGE_PRESENT | _PAGE_PSE)
285 #define mk_pte_phys(physpage, pgprot) pfn_pte((physpage) >> PAGE_SHIFT, pgprot)
287 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
289 pte.pte_low &= _PAGE_CHG_MASK;
290 pte.pte_low |= pgprot_val(newprot);
291 #ifdef CONFIG_X86_PAE
293 * Chop off the NX bit (if present), and add the NX portion of
294 * the newprot (if present):
296 pte.pte_high &= ~(1 << (_PAGE_BIT_NX - 32));
297 pte.pte_high |= (pgprot_val(newprot) >> 32) & \
298 (__supported_pte_mask >> 32);
303 #define page_pte(page) page_pte_prot(page, __pgprot(0))
305 #define pmd_page_kernel(pmd) \
306 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
308 #ifndef CONFIG_DISCONTIGMEM
309 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
310 #endif /* !CONFIG_DISCONTIGMEM */
312 #define pmd_large(pmd) \
313 ((pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT))
316 * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
318 * this macro returns the index of the entry in the pgd page which would
319 * control the given virtual address
321 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
324 * pgd_offset() returns a (pgd_t *)
325 * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
327 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
330 * a shortcut which implies the use of the kernel's pgd, instead
333 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
336 * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
338 * this macro returns the index of the entry in the pmd page which would
339 * control the given virtual address
341 #define pmd_index(address) \
342 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
345 * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
347 * this macro returns the index of the entry in the pte page which would
348 * control the given virtual address
350 #define pte_index(address) \
351 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
352 #define pte_offset_kernel(dir, address) \
353 ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address))
356 * Helper function that returns the kernel pagetable entry controlling
357 * the virtual address 'address'. NULL means no pagetable entry present.
358 * NOTE: the return type is pte_t but if the pmd is PSE then we return it
361 extern pte_t *lookup_address(unsigned long address);
364 * Make a given kernel text page executable/non-executable.
365 * Returns the previous executability setting of that page (which
366 * is used to restore the previous state). Used by the SMP bootup code.
367 * NOTE: this is an __init function for security reasons.
369 #ifdef CONFIG_X86_PAE
370 extern int set_kernel_exec(unsigned long vaddr, int enable);
372 static inline int set_kernel_exec(unsigned long vaddr, int enable) { return 0;}
375 #if defined(CONFIG_HIGHPTE)
376 #define pte_offset_map(dir, address) \
377 ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE0) + pte_index(address))
378 #define pte_offset_map_nested(dir, address) \
379 ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE1) + pte_index(address))
380 #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
381 #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
383 #define pte_offset_map(dir, address) \
384 ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
385 #define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
386 #define pte_unmap(pte) do { } while (0)
387 #define pte_unmap_nested(pte) do { } while (0)
391 * The i386 doesn't have any external MMU info: the kernel page
392 * tables contain all the necessary information.
394 * Also, we only update the dirty/accessed state if we set
395 * the dirty bit by hand in the kernel, since the hardware
396 * will do the accessed bit for us, and we don't want to
397 * race with other CPU's that might be updating the dirty
398 * bit at the same time.
400 #define update_mmu_cache(vma,address,pte) do { } while (0)
401 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
402 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
405 (__ptep)->pte_low = (__entry).pte_low; \
406 flush_tlb_page(__vma, __address); \
410 /* Encode and de-code a swap entry */
411 #define __swp_type(x) (((x).val >> 1) & 0x1f)
412 #define __swp_offset(x) ((x).val >> 8)
413 #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
414 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low })
415 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
417 #endif /* !__ASSEMBLY__ */
419 #ifndef CONFIG_DISCONTIGMEM
420 #define kern_addr_valid(addr) (1)
421 #endif /* !CONFIG_DISCONTIGMEM */
423 #define io_remap_page_range remap_page_range
425 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
426 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
427 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
428 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
429 #define __HAVE_ARCH_PTEP_MKDIRTY
430 #define __HAVE_ARCH_PTE_SAME
431 #include <asm-generic/pgtable.h>
434 * The size of the low 1:1 mappings we use during bootup,
435 * SMP-boot and ACPI-sleep:
437 #define LOW_MAPPINGS_SIZE (16*1024*1024)
440 #endif /* _I386_PGTABLE_H */