1 #ifndef _I386_PGTABLE_H
2 #define _I386_PGTABLE_H
4 #include <linux/config.h>
7 * The Linux memory management assumes a three-level page table setup. On
8 * the i386, we use that, but "fold" the mid level into the top-level page
9 * table, so that we physically have the same two-level page table as the
12 * This file contains the functions and defines necessary to modify and use
13 * the i386 page table tree.
16 #include <asm/processor.h>
17 #include <asm/fixmap.h>
18 #include <linux/threads.h>
20 #ifndef _I386_BITOPS_H
21 #include <asm/bitops.h>
24 #include <linux/slab.h>
25 #include <linux/list.h>
26 #include <linux/spinlock.h>
29 * ZERO_PAGE is a global shared page that is always zero: used
30 * for zero-mapped memory areas etc..
32 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
33 extern unsigned long empty_zero_page[1024];
34 extern pgd_t swapper_pg_dir[1024];
35 extern kmem_cache_t *pgd_cache;
36 extern kmem_cache_t *pmd_cache;
37 extern spinlock_t pgd_lock;
38 extern struct page *pgd_list;
40 void pmd_ctor(void *, kmem_cache_t *, unsigned long);
41 void pgd_ctor(void *, kmem_cache_t *, unsigned long);
42 void pgd_dtor(void *, kmem_cache_t *, unsigned long);
43 void pgtable_cache_init(void);
44 void paging_init(void);
46 #endif /* !__ASSEMBLY__ */
49 * The Linux x86 paging architecture is 'compile-time dual-mode', it
50 * implements both the traditional 2-level x86 page tables and the
51 * newer 3-level PAE-mode page tables.
55 # include <asm/pgtable-3level.h>
57 # include <asm/pgtable-2level.h>
61 #define PMD_SIZE (1UL << PMD_SHIFT)
62 #define PMD_MASK (~(PMD_SIZE-1))
63 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
64 #define PGDIR_MASK (~(PGDIR_SIZE-1))
66 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
67 #define FIRST_USER_PGD_NR 0
69 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
70 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
72 #define TWOLEVEL_PGDIR_SHIFT 22
73 #define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
74 #define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS)
78 /* Just any arbitrary offset to the start of the vmalloc VM area: the
79 * current 8MB value just means that there will be a 8MB "hole" after the
80 * physical memory until the kernel virtual memory starts. That means that
81 * any out-of-bounds memory accesses will hopefully be caught.
82 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
83 * area for the same reason. ;)
85 #define VMALLOC_OFFSET (8*1024*1024)
86 #define VMALLOC_START (((unsigned long) high_memory + 2*VMALLOC_OFFSET-1) & \
89 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
91 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
95 * The 4MB page is guessing.. Detailed in the infamous "Chapter H"
96 * of the Pentium details, but assuming intel did the straightforward
97 * thing, this bit set in the page directory entry just means that
98 * the page directory entry points directly to a 4MB-aligned block of
101 #define _PAGE_BIT_PRESENT 0
102 #define _PAGE_BIT_RW 1
103 #define _PAGE_BIT_USER 2
104 #define _PAGE_BIT_PWT 3
105 #define _PAGE_BIT_PCD 4
106 #define _PAGE_BIT_ACCESSED 5
107 #define _PAGE_BIT_DIRTY 6
108 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page, Pentium+, if present.. */
109 #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
110 #define _PAGE_BIT_UNUSED1 9 /* available for programmer */
111 #define _PAGE_BIT_UNUSED2 10
112 #define _PAGE_BIT_UNUSED3 11
114 #define _PAGE_PRESENT 0x001
115 #define _PAGE_RW 0x002
116 #define _PAGE_USER 0x004
117 #define _PAGE_PWT 0x008
118 #define _PAGE_PCD 0x010
119 #define _PAGE_ACCESSED 0x020
120 #define _PAGE_DIRTY 0x040
121 #define _PAGE_PSE 0x080 /* 4 MB (or 2MB) page, Pentium+, if present.. */
122 #define _PAGE_GLOBAL 0x100 /* Global TLB entry PPro+ */
123 #define _PAGE_UNUSED1 0x200 /* available for programmer */
124 #define _PAGE_UNUSED2 0x400
125 #define _PAGE_UNUSED3 0x800
127 #define _PAGE_FILE 0x040 /* set:pagecache unset:swap */
128 #define _PAGE_PROTNONE 0x080 /* If not present */
130 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
131 #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
132 #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
134 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
135 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
136 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
137 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
139 #define _PAGE_KERNEL \
140 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
142 extern unsigned long __PAGE_KERNEL;
143 #define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
144 #define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_PCD)
145 #define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
147 #define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
148 #define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
149 #define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
150 #define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
153 * The i386 can't do page protection for execute, and considers that
154 * the same are read. Also, write permissions imply read permissions.
155 * This is the closest we can get..
157 #define __P000 PAGE_NONE
158 #define __P001 PAGE_READONLY
159 #define __P010 PAGE_COPY
160 #define __P011 PAGE_COPY
161 #define __P100 PAGE_READONLY
162 #define __P101 PAGE_READONLY
163 #define __P110 PAGE_COPY
164 #define __P111 PAGE_COPY
166 #define __S000 PAGE_NONE
167 #define __S001 PAGE_READONLY
168 #define __S010 PAGE_SHARED
169 #define __S011 PAGE_SHARED
170 #define __S100 PAGE_READONLY
171 #define __S101 PAGE_READONLY
172 #define __S110 PAGE_SHARED
173 #define __S111 PAGE_SHARED
176 * Define this if things work differently on an i386 and an i486:
177 * it will (on an i486) warn about kernel memory accesses that are
178 * done without a 'verify_area(VERIFY_WRITE,..)'
180 #undef TEST_VERIFY_AREA
182 /* The boot page tables (all created as a single array) */
183 extern unsigned long pg0[];
185 #define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
186 #define pte_clear(xp) do { set_pte(xp, __pte(0)); } while (0)
188 #define pmd_none(x) (!pmd_val(x))
189 #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
190 #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
191 #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
194 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
197 * The following only work if pte_present() is true.
198 * Undefined behaviour if not..
200 static inline int pte_user(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
201 static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
202 static inline int pte_exec(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
203 static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_DIRTY; }
204 static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; }
205 static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_RW; }
208 * The following only works if pte_present() is not true.
210 static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; }
212 static inline pte_t pte_rdprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
213 static inline pte_t pte_exprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
214 static inline pte_t pte_mkclean(pte_t pte) { (pte).pte_low &= ~_PAGE_DIRTY; return pte; }
215 static inline pte_t pte_mkold(pte_t pte) { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; }
216 static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_RW; return pte; }
217 static inline pte_t pte_mkread(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
218 static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
219 static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; }
220 static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
221 static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; }
223 static inline int ptep_test_and_clear_dirty(pte_t *ptep) { return test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte_low); }
224 static inline int ptep_test_and_clear_young(pte_t *ptep) { return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte_low); }
225 static inline void ptep_set_wrprotect(pte_t *ptep) { clear_bit(_PAGE_BIT_RW, &ptep->pte_low); }
226 static inline void ptep_mkdirty(pte_t *ptep) { set_bit(_PAGE_BIT_DIRTY, &ptep->pte_low); }
229 * Macro to mark a page protection value as "uncacheable". On processors which do not support
230 * it, this is a no-op.
232 #define pgprot_noncached(prot) ((boot_cpu_data.x86 > 3) \
233 ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) : (prot))
236 * Conversion functions: convert a page and protection to a page entry,
237 * and a page entry and page directory to the page they refer to.
240 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
241 #define mk_pte_huge(entry) ((entry).pte_low |= _PAGE_PRESENT | _PAGE_PSE)
243 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
245 pte.pte_low &= _PAGE_CHG_MASK;
246 pte.pte_low |= pgprot_val(newprot);
250 #define page_pte(page) page_pte_prot(page, __pgprot(0))
252 #define pmd_page_kernel(pmd) \
253 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
255 #ifndef CONFIG_DISCONTIGMEM
256 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
257 #endif /* !CONFIG_DISCONTIGMEM */
259 #define pmd_large(pmd) \
260 ((pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT))
263 * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
265 * this macro returns the index of the entry in the pgd page which would
266 * control the given virtual address
268 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
271 * pgd_offset() returns a (pgd_t *)
272 * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
274 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
277 * a shortcut which implies the use of the kernel's pgd, instead
280 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
283 * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
285 * this macro returns the index of the entry in the pmd page which would
286 * control the given virtual address
288 #define pmd_index(address) \
289 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
292 * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
294 * this macro returns the index of the entry in the pte page which would
295 * control the given virtual address
297 #define pte_index(address) \
298 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
299 #define pte_offset_kernel(dir, address) \
300 ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address))
302 #if defined(CONFIG_HIGHPTE)
303 #define pte_offset_map(dir, address) \
304 ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE0) + pte_index(address))
305 #define pte_offset_map_nested(dir, address) \
306 ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE1) + pte_index(address))
307 #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
308 #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
310 #define pte_offset_map(dir, address) \
311 ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
312 #define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
313 #define pte_unmap(pte) do { } while (0)
314 #define pte_unmap_nested(pte) do { } while (0)
317 #if defined(CONFIG_HIGHPTE) && defined(CONFIG_HIGHMEM4G)
318 typedef u32 pte_addr_t;
321 #if defined(CONFIG_HIGHPTE) && defined(CONFIG_HIGHMEM64G)
322 typedef u64 pte_addr_t;
325 #if !defined(CONFIG_HIGHPTE)
326 typedef pte_t *pte_addr_t;
330 * The i386 doesn't have any external MMU info: the kernel page
331 * tables contain all the necessary information.
333 #define update_mmu_cache(vma,address,pte) do { } while (0)
335 /* Encode and de-code a swap entry */
336 #define __swp_type(x) (((x).val >> 1) & 0x1f)
337 #define __swp_offset(x) ((x).val >> 8)
338 #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
339 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low })
340 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
342 #endif /* !__ASSEMBLY__ */
344 #ifndef CONFIG_DISCONTIGMEM
345 #define kern_addr_valid(addr) (1)
346 #endif /* !CONFIG_DISCONTIGMEM */
348 #define io_remap_page_range remap_page_range
350 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
351 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
352 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
353 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
354 #define __HAVE_ARCH_PTEP_MKDIRTY
355 #define __HAVE_ARCH_PTE_SAME
356 #include <asm-generic/pgtable.h>
358 #endif /* _I386_PGTABLE_H */