2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/threads.h>
21 #include <asm/percpu.h>
22 #include <linux/cpumask.h>
24 /* flag for disabling the tsc */
25 extern int tsc_disable;
31 #define desc_empty(desc) \
32 (!((desc)->a | (desc)->b))
34 #define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
63 int x86_cache_alignment; /* In bytes */
69 unsigned long loops_per_jiffy;
71 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
73 unsigned char x86_max_cores; /* cpuid returned max cores value */
76 unsigned char booted_cores; /* number of cores as seen by OS */
77 __u8 phys_proc_id; /* Physical processor id. */
78 __u8 cpu_core_id; /* Core id */
80 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
82 #define X86_VENDOR_INTEL 0
83 #define X86_VENDOR_CYRIX 1
84 #define X86_VENDOR_AMD 2
85 #define X86_VENDOR_UMC 3
86 #define X86_VENDOR_NEXGEN 4
87 #define X86_VENDOR_CENTAUR 5
88 #define X86_VENDOR_RISE 6
89 #define X86_VENDOR_TRANSMETA 7
90 #define X86_VENDOR_NSC 8
91 #define X86_VENDOR_NUM 9
92 #define X86_VENDOR_UNKNOWN 0xff
95 * capabilities of CPUs
98 extern struct cpuinfo_x86 boot_cpu_data;
99 extern struct cpuinfo_x86 new_cpu_data;
100 extern struct tss_struct doublefault_tss;
101 DECLARE_PER_CPU(struct tss_struct, init_tss);
104 extern struct cpuinfo_x86 cpu_data[];
105 #define current_cpu_data cpu_data[smp_processor_id()]
107 #define cpu_data (&boot_cpu_data)
108 #define current_cpu_data boot_cpu_data
111 extern int cpu_llc_id[NR_CPUS];
112 extern char ignore_fpu_irq;
114 extern void identify_cpu(struct cpuinfo_x86 *);
115 extern void print_cpu_info(struct cpuinfo_x86 *);
116 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
117 extern unsigned short num_cache_leaves;
120 extern void detect_ht(struct cpuinfo_x86 *c);
122 static inline void detect_ht(struct cpuinfo_x86 *c) {}
128 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
129 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
130 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
131 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
132 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
133 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
134 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
135 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
136 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
137 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
138 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
139 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
140 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
141 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
142 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
143 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
144 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
147 * Generic CPUID function
148 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
149 * resulting in stale register contents being returned.
151 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
161 /* Some CPUID calls want 'count' to be placed in ecx */
162 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
170 : "0" (op), "c" (count));
174 * CPUID functions returning a single datum
176 static inline unsigned int cpuid_eax(unsigned int op)
186 static inline unsigned int cpuid_ebx(unsigned int op)
188 unsigned int eax, ebx;
191 : "=a" (eax), "=b" (ebx)
196 static inline unsigned int cpuid_ecx(unsigned int op)
198 unsigned int eax, ecx;
201 : "=a" (eax), "=c" (ecx)
206 static inline unsigned int cpuid_edx(unsigned int op)
208 unsigned int eax, edx;
211 : "=a" (eax), "=d" (edx)
217 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
220 * Intel CPU features in CR4
222 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
223 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
224 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
225 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
226 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
227 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
228 #define X86_CR4_MCE 0x0040 /* Machine check enable */
229 #define X86_CR4_PGE 0x0080 /* enable global pages */
230 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
231 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
232 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
235 * Save the cr4 feature set we're using (ie
236 * Pentium 4MB enable and PPro Global page
237 * enable), so that any CPU's that boot up
238 * after us can get the correct flags.
240 extern unsigned long mmu_cr4_features;
242 static inline void set_in_cr4 (unsigned long mask)
245 mmu_cr4_features |= mask;
251 static inline void clear_in_cr4 (unsigned long mask)
254 mmu_cr4_features &= ~mask;
261 * NSC/Cyrix CPU configuration register indexes
264 #define CX86_PCR0 0x20
265 #define CX86_GCR 0xb8
266 #define CX86_CCR0 0xc0
267 #define CX86_CCR1 0xc1
268 #define CX86_CCR2 0xc2
269 #define CX86_CCR3 0xc3
270 #define CX86_CCR4 0xe8
271 #define CX86_CCR5 0xe9
272 #define CX86_CCR6 0xea
273 #define CX86_CCR7 0xeb
274 #define CX86_PCR1 0xf0
275 #define CX86_DIR0 0xfe
276 #define CX86_DIR1 0xff
277 #define CX86_ARR_BASE 0xc4
278 #define CX86_RCR_BASE 0xdc
281 * NSC/Cyrix CPU indexed register access macros
284 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
286 #define setCx86(reg, data) do { \
288 outb((data), 0x23); \
291 /* Stop speculative execution */
292 static inline void sync_core(void)
295 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
298 static inline void __monitor(const void *eax, unsigned long ecx,
301 /* "monitor %eax,%ecx,%edx;" */
303 ".byte 0x0f,0x01,0xc8;"
304 : :"a" (eax), "c" (ecx), "d"(edx));
307 static inline void __mwait(unsigned long eax, unsigned long ecx)
309 /* "mwait %eax,%ecx;" */
311 ".byte 0x0f,0x01,0xc9;"
312 : :"a" (eax), "c" (ecx));
315 /* from system description table in BIOS. Mostly for MCA use, but
316 others may find it useful. */
317 extern unsigned int machine_id;
318 extern unsigned int machine_submodel_id;
319 extern unsigned int BIOS_revision;
320 extern unsigned int mca_pentium_flag;
322 /* Boot loader type from the setup header */
323 extern int bootloader_type;
326 * User space process size: 3GB (default).
328 #define TASK_SIZE (PAGE_OFFSET)
330 /* This decides where the kernel will search for a free chunk of vm
331 * space during mmap's.
333 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE/3)
335 #define __HAVE_ARCH_ALIGN_STACK
336 extern unsigned long arch_align_stack(unsigned long sp);
338 #define HAVE_ARCH_PICK_MMAP_LAYOUT
343 #define IO_BITMAP_BITS 65536
344 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
345 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
346 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
347 #define INVALID_IO_BITMAP_OFFSET 0x8000
348 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
350 struct i387_fsave_struct {
358 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
359 long status; /* software status information */
362 struct i387_fxsave_struct {
373 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
374 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
376 } __attribute__ ((aligned (16)));
378 struct i387_soft_struct {
386 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
387 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
389 unsigned long entry_eip;
393 struct i387_fsave_struct fsave;
394 struct i387_fxsave_struct fxsave;
395 struct i387_soft_struct soft;
402 struct thread_struct;
405 unsigned short back_link,__blh;
407 unsigned short ss0,__ss0h;
409 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
411 unsigned short ss2,__ss2h;
414 unsigned long eflags;
415 unsigned long eax,ecx,edx,ebx;
420 unsigned short es, __esh;
421 unsigned short cs, __csh;
422 unsigned short ss, __ssh;
423 unsigned short ds, __dsh;
424 unsigned short fs, __fsh;
425 unsigned short gs, __gsh;
426 unsigned short ldt, __ldth;
427 unsigned short trace, io_bitmap_base;
429 * The extra 1 is there because the CPU will access an
430 * additional byte beyond the end of the IO permission
431 * bitmap. The extra byte must be all 1 bits, and must
432 * be within the limit.
434 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
436 * Cache the current maximum and the last task that used the bitmap:
438 unsigned long io_bitmap_max;
439 struct thread_struct *io_bitmap_owner;
441 * pads the TSS to be cacheline-aligned (size is 0x100)
443 unsigned long __cacheline_filler[35];
445 * .. and then another 0x100 bytes for emergency kernel stack
447 unsigned long stack[64];
448 } __attribute__((packed));
450 #define ARCH_MIN_TASKALIGN 16
452 struct thread_struct {
453 /* cached TLS descriptors. */
454 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
456 unsigned long sysenter_cs;
461 /* Hardware debugging registers */
462 unsigned long debugreg[8]; /* %%db0-7 debug registers */
464 unsigned long cr2, trap_no, error_code;
465 /* floating point info */
466 union i387_union i387;
467 /* virtual 86 mode info */
468 struct vm86_struct __user * vm86_info;
469 unsigned long screen_bitmap;
470 unsigned long v86flags, v86mask, saved_esp0;
471 unsigned int saved_fs, saved_gs;
473 unsigned long *io_bitmap_ptr;
475 /* max allowed port in the bitmap, in bytes: */
476 unsigned long io_bitmap_max;
479 #define INIT_THREAD { \
481 .sysenter_cs = __KERNEL_CS, \
482 .io_bitmap_ptr = NULL, \
486 * Note that the .io_bitmap member must be extra-big. This is because
487 * the CPU will access an additional byte beyond the end of the IO
488 * permission bitmap. The extra byte must be all 1 bits, and must
489 * be within the limit.
492 .esp0 = sizeof(init_stack) + (long)&init_stack, \
493 .ss0 = __KERNEL_DS, \
494 .ss1 = __KERNEL_CS, \
495 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
496 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
499 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
501 tss->esp0 = thread->esp0;
502 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
503 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
504 tss->ss1 = thread->sysenter_cs;
505 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
509 #define start_thread(regs, new_eip, new_esp) do { \
510 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
512 regs->xds = __USER_DS; \
513 regs->xes = __USER_DS; \
514 regs->xss = __USER_DS; \
515 regs->xcs = __USER_CS; \
516 regs->eip = new_eip; \
517 regs->esp = new_esp; \
519 load_user_cs_desc(smp_processor_id(), current->mm); \
524 * These special macros can be used to get or set a debugging register
526 #define get_debugreg(var, register) \
527 __asm__("movl %%db" #register ", %0" \
529 #define set_debugreg(value, register) \
530 __asm__("movl %0,%%db" #register \
535 * Set IOPL bits in EFLAGS from given mask
537 static inline void set_iopl_mask(unsigned mask)
540 __asm__ __volatile__ ("pushfl;"
547 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
550 /* Forward declaration, a strange C thing */
554 /* Free all resources held by a thread. */
555 extern void release_thread(struct task_struct *);
557 /* Prepare to copy thread state - unlazy all lazy status */
558 extern void prepare_to_copy(struct task_struct *tsk);
561 * create a kernel thread without removing it from tasklists
563 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
565 extern unsigned long thread_saved_pc(struct task_struct *tsk);
566 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
568 unsigned long get_wchan(struct task_struct *p);
570 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
571 #define KSTK_TOP(info) \
573 unsigned long *__ptr = (unsigned long *)(info); \
574 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
578 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
579 * This is necessary to guarantee that the entire "struct pt_regs"
580 * is accessable even if the CPU haven't stored the SS/ESP registers
581 * on the stack (interrupt gate does not save these registers
582 * when switching to the same priv ring).
583 * Therefore beware: accessing the xss/esp fields of the
584 * "struct pt_regs" is possible, but they may contain the
585 * completely wrong values.
587 #define task_pt_regs(task) \
589 struct pt_regs *__regs__; \
590 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
594 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
595 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
598 struct microcode_header {
606 unsigned int datasize;
607 unsigned int totalsize;
608 unsigned int reserved[3];
612 struct microcode_header hdr;
613 unsigned int bits[0];
616 typedef struct microcode microcode_t;
617 typedef struct microcode_header microcode_header_t;
619 /* microcode format is extended from prescott processors */
620 struct extended_signature {
626 struct extended_sigtable {
629 unsigned int reserved[3];
630 struct extended_signature sigs[0];
633 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
634 static inline void rep_nop(void)
636 __asm__ __volatile__("rep;nop": : :"memory");
639 #define cpu_relax() rep_nop()
641 /* generic versions from gas */
642 #define GENERIC_NOP1 ".byte 0x90\n"
643 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
644 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
645 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
646 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
647 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
648 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
649 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
652 #define K8_NOP1 GENERIC_NOP1
653 #define K8_NOP2 ".byte 0x66,0x90\n"
654 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
655 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
656 #define K8_NOP5 K8_NOP3 K8_NOP2
657 #define K8_NOP6 K8_NOP3 K8_NOP3
658 #define K8_NOP7 K8_NOP4 K8_NOP3
659 #define K8_NOP8 K8_NOP4 K8_NOP4
662 /* uses eax dependencies (arbitary choice) */
663 #define K7_NOP1 GENERIC_NOP1
664 #define K7_NOP2 ".byte 0x8b,0xc0\n"
665 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
666 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
667 #define K7_NOP5 K7_NOP4 ASM_NOP1
668 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
669 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
670 #define K7_NOP8 K7_NOP7 ASM_NOP1
673 #define ASM_NOP1 K8_NOP1
674 #define ASM_NOP2 K8_NOP2
675 #define ASM_NOP3 K8_NOP3
676 #define ASM_NOP4 K8_NOP4
677 #define ASM_NOP5 K8_NOP5
678 #define ASM_NOP6 K8_NOP6
679 #define ASM_NOP7 K8_NOP7
680 #define ASM_NOP8 K8_NOP8
681 #elif defined(CONFIG_MK7)
682 #define ASM_NOP1 K7_NOP1
683 #define ASM_NOP2 K7_NOP2
684 #define ASM_NOP3 K7_NOP3
685 #define ASM_NOP4 K7_NOP4
686 #define ASM_NOP5 K7_NOP5
687 #define ASM_NOP6 K7_NOP6
688 #define ASM_NOP7 K7_NOP7
689 #define ASM_NOP8 K7_NOP8
691 #define ASM_NOP1 GENERIC_NOP1
692 #define ASM_NOP2 GENERIC_NOP2
693 #define ASM_NOP3 GENERIC_NOP3
694 #define ASM_NOP4 GENERIC_NOP4
695 #define ASM_NOP5 GENERIC_NOP5
696 #define ASM_NOP6 GENERIC_NOP6
697 #define ASM_NOP7 GENERIC_NOP7
698 #define ASM_NOP8 GENERIC_NOP8
701 #define ASM_NOP_MAX 8
703 /* Prefetch instructions for Pentium III and AMD Athlon */
704 /* It's not worth to care about 3dnow! prefetches for the K6
705 because they are microcoded there and very slow.
706 However we don't do prefetches for pre XP Athlons currently
707 That should be fixed. */
708 #define ARCH_HAS_PREFETCH
709 static inline void prefetch(const void *x)
711 alternative_input(ASM_NOP4,
717 #define ARCH_HAS_PREFETCH
718 #define ARCH_HAS_PREFETCHW
719 #define ARCH_HAS_SPINLOCK_PREFETCH
721 /* 3dnow! prefetch to get an exclusive cache line. Useful for
722 spinlocks to avoid one state transition in the cache coherency protocol. */
723 static inline void prefetchw(const void *x)
725 alternative_input(ASM_NOP4,
730 #define spin_lock_prefetch(x) prefetchw(x)
732 extern void select_idle_routine(const struct cpuinfo_x86 *c);
734 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
736 extern unsigned long boot_option_idle_override;
737 extern void enable_sep_cpu(void);
738 extern int sysenter_setup(void);
740 #endif /* __ASM_I386_PROCESSOR_H */