2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/config.h>
21 #include <linux/threads.h>
22 #include <asm/percpu.h>
24 /* flag for disabling the tsc */
25 extern int tsc_disable;
31 #define desc_empty(desc) \
32 (!((desc)->a + (desc)->b))
34 #define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
63 int x86_cache_alignment; /* In bytes */
67 unsigned long loops_per_jiffy;
68 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
70 #define X86_VENDOR_INTEL 0
71 #define X86_VENDOR_CYRIX 1
72 #define X86_VENDOR_AMD 2
73 #define X86_VENDOR_UMC 3
74 #define X86_VENDOR_NEXGEN 4
75 #define X86_VENDOR_CENTAUR 5
76 #define X86_VENDOR_RISE 6
77 #define X86_VENDOR_TRANSMETA 7
78 #define X86_VENDOR_NSC 8
79 #define X86_VENDOR_NUM 9
80 #define X86_VENDOR_UNKNOWN 0xff
83 * capabilities of CPUs
86 extern struct cpuinfo_x86 boot_cpu_data;
87 extern struct cpuinfo_x86 new_cpu_data;
88 extern struct tss_struct doublefault_tss;
89 DECLARE_PER_CPU(struct tss_struct, init_tss);
92 extern struct cpuinfo_x86 cpu_data[];
93 #define current_cpu_data cpu_data[smp_processor_id()]
95 #define cpu_data (&boot_cpu_data)
96 #define current_cpu_data boot_cpu_data
99 extern char ignore_fpu_irq;
101 extern void identify_cpu(struct cpuinfo_x86 *);
102 extern void print_cpu_info(struct cpuinfo_x86 *);
103 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
104 extern void dodgy_tsc(void);
109 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
110 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
111 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
112 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
113 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
114 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
115 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
116 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
117 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
118 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
119 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
120 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
121 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
122 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
123 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
124 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
125 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
128 * Generic CPUID function
130 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
141 * CPUID functions returning a single datum
143 static inline unsigned int cpuid_eax(unsigned int op)
153 static inline unsigned int cpuid_ebx(unsigned int op)
155 unsigned int eax, ebx;
158 : "=a" (eax), "=b" (ebx)
163 static inline unsigned int cpuid_ecx(unsigned int op)
165 unsigned int eax, ecx;
168 : "=a" (eax), "=c" (ecx)
173 static inline unsigned int cpuid_edx(unsigned int op)
175 unsigned int eax, edx;
178 : "=a" (eax), "=d" (edx)
184 #define load_cr3(pgdir) \
185 asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)))
189 * Intel CPU features in CR4
191 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
192 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
193 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
194 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
195 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
196 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
197 #define X86_CR4_MCE 0x0040 /* Machine check enable */
198 #define X86_CR4_PGE 0x0080 /* enable global pages */
199 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
200 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
201 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
204 * Save the cr4 feature set we're using (ie
205 * Pentium 4MB enable and PPro Global page
206 * enable), so that any CPU's that boot up
207 * after us can get the correct flags.
209 extern unsigned long mmu_cr4_features;
211 static inline void set_in_cr4 (unsigned long mask)
213 mmu_cr4_features |= mask;
214 __asm__("movl %%cr4,%%eax\n\t"
221 static inline void clear_in_cr4 (unsigned long mask)
223 mmu_cr4_features &= ~mask;
224 __asm__("movl %%cr4,%%eax\n\t"
232 * NSC/Cyrix CPU configuration register indexes
235 #define CX86_PCR0 0x20
236 #define CX86_GCR 0xb8
237 #define CX86_CCR0 0xc0
238 #define CX86_CCR1 0xc1
239 #define CX86_CCR2 0xc2
240 #define CX86_CCR3 0xc3
241 #define CX86_CCR4 0xe8
242 #define CX86_CCR5 0xe9
243 #define CX86_CCR6 0xea
244 #define CX86_CCR7 0xeb
245 #define CX86_PCR1 0xf0
246 #define CX86_DIR0 0xfe
247 #define CX86_DIR1 0xff
248 #define CX86_ARR_BASE 0xc4
249 #define CX86_RCR_BASE 0xdc
252 * NSC/Cyrix CPU indexed register access macros
255 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
257 #define setCx86(reg, data) do { \
259 outb((data), 0x23); \
263 * Bus types (default is ISA, but people can check others with these..)
267 static inline void __monitor(const void *eax, unsigned long ecx,
270 /* "monitor %eax,%ecx,%edx;" */
272 ".byte 0x0f,0x01,0xc8;"
273 : :"a" (eax), "c" (ecx), "d"(edx));
276 static inline void __mwait(unsigned long eax, unsigned long ecx)
278 /* "mwait %eax,%ecx;" */
280 ".byte 0x0f,0x01,0xc9;"
281 : :"a" (eax), "c" (ecx));
284 /* from system description table in BIOS. Mostly for MCA use, but
285 others may find it useful. */
286 extern unsigned int machine_id;
287 extern unsigned int machine_submodel_id;
288 extern unsigned int BIOS_revision;
289 extern unsigned int mca_pentium_flag;
292 * User space process size: (3GB default).
294 #define __TASK_SIZE (__PAGE_OFFSET)
295 #define TASK_SIZE ((unsigned long)__TASK_SIZE)
297 /* This decides where the kernel will search for a free chunk of vm
298 * space during mmap's.
300 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE/3)
302 #define __HAVE_ARCH_ALIGN_STACK
303 extern unsigned long arch_align_stack(unsigned long sp);
305 #define HAVE_ARCH_PICK_MMAP_LAYOUT
307 #define HAVE_ARCH_PICK_MMAP_LAYOUT
312 #define IO_BITMAP_BITS 65536
313 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
314 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
315 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
316 #define INVALID_IO_BITMAP_OFFSET 0x8000
317 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
319 struct i387_fsave_struct {
327 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
328 long status; /* software status information */
331 struct i387_fxsave_struct {
342 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
343 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
345 } __attribute__ ((aligned (16)));
347 struct i387_soft_struct {
355 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
356 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
358 unsigned long entry_eip;
362 struct i387_fsave_struct fsave;
363 struct i387_fxsave_struct fxsave;
364 struct i387_soft_struct soft;
371 struct thread_struct;
374 unsigned short back_link,__blh;
376 unsigned short ss0,__ss0h;
378 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
380 unsigned short ss2,__ss2h;
383 unsigned long eflags;
384 unsigned long eax,ecx,edx,ebx;
389 unsigned short es, __esh;
390 unsigned short cs, __csh;
391 unsigned short ss, __ssh;
392 unsigned short ds, __dsh;
393 unsigned short fs, __fsh;
394 unsigned short gs, __gsh;
395 unsigned short ldt, __ldth;
396 unsigned short trace, io_bitmap_base;
398 * The extra 1 is there because the CPU will access an
399 * additional byte beyond the end of the IO permission
400 * bitmap. The extra byte must be all 1 bits, and must
401 * be within the limit.
403 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
405 * Cache the current maximum and the last task that used the bitmap:
407 unsigned long io_bitmap_max;
408 struct thread_struct *io_bitmap_owner;
410 * pads the TSS to be cacheline-aligned (size is 0x100)
412 unsigned long __cacheline_filler[35];
414 * .. and then another 0x100 bytes for emergency kernel stack
416 unsigned long stack[64];
417 } __attribute__((packed));
419 #define ARCH_MIN_TASKALIGN 16
421 #if ((1<<CONFIG_STACK_SIZE_SHIFT) < PAGE_SIZE)
422 #error (1<<CONFIG_STACK_SIZE_SHIFT) must be at least PAGE_SIZE
424 #define STACK_PAGE_COUNT ((1<<CONFIG_STACK_SIZE_SHIFT)/PAGE_SIZE)
426 struct thread_struct {
427 /* cached TLS descriptors. */
428 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
430 unsigned long sysenter_cs;
435 /* Hardware debugging registers */
436 unsigned long debugreg[8]; /* %%db0-7 debug registers */
438 unsigned long cr2, trap_no, error_code;
439 /* floating point info */
440 union i387_union i387;
441 /* virtual 86 mode info */
442 struct vm86_struct __user * vm86_info;
443 unsigned long screen_bitmap;
444 unsigned long v86flags, v86mask, saved_esp0;
445 unsigned int saved_fs, saved_gs;
447 unsigned long *io_bitmap_ptr;
448 /* max allowed port in the bitmap, in bytes: */
449 unsigned long io_bitmap_max;
452 #define INIT_THREAD { \
454 .sysenter_cs = __KERNEL_CS, \
455 .io_bitmap_ptr = NULL, \
459 * Note that the .io_bitmap member must be extra-big. This is because
460 * the CPU will access an additional byte beyond the end of the IO
461 * permission bitmap. The extra byte must be all 1 bits, and must
462 * be within the limit.
465 .esp0 = sizeof(init_stack) + (long)&init_stack, \
466 .ss0 = __KERNEL_DS, \
467 .ss1 = __KERNEL_CS, \
468 .ldt = GDT_ENTRY_LDT, \
469 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
470 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
473 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
475 tss->esp0 = thread->esp0;
476 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
477 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
478 tss->ss1 = thread->sysenter_cs;
479 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
483 #define start_thread(regs, new_eip, new_esp) do { \
484 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
486 regs->xds = __USER_DS; \
487 regs->xes = __USER_DS; \
488 regs->xss = __USER_DS; \
489 regs->xcs = __USER_CS; \
490 regs->eip = new_eip; \
491 regs->esp = new_esp; \
492 load_user_cs_desc(smp_processor_id(), current->mm); \
495 /* Forward declaration, a strange C thing */
499 /* Free all resources held by a thread. */
500 extern void release_thread(struct task_struct *);
502 /* Prepare to copy thread state - unlazy all lazy status */
503 extern void prepare_to_copy(struct task_struct *tsk);
506 * create a kernel thread without removing it from tasklists
508 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
510 extern unsigned long thread_saved_pc(struct task_struct *tsk);
511 void show_trace(struct task_struct *task, unsigned long *stack);
513 unsigned long get_wchan(struct task_struct *p);
515 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
516 #define KSTK_TOP(info) \
518 unsigned long *__ptr = (unsigned long *)(info); \
519 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
522 #define task_pt_regs(task) \
524 struct pt_regs *__regs__; \
525 __regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info); \
529 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
530 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
533 struct microcode_header {
541 unsigned int datasize;
542 unsigned int totalsize;
543 unsigned int reserved[3];
547 struct microcode_header hdr;
548 unsigned int bits[0];
551 typedef struct microcode microcode_t;
552 typedef struct microcode_header microcode_header_t;
554 /* microcode format is extended from prescott processors */
555 struct extended_signature {
561 struct extended_sigtable {
564 unsigned int reserved[3];
565 struct extended_signature sigs[0];
567 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
568 #define MICROCODE_IOCFREE _IO('6',0)
570 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
571 static inline void rep_nop(void)
573 __asm__ __volatile__("rep;nop": : :"memory");
576 #define cpu_relax() rep_nop()
578 /* generic versions from gas */
579 #define GENERIC_NOP1 ".byte 0x90\n"
580 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
581 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
582 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
583 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
584 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
585 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
586 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
589 #define K8_NOP1 GENERIC_NOP1
590 #define K8_NOP2 ".byte 0x66,0x90\n"
591 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
592 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
593 #define K8_NOP5 K8_NOP3 K8_NOP2
594 #define K8_NOP6 K8_NOP3 K8_NOP3
595 #define K8_NOP7 K8_NOP4 K8_NOP3
596 #define K8_NOP8 K8_NOP4 K8_NOP4
599 /* uses eax dependencies (arbitary choice) */
600 #define K7_NOP1 GENERIC_NOP1
601 #define K7_NOP2 ".byte 0x8b,0xc0\n"
602 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
603 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
604 #define K7_NOP5 K7_NOP4 ASM_NOP1
605 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
606 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
607 #define K7_NOP8 K7_NOP7 ASM_NOP1
610 #define ASM_NOP1 K8_NOP1
611 #define ASM_NOP2 K8_NOP2
612 #define ASM_NOP3 K8_NOP3
613 #define ASM_NOP4 K8_NOP4
614 #define ASM_NOP5 K8_NOP5
615 #define ASM_NOP6 K8_NOP6
616 #define ASM_NOP7 K8_NOP7
617 #define ASM_NOP8 K8_NOP8
618 #elif defined(CONFIG_MK7)
619 #define ASM_NOP1 K7_NOP1
620 #define ASM_NOP2 K7_NOP2
621 #define ASM_NOP3 K7_NOP3
622 #define ASM_NOP4 K7_NOP4
623 #define ASM_NOP5 K7_NOP5
624 #define ASM_NOP6 K7_NOP6
625 #define ASM_NOP7 K7_NOP7
626 #define ASM_NOP8 K7_NOP8
628 #define ASM_NOP1 GENERIC_NOP1
629 #define ASM_NOP2 GENERIC_NOP2
630 #define ASM_NOP3 GENERIC_NOP3
631 #define ASM_NOP4 GENERIC_NOP4
632 #define ASM_NOP5 GENERIC_NOP5
633 #define ASM_NOP6 GENERIC_NOP6
634 #define ASM_NOP7 GENERIC_NOP7
635 #define ASM_NOP8 GENERIC_NOP8
638 #define ASM_NOP_MAX 8
640 /* Prefetch instructions for Pentium III and AMD Athlon */
641 /* It's not worth to care about 3dnow! prefetches for the K6
642 because they are microcoded there and very slow.
643 However we don't do prefetches for pre XP Athlons currently
644 That should be fixed. */
645 #define ARCH_HAS_PREFETCH
646 extern inline void prefetch(const void *x)
648 alternative_input(ASM_NOP4,
654 #define ARCH_HAS_PREFETCH
655 #define ARCH_HAS_PREFETCHW
656 #define ARCH_HAS_SPINLOCK_PREFETCH
658 /* 3dnow! prefetch to get an exclusive cache line. Useful for
659 spinlocks to avoid one state transition in the cache coherency protocol. */
660 extern inline void prefetchw(const void *x)
662 alternative_input(ASM_NOP4,
667 #define spin_lock_prefetch(x) prefetchw(x)
669 extern void select_idle_routine(const struct cpuinfo_x86 *c);
671 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
673 #endif /* __ASM_I386_PROCESSOR_H */