4 * Copyright (C) 1999 Silicon Graphics, Inc.
5 * Copyright (C) Vijay Chander (vijay@engr.sgi.com)
6 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
7 * Copyright (C) 2000 Hewlett-Packard Co.
8 * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
12 #ifndef _ASM_IA64_MCA_ASM_H
13 #define _ASM_IA64_MCA_ASM_H
24 * This macro converts a instruction virtual address to a physical address
25 * Right now for simulation purposes the virtual addresses are
26 * direct mapped to physical addresses.
27 * 1. Lop off bits 61 thru 63 in the virtual address
29 #define INST_VA_TO_PA(addr) \
30 dep addr = 0, addr, 61, 3
32 * This macro converts a data virtual address to a physical address
33 * Right now for simulation purposes the virtual addresses are
34 * direct mapped to physical addresses.
35 * 1. Lop off bits 61 thru 63 in the virtual address
37 #define DATA_VA_TO_PA(addr) \
40 * This macro converts a data physical address to a virtual address
41 * Right now for simulation purposes the virtual addresses are
42 * direct mapped to physical addresses.
43 * 1. Put 0x7 in bits 61 thru 63.
45 #define DATA_PA_TO_VA(addr,temp) \
47 dep addr = temp, addr, 61, 3
50 * This macro jumps to the instruction at the given virtual address
51 * and starts execution in physical mode with all the address
52 * translations turned off.
53 * 1. Save the current psr
54 * 2. Make sure that all the upper 32 bits are off
56 * 3. Clear the interrupt enable and interrupt state collection bits
57 * in the psr before updating the ipsr and iip.
59 * 4. Turn off the instruction, data and rse translation bits of the psr
60 * and store the new value into ipsr
61 * Also make sure that the interrupts are disabled.
62 * Ensure that we are in little endian mode.
63 * [psr.{rt, it, dt, i, be} = 0]
65 * 5. Get the physical address corresponding to the virtual address
66 * of the next instruction bundle and put it in iip.
67 * (Using magic numbers 24 and 40 in the deposint instruction since
68 * the IA64_SDK code directly maps to lower 24bits as physical address
69 * from a virtual address).
71 * 6. Do an rfi to move the values from ipsr to psr and iip to ip.
73 #define PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
76 dep old_psr = 0, old_psr, 32, 32; \
81 mov temp2 = ar.bspstore; \
83 DATA_VA_TO_PA(temp2); \
85 mov temp1 = ar.rnat; \
87 mov ar.bspstore = temp2; \
89 mov ar.rnat = temp1; \
94 dep temp2 = 0, temp2, PSR_IC, 2; \
99 dep temp1 = 0, temp1, 32, 32; \
101 dep temp1 = 0, temp1, PSR_IT, 1; \
103 dep temp1 = 0, temp1, PSR_DT, 1; \
105 dep temp1 = 0, temp1, PSR_RT, 1; \
107 dep temp1 = 0, temp1, PSR_I, 1; \
109 dep temp1 = 0, temp1, PSR_IC, 1; \
111 dep temp1 = -1, temp1, PSR_MC, 1; \
113 mov cr.ipsr = temp1; \
115 LOAD_PHYSICAL(p0, temp2, start_addr); \
117 mov cr.iip = temp2; \
132 * This macro jumps to the instruction at the given virtual address
133 * and starts execution in virtual mode with all the address
134 * translations turned on.
135 * 1. Get the old saved psr
137 * 2. Clear the interrupt state collection bit in the current psr.
139 * 3. Set the instruction translation bit back in the old psr
140 * Note we have to do this since we are right now saving only the
141 * lower 32-bits of old psr.(Also the old psr has the data and
142 * rse translation bits on)
144 * 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1.
146 * 5. Reset the current thread pointer (r13).
148 * 6. Set iip to the virtual address of the next instruction bundle.
150 * 7. Do an rfi to move ipsr to psr and iip to ip.
153 #define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
156 mov old_psr = temp2; \
158 dep temp2 = 0, temp2, PSR_IC, 2; \
166 DATA_PA_TO_VA(r13,temp1); \
168 mov temp2 = ar.bspstore; \
170 DATA_PA_TO_VA(temp2,temp1); \
172 mov temp1 = ar.rnat; \
174 mov ar.bspstore = temp2; \
176 mov ar.rnat = temp1; \
178 mov temp1 = old_psr; \
182 dep temp1 = temp2, temp1, PSR_IC, 1; \
184 dep temp1 = temp2, temp1, PSR_IT, 1; \
186 dep temp1 = temp2, temp1, PSR_DT, 1; \
188 dep temp1 = temp2, temp1, PSR_RT, 1; \
190 dep temp1 = temp2, temp1, PSR_BN, 1; \
193 mov cr.ipsr = temp1; \
194 movl temp2 = start_addr; \
196 mov cr.iip = temp2; \
198 DATA_PA_TO_VA(sp, temp1); \
199 DATA_PA_TO_VA(gp, temp2); \
209 * The following offsets capture the order in which the
210 * RSE related registers from the old context are
211 * saved onto the new stack frame.
213 * +-----------------------+
214 * |NDIRTY [BSP - BSPSTORE]|
215 * +-----------------------+
217 * +-----------------------+
219 * +-----------------------+
221 * +-----------------------+
223 * +-----------------------+
225 * +-----------------------+ <-------- Bottom of new stack frame
227 #define rse_rsc_offset 0
228 #define rse_pfs_offset (rse_rsc_offset+0x08)
229 #define rse_ifs_offset (rse_pfs_offset+0x08)
230 #define rse_bspstore_offset (rse_ifs_offset+0x08)
231 #define rse_rnat_offset (rse_bspstore_offset+0x08)
232 #define rse_ndirty_offset (rse_rnat_offset+0x08)
237 * 1. Save old RSC onto the new stack frame
238 * 2. Save PFS onto new stack frame
239 * 3. Cover the old frame and start a new frame.
240 * 4. Save IFS onto new stack frame
241 * 5. Save the old BSPSTORE on the new stack frame
242 * 6. Save the old RNAT on the new stack frame
243 * 7. Write BSPSTORE with the new backing store pointer
244 * 8. Read and save the new BSP to calculate the #dirty registers
245 * NOTE: Look at pages 11-10, 11-11 in PRM Vol 2
247 #define rse_switch_context(temp,p_stackframe,p_bspstore) \
250 st8 [p_stackframe]=temp,8;; \
252 st8 [p_stackframe]=temp,8; \
255 st8 [p_stackframe]=temp,8;; \
256 mov temp=ar.bspstore;; \
257 st8 [p_stackframe]=temp,8;; \
259 st8 [p_stackframe]=temp,8; \
260 mov ar.bspstore=p_bspstore;; \
262 sub temp=temp,p_bspstore;; \
263 st8 [p_stackframe]=temp,8;;
267 * 1. Allocate a zero-sized frame
268 * 2. Store the number of dirty registers RSC.loadrs field
269 * 3. Issue a loadrs to insure that any registers from the interrupted
270 * context which were saved on the new stack frame have been loaded
271 * back into the stacked registers
272 * 4. Restore BSPSTORE
279 #define rse_return_context(psr_mask_reg,temp,p_stackframe) \
281 alloc temp=ar.pfs,0,0,0,0; \
282 add p_stackframe=rse_ndirty_offset,p_stackframe;; \
283 ld8 temp=[p_stackframe];; \
287 add p_stackframe=-rse_ndirty_offset+rse_bspstore_offset,p_stackframe;;\
288 ld8 temp=[p_stackframe];; \
289 mov ar.bspstore=temp;; \
290 add p_stackframe=-rse_bspstore_offset+rse_rnat_offset,p_stackframe;;\
291 ld8 temp=[p_stackframe];; \
293 add p_stackframe=-rse_rnat_offset+rse_pfs_offset,p_stackframe;; \
294 ld8 temp=[p_stackframe];; \
296 add p_stackframe=-rse_pfs_offset+rse_ifs_offset,p_stackframe;; \
297 ld8 temp=[p_stackframe];; \
299 add p_stackframe=-rse_ifs_offset+rse_rsc_offset,p_stackframe;; \
300 ld8 temp=[p_stackframe];; \
303 or temp=temp,psr_mask_reg;; \
306 add temp=0x30,temp;; \
311 #endif /* _ASM_IA64_MCA_ASM_H */