2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 1992-1999,2001-2004 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_IA64_SN_ADDRS_H
10 #define _ASM_IA64_SN_ADDRS_H
12 #include <asm/percpu.h>
13 #include <asm/sn/types.h>
14 #include <asm/sn/pda.h>
17 * Memory/SHUB Address Format:
18 * +-+---------+--+--------------+
19 * |0| NASID |AS| NodeOffset |
20 * +-+---------+--+--------------+
22 * NASID: (low NASID bit is 0) Memory and SHUB MMRs
23 * AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
24 * 00: Local Resources and MMR space
25 * Top bit of NodeOffset
26 * 0: Local resources space
28 * 0: IA64/NT compatibility space
30 * 4: Local memory, regardless of local node id
34 * 11: Cacheable memory space.
36 * NodeOffset: byte offset
40 * +-+----------+--+--------------+
41 * |0| NASID |AS| Nodeoffset |
42 * +-+----------+--+--------------+
44 * NASID: (low NASID bit is 1) TIO
45 * AS: 2-bit Chiplet Identifier
46 * 00: TIO LB (Indicates TIO MMR access.)
47 * 01: TIO ICE (indicates coretalk space access.)
49 * NodeOffset: top bit must be set.
52 * Note that in both of the above address formats, the low
53 * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
58 * Define basic shift & mask constants for manipulating NASIDs and AS values.
60 #define NASID_BITMASK (pda->nasid_bitmask)
61 #define NASID_SHIFT (pda->nasid_shift)
62 #define AS_SHIFT (pda->as_shift)
63 #define AS_BITMASK 0x3UL
65 #define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT)
66 #define AS_MASK ((u64)AS_BITMASK << AS_SHIFT)
67 #define REGION_BITS 0xe000000000000000UL
71 * AS values. These are the same on both SHUB1 & SHUB2.
73 #define AS_GET_VAL 1UL
74 #define AS_AMO_VAL 2UL
75 #define AS_CAC_VAL 3UL
76 #define AS_GET_SPACE (AS_GET_VAL << AS_SHIFT)
77 #define AS_AMO_SPACE (AS_AMO_VAL << AS_SHIFT)
78 #define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT)
82 * Base addresses for various address ranges.
84 #define CACHED 0xe000000000000000UL
85 #define UNCACHED 0xc000000000000000UL
86 #define UNCACHED_PHYS 0x8000000000000000UL
90 * Virtual Mode Local & Global MMR space.
92 #define SH1_LOCAL_MMR_OFFSET 0x8000000000UL
93 #define SH2_LOCAL_MMR_OFFSET 0x0200000000UL
94 #define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
95 #define LOCAL_MMR_SPACE (UNCACHED | LOCAL_MMR_OFFSET)
96 #define LOCAL_PHYS_MMR_SPACE (UNCACHED_PHYS | LOCAL_MMR_OFFSET)
98 #define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL
99 #define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL
100 #define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
101 #define GLOBAL_MMR_SPACE (UNCACHED | GLOBAL_MMR_OFFSET)
104 * Physical mode addresses
106 #define GLOBAL_PHYS_MMR_SPACE (UNCACHED_PHYS | GLOBAL_MMR_OFFSET)
110 * Clear region & AS bits.
112 #define TO_PHYS_MASK (~(REGION_BITS | AS_MASK))
116 * Misc NASID manipulation.
118 #define NASID_SPACE(n) ((u64)(n) << NASID_SHIFT)
119 #define REMOTE_ADDR(n,a) (NASID_SPACE(n) | (a))
120 #define NODE_OFFSET(x) ((x) & (NODE_ADDRSPACE_SIZE - 1))
121 #define NODE_ADDRSPACE_SIZE (1UL << AS_SHIFT)
122 #define NASID_GET(x) (int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
123 #define LOCAL_MMR_ADDR(a) (LOCAL_MMR_SPACE | (a))
124 #define GLOBAL_MMR_ADDR(n,a) (GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
125 #define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
126 #define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a))
127 #define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
130 /* non-II mmr's start at top of big window space (4G) */
131 #define BWIN_TOP 0x0000000100000000UL
134 * general address defines
136 #define CAC_BASE (CACHED | AS_CAC_SPACE)
137 #define AMO_BASE (UNCACHED | AS_AMO_SPACE)
138 #define GET_BASE (CACHED | AS_GET_SPACE)
141 * Convert Memory addresses between various addressing modes.
143 #define TO_PHYS(x) (TO_PHYS_MASK & (x))
144 #define TO_CAC(x) (CAC_BASE | TO_PHYS(x))
145 #define TO_AMO(x) (AMO_BASE | TO_PHYS(x))
146 #define TO_GET(x) (GET_BASE | TO_PHYS(x))
150 * Covert from processor physical address to II/TIO physical address:
151 * II - squeeze out the AS bits
152 * TIO- requires a chiplet id in bits 38-39. For DMA to memory,
153 * the chiplet id is zero. If we implement TIO-TIO dma, we might need
154 * to insert a chiplet id into this macro. However, it is our belief
155 * right now that this chiplet id will be ICE, which is also zero.
157 #define PHYS_TO_TIODMA(x) ( (((u64)(x) & NASID_MASK) << 2) | NODE_OFFSET(x))
158 #define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
162 * The following definitions pertain to the IO special address
163 * space. They define the location of the big and little windows
166 #define BWIN_SIZE_BITS 29 /* big window size: 512M */
167 #define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */
168 #define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
169 : RAW_NODE_SWIN_BASE(n, w))
170 #define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n))
171 #define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
172 #define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
173 #define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
174 #define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
175 #define BWIN_WIDGET_MASK 0x7
176 #define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
178 #define TIO_BWIN_WINDOW_SELECT_MASK 0x7
179 #define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
184 * The following definitions pertain to the IO special address
185 * space. They define the location of the big and little windows
189 #define SWIN_SIZE_BITS 24
190 #define SWIN_WIDGET_MASK 0xF
192 #define TIO_SWIN_SIZE_BITS 28
193 #define TIO_SWIN_SIZE (1UL << TIO_SWIN_SIZE_BITS)
194 #define TIO_SWIN_WIDGET_MASK 0x3
197 * Convert smallwindow address to xtalk address.
199 * 'addr' can be physical or virtual address, but will be converted
200 * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
202 #define SWIN_WIDGETNUM(x) (((x) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
203 #define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
207 * The following macros produce the correct base virtual address for
208 * the hub registers. The REMOTE_HUB_* macro produce
209 * the address for the specified hub's registers. The intent is
210 * that the appropriate PI, MD, NI, or II register would be substituted
214 * When certain Hub chip workaround are defined, it's not sufficient
215 * to dereference the *_HUB_ADDR() macros. You should instead use
216 * HUB_L() and HUB_S() if you must deal with pointers to hub registers.
217 * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
218 * They're always safe.
220 #define REMOTE_HUB_ADDR(n,x) \
223 ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
225 (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))\
226 : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
230 #define HUB_L(x) (*((volatile typeof(*x) *)x))
231 #define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
233 #define REMOTE_HUB_L(n, a) HUB_L(REMOTE_HUB_ADDR((n), (a)))
234 #define REMOTE_HUB_S(n, a, d) HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
237 #endif /* _ASM_IA64_SN_ADDRS_H */