2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_IA64_SN_INTR_H
10 #define _ASM_IA64_SN_INTR_H
12 #define SGI_UART_VECTOR (0xe9)
13 #define SGI_PCIBR_ERROR (0x33)
15 // These two IRQ's are used by partitioning.
16 #define SGI_XPC_ACTIVATE (0x30)
17 #define SGI_II_ERROR (0x31)
18 #define SGI_XBOW_ERROR (0x32)
19 #define SGI_PCIBR_ERROR (0x33)
20 #define SGI_ACPI_SCI_INT (0x34)
21 #define SGI_TIO_ERROR (0x36)
22 #define SGI_XPC_NOTIFY (0xe7)
24 #define SN2_IRQ_RESERVED (0x1)
25 #define SN2_IRQ_CONNECTED (0x2)
26 #define SN2_IRQ_SHARED (0x4)
28 // The SN PROM irq struct
30 struct sn_irq_info *irq_next; /* sharing irq list */
31 short irq_nasid; /* Nasid IRQ is assigned to */
32 int irq_slice; /* slice IRQ is assigned to */
33 int irq_cpuid; /* kernel logical cpuid */
34 int irq_irq; /* the IRQ number */
35 int irq_int_bit; /* Bridge interrupt pin */
36 uint64_t irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
37 int irq_bridge_type;/* pciio asic type (pciio.h) */
38 void *irq_bridge; /* bridge generating irq */
39 void *irq_pciioinfo; /* associated pciio_info_t */
40 int irq_last_intr; /* For Shub lb lost intr WAR */
41 int irq_cookie; /* unique cookie */
42 int irq_flags; /* flags */
43 int irq_share_cnt; /* num devices sharing IRQ */
46 extern void sn_send_IPI_phys(int, long, int, int);
48 #define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
50 #endif /* _ASM_IA64_SN_INTR_H */