2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_IA64_SN_ROUTER_H
10 #define _ASM_IA64_SN_ROUTER_H
13 * Router Register definitions
15 * Macro argument _L always stands for a link number (1 to 8, inclusive).
20 #include <asm/sn/vector.h>
21 #include <asm/sn/slotnum.h>
22 #include <asm/sn/arch.h>
23 #include <asm/sn/sgi.h>
25 typedef uint64_t router_reg_t;
27 #define MAX_ROUTERS 64
29 #define MAX_ROUTER_PATH 80
31 #define ROUTER_REG_CAST (volatile router_reg_t *)
32 typedef signed char port_no_t; /* Type for router port number */
36 #define ROUTERREG_CAST
38 #endif /* __ASSEMBLY__ */
40 #define MAX_ROUTER_PORTS 8 /* Max. number of ports on a router */
42 #define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1) /* for 0 based references */
44 #define PORT_INVALID -1 /* Invalid port number */
46 #define IS_META(_rp) ((_rp)->flags & PCFG_ROUTER_META)
48 #define IS_REPEATER(_rp)((_rp)->flags & PCFG_ROUTER_REPEATER)
51 * RR_TURN makes a given number of clockwise turns (0 to 7) from an inport
52 * port to generate an output port.
54 * RR_DISTANCE returns the number of turns necessary (0 to 7) to go from
55 * an input port (_L1 = 1 to 8) to an output port ( _L2 = 1 to 8).
57 * These are written to work on unsigned data.
60 #define RR_TURN(_L, count) ((_L) + (count) > MAX_ROUTER_PORTS ? \
61 (_L) + (count) - MAX_ROUTER_PORTS : \
64 #define RR_DISTANCE(_LS, _LD) ((_LD) >= (_LS) ? \
66 (_LD) + MAX_ROUTER_PORTS - (_LS))
68 /* Router register addresses */
70 #define RR_STATUS_REV_ID 0x00000 /* Status register and Revision ID */
71 #define RR_PORT_RESET 0x00008 /* Multiple port reset */
72 #define RR_PROT_CONF 0x00010 /* Inter-partition protection conf. */
73 #define RR_GLOBAL_PORT_DEF 0x00018 /* Global Port definitions */
74 #define RR_GLOBAL_PARMS0 0x00020 /* Parameters shared by all 8 ports */
75 #define RR_GLOBAL_PARMS1 0x00028 /* Parameters shared by all 8 ports */
76 #define RR_DIAG_PARMS 0x00030 /* Parameters for diag. testing */
77 #define RR_DEBUG_ADDR 0x00038 /* Debug address select - debug port*/
78 #define RR_LB_TO_L2 0x00040 /* Local Block to L2 cntrl intf reg */
79 #define RR_L2_TO_LB 0x00048 /* L2 cntrl intf to Local Block reg */
80 #define RR_JBUS_CONTROL 0x00050 /* read/write timing for JBUS intf */
82 #define RR_SCRATCH_REG0 0x00100 /* Scratch 0 is 64 bits */
83 #define RR_SCRATCH_REG1 0x00108 /* Scratch 1 is 64 bits */
84 #define RR_SCRATCH_REG2 0x00110 /* Scratch 2 is 64 bits */
85 #define RR_SCRATCH_REG3 0x00118 /* Scratch 3 is 1 bit */
86 #define RR_SCRATCH_REG4 0x00120 /* Scratch 4 is 1 bit */
88 #define RR_JBUS0(_D) (((_D) & 0x7) << 3 | 0x00200) /* JBUS0 addresses */
89 #define RR_JBUS1(_D) (((_D) & 0x7) << 3 | 0x00240) /* JBUS1 addresses */
91 #define RR_SCRATCH_REG0_WZ 0x00500 /* Scratch 0 is 64 bits */
92 #define RR_SCRATCH_REG1_WZ 0x00508 /* Scratch 1 is 64 bits */
93 #define RR_SCRATCH_REG2_WZ 0x00510 /* Scratch 2 is 64 bits */
94 #define RR_SCRATCH_REG3_SZ 0x00518 /* Scratch 3 is 1 bit */
95 #define RR_SCRATCH_REG4_SZ 0x00520 /* Scratch 4 is 1 bit */
97 #define RR_VECTOR_HW_BAR(context) (0x08000 | (context)<<3) /* barrier config registers */
98 /* Port-specific registers (_L is the link number from 1 to 8) */
100 #define RR_PORT_PARMS(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0000) /* LLP parameters */
101 #define RR_STATUS_ERROR(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0008) /* Port-related errs */
102 #define RR_CHANNEL_TEST(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0010) /* Port LLP chan test */
103 #define RR_RESET_MASK(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0018) /* Remote reset mask */
104 #define RR_HISTOGRAM0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0020) /* Port usage histgrm */
105 #define RR_HISTOGRAM1(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0028) /* Port usage histgrm */
106 #define RR_HISTOGRAM0_WC(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0030) /* Port usage histgrm */
107 #define RR_HISTOGRAM1_WC(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0038) /* Port usage histgrm */
108 #define RR_ERROR_CLEAR(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0088) /* Read/clear errors */
109 #define RR_GLOBAL_TABLE0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0100) /* starting address of global table for this port */
110 #define RR_GLOBAL_TABLE(_L, _x) (RR_GLOBAL_TABLE0(_L) + ((_x) << 3))
111 #define RR_LOCAL_TABLE0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0200) /* starting address of local table for this port */
112 #define RR_LOCAL_TABLE(_L, _x) (RR_LOCAL_TABLE0(_L) + ((_x) << 3))
114 #define RR_META_ENTRIES 16
116 #define RR_LOCAL_ENTRIES 128
119 * RR_STATUS_REV_ID mask and shift definitions
122 #define RSRI_INPORT_SHFT 52
123 #define RSRI_INPORT_MASK (0xfUL << 52)
124 #define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L))
125 #define RSRI_LINKWORKING(_L) (1UL << (35 + 2 * (_L)))
126 #define RSRI_LINKRESETFAIL(_L) (1UL << (34 + 2 * (_L)))
127 #define RSRI_LSTAT_SHFT(_L) (34 + 2 * (_L))
128 #define RSRI_LSTAT_MASK(_L) (0x3UL << 34 + 2 * (_L))
129 #define RSRI_LOCALSBERROR (1UL << 35)
130 #define RSRI_LOCALSTUCK (1UL << 34)
131 #define RSRI_LOCALBADVEC (1UL << 33)
132 #define RSRI_LOCALTAILERR (1UL << 32)
133 #define RSRI_LOCAL_SHFT 32
134 #define RSRI_LOCAL_MASK (0xfUL << 32)
135 #define RSRI_CHIPREV_SHFT 28
136 #define RSRI_CHIPREV_MASK (0xfUL << 28)
137 #define RSRI_CHIPID_SHFT 12
138 #define RSRI_CHIPID_MASK (0xffffUL << 12)
139 #define RSRI_MFGID_SHFT 1
140 #define RSRI_MFGID_MASK (0x7ffUL << 1)
142 #define RSRI_LSTAT_WENTDOWN 0
143 #define RSRI_LSTAT_RESETFAIL 1
144 #define RSRI_LSTAT_LINKUP 2
145 #define RSRI_LSTAT_NOTUSED 3
148 * RR_PORT_RESET mask definitions
151 #define RPRESET_WARM (1UL << 9)
152 #define RPRESET_LINK(_L) (1UL << (_L))
153 #define RPRESET_LOCAL 1UL
156 * RR_PROT_CONF mask and shift definitions
159 #define RPCONF_DIRCMPDIS_SHFT 13
160 #define RPCONF_DIRCMPDIS_MASK (1UL << 13)
161 #define RPCONF_FORCELOCAL (1UL << 12)
162 #define RPCONF_FLOCAL_SHFT 12
163 #define RPCONF_METAID_SHFT 8
164 #define RPCONF_METAID_MASK (0xfUL << 8)
165 #define RPCONF_RESETOK(_L) (1UL << ((_L) - 1))
168 * RR_GLOBAL_PORT_DEF mask and shift definitions
171 #define RGPD_MGLBLNHBR_ID_SHFT 12 /* -global neighbor ID */
172 #define RGPD_MGLBLNHBR_ID_MASK (0xfUL << 12)
173 #define RGPD_MGLBLNHBR_VLD_SHFT 11 /* -global neighbor Valid */
174 #define RGPD_MGLBLNHBR_VLD_MASK (0x1UL << 11)
175 #define RGPD_MGLBLPORT_SHFT 8 /* -global neighbor Port */
176 #define RGPD_MGLBLPORT_MASK (0x7UL << 8)
177 #define RGPD_PGLBLNHBR_ID_SHFT 4 /* +global neighbor ID */
178 #define RGPD_PGLBLNHBR_ID_MASK (0xfUL << 4)
179 #define RGPD_PGLBLNHBR_VLD_SHFT 3 /* +global neighbor Valid */
180 #define RGPD_PGLBLNHBR_VLD_MASK (0x1UL << 3)
181 #define RGPD_PGLBLPORT_SHFT 0 /* +global neighbor Port */
182 #define RGPD_PGLBLPORT_MASK (0x7UL << 0)
184 #define GLBL_PARMS_REGS 2 /* Two Global Parms registers */
187 * RR_GLOBAL_PARMS0 mask and shift definitions
190 #define RGPARM0_ARB_VALUE_SHFT 54 /* Local Block Arbitration State */
191 #define RGPARM0_ARB_VALUE_MASK (0x7UL << 54)
192 #define RGPARM0_ROTATEARB_SHFT 53 /* Rotate Local Block Arbitration */
193 #define RGPARM0_ROTATEARB_MASK (1UL << 53)
194 #define RGPARM0_FAIREN_SHFT 52 /* Fairness logic Enable */
195 #define RGPARM0_FAIREN_MASK (1UL << 52)
196 #define RGPARM0_LOCGNTTO_SHFT 40 /* Local grant timeout */
197 #define RGPARM0_LOCGNTTO_MASK (0xfffUL << 40)
198 #define RGPARM0_DATELINE_SHFT 38 /* Dateline crossing router */
199 #define RGPARM0_DATELINE_MASK (1UL << 38)
200 #define RGPARM0_MAXRETRY_SHFT 28 /* Max retry count */
201 #define RGPARM0_MAXRETRY_MASK (0x3ffUL << 28)
202 #define RGPARM0_URGWRAP_SHFT 20 /* Urgent wrap */
203 #define RGPARM0_URGWRAP_MASK (0xffUL << 20)
204 #define RGPARM0_DEADLKTO_SHFT 16 /* Deadlock timeout */
205 #define RGPARM0_DEADLKTO_MASK (0xfUL << 16)
206 #define RGPARM0_URGVAL_SHFT 12 /* Urgent value */
207 #define RGPARM0_URGVAL_MASK (0xfUL << 12)
208 #define RGPARM0_VCHSELEN_SHFT 11 /* VCH_SEL_EN */
209 #define RGPARM0_VCHSELEN_MASK (1UL << 11)
210 #define RGPARM0_LOCURGTO_SHFT 9 /* Local urgent timeout */
211 #define RGPARM0_LOCURGTO_MASK (0x3UL << 9)
212 #define RGPARM0_TAILVAL_SHFT 5 /* Tail value */
213 #define RGPARM0_TAILVAL_MASK (0xfUL << 5)
214 #define RGPARM0_CLOCK_SHFT 1 /* Global clock select */
215 #define RGPARM0_CLOCK_MASK (0xfUL << 1)
216 #define RGPARM0_BYPEN_SHFT 0
217 #define RGPARM0_BYPEN_MASK 1UL /* Bypass enable */
220 * RR_GLOBAL_PARMS1 shift and mask definitions
223 #define RGPARM1_TTOWRAP_SHFT 12 /* Tail timeout wrap */
224 #define RGPARM1_TTOWRAP_MASK (0xfffffUL << 12)
225 #define RGPARM1_AGERATE_SHFT 8 /* Age rate */
226 #define RGPARM1_AGERATE_MASK (0xfUL << 8)
227 #define RGPARM1_JSWSTAT_SHFT 0 /* JTAG Sw Register bits */
228 #define RGPARM1_JSWSTAT_MASK (0xffUL << 0)
231 * RR_DIAG_PARMS mask and shift definitions
234 #define RDPARM_ABSHISTOGRAM (1UL << 17) /* Absolute histgrm */
235 #define RDPARM_DEADLOCKRESET (1UL << 16) /* Reset on deadlck */
236 #define RDPARM_DISABLE(_L) (1UL << ((_L) + 7))
237 #define RDPARM_SENDERROR(_L) (1UL << ((_L) - 1))
240 * RR_DEBUG_ADDR mask and shift definitions
243 #define RDA_DATA_SHFT 10 /* Observed debug data */
244 #define RDA_DATA_MASK (0xffffUL << 10)
245 #define RDA_ADDR_SHFT 0 /* debug address for data */
246 #define RDA_ADDR_MASK (0x3ffUL << 0)
249 * RR_LB_TO_L2 mask and shift definitions
252 #define RLBTOL2_DATA_VLD_SHFT 32 /* data is valid for JTAG controller */
253 #define RLBTOL2_DATA_VLD_MASK (1UL << 32)
254 #define RLBTOL2_DATA_SHFT 0 /* data bits for JTAG controller */
255 #define RLBTOL2_DATA_MASK 0xffffffffUL
258 * RR_L2_TO_LB mask and shift definitions
261 #define RL2TOLB_DATA_VLD_SHFT 33 /* data is valid from JTAG controller */
262 #define RL2TOLB_DATA_VLD_MASK (1UL << 33)
263 #define RL2TOLB_PARITY_SHFT 32 /* sw implemented parity for data */
264 #define RL2TOLB_PARITY_MASK (1UL << 32)
265 #define RL2TOLB_DATA_SHFT 0 /* data bits from JTAG controller */
266 #define RL2TOLB_DATA_MASK 0xffffffffUL
269 * RR_JBUS_CONTROL mask and shift definitions
272 #define RJC_POS_BITS_SHFT 20 /* Router position bits */
273 #define RJC_POS_BITS_MASK (0xfUL << 20)
274 #define RJC_RD_DATA_STROBE_SHFT 16 /* count when read data is strobed in */
275 #define RJC_RD_DATA_STROBE_MASK (0xfUL << 16)
276 #define RJC_WE_OE_HOLD_SHFT 8 /* time OE or WE is held */
277 #define RJC_WE_OE_HOLD_MASK (0xffUL << 8)
278 #define RJC_ADDR_SET_HLD_SHFT 0 /* time address driven around OE/WE */
279 #define RJC_ADDR_SET_HLD_MASK 0xffUL
282 * RR_SCRATCH_REGx mask and shift definitions
283 * note: these fields represent a software convention, and are not
284 * understood/interpreted by the hardware.
287 #define RSCR0_BOOTED_SHFT 63
288 #define RSCR0_BOOTED_MASK (0x1UL << RSCR0_BOOTED_SHFT)
289 #define RSCR0_LOCALID_SHFT 56
290 #define RSCR0_LOCALID_MASK (0x7fUL << RSCR0_LOCALID_SHFT)
291 #define RSCR0_UNUSED_SHFT 48
292 #define RSCR0_UNUSED_MASK (0xffUL << RSCR0_UNUSED_SHFT)
293 #define RSCR0_NIC_SHFT 0
294 #define RSCR0_NIC_MASK 0xffffffffffffUL
296 #define RSCR1_MODID_SHFT 0
297 #define RSCR1_MODID_MASK 0xffffUL
300 * RR_VECTOR_HW_BAR mask and shift definitions
303 #define BAR_TX_SHFT 27 /* Barrier in trans(m)it when read */
304 #define BAR_TX_MASK (1UL << BAR_TX_SHFT)
305 #define BAR_VLD_SHFT 26 /* Valid Configuration */
306 #define BAR_VLD_MASK (1UL << BAR_VLD_SHFT)
307 #define BAR_SEQ_SHFT 24 /* Sequence number */
308 #define BAR_SEQ_MASK (3UL << BAR_SEQ_SHFT)
309 #define BAR_LEAFSTATE_SHFT 18 /* Leaf State */
310 #define BAR_LEAFSTATE_MASK (0x3fUL << BAR_LEAFSTATE_SHFT)
311 #define BAR_PARENT_SHFT 14 /* Parent Port */
312 #define BAR_PARENT_MASK (0xfUL << BAR_PARENT_SHFT)
313 #define BAR_CHILDREN_SHFT 6 /* Child Select port bits */
314 #define BAR_CHILDREN_MASK (0xffUL << BAR_CHILDREN_SHFT)
315 #define BAR_LEAFCOUNT_SHFT 0 /* Leaf Count to trigger parent */
316 #define BAR_LEAFCOUNT_MASK 0x3fUL
319 * RR_PORT_PARMS(_L) mask and shift definitions
322 #define RPPARM_MIPRESETEN_SHFT 29 /* Message In Progress reset enable */
323 #define RPPARM_MIPRESETEN_MASK (0x1UL << 29)
324 #define RPPARM_UBAREN_SHFT 28 /* Enable user barrier requests */
325 #define RPPARM_UBAREN_MASK (0x1UL << 28)
326 #define RPPARM_OUTPDTO_SHFT 24 /* Output Port Deadlock TO value */
327 #define RPPARM_OUTPDTO_MASK (0xfUL << 24)
328 #define RPPARM_PORTMATE_SHFT 21 /* Port Mate for the port */
329 #define RPPARM_PORTMATE_MASK (0x7UL << 21)
330 #define RPPARM_HISTEN_SHFT 20 /* Histogram counter enable */
331 #define RPPARM_HISTEN_MASK (0x1UL << 20)
332 #define RPPARM_HISTSEL_SHFT 18
333 #define RPPARM_HISTSEL_MASK (0x3UL << 18)
334 #define RPPARM_DAMQHS_SHFT 16
335 #define RPPARM_DAMQHS_MASK (0x3UL << 16)
336 #define RPPARM_NULLTO_SHFT 10
337 #define RPPARM_NULLTO_MASK (0x3fUL << 10)
338 #define RPPARM_MAXBURST_SHFT 0
339 #define RPPARM_MAXBURST_MASK 0x3ffUL
342 * NOTE: Normally the kernel tracks only UTILIZATION statistics.
343 * The other 2 should not be used, except during any experimentation
346 #define RPPARM_HISTSEL_AGE 0 /* Histogram age characterization. */
347 #define RPPARM_HISTSEL_UTIL 1 /* Histogram link utilization */
348 #define RPPARM_HISTSEL_DAMQ 2 /* Histogram DAMQ characterization. */
351 * RR_STATUS_ERROR(_L) and RR_ERROR_CLEAR(_L) mask and shift definitions
353 #define RSERR_POWERNOK (1UL << 38)
354 #define RSERR_PORT_DEADLOCK (1UL << 37)
355 #define RSERR_WARMRESET (1UL << 36)
356 #define RSERR_LINKRESET (1UL << 35)
357 #define RSERR_RETRYTIMEOUT (1UL << 34)
358 #define RSERR_FIFOOVERFLOW (1UL << 33)
359 #define RSERR_ILLEGALPORT (1UL << 32)
360 #define RSERR_DEADLOCKTO_SHFT 28
361 #define RSERR_DEADLOCKTO_MASK (0xfUL << 28)
362 #define RSERR_RECVTAILTO_SHFT 24
363 #define RSERR_RECVTAILTO_MASK (0xfUL << 24)
364 #define RSERR_RETRYCNT_SHFT 16
365 #define RSERR_RETRYCNT_MASK (0xffUL << 16)
366 #define RSERR_CBERRCNT_SHFT 8
367 #define RSERR_CBERRCNT_MASK (0xffUL << 8)
368 #define RSERR_SNERRCNT_SHFT 0
369 #define RSERR_SNERRCNT_MASK (0xffUL << 0)
372 #define PORT_STATUS_UP (1 << 0) /* Router link up */
373 #define PORT_STATUS_FENCE (1 << 1) /* Router link fenced */
374 #define PORT_STATUS_RESETFAIL (1 << 2) /* Router link didnot
375 * come out of reset */
376 #define PORT_STATUS_DISCFAIL (1 << 3) /* Router link failed after
377 * out of reset but before
381 #define PORT_STATUS_KERNFAIL (1 << 4) /* Router link failed
382 * after reset and the
386 #define PORT_STATUS_UNDEF (1 << 5) /* Unable to pinpoint
387 * why the router link
390 #define PROBE_RESULT_BAD -1 /* Set if any of the router
391 * links failed after reset
393 #define PROBE_RESULT_GOOD 0 /* Set if all the router links
394 * which came out of reset
398 /* Should be enough for 256 CPUs */
399 #define MAX_RTR_BREADTH 64 /* Max # of routers possible */
401 /* Get the require set of bits in a var. corr to a sequence of bits */
402 #define GET_FIELD(var, fname) \
403 ((var) >> fname##_SHFT & fname##_MASK >> fname##_SHFT)
404 /* Set the require set of bits in a var. corr to a sequence of bits */
405 #define SET_FIELD(var, fname, fval) \
406 ((var) = (var) & ~fname##_MASK | (uint64_t) (fval) << fname##_SHFT)
411 typedef struct router_map_ent_s {
417 struct rr_status_error_fmt {
418 uint64_t rserr_unused : 30,
419 rserr_fifooverflow : 1,
420 rserr_illegalport : 1,
421 rserr_deadlockto : 4,
422 rserr_recvtailto : 4,
429 * This type is used to store "absolute" counts of router events
431 typedef int router_count_t;
433 /* All utilizations are on a scale from 0 - 1023. */
434 #define RP_BYPASS_UTIL 0
435 #define RP_RCV_UTIL 1
436 #define RP_SEND_UTIL 2
437 #define RP_TOTAL_PKTS 3 /* Free running clock/packet counter */
439 #define RP_NUM_UTILS 3
441 #define RP_HIST_REGS 2
442 #define RP_NUM_BUCKETS 4
443 #define RP_HIST_TYPES 3
451 #define RR_UTIL_SCALE 1024
454 * Router port-oriented information
456 typedef struct router_port_info_s {
457 router_reg_t rp_histograms[RP_HIST_REGS];/* Port usage info */
458 router_reg_t rp_port_error; /* Port error info */
459 router_count_t rp_retry_errors; /* Total retry errors */
460 router_count_t rp_sn_errors; /* Total sn errors */
461 router_count_t rp_cb_errors; /* Total cb errors */
462 int rp_overflows; /* Total count overflows */
463 int rp_excess_err; /* Port has excessive errors */
464 ushort rp_util[RP_NUM_BUCKETS];/* Port utilization */
465 } router_port_info_t;
467 #define ROUTER_INFO_VERSION 7
474 typedef struct router_info_s {
475 char ri_version; /* structure version */
476 cnodeid_t ri_cnode; /* cnode of its legal guardian hub */
477 nasid_t ri_nasid; /* Nasid of same */
478 char ri_ledcache; /* Last LED bitmap */
479 char ri_leds; /* Current LED bitmap */
480 char ri_portmask; /* Active port bitmap */
481 router_reg_t ri_stat_rev_id; /* Status rev ID value */
482 net_vec_t ri_vector; /* vector from guardian to router */
483 int ri_writeid; /* router's vector write ID */
484 int64_t ri_timebase; /* Time of first sample */
485 int64_t ri_timestamp; /* Time of last sample */
486 router_port_info_t ri_port[MAX_ROUTER_PORTS]; /* per port info */
487 moduleid_t ri_module; /* Which module are we in? */
488 slotid_t ri_slotnum; /* Which slot are we in? */
489 router_reg_t ri_glbl_parms[GLBL_PARMS_REGS];
490 /* Global parms0&1 register contents*/
491 vertex_hdl_t ri_vertex; /* hardware graph vertex */
492 router_reg_t ri_prot_conf; /* protection config. register */
493 int64_t ri_per_minute; /* Ticks per minute */
496 * Everything below here is for kernel use only and may change at
497 * at any time with or without a change in the revision number
499 * Any pointers or things that come and go with DEBUG must go at
500 * the bottom of the structure, below the user stuff.
502 char ri_hist_type; /* histogram type */
503 vertex_hdl_t ri_guardian; /* guardian node for the router */
504 int64_t ri_last_print; /* When did we last print */
505 char ri_print; /* Should we print */
506 char ri_just_blink; /* Should we blink the LEDs */
509 int64_t ri_deltatime; /* Time it took to sample */
511 spinlock_t ri_lock; /* Lock for access to router info */
512 net_vec_t *ri_vecarray; /* Pointer to array of vectors */
513 struct lboard_s *ri_brd; /* Pointer to board structure */
514 char * ri_name; /* This board's hwg path */
515 unsigned char ri_port_maint[MAX_ROUTER_PORTS]; /* should we send a
516 message to availmon */
520 /* Router info location specifiers */
522 #define RIP_PROMLOG 2 /* Router info in promlog */
523 #define RIP_CONSOLE 4 /* Router info on console */
526 * Router info hanging in the nodepda
528 typedef struct nodepda_router_info_s {
529 vertex_hdl_t router_vhdl; /* vertex handle of the router */
530 short router_port; /* port thru which we entered */
531 short router_portmask;
532 moduleid_t router_module; /* module in which router is there */
533 slotid_t router_slot; /* router slot */
534 unsigned char router_type; /* kind of router */
535 net_vec_t router_vector; /* vector from the guardian node */
537 router_info_t *router_infop; /* info hanging off the hwg vertex */
538 struct nodepda_router_info_s *router_next;
539 /* pointer to next element */
540 } nodepda_router_info_t;
542 #define ROUTER_NAME_SIZE 20 /* Max size of a router name */
544 #define NORMAL_ROUTER_NAME "normal_router"
545 #define NULL_ROUTER_NAME "null_router"
546 #define META_ROUTER_NAME "meta_router"
547 #define REPEATER_ROUTER_NAME "repeater_router"
548 #define UNKNOWN_ROUTER_NAME "unknown_router"
550 /* The following definitions are needed by the router traversing
551 * code either using the hardware graph or using vector operations.
553 /* Structure of the router queue element */
554 typedef struct router_elt_s {
556 /* queue element structure during router probing */
558 /* number-in-a-can (unique) for the router */
560 /* vector route from the master hub to
566 char port_status[MAX_ROUTER_PORTS + 1];
568 /* queue element structure during router guardian
572 /* vertex handle for the router */
574 /* guardian for this router */
576 /* vector router from the guardian to the router */
580 /* easy to use port status interpretation */
583 /* structure of the router queue */
585 typedef struct router_queue_s {
586 char head; /* Point where a queue element is inserted */
587 char tail; /* Point where a queue element is removed */
589 router_elt_t array[MAX_RTR_BREADTH];
590 /* Entries for queue elements */
594 #endif /* __ASSEMBLY__ */
597 * RR_HISTOGRAM(_L) mask and shift definitions
598 * There are two 64 bit histogram registers, so the following macros take
599 * into account dealing with an array of 4 32 bit values indexed by _x
602 #define RHIST_BUCKET_SHFT(_x) (32 * ((_x) & 0x1))
603 #define RHIST_BUCKET_MASK(_x) (0xffffffffUL << RHIST_BUCKET_SHFT((_x) & 0x1))
604 #define RHIST_GET_BUCKET(_x, _reg) \
605 ((RHIST_BUCKET_MASK(_x) & ((_reg)[(_x) >> 1])) >> RHIST_BUCKET_SHFT(_x))
608 * RR_RESET_MASK(_L) mask and shift definitions
611 #define RRM_RESETOK(_L) (1UL << ((_L) - 1))
612 #define RRM_RESETOK_ALL ALL_PORTS
615 * RR_META_TABLE(_x) and RR_LOCAL_TABLE(_x) mask and shift definitions
618 #define RTABLE_SHFT(_L) (4 * ((_L) - 1))
619 #define RTABLE_MASK(_L) (0x7UL << RTABLE_SHFT(_L))
622 #define ROUTERINFO_STKSZ 4096
626 int router_reg_read(router_info_t *rip, int regno, router_reg_t *val);
627 int router_reg_write(router_info_t *rip, int regno, router_reg_t val);
628 int router_get_info(vertex_hdl_t routerv, router_info_t *, int);
629 int router_set_leds(router_info_t *rip);
630 void router_print_state(router_info_t *rip, int level,
631 void (*pf)(int, char *, ...),int print_where);
632 void capture_router_stats(router_info_t *rip);
635 int probe_routers(void);
636 void get_routername(unsigned char brd_type,char *rtrname);
637 void router_guardians_set(vertex_hdl_t hwgraph_root);
638 int router_hist_reselect(router_info_t *, int64_t);
639 #endif /* __ASSEMBLY__ */
641 #endif /* _ASM_IA64_SN_ROUTER_H */