2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_IA64_SN_SN2_ADDRS_H
10 #define _ASM_IA64_SN_SN2_ADDRS_H
12 /* McKinley Address Format:
16 * +-+---------+----+--------------+
17 * |0| Node ID | AS | Node Offset |
18 * +-+---------+----+--------------+
20 * Node ID: If bit 38 = 1, is ICE, else is SHUB
21 * AS: Address Space Identifier. Used only if bit 38 = 0.
22 * b'00: Local Resources and MMR space
24 * 0: Local resources space
26 * 0: IA64/NT compatibility space
28 * 4: Local memory, regardless of local node id
32 * b'11: Cacheable memory space.
34 * NodeOffset: byte offset
38 typedef union ia64_sn2_pa {
40 unsigned long off : 36;
42 unsigned long nasid: 11;
43 unsigned long fill : 15;
50 #define TO_PHYS_MASK 0x0001ffcfffffffff /* Note - clear AS bits */
53 /* Regions determined by AS */
54 #define LOCAL_MMR_SPACE 0xc000008000000000 /* Local MMR space */
55 #define LOCAL_PHYS_MMR_SPACE 0x8000008000000000 /* Local PhysicalMMR space */
56 #define LOCAL_MEM_SPACE 0xc000010000000000 /* Local Memory space */
57 #define GLOBAL_MMR_SPACE 0xc000000800000000 /* Global MMR space */
58 #define GLOBAL_PHYS_MMR_SPACE 0x0000000800000000 /* Global Physical MMR space */
59 #define GET_SPACE 0xe000001000000000 /* GET space */
60 #define AMO_SPACE 0xc000002000000000 /* AMO space */
61 #define CACHEABLE_MEM_SPACE 0xe000003000000000 /* Cacheable memory space */
62 #define UNCACHED 0xc000000000000000 /* UnCacheable memory space */
63 #define UNCACHED_PHYS 0x8000000000000000 /* UnCacheable physical memory space */
65 #define PHYS_MEM_SPACE 0x0000003000000000 /* physical memory space */
67 /* SN2 address macros */
69 #define LOCAL_MMR_ADDR(a) (UNCACHED | LOCAL_MMR_SPACE | (a))
70 #define LOCAL_MMR_PHYS_ADDR(a) (UNCACHED_PHYS | LOCAL_PHYS_MMR_SPACE | (a))
71 #define LOCAL_MEM_ADDR(a) (LOCAL_MEM_SPACE | (a))
72 #define REMOTE_ADDR(n,a) ((((unsigned long)(n))<<NID_SHFT) | (a))
73 #define GLOBAL_MMR_ADDR(n,a) (UNCACHED | GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
74 #define GLOBAL_MMR_PHYS_ADDR(n,a) (UNCACHED_PHYS | GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
75 #define GET_ADDR(n,a) (GET_SPACE | REMOTE_ADDR(n,a))
76 #define AMO_ADDR(n,a) (UNCACHED | AMO_SPACE | REMOTE_ADDR(n,a))
77 #define GLOBAL_MEM_ADDR(n,a) (CACHEABLE_MEM_SPACE | REMOTE_ADDR(n,a))
79 /* non-II mmr's start at top of big window space (4G) */
80 #define BWIN_TOP 0x0000000100000000
83 * general address defines - for code common to SN0/SN1/SN2
85 #define CAC_BASE CACHEABLE_MEM_SPACE /* cacheable memory space */
86 #define IO_BASE (UNCACHED | GLOBAL_MMR_SPACE) /* lower 4G maps II's XIO space */
87 #define AMO_BASE (UNCACHED | AMO_SPACE) /* fetch & op space */
88 #define MSPEC_BASE AMO_BASE /* fetch & op space */
89 #define UNCAC_BASE (UNCACHED | CACHEABLE_MEM_SPACE) /* uncached global memory */
90 #define GET_BASE GET_SPACE /* momentarily coherent remote mem. */
91 #define CALIAS_BASE LOCAL_CACHEABLE_BASE /* cached node-local memory */
92 #define UALIAS_BASE (UNCACHED | LOCAL_CACHEABLE_BASE) /* uncached node-local memory */
94 #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
95 #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
96 #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
97 #define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK))
98 #define TO_GET(x) (GET_BASE | ((x) & TO_PHYS_MASK))
99 #define TO_CALIAS(x) (CALIAS_BASE | TO_NODE_ADDRSPACE(x))
100 #define TO_UALIAS(x) (UALIAS_BASE | TO_NODE_ADDRSPACE(x))
101 #define NODE_SIZE_BITS 36 /* node offset : bits <35:0> */
102 #define BWIN_SIZE_BITS 29 /* big window size: 512M */
103 #define NASID_BITS 11 /* bits <48:38> */
104 #define NASID_BITMASK (0x7ffULL)
105 #define NASID_SHFT NID_SHFT
106 #define NASID_META_BITS 0 /* ???? */
107 #define NASID_LOCAL_BITS 7 /* same router as SN1 */
109 #define NODE_ADDRSPACE_SIZE (1UL << NODE_SIZE_BITS)
110 #define NASID_MASK ((uint64_t) NASID_BITMASK << NASID_SHFT)
111 #define NASID_GET(_pa) (int) (((uint64_t) (_pa) >> \
112 NASID_SHFT) & NASID_BITMASK)
113 #define PHYS_TO_DMA(x) ( ((x & NASID_MASK) >> 2) | \
114 (x & (NODE_ADDRSPACE_SIZE - 1)) )
116 #define CHANGE_NASID(n,x) ({ia64_sn2_pa_t _v; _v.l = (long) (x); _v.f.nasid = n; _v.p;})
119 * Determine if a physical address should be referenced as cached or uncached.
120 * For now, assume all memory is cached and everything else is noncached.
121 * (Later, we may need to special case areas of memory to be reference uncached).
123 #define IS_CACHED_ADDRESS(x) (((x) & PHYS_MEM_SPACE) == PHYS_MEM_SPACE)
127 #define NODE_SWIN_BASE(nasid, widget) \
128 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
129 : RAW_NODE_SWIN_BASE(nasid, widget))
131 #define NODE_SWIN_BASE(nasid, widget) \
132 (NODE_IO_BASE(nasid) + ((uint64_t) (widget) << SWIN_SIZE_BITS))
133 #define LOCAL_SWIN_BASE(widget) \
134 (UNCACHED | LOCAL_MMR_SPACE | (((uint64_t) (widget) << SWIN_SIZE_BITS)))
135 #endif /* __ASSEMBLY__ */
138 * The following definitions pertain to the IO special address
139 * space. They define the location of the big and little windows
143 #define BWIN_INDEX_BITS 3
144 #define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
145 #define BWIN_SIZEMASK (BWIN_SIZE - 1)
146 #define BWIN_WIDGET_MASK 0x7
147 #define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
148 #define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
149 ((uint64_t) (bigwin) << BWIN_SIZE_BITS))
151 #define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
152 #define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
155 * Verify if addr belongs to large window address of node with "nasid"
158 * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
164 #define NODE_BWIN_ADDR(nasid, addr) \
165 (((addr) >= NODE_BWIN_BASE0(nasid)) && \
166 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
169 #endif /* _ASM_IA64_SN_SN2_ADDRS_H */