2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 2001, 2002-2003 Silicon Graphics, Inc. All rights reserved.
10 #ifndef _ASM_IA64_SN_SN2_SHUB_MD_H
11 #define _ASM_IA64_SN_SN2_SHUB_MD_H
13 /* SN2 supports a mostly-flat address space with 4 CPU-visible, evenly spaced,
14 contiguous regions, or "software banks". On SN2, software bank n begins at
15 addresses n * 16GB, 0 <= n < 4. Each bank has a 16GB address space. If
16 the 4 dimms do not use up this space there will be holes between the
17 banks. Even with these holes the whole memory space within a bank is
18 not addressable address space. The top 1/32 of each bank is directory
19 memory space and is accessible through bist only.
21 Physically a SN2 node board contains 2 daughter cards with 8 dimm sockets
22 each. A total of 16 dimm sockets arranged as 4 "DIMM banks" of 4 dimms
23 each. The data is stripped across the 4 memory busses so all dimms within
24 a dimm bank must have identical capacity dimms. Memory is increased or
25 decreased in sets of 4. Each dimm bank has 2 dimms on each side.
27 Physical Dimm Bank layout.
30 Dimm Bank 3 | MemYL3 | CS 3
33 Dimm Bank 2 | MemYL2 | CS 2
36 Dimm Bank 1 | MemYL1 | CS 1
39 Dimm Bank 0 | MemYL0 | CS 0
55 Dimm Bank 0 | MemXR0 | CS 0
58 Dimm Bank 1 | MemXR1 | CS 1
61 Dimm Bank 2 | MemXR2 | CS 2
64 Dimm Bank 3 | MemXR3 | CS 3
69 The dimms can be 1 or 2 sided dimms. The size and bankness is defined
70 separately for each dimm bank in the sh_[x,y,jnr]_dimm_cfg MMR register.
72 Normally software bank 0 would map directly to physical dimm bank 0. The
73 software banks can map to the different physical dimm banks via the
74 DIMM[0-3]_CS field in SH_[x,y,jnr]_DIMM_CFG for each dimm slot.
76 All the PROM's data structures (promlog variables, klconfig, etc.)
77 track memory by the physical dimm bank number. The kernel usually
78 tracks memory by the software bank number.
83 /* Preprocessor macros */
84 #define MD_MEM_BANKS 4
85 #define MD_PHYS_BANKS_PER_DIMM 2 /* dimms may be 2 sided. */
86 #define MD_NUM_PHYS_BANKS (MD_MEM_BANKS * MD_PHYS_BANKS_PER_DIMM)
87 #define MD_DIMMS_IN_SLOT 4 /* 4 dimms in each dimm bank. aka slot */
89 /* Address bits 35,34 control dimm bank access. */
90 #define MD_BANK_SHFT 34
91 #define MD_BANK_MASK (UINT64_CAST 0x3 << MD_BANK_SHFT )
92 #define MD_BANK_GET(addr) (((addr) & MD_BANK_MASK) >> MD_BANK_SHFT)
93 #define MD_BANK_SIZE (UINT64_CAST 0x1 << MD_BANK_SHFT ) /* 16 gb */
94 #define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT)
96 /*Address bit 12 selects side of dimm if 2bnk dimms present. */
97 #define MD_PHYS_BANK_SEL_SHFT 12
98 #define MD_PHYS_BANK_SEL_MASK (UINT64_CAST 0x1 << MD_PHYS_BANK_SEL_SHFT)
100 /* Address bit 7 determines if data resides on X or Y memory system.
101 * If addr Bit 7 is set the data resides on Y memory system and
102 * the corresponing directory entry reside on the X.
104 #define MD_X_OR_Y_SEL_SHFT 7
105 #define MD_X_OR_Y_SEL_MASK (1 << MD_X_OR_Y_SEL_SHFT)
107 /* Address bit 8 determines which directory entry of the pair the address
108 * corresponds to. If addr Bit 8 is set DirB corresponds to the memory address.
110 #define MD_DIRA_OR_DIRB_SEL_SHFT 8
111 #define MD_DIRA_OR_DIRB_SEL_MASK (1 << MD_DIRA_OR_DIRB_SEL_SHFT)
113 /* Address bit 11 determines if corresponding directory entry resides
114 * on Left or Right memory bus. If addr Bit 11 is set the corresponding
115 * directory entry resides on Right memory bus.
117 #define MD_L_OR_R_SEL_SHFT 11
118 #define MD_L_OR_R_SEL_MASK (1 << MD_L_OR_R_SEL_SHFT)
121 #define MD_SZ_64_Mb 0x0
122 #define MD_SZ_128_Mb 0x1
123 #define MD_SZ_256_Mb 0x2
124 #define MD_SZ_512_Mb 0x3
125 #define MD_SZ_1024_Mb 0x4
126 #define MD_SZ_2048_Mb 0x5
127 #define MD_SZ_UNUSED 0x7
129 #define MD_DIMM_SIZE_BYTES(_size, _2bk) ( \
130 ( (_size) == 7 ? 0 : ( 0x4000000L << (_size)) << (_2bk)))\
132 #define MD_DIMM_SIZE_MBYTES(_size, _2bk) ( \
133 ( (_size) == 7 ? 0 : ( 0x40L << (_size) ) << (_2bk))) \
135 /* The top 1/32 of each bank is directory memory, and not accessible
136 * via normal reads and writes */
137 #define MD_DIMM_USER_SIZE(_size) ((_size) * 31 / 32)
139 /* Minimum size of a populated bank is 64M (62M usable) */
140 #define MIN_BANK_SIZE MD_DIMM_USER_SIZE((64 * 0x100000))
141 #define MIN_BANK_STRING "62"
144 /*Possible values for FREQ field in sh_[x,y,jnr]_dimm_cfg regs */
145 #define MD_DIMM_100_CL2_0 0x0
146 #define MD_DIMM_133_CL2_0 0x1
147 #define MD_DIMM_133_CL2_5 0x2
148 #define MD_DIMM_160_CL2_0 0x3
149 #define MD_DIMM_160_CL2_5 0x4
150 #define MD_DIMM_160_CL3_0 0x5
151 #define MD_DIMM_200_CL2_0 0x6
152 #define MD_DIMM_200_CL2_5 0x7
153 #define MD_DIMM_200_CL3_0 0x8
155 /* DIMM_CFG fields */
156 #define MD_DIMM_SHFT(_dimm) ((_dimm) << 3)
157 #define MD_DIMM_SIZE_MASK(_dimm) \
158 (SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK << \
159 (MD_DIMM_SHFT(_dimm)))
161 #define MD_DIMM_2BK_MASK(_dimm) \
162 (SH_JNR_DIMM_CFG_DIMM0_2BK_MASK << \
165 #define MD_DIMM_REV_MASK(_dimm) \
166 (SH_JNR_DIMM_CFG_DIMM0_REV_MASK << \
169 #define MD_DIMM_CS_MASK(_dimm) \
170 (SH_JNR_DIMM_CFG_DIMM0_CS_MASK << \
173 #define MD_DIMM_SIZE(_dimm, _cfg) \
174 (((_cfg) & MD_DIMM_SIZE_MASK(_dimm)) \
175 >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT))
177 #define MD_DIMM_TWO_SIDED(_dimm,_cfg) \
178 ( ((_cfg) & MD_DIMM_2BK_MASK(_dimm)) \
179 >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT))
181 #define MD_DIMM_REVERSED(_dimm,_cfg) \
182 (((_cfg) & MD_DIMM_REV_MASK(_dimm)) \
183 >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_REV_SHFT))
185 #define MD_DIMM_CS(_dimm,_cfg) \
186 (((_cfg) & MD_DIMM_CS_MASK(_dimm)) \
187 >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_CS_SHFT))
191 /* Macros to set MMRs that must be set identically to others. */
192 #define MD_SET_DIMM_CFG(_n, _value) { \
193 REMOTE_HUB_S(_n, SH_X_DIMM_CFG,_value); \
194 REMOTE_HUB_S(_n, SH_Y_DIMM_CFG, _value); \
195 REMOTE_HUB_S(_n, SH_JNR_DIMM_CFG, _value);}
197 #define MD_SET_DQCT_CFG(_n, _value) { \
198 REMOTE_HUB_S(_n, SH_X_DQCT_CFG,_value); \
199 REMOTE_HUB_S(_n, SH_Y_DQCT_CFG,_value); }
201 #define MD_SET_CFG(_n, _value) { \
202 REMOTE_HUB_S(_n, SH_X_CFG,_value); \
203 REMOTE_HUB_S(_n, SH_Y_CFG,_value);}
205 #define MD_SET_REFRESH_CONTROL(_n, _value) { \
206 REMOTE_HUB_S(_n, SH_X_REFRESH_CONTROL, _value); \
207 REMOTE_HUB_S(_n, SH_Y_REFRESH_CONTROL, _value);}
209 #define MD_SET_DQ_MMR_DIR_COFIG(_n, _value) { \
210 REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_CONFIG, _value); \
211 REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_CONFIG, _value);}
213 #define MD_SET_PIOWD_DIR_ENTRYS(_n, _value) { \
214 REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY, _value);\
215 REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY, _value);}
218 * There are 12 Node Presence MMRs, 4 in each primary DQ and 4 in the
219 * LB. The data in the left and right DQ MMRs and the LB must match.
221 #define MD_SET_PRESENT_VEC(_n, _vec, _value) { \
222 REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRESVEC0+((_vec)*0x10),\
224 REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRESVEC0+((_vec)*0x10),\
226 REMOTE_HUB_S(_n, SH_SHUBS_PRESENT0+((_vec)*0x80), _value);}
228 * There are 16 Privilege Vector MMRs, 8 in each primary DQ. The data
229 * in the corresponding left and right DQ MMRs must match. Each MMR
230 * pair is used for a single partition.
232 #define MD_SET_PRI_VEC(_n, _vec, _value) { \
233 REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRIVEC0+((_vec)*0x10),\
235 REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRIVEC0+((_vec)*0x10),\
238 * There are 16 Local/Remote MMRs, 8 in each primary DQ. The data in
239 * the corresponding left and right DQ MMRs must match. Each MMR pair
240 * is used for a single partition.
242 #define MD_SET_LOC_VEC(_n, _vec, _value) { \
243 REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_LOCVEC0+((_vec)*0x10),\
245 REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_LOCVEC0+((_vec)*0x10),\
248 /* Memory BIST CMDS */
249 #define MD_DIMM_INIT_MODE_SET 0x0
250 #define MD_DIMM_INIT_REFRESH 0x1
251 #define MD_DIMM_INIT_PRECHARGE 0x2
252 #define MD_DIMM_INIT_BURST_TERM 0x6
253 #define MD_DIMM_INIT_NOP 0x7
254 #define MD_DIMM_BIST_READ 0x10
255 #define MD_FILL_DIR 0x20
256 #define MD_FILL_DATA 0x30
257 #define MD_FILL_DIR_ACCESS 0X40
258 #define MD_READ_DIR_PAIR 0x50
259 #define MD_READ_DIR_TAG 0x60
261 /* SH_MMRBIST_CTL macros */
262 #define MD_BIST_FAIL(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \
263 SH_MMRBIST_CTL_FAIL_MASK)
265 #define MD_BIST_IN_PROGRESS(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \
266 SH_MMRBIST_CTL_IN_PROGRESS_MASK)
268 #define MD_BIST_MEM_IDLE(_n); (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \
269 SH_MMRBIST_CTL_MEM_IDLE_MASK)
271 /* SH_MMRBIST_ERR macros */
272 #define MD_BIST_MISCOMPARE(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_ERR) & \
273 SH_MMRBIST_ERR_DETECTED_MASK)
275 #endif /* _ASM_IA64_SN_SN2_SHUB_MD_H */