3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved.
11 #ifndef _ASM_IA64_SN_SN2_SHUB_MMR_H
12 #define _ASM_IA64_SN_SN2_SHUB_MMR_H
14 /* ==================================================================== */
15 /* Register "SH_FSB_BINIT_CONTROL" */
16 /* FSB BINIT# Control */
17 /* ==================================================================== */
19 #define SH_FSB_BINIT_CONTROL 0x0000000120010000
20 #define SH_FSB_BINIT_CONTROL_MASK 0x0000000000000001
21 #define SH_FSB_BINIT_CONTROL_INIT 0x0000000000000000
23 /* SH_FSB_BINIT_CONTROL_BINIT */
24 /* Description: Assert the FSB's BINIT# Signal */
25 #define SH_FSB_BINIT_CONTROL_BINIT_SHFT 0
26 #define SH_FSB_BINIT_CONTROL_BINIT_MASK 0x0000000000000001
28 /* ==================================================================== */
29 /* Register "SH_FSB_RESET_CONTROL" */
30 /* FSB Reset Control */
31 /* ==================================================================== */
33 #define SH_FSB_RESET_CONTROL 0x0000000120010080
34 #define SH_FSB_RESET_CONTROL_MASK 0x0000000000000001
35 #define SH_FSB_RESET_CONTROL_INIT 0x0000000000000000
37 /* SH_FSB_RESET_CONTROL_RESET */
38 /* Description: Assert the FSB's RESET# Signal */
39 #define SH_FSB_RESET_CONTROL_RESET_SHFT 0
40 #define SH_FSB_RESET_CONTROL_RESET_MASK 0x0000000000000001
42 /* ==================================================================== */
43 /* Register "SH_FSB_SYSTEM_AGENT_CONFIG" */
44 /* FSB System Agent Configuration */
45 /* ==================================================================== */
47 #define SH_FSB_SYSTEM_AGENT_CONFIG 0x0000000120010100
48 #define SH_FSB_SYSTEM_AGENT_CONFIG_MASK 0x00003fff0187fff9
49 #define SH_FSB_SYSTEM_AGENT_CONFIG_INIT 0x0000000000000000
51 /* SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN */
52 /* Description: RCNT/SCNT Assertion Enabled */
53 #define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_SHFT 0
54 #define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_MASK 0x0000000000000001
56 /* SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN */
57 /* Description: BERR Assertion Enabled for Bus Errors */
58 #define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_SHFT 3
59 #define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_MASK 0x0000000000000008
61 /* SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN */
62 /* Description: BERR Sampling Enabled */
63 #define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_SHFT 4
64 #define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_MASK 0x0000000000000010
66 /* SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN */
67 /* Description: BINIT Assertion Enabled */
68 #define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_SHFT 5
69 #define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_MASK 0x0000000000000020
71 /* SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN */
72 /* Description: stutter FSB request assertion */
73 #define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_SHFT 6
74 #define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_MASK 0x0000000000000040
76 /* SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN */
77 /* Description: use short duration hang timeout */
78 #define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_SHFT 7
79 #define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_MASK 0x0000000000000080
81 /* SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA */
82 /* Description: Interrupt Acknowledge Response Data */
83 #define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_SHFT 8
84 #define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_MASK 0x000000000000ff00
86 /* SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP */
87 /* Description: IO Transaction Response */
88 #define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_SHFT 16
89 #define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_MASK 0x0000000000010000
91 /* SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP */
92 /* Description: External Task Priority Register (xTPR) Transaction */
94 #define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_SHFT 17
95 #define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_MASK 0x0000000000020000
97 /* SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP */
98 /* Description: Interrupt Acknowledge Transaction Response */
99 #define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_SHFT 18
100 #define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_MASK 0x0000000000040000
102 /* SH_FSB_SYSTEM_AGENT_CONFIG_TDOT */
103 /* Description: Throttle Data-bus Ownership Transitions */
104 #define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_SHFT 23
105 #define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_MASK 0x0000000000800000
107 /* SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN */
108 /* Description: serialize processor transactions */
109 #define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_SHFT 24
110 #define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_MASK 0x0000000001000000
112 /* SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES */
113 /* Description: FSB error binit enables */
114 #define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_SHFT 32
115 #define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_MASK 0x00003fff00000000
117 /* ==================================================================== */
118 /* Register "SH_FSB_VGA_REMAP" */
119 /* FSB VGA Address Space Remap */
120 /* ==================================================================== */
122 #define SH_FSB_VGA_REMAP 0x0000000120010180
123 #define SH_FSB_VGA_REMAP_MASK 0x4001fffffffe0000
124 #define SH_FSB_VGA_REMAP_INIT 0x0000000000000000
126 /* SH_FSB_VGA_REMAP_OFFSET */
127 /* Description: VGA Remap Node Offset */
128 #define SH_FSB_VGA_REMAP_OFFSET_SHFT 17
129 #define SH_FSB_VGA_REMAP_OFFSET_MASK 0x0000000ffffe0000
131 /* SH_FSB_VGA_REMAP_ASID */
132 /* Description: VGA Remap Address Space ID */
133 #define SH_FSB_VGA_REMAP_ASID_SHFT 36
134 #define SH_FSB_VGA_REMAP_ASID_MASK 0x0000003000000000
136 /* SH_FSB_VGA_REMAP_NID */
137 /* Description: VGA Remap Node ID */
138 #define SH_FSB_VGA_REMAP_NID_SHFT 38
139 #define SH_FSB_VGA_REMAP_NID_MASK 0x0001ffc000000000
141 /* SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED */
142 /* Description: VGA Remapping Enabled */
143 #define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_SHFT 62
144 #define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_MASK 0x4000000000000000
146 /* ==================================================================== */
147 /* Register "SH_FSB_RESET_STATUS" */
148 /* FSB Reset Status */
149 /* ==================================================================== */
151 #define SH_FSB_RESET_STATUS 0x0000000120020000
152 #define SH_FSB_RESET_STATUS_MASK 0x0000000000000001
153 #define SH_FSB_RESET_STATUS_INIT 0x0000000000000000
155 /* SH_FSB_RESET_STATUS_RESET_IN_PROGRESS */
156 /* Description: Reset in Progress */
157 #define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_SHFT 0
158 #define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_MASK 0x0000000000000001
160 /* ==================================================================== */
161 /* Register "SH_FSB_SYMMETRIC_AGENT_STATUS" */
162 /* FSB Symmetric Agent Status */
163 /* ==================================================================== */
165 #define SH_FSB_SYMMETRIC_AGENT_STATUS 0x0000000120020080
166 #define SH_FSB_SYMMETRIC_AGENT_STATUS_MASK 0x0000000000000007
167 #define SH_FSB_SYMMETRIC_AGENT_STATUS_INIT 0x0000000000000000
169 /* SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE */
170 /* Description: CPU 0 Active. */
171 #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_SHFT 0
172 #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_MASK 0x0000000000000001
174 /* SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE */
175 /* Description: CPU 1 Active. */
176 #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_SHFT 1
177 #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_MASK 0x0000000000000002
179 /* SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY */
180 /* Description: The Processors are Ready */
181 #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_SHFT 2
182 #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_MASK 0x0000000000000004
184 /* ==================================================================== */
185 /* Register "SH_GFX_CREDIT_COUNT_0" */
186 /* Graphics-write Credit Count for CPU 0 */
187 /* ==================================================================== */
189 #define SH_GFX_CREDIT_COUNT_0 0x0000000120030000
190 #define SH_GFX_CREDIT_COUNT_0_MASK 0x80000000000fffff
191 #define SH_GFX_CREDIT_COUNT_0_INIT 0x000000000000003f
193 /* SH_GFX_CREDIT_COUNT_0_COUNT */
194 /* Description: Credit Count */
195 #define SH_GFX_CREDIT_COUNT_0_COUNT_SHFT 0
196 #define SH_GFX_CREDIT_COUNT_0_COUNT_MASK 0x00000000000fffff
198 /* SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE */
199 /* Description: Reset GFX state */
200 #define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_SHFT 63
201 #define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_MASK 0x8000000000000000
203 /* ==================================================================== */
204 /* Register "SH_GFX_CREDIT_COUNT_1" */
205 /* Graphics-write Credit Count for CPU 1 */
206 /* ==================================================================== */
208 #define SH_GFX_CREDIT_COUNT_1 0x0000000120030080
209 #define SH_GFX_CREDIT_COUNT_1_MASK 0x80000000000fffff
210 #define SH_GFX_CREDIT_COUNT_1_INIT 0x000000000000003f
212 /* SH_GFX_CREDIT_COUNT_1_COUNT */
213 /* Description: Credit Count */
214 #define SH_GFX_CREDIT_COUNT_1_COUNT_SHFT 0
215 #define SH_GFX_CREDIT_COUNT_1_COUNT_MASK 0x00000000000fffff
217 /* SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE */
218 /* Description: Reset GFX state */
219 #define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_SHFT 63
220 #define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_MASK 0x8000000000000000
222 /* ==================================================================== */
223 /* Register "SH_GFX_MODE_CNTRL_0" */
224 /* Graphics credit mode amd message ordering for CPU 0 */
225 /* ==================================================================== */
227 #define SH_GFX_MODE_CNTRL_0 0x0000000120030100
228 #define SH_GFX_MODE_CNTRL_0_MASK 0x0000000000000007
229 #define SH_GFX_MODE_CNTRL_0_INIT 0x0000000000000003
231 /* SH_GFX_MODE_CNTRL_0_DWORD_CREDITS */
232 /* Description: GFX credits are tracked by D-words */
233 #define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_SHFT 0
234 #define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_MASK 0x0000000000000001
236 /* SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS */
237 /* Description: GFX credits are tracked by D-words and messages */
238 #define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_SHFT 1
239 #define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_MASK 0x0000000000000002
241 /* SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING */
242 /* Description: GFX message routing order */
243 #define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_SHFT 2
244 #define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_MASK 0x0000000000000004
246 /* ==================================================================== */
247 /* Register "SH_GFX_MODE_CNTRL_1" */
248 /* Graphics credit mode amd message ordering for CPU 1 */
249 /* ==================================================================== */
251 #define SH_GFX_MODE_CNTRL_1 0x0000000120030180
252 #define SH_GFX_MODE_CNTRL_1_MASK 0x0000000000000007
253 #define SH_GFX_MODE_CNTRL_1_INIT 0x0000000000000003
255 /* SH_GFX_MODE_CNTRL_1_DWORD_CREDITS */
256 /* Description: GFX credits are tracked by D-words */
257 #define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_SHFT 0
258 #define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_MASK 0x0000000000000001
260 /* SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS */
261 /* Description: GFX credits are tracked by D-words and messages */
262 #define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_SHFT 1
263 #define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_MASK 0x0000000000000002
265 /* SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING */
266 /* Description: GFX message routing order */
267 #define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_SHFT 2
268 #define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_MASK 0x0000000000000004
270 /* ==================================================================== */
271 /* Register "SH_GFX_SKID_CREDIT_COUNT_0" */
272 /* Graphics-write Skid Credit Count for CPU 0 */
273 /* ==================================================================== */
275 #define SH_GFX_SKID_CREDIT_COUNT_0 0x0000000120030200
276 #define SH_GFX_SKID_CREDIT_COUNT_0_MASK 0x00000000000fffff
277 #define SH_GFX_SKID_CREDIT_COUNT_0_INIT 0x0000000000000030
279 /* SH_GFX_SKID_CREDIT_COUNT_0_SKID */
280 /* Description: Skid Credit Count */
281 #define SH_GFX_SKID_CREDIT_COUNT_0_SKID_SHFT 0
282 #define SH_GFX_SKID_CREDIT_COUNT_0_SKID_MASK 0x00000000000fffff
284 /* ==================================================================== */
285 /* Register "SH_GFX_SKID_CREDIT_COUNT_1" */
286 /* Graphics-write Skid Credit Count for CPU 1 */
287 /* ==================================================================== */
289 #define SH_GFX_SKID_CREDIT_COUNT_1 0x0000000120030280
290 #define SH_GFX_SKID_CREDIT_COUNT_1_MASK 0x00000000000fffff
291 #define SH_GFX_SKID_CREDIT_COUNT_1_INIT 0x0000000000000030
293 /* SH_GFX_SKID_CREDIT_COUNT_1_SKID */
294 /* Description: Skid Credit Count */
295 #define SH_GFX_SKID_CREDIT_COUNT_1_SKID_SHFT 0
296 #define SH_GFX_SKID_CREDIT_COUNT_1_SKID_MASK 0x00000000000fffff
298 /* ==================================================================== */
299 /* Register "SH_GFX_STALL_LIMIT_0" */
300 /* Graphics-write Stall Limit for CPU 0 */
301 /* ==================================================================== */
303 #define SH_GFX_STALL_LIMIT_0 0x0000000120030300
304 #define SH_GFX_STALL_LIMIT_0_MASK 0x0000000003ffffff
305 #define SH_GFX_STALL_LIMIT_0_INIT 0x0000000000010000
307 /* SH_GFX_STALL_LIMIT_0_LIMIT */
308 /* Description: Graphics Stall Limit for CPU 0 */
309 #define SH_GFX_STALL_LIMIT_0_LIMIT_SHFT 0
310 #define SH_GFX_STALL_LIMIT_0_LIMIT_MASK 0x0000000003ffffff
312 /* ==================================================================== */
313 /* Register "SH_GFX_STALL_LIMIT_1" */
314 /* Graphics-write Stall Limit for CPU 1 */
315 /* ==================================================================== */
317 #define SH_GFX_STALL_LIMIT_1 0x0000000120030380
318 #define SH_GFX_STALL_LIMIT_1_MASK 0x0000000003ffffff
319 #define SH_GFX_STALL_LIMIT_1_INIT 0x0000000000010000
321 /* SH_GFX_STALL_LIMIT_1_LIMIT */
322 /* Description: Graphics Stall Limit for CPU 1 */
323 #define SH_GFX_STALL_LIMIT_1_LIMIT_SHFT 0
324 #define SH_GFX_STALL_LIMIT_1_LIMIT_MASK 0x0000000003ffffff
326 /* ==================================================================== */
327 /* Register "SH_GFX_STALL_TIMER_0" */
328 /* Graphics-write Stall Timer for CPU 0 */
329 /* ==================================================================== */
331 #define SH_GFX_STALL_TIMER_0 0x0000000120030400
332 #define SH_GFX_STALL_TIMER_0_MASK 0x0000000003ffffff
333 #define SH_GFX_STALL_TIMER_0_INIT 0x0000000000000000
335 /* SH_GFX_STALL_TIMER_0_TIMER_VALUE */
336 /* Description: Timer Value */
337 #define SH_GFX_STALL_TIMER_0_TIMER_VALUE_SHFT 0
338 #define SH_GFX_STALL_TIMER_0_TIMER_VALUE_MASK 0x0000000003ffffff
340 /* ==================================================================== */
341 /* Register "SH_GFX_STALL_TIMER_1" */
342 /* Graphics-write Stall Timer for CPU 1 */
343 /* ==================================================================== */
345 #define SH_GFX_STALL_TIMER_1 0x0000000120030480
346 #define SH_GFX_STALL_TIMER_1_MASK 0x0000000003ffffff
347 #define SH_GFX_STALL_TIMER_1_INIT 0x0000000000000000
349 /* SH_GFX_STALL_TIMER_1_TIMER_VALUE */
350 /* Description: Timer Value */
351 #define SH_GFX_STALL_TIMER_1_TIMER_VALUE_SHFT 0
352 #define SH_GFX_STALL_TIMER_1_TIMER_VALUE_MASK 0x0000000003ffffff
354 /* ==================================================================== */
355 /* Register "SH_GFX_WINDOW_0" */
356 /* Graphics-write Window for CPU 0 */
357 /* ==================================================================== */
359 #define SH_GFX_WINDOW_0 0x0000000120030500
360 #define SH_GFX_WINDOW_0_MASK 0x8000000fff000000
361 #define SH_GFX_WINDOW_0_INIT 0x0000000000000000
363 /* SH_GFX_WINDOW_0_BASE_ADDR */
364 /* Description: Base Address for CPU 0's 16 MB Graphics Window */
365 #define SH_GFX_WINDOW_0_BASE_ADDR_SHFT 24
366 #define SH_GFX_WINDOW_0_BASE_ADDR_MASK 0x0000000fff000000
368 /* SH_GFX_WINDOW_0_GFX_WINDOW_EN */
369 /* Description: Graphics Window Enabled */
370 #define SH_GFX_WINDOW_0_GFX_WINDOW_EN_SHFT 63
371 #define SH_GFX_WINDOW_0_GFX_WINDOW_EN_MASK 0x8000000000000000
373 /* ==================================================================== */
374 /* Register "SH_GFX_WINDOW_1" */
375 /* Graphics-write Window for CPU 1 */
376 /* ==================================================================== */
378 #define SH_GFX_WINDOW_1 0x0000000120030580
379 #define SH_GFX_WINDOW_1_MASK 0x8000000fff000000
380 #define SH_GFX_WINDOW_1_INIT 0x0000000000000000
382 /* SH_GFX_WINDOW_1_BASE_ADDR */
383 /* Description: Base Address for CPU 1's 16 MB Graphics Window */
384 #define SH_GFX_WINDOW_1_BASE_ADDR_SHFT 24
385 #define SH_GFX_WINDOW_1_BASE_ADDR_MASK 0x0000000fff000000
387 /* SH_GFX_WINDOW_1_GFX_WINDOW_EN */
388 /* Description: Graphics Window Enabled */
389 #define SH_GFX_WINDOW_1_GFX_WINDOW_EN_SHFT 63
390 #define SH_GFX_WINDOW_1_GFX_WINDOW_EN_MASK 0x8000000000000000
392 /* ==================================================================== */
393 /* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0" */
394 /* Graphics-write Interrupt Limit for CPU 0 */
395 /* ==================================================================== */
397 #define SH_GFX_INTERRUPT_TIMER_LIMIT_0 0x0000000120030600
398 #define SH_GFX_INTERRUPT_TIMER_LIMIT_0_MASK 0x00000000000000ff
399 #define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INIT 0x0000000000000040
401 /* SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT */
402 /* Description: GFX Interrupt Timer Limit */
403 #define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_SHFT 0
404 #define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff
406 /* ==================================================================== */
407 /* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1" */
408 /* Graphics-write Interrupt Limit for CPU 1 */
409 /* ==================================================================== */
411 #define SH_GFX_INTERRUPT_TIMER_LIMIT_1 0x0000000120030680
412 #define SH_GFX_INTERRUPT_TIMER_LIMIT_1_MASK 0x00000000000000ff
413 #define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INIT 0x0000000000000040
415 /* SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT */
416 /* Description: GFX Interrupt Timer Limit */
417 #define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_SHFT 0
418 #define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff
420 /* ==================================================================== */
421 /* Register "SH_GFX_WRITE_STATUS_0" */
422 /* Graphics Write Status for CPU 0 */
423 /* ==================================================================== */
425 #define SH_GFX_WRITE_STATUS_0 0x0000000120040000
426 #define SH_GFX_WRITE_STATUS_0_MASK 0x8000000000000001
427 #define SH_GFX_WRITE_STATUS_0_INIT 0x0000000000000000
429 /* SH_GFX_WRITE_STATUS_0_BUSY */
430 /* Description: Busy */
431 #define SH_GFX_WRITE_STATUS_0_BUSY_SHFT 0
432 #define SH_GFX_WRITE_STATUS_0_BUSY_MASK 0x0000000000000001
434 /* SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL */
435 /* Description: Re-enable GFX stall logic for this processor */
436 #define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_SHFT 63
437 #define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000
439 /* ==================================================================== */
440 /* Register "SH_GFX_WRITE_STATUS_1" */
441 /* Graphics Write Status for CPU 1 */
442 /* ==================================================================== */
444 #define SH_GFX_WRITE_STATUS_1 0x0000000120040080
445 #define SH_GFX_WRITE_STATUS_1_MASK 0x8000000000000001
446 #define SH_GFX_WRITE_STATUS_1_INIT 0x0000000000000000
448 /* SH_GFX_WRITE_STATUS_1_BUSY */
449 /* Description: Busy */
450 #define SH_GFX_WRITE_STATUS_1_BUSY_SHFT 0
451 #define SH_GFX_WRITE_STATUS_1_BUSY_MASK 0x0000000000000001
453 /* SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL */
454 /* Description: Re-enable GFX stall logic for this processor */
455 #define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_SHFT 63
456 #define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000
458 /* ==================================================================== */
459 /* Register "SH_II_INT0" */
460 /* SHub II Interrupt 0 Registers */
461 /* ==================================================================== */
463 #define SH_II_INT0 0x0000000110000000
464 #define SH_II_INT0_MASK 0x00000000000001ff
465 #define SH_II_INT0_INIT 0x0000000000000000
468 /* Description: Targeted McKinley interrupt vector */
469 #define SH_II_INT0_IDX_SHFT 0
470 #define SH_II_INT0_IDX_MASK 0x00000000000000ff
472 /* SH_II_INT0_SEND */
473 /* Description: Send Interrupt Message to PI, This generates a puls */
474 #define SH_II_INT0_SEND_SHFT 8
475 #define SH_II_INT0_SEND_MASK 0x0000000000000100
477 /* ==================================================================== */
478 /* Register "SH_II_INT0_CONFIG" */
479 /* SHub II Interrupt 0 Config Registers */
480 /* ==================================================================== */
482 #define SH_II_INT0_CONFIG 0x0000000110000080
483 #define SH_II_INT0_CONFIG_MASK 0x0003ffffffefffff
484 #define SH_II_INT0_CONFIG_INIT 0x0000000000000000
486 /* SH_II_INT0_CONFIG_TYPE */
487 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
488 #define SH_II_INT0_CONFIG_TYPE_SHFT 0
489 #define SH_II_INT0_CONFIG_TYPE_MASK 0x0000000000000007
491 /* SH_II_INT0_CONFIG_AGT */
492 /* Description: Agent, must be 0 for SHub */
493 #define SH_II_INT0_CONFIG_AGT_SHFT 3
494 #define SH_II_INT0_CONFIG_AGT_MASK 0x0000000000000008
496 /* SH_II_INT0_CONFIG_PID */
497 /* Description: Processor ID, same setting as on targeted McKinley */
498 #define SH_II_INT0_CONFIG_PID_SHFT 4
499 #define SH_II_INT0_CONFIG_PID_MASK 0x00000000000ffff0
501 /* SH_II_INT0_CONFIG_BASE */
502 /* Description: Optional interrupt vector area, 2MB aligned */
503 #define SH_II_INT0_CONFIG_BASE_SHFT 21
504 #define SH_II_INT0_CONFIG_BASE_MASK 0x0003ffffffe00000
506 /* ==================================================================== */
507 /* Register "SH_II_INT0_ENABLE" */
508 /* SHub II Interrupt 0 Enable Registers */
509 /* ==================================================================== */
511 #define SH_II_INT0_ENABLE 0x0000000110000200
512 #define SH_II_INT0_ENABLE_MASK 0x0000000000000001
513 #define SH_II_INT0_ENABLE_INIT 0x0000000000000000
515 /* SH_II_INT0_ENABLE_II_ENABLE */
516 /* Description: Enable II Interrupt */
517 #define SH_II_INT0_ENABLE_II_ENABLE_SHFT 0
518 #define SH_II_INT0_ENABLE_II_ENABLE_MASK 0x0000000000000001
520 /* ==================================================================== */
521 /* Register "SH_II_INT1" */
522 /* SHub II Interrupt 1 Registers */
523 /* ==================================================================== */
525 #define SH_II_INT1 0x0000000110000100
526 #define SH_II_INT1_MASK 0x00000000000001ff
527 #define SH_II_INT1_INIT 0x0000000000000000
530 /* Description: Targeted McKinley interrupt vector */
531 #define SH_II_INT1_IDX_SHFT 0
532 #define SH_II_INT1_IDX_MASK 0x00000000000000ff
534 /* SH_II_INT1_SEND */
535 /* Description: Send Interrupt Message to PI, This generates a puls */
536 #define SH_II_INT1_SEND_SHFT 8
537 #define SH_II_INT1_SEND_MASK 0x0000000000000100
539 /* ==================================================================== */
540 /* Register "SH_II_INT1_CONFIG" */
541 /* SHub II Interrupt 1 Config Registers */
542 /* ==================================================================== */
544 #define SH_II_INT1_CONFIG 0x0000000110000180
545 #define SH_II_INT1_CONFIG_MASK 0x0003ffffffefffff
546 #define SH_II_INT1_CONFIG_INIT 0x0000000000000000
548 /* SH_II_INT1_CONFIG_TYPE */
549 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
550 #define SH_II_INT1_CONFIG_TYPE_SHFT 0
551 #define SH_II_INT1_CONFIG_TYPE_MASK 0x0000000000000007
553 /* SH_II_INT1_CONFIG_AGT */
554 /* Description: Agent, must be 0 for SHub */
555 #define SH_II_INT1_CONFIG_AGT_SHFT 3
556 #define SH_II_INT1_CONFIG_AGT_MASK 0x0000000000000008
558 /* SH_II_INT1_CONFIG_PID */
559 /* Description: Processor ID, same setting as on targeted McKinley */
560 #define SH_II_INT1_CONFIG_PID_SHFT 4
561 #define SH_II_INT1_CONFIG_PID_MASK 0x00000000000ffff0
563 /* SH_II_INT1_CONFIG_BASE */
564 /* Description: Optional interrupt vector area, 2MB aligned */
565 #define SH_II_INT1_CONFIG_BASE_SHFT 21
566 #define SH_II_INT1_CONFIG_BASE_MASK 0x0003ffffffe00000
568 /* ==================================================================== */
569 /* Register "SH_II_INT1_ENABLE" */
570 /* SHub II Interrupt 1 Enable Registers */
571 /* ==================================================================== */
573 #define SH_II_INT1_ENABLE 0x0000000110000280
574 #define SH_II_INT1_ENABLE_MASK 0x0000000000000001
575 #define SH_II_INT1_ENABLE_INIT 0x0000000000000000
577 /* SH_II_INT1_ENABLE_II_ENABLE */
578 /* Description: Enable II 1 Interrupt */
579 #define SH_II_INT1_ENABLE_II_ENABLE_SHFT 0
580 #define SH_II_INT1_ENABLE_II_ENABLE_MASK 0x0000000000000001
582 /* ==================================================================== */
583 /* Register "SH_INT_NODE_ID_CONFIG" */
584 /* SHub Interrupt Node ID Configuration */
585 /* ==================================================================== */
587 #define SH_INT_NODE_ID_CONFIG 0x0000000110000300
588 #define SH_INT_NODE_ID_CONFIG_MASK 0x0000000000000fff
589 #define SH_INT_NODE_ID_CONFIG_INIT 0x0000000000000000
591 /* SH_INT_NODE_ID_CONFIG_NODE_ID */
592 /* Description: Node ID for interrupt messages */
593 #define SH_INT_NODE_ID_CONFIG_NODE_ID_SHFT 0
594 #define SH_INT_NODE_ID_CONFIG_NODE_ID_MASK 0x00000000000007ff
596 /* SH_INT_NODE_ID_CONFIG_ID_SEL */
597 /* Description: Select node id for interrupt messages */
598 #define SH_INT_NODE_ID_CONFIG_ID_SEL_SHFT 11
599 #define SH_INT_NODE_ID_CONFIG_ID_SEL_MASK 0x0000000000000800
601 /* ==================================================================== */
602 /* Register "SH_IPI_INT" */
603 /* SHub Inter-Processor Interrupt Registers */
604 /* ==================================================================== */
606 #define SH_IPI_INT 0x0000000110000380
607 #define SH_IPI_INT_MASK 0x8ff3ffffffefffff
608 #define SH_IPI_INT_INIT 0x0000000000000000
610 /* SH_IPI_INT_TYPE */
611 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
612 #define SH_IPI_INT_TYPE_SHFT 0
613 #define SH_IPI_INT_TYPE_MASK 0x0000000000000007
616 /* Description: Agent, must be 0 for SHub */
617 #define SH_IPI_INT_AGT_SHFT 3
618 #define SH_IPI_INT_AGT_MASK 0x0000000000000008
621 /* Description: Processor ID, same setting as on targeted McKinley */
622 #define SH_IPI_INT_PID_SHFT 4
623 #define SH_IPI_INT_PID_MASK 0x00000000000ffff0
625 /* SH_IPI_INT_BASE */
626 /* Description: Optional interrupt vector area, 2MB aligned */
627 #define SH_IPI_INT_BASE_SHFT 21
628 #define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000
631 /* Description: Targeted McKinley interrupt vector */
632 #define SH_IPI_INT_IDX_SHFT 52
633 #define SH_IPI_INT_IDX_MASK 0x0ff0000000000000
635 /* SH_IPI_INT_SEND */
636 /* Description: Send Interrupt Message to PI, This generates a puls */
637 #define SH_IPI_INT_SEND_SHFT 63
638 #define SH_IPI_INT_SEND_MASK 0x8000000000000000
640 /* ==================================================================== */
641 /* Register "SH_IPI_INT_ENABLE" */
642 /* SHub Inter-Processor Interrupt Enable Registers */
643 /* ==================================================================== */
645 #define SH_IPI_INT_ENABLE 0x0000000110000400
646 #define SH_IPI_INT_ENABLE_MASK 0x0000000000000001
647 #define SH_IPI_INT_ENABLE_INIT 0x0000000000000000
649 /* SH_IPI_INT_ENABLE_PIO_ENABLE */
650 /* Description: Enable PIO Interrupt */
651 #define SH_IPI_INT_ENABLE_PIO_ENABLE_SHFT 0
652 #define SH_IPI_INT_ENABLE_PIO_ENABLE_MASK 0x0000000000000001
654 /* ==================================================================== */
655 /* Register "SH_LOCAL_INT0_CONFIG" */
656 /* SHub Local Interrupt 0 Registers */
657 /* ==================================================================== */
659 #define SH_LOCAL_INT0_CONFIG 0x0000000110000480
660 #define SH_LOCAL_INT0_CONFIG_MASK 0x0ff3ffffffefffff
661 #define SH_LOCAL_INT0_CONFIG_INIT 0x0000000000000000
663 /* SH_LOCAL_INT0_CONFIG_TYPE */
664 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
665 #define SH_LOCAL_INT0_CONFIG_TYPE_SHFT 0
666 #define SH_LOCAL_INT0_CONFIG_TYPE_MASK 0x0000000000000007
668 /* SH_LOCAL_INT0_CONFIG_AGT */
669 /* Description: Agent, must be 0 for SHub */
670 #define SH_LOCAL_INT0_CONFIG_AGT_SHFT 3
671 #define SH_LOCAL_INT0_CONFIG_AGT_MASK 0x0000000000000008
673 /* SH_LOCAL_INT0_CONFIG_PID */
674 /* Description: Processor ID, same setting as on targeted McKinley */
675 #define SH_LOCAL_INT0_CONFIG_PID_SHFT 4
676 #define SH_LOCAL_INT0_CONFIG_PID_MASK 0x00000000000ffff0
678 /* SH_LOCAL_INT0_CONFIG_BASE */
679 /* Description: Optional interrupt vector area, 2MB aligned */
680 #define SH_LOCAL_INT0_CONFIG_BASE_SHFT 21
681 #define SH_LOCAL_INT0_CONFIG_BASE_MASK 0x0003ffffffe00000
683 /* SH_LOCAL_INT0_CONFIG_IDX */
684 /* Description: Targeted McKinley interrupt vector */
685 #define SH_LOCAL_INT0_CONFIG_IDX_SHFT 52
686 #define SH_LOCAL_INT0_CONFIG_IDX_MASK 0x0ff0000000000000
688 /* ==================================================================== */
689 /* Register "SH_LOCAL_INT0_ENABLE" */
690 /* SHub Local Interrupt 0 Enable */
691 /* ==================================================================== */
693 #define SH_LOCAL_INT0_ENABLE 0x0000000110000500
694 #define SH_LOCAL_INT0_ENABLE_MASK 0x000000000000f7ff
695 #define SH_LOCAL_INT0_ENABLE_INIT 0x0000000000000000
697 /* SH_LOCAL_INT0_ENABLE_PI_HW_INT */
698 /* Description: Enable PI Hardware interrupt */
699 #define SH_LOCAL_INT0_ENABLE_PI_HW_INT_SHFT 0
700 #define SH_LOCAL_INT0_ENABLE_PI_HW_INT_MASK 0x0000000000000001
702 /* SH_LOCAL_INT0_ENABLE_MD_HW_INT */
703 /* Description: Enable MD Hardware interrupt */
704 #define SH_LOCAL_INT0_ENABLE_MD_HW_INT_SHFT 1
705 #define SH_LOCAL_INT0_ENABLE_MD_HW_INT_MASK 0x0000000000000002
707 /* SH_LOCAL_INT0_ENABLE_XN_HW_INT */
708 /* Description: Enable XN Hardware interrupt */
709 #define SH_LOCAL_INT0_ENABLE_XN_HW_INT_SHFT 2
710 #define SH_LOCAL_INT0_ENABLE_XN_HW_INT_MASK 0x0000000000000004
712 /* SH_LOCAL_INT0_ENABLE_LB_HW_INT */
713 /* Description: Enable LB Hardware interrupt */
714 #define SH_LOCAL_INT0_ENABLE_LB_HW_INT_SHFT 3
715 #define SH_LOCAL_INT0_ENABLE_LB_HW_INT_MASK 0x0000000000000008
717 /* SH_LOCAL_INT0_ENABLE_II_HW_INT */
718 /* Description: Enable II wrapper Hardware interrupt */
719 #define SH_LOCAL_INT0_ENABLE_II_HW_INT_SHFT 4
720 #define SH_LOCAL_INT0_ENABLE_II_HW_INT_MASK 0x0000000000000010
722 /* SH_LOCAL_INT0_ENABLE_PI_CE_INT */
723 /* Description: Enable PI Correctable Error Interrupt */
724 #define SH_LOCAL_INT0_ENABLE_PI_CE_INT_SHFT 5
725 #define SH_LOCAL_INT0_ENABLE_PI_CE_INT_MASK 0x0000000000000020
727 /* SH_LOCAL_INT0_ENABLE_MD_CE_INT */
728 /* Description: Enable MD Correctable Error Interrupt */
729 #define SH_LOCAL_INT0_ENABLE_MD_CE_INT_SHFT 6
730 #define SH_LOCAL_INT0_ENABLE_MD_CE_INT_MASK 0x0000000000000040
732 /* SH_LOCAL_INT0_ENABLE_XN_CE_INT */
733 /* Description: Enable XN Correctable Error Interrupt */
734 #define SH_LOCAL_INT0_ENABLE_XN_CE_INT_SHFT 7
735 #define SH_LOCAL_INT0_ENABLE_XN_CE_INT_MASK 0x0000000000000080
737 /* SH_LOCAL_INT0_ENABLE_PI_UCE_INT */
738 /* Description: Enable PI Correctable Error Interrupt */
739 #define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_SHFT 8
740 #define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_MASK 0x0000000000000100
742 /* SH_LOCAL_INT0_ENABLE_MD_UCE_INT */
743 /* Description: Enable MD Correctable Error Interrupt */
744 #define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_SHFT 9
745 #define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_MASK 0x0000000000000200
747 /* SH_LOCAL_INT0_ENABLE_XN_UCE_INT */
748 /* Description: Enable XN Correctable Error Interrupt */
749 #define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_SHFT 10
750 #define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_MASK 0x0000000000000400
752 /* SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT */
753 /* Description: Enable System Shutdown Interrupt */
754 #define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
755 #define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
757 /* SH_LOCAL_INT0_ENABLE_UART_INT */
758 /* Description: Enable Junk Bus UART Interrupt */
759 #define SH_LOCAL_INT0_ENABLE_UART_INT_SHFT 13
760 #define SH_LOCAL_INT0_ENABLE_UART_INT_MASK 0x0000000000002000
762 /* SH_LOCAL_INT0_ENABLE_L1_NMI_INT */
763 /* Description: Enable L1 Controller NMI Interrupt */
764 #define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 14
765 #define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000000000004000
767 /* SH_LOCAL_INT0_ENABLE_STOP_CLOCK */
768 /* Description: Stop Clock Interrupt */
769 #define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 15
770 #define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000000000008000
772 /* ==================================================================== */
773 /* Register "SH_LOCAL_INT1_CONFIG" */
774 /* SHub Local Interrupt 1 Registers */
775 /* ==================================================================== */
777 #define SH_LOCAL_INT1_CONFIG 0x0000000110000580
778 #define SH_LOCAL_INT1_CONFIG_MASK 0x0ff3ffffffefffff
779 #define SH_LOCAL_INT1_CONFIG_INIT 0x0000000000000000
781 /* SH_LOCAL_INT1_CONFIG_TYPE */
782 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
783 #define SH_LOCAL_INT1_CONFIG_TYPE_SHFT 0
784 #define SH_LOCAL_INT1_CONFIG_TYPE_MASK 0x0000000000000007
786 /* SH_LOCAL_INT1_CONFIG_AGT */
787 /* Description: Agent, must be 0 for SHub */
788 #define SH_LOCAL_INT1_CONFIG_AGT_SHFT 3
789 #define SH_LOCAL_INT1_CONFIG_AGT_MASK 0x0000000000000008
791 /* SH_LOCAL_INT1_CONFIG_PID */
792 /* Description: Processor ID, same setting as on targeted McKinley */
793 #define SH_LOCAL_INT1_CONFIG_PID_SHFT 4
794 #define SH_LOCAL_INT1_CONFIG_PID_MASK 0x00000000000ffff0
796 /* SH_LOCAL_INT1_CONFIG_BASE */
797 /* Description: Optional interrupt vector area, 2MB aligned */
798 #define SH_LOCAL_INT1_CONFIG_BASE_SHFT 21
799 #define SH_LOCAL_INT1_CONFIG_BASE_MASK 0x0003ffffffe00000
801 /* SH_LOCAL_INT1_CONFIG_IDX */
802 /* Description: Targeted McKinley interrupt vector */
803 #define SH_LOCAL_INT1_CONFIG_IDX_SHFT 52
804 #define SH_LOCAL_INT1_CONFIG_IDX_MASK 0x0ff0000000000000
806 /* ==================================================================== */
807 /* Register "SH_LOCAL_INT1_ENABLE" */
808 /* SHub Local Interrupt 1 Enable */
809 /* ==================================================================== */
811 #define SH_LOCAL_INT1_ENABLE 0x0000000110000600
812 #define SH_LOCAL_INT1_ENABLE_MASK 0x000000000000f7ff
813 #define SH_LOCAL_INT1_ENABLE_INIT 0x0000000000000000
815 /* SH_LOCAL_INT1_ENABLE_PI_HW_INT */
816 /* Description: Enable PI Hardware interrupt */
817 #define SH_LOCAL_INT1_ENABLE_PI_HW_INT_SHFT 0
818 #define SH_LOCAL_INT1_ENABLE_PI_HW_INT_MASK 0x0000000000000001
820 /* SH_LOCAL_INT1_ENABLE_MD_HW_INT */
821 /* Description: Enable MD Hardware interrupt */
822 #define SH_LOCAL_INT1_ENABLE_MD_HW_INT_SHFT 1
823 #define SH_LOCAL_INT1_ENABLE_MD_HW_INT_MASK 0x0000000000000002
825 /* SH_LOCAL_INT1_ENABLE_XN_HW_INT */
826 /* Description: Enable XN Hardware interrupt */
827 #define SH_LOCAL_INT1_ENABLE_XN_HW_INT_SHFT 2
828 #define SH_LOCAL_INT1_ENABLE_XN_HW_INT_MASK 0x0000000000000004
830 /* SH_LOCAL_INT1_ENABLE_LB_HW_INT */
831 /* Description: Enable LB Hardware interrupt */
832 #define SH_LOCAL_INT1_ENABLE_LB_HW_INT_SHFT 3
833 #define SH_LOCAL_INT1_ENABLE_LB_HW_INT_MASK 0x0000000000000008
835 /* SH_LOCAL_INT1_ENABLE_II_HW_INT */
836 /* Description: Enable II wrapper Hardware interrupt */
837 #define SH_LOCAL_INT1_ENABLE_II_HW_INT_SHFT 4
838 #define SH_LOCAL_INT1_ENABLE_II_HW_INT_MASK 0x0000000000000010
840 /* SH_LOCAL_INT1_ENABLE_PI_CE_INT */
841 /* Description: Enable PI Correctable Error Interrupt */
842 #define SH_LOCAL_INT1_ENABLE_PI_CE_INT_SHFT 5
843 #define SH_LOCAL_INT1_ENABLE_PI_CE_INT_MASK 0x0000000000000020
845 /* SH_LOCAL_INT1_ENABLE_MD_CE_INT */
846 /* Description: Enable MD Correctable Error Interrupt */
847 #define SH_LOCAL_INT1_ENABLE_MD_CE_INT_SHFT 6
848 #define SH_LOCAL_INT1_ENABLE_MD_CE_INT_MASK 0x0000000000000040
850 /* SH_LOCAL_INT1_ENABLE_XN_CE_INT */
851 /* Description: Enable XN Correctable Error Interrupt */
852 #define SH_LOCAL_INT1_ENABLE_XN_CE_INT_SHFT 7
853 #define SH_LOCAL_INT1_ENABLE_XN_CE_INT_MASK 0x0000000000000080
855 /* SH_LOCAL_INT1_ENABLE_PI_UCE_INT */
856 /* Description: Enable PI Correctable Error Interrupt */
857 #define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_SHFT 8
858 #define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_MASK 0x0000000000000100
860 /* SH_LOCAL_INT1_ENABLE_MD_UCE_INT */
861 /* Description: Enable MD Correctable Error Interrupt */
862 #define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_SHFT 9
863 #define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_MASK 0x0000000000000200
865 /* SH_LOCAL_INT1_ENABLE_XN_UCE_INT */
866 /* Description: Enable XN Correctable Error Interrupt */
867 #define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_SHFT 10
868 #define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_MASK 0x0000000000000400
870 /* SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT */
871 /* Description: Enable System Shutdown Interrupt */
872 #define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
873 #define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
875 /* SH_LOCAL_INT1_ENABLE_UART_INT */
876 /* Description: Enable Junk Bus UART Interrupt */
877 #define SH_LOCAL_INT1_ENABLE_UART_INT_SHFT 13
878 #define SH_LOCAL_INT1_ENABLE_UART_INT_MASK 0x0000000000002000
880 /* SH_LOCAL_INT1_ENABLE_L1_NMI_INT */
881 /* Description: Enable L1 Controller NMI Interrupt */
882 #define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_SHFT 14
883 #define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_MASK 0x0000000000004000
885 /* SH_LOCAL_INT1_ENABLE_STOP_CLOCK */
886 /* Description: Stop Clock Interrupt */
887 #define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_SHFT 15
888 #define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_MASK 0x0000000000008000
890 /* ==================================================================== */
891 /* Register "SH_LOCAL_INT2_CONFIG" */
892 /* SHub Local Interrupt 2 Registers */
893 /* ==================================================================== */
895 #define SH_LOCAL_INT2_CONFIG 0x0000000110000680
896 #define SH_LOCAL_INT2_CONFIG_MASK 0x0ff3ffffffefffff
897 #define SH_LOCAL_INT2_CONFIG_INIT 0x0000000000000000
899 /* SH_LOCAL_INT2_CONFIG_TYPE */
900 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
901 #define SH_LOCAL_INT2_CONFIG_TYPE_SHFT 0
902 #define SH_LOCAL_INT2_CONFIG_TYPE_MASK 0x0000000000000007
904 /* SH_LOCAL_INT2_CONFIG_AGT */
905 /* Description: Agent, must be 0 for SHub */
906 #define SH_LOCAL_INT2_CONFIG_AGT_SHFT 3
907 #define SH_LOCAL_INT2_CONFIG_AGT_MASK 0x0000000000000008
909 /* SH_LOCAL_INT2_CONFIG_PID */
910 /* Description: Processor ID, same setting as on targeted McKinley */
911 #define SH_LOCAL_INT2_CONFIG_PID_SHFT 4
912 #define SH_LOCAL_INT2_CONFIG_PID_MASK 0x00000000000ffff0
914 /* SH_LOCAL_INT2_CONFIG_BASE */
915 /* Description: Optional interrupt vector area, 2MB aligned */
916 #define SH_LOCAL_INT2_CONFIG_BASE_SHFT 21
917 #define SH_LOCAL_INT2_CONFIG_BASE_MASK 0x0003ffffffe00000
919 /* SH_LOCAL_INT2_CONFIG_IDX */
920 /* Description: Targeted McKinley interrupt vector */
921 #define SH_LOCAL_INT2_CONFIG_IDX_SHFT 52
922 #define SH_LOCAL_INT2_CONFIG_IDX_MASK 0x0ff0000000000000
924 /* ==================================================================== */
925 /* Register "SH_LOCAL_INT2_ENABLE" */
926 /* SHub Local Interrupt 2 Enable */
927 /* ==================================================================== */
929 #define SH_LOCAL_INT2_ENABLE 0x0000000110000700
930 #define SH_LOCAL_INT2_ENABLE_MASK 0x000000000000f7ff
931 #define SH_LOCAL_INT2_ENABLE_INIT 0x0000000000000000
933 /* SH_LOCAL_INT2_ENABLE_PI_HW_INT */
934 /* Description: Enable PI Hardware interrupt */
935 #define SH_LOCAL_INT2_ENABLE_PI_HW_INT_SHFT 0
936 #define SH_LOCAL_INT2_ENABLE_PI_HW_INT_MASK 0x0000000000000001
938 /* SH_LOCAL_INT2_ENABLE_MD_HW_INT */
939 /* Description: Enable MD Hardware interrupt */
940 #define SH_LOCAL_INT2_ENABLE_MD_HW_INT_SHFT 1
941 #define SH_LOCAL_INT2_ENABLE_MD_HW_INT_MASK 0x0000000000000002
943 /* SH_LOCAL_INT2_ENABLE_XN_HW_INT */
944 /* Description: Enable XN Hardware interrupt */
945 #define SH_LOCAL_INT2_ENABLE_XN_HW_INT_SHFT 2
946 #define SH_LOCAL_INT2_ENABLE_XN_HW_INT_MASK 0x0000000000000004
948 /* SH_LOCAL_INT2_ENABLE_LB_HW_INT */
949 /* Description: Enable LB Hardware interrupt */
950 #define SH_LOCAL_INT2_ENABLE_LB_HW_INT_SHFT 3
951 #define SH_LOCAL_INT2_ENABLE_LB_HW_INT_MASK 0x0000000000000008
953 /* SH_LOCAL_INT2_ENABLE_II_HW_INT */
954 /* Description: Enable II wrapper Hardware interrupt */
955 #define SH_LOCAL_INT2_ENABLE_II_HW_INT_SHFT 4
956 #define SH_LOCAL_INT2_ENABLE_II_HW_INT_MASK 0x0000000000000010
958 /* SH_LOCAL_INT2_ENABLE_PI_CE_INT */
959 /* Description: Enable PI Correctable Error Interrupt */
960 #define SH_LOCAL_INT2_ENABLE_PI_CE_INT_SHFT 5
961 #define SH_LOCAL_INT2_ENABLE_PI_CE_INT_MASK 0x0000000000000020
963 /* SH_LOCAL_INT2_ENABLE_MD_CE_INT */
964 /* Description: Enable MD Correctable Error Interrupt */
965 #define SH_LOCAL_INT2_ENABLE_MD_CE_INT_SHFT 6
966 #define SH_LOCAL_INT2_ENABLE_MD_CE_INT_MASK 0x0000000000000040
968 /* SH_LOCAL_INT2_ENABLE_XN_CE_INT */
969 /* Description: Enable XN Correctable Error Interrupt */
970 #define SH_LOCAL_INT2_ENABLE_XN_CE_INT_SHFT 7
971 #define SH_LOCAL_INT2_ENABLE_XN_CE_INT_MASK 0x0000000000000080
973 /* SH_LOCAL_INT2_ENABLE_PI_UCE_INT */
974 /* Description: Enable PI Correctable Error Interrupt */
975 #define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_SHFT 8
976 #define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_MASK 0x0000000000000100
978 /* SH_LOCAL_INT2_ENABLE_MD_UCE_INT */
979 /* Description: Enable MD Correctable Error Interrupt */
980 #define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_SHFT 9
981 #define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_MASK 0x0000000000000200
983 /* SH_LOCAL_INT2_ENABLE_XN_UCE_INT */
984 /* Description: Enable XN Correctable Error Interrupt */
985 #define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_SHFT 10
986 #define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_MASK 0x0000000000000400
988 /* SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT */
989 /* Description: Enable System Shutdown Interrupt */
990 #define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
991 #define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
993 /* SH_LOCAL_INT2_ENABLE_UART_INT */
994 /* Description: Enable Junk Bus UART Interrupt */
995 #define SH_LOCAL_INT2_ENABLE_UART_INT_SHFT 13
996 #define SH_LOCAL_INT2_ENABLE_UART_INT_MASK 0x0000000000002000
998 /* SH_LOCAL_INT2_ENABLE_L1_NMI_INT */
999 /* Description: Enable L1 Controller NMI Interrupt */
1000 #define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_SHFT 14
1001 #define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_MASK 0x0000000000004000
1003 /* SH_LOCAL_INT2_ENABLE_STOP_CLOCK */
1004 /* Description: Stop Clock Interrupt */
1005 #define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_SHFT 15
1006 #define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_MASK 0x0000000000008000
1008 /* ==================================================================== */
1009 /* Register "SH_LOCAL_INT3_CONFIG" */
1010 /* SHub Local Interrupt 3 Registers */
1011 /* ==================================================================== */
1013 #define SH_LOCAL_INT3_CONFIG 0x0000000110000780
1014 #define SH_LOCAL_INT3_CONFIG_MASK 0x0ff3ffffffefffff
1015 #define SH_LOCAL_INT3_CONFIG_INIT 0x0000000000000000
1017 /* SH_LOCAL_INT3_CONFIG_TYPE */
1018 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1019 #define SH_LOCAL_INT3_CONFIG_TYPE_SHFT 0
1020 #define SH_LOCAL_INT3_CONFIG_TYPE_MASK 0x0000000000000007
1022 /* SH_LOCAL_INT3_CONFIG_AGT */
1023 /* Description: Agent, must be 0 for SHub */
1024 #define SH_LOCAL_INT3_CONFIG_AGT_SHFT 3
1025 #define SH_LOCAL_INT3_CONFIG_AGT_MASK 0x0000000000000008
1027 /* SH_LOCAL_INT3_CONFIG_PID */
1028 /* Description: Processor ID, same setting as on targeted McKinley */
1029 #define SH_LOCAL_INT3_CONFIG_PID_SHFT 4
1030 #define SH_LOCAL_INT3_CONFIG_PID_MASK 0x00000000000ffff0
1032 /* SH_LOCAL_INT3_CONFIG_BASE */
1033 /* Description: Optional interrupt vector area, 2MB aligned */
1034 #define SH_LOCAL_INT3_CONFIG_BASE_SHFT 21
1035 #define SH_LOCAL_INT3_CONFIG_BASE_MASK 0x0003ffffffe00000
1037 /* SH_LOCAL_INT3_CONFIG_IDX */
1038 /* Description: Targeted McKinley interrupt vector */
1039 #define SH_LOCAL_INT3_CONFIG_IDX_SHFT 52
1040 #define SH_LOCAL_INT3_CONFIG_IDX_MASK 0x0ff0000000000000
1042 /* ==================================================================== */
1043 /* Register "SH_LOCAL_INT3_ENABLE" */
1044 /* SHub Local Interrupt 3 Enable */
1045 /* ==================================================================== */
1047 #define SH_LOCAL_INT3_ENABLE 0x0000000110000800
1048 #define SH_LOCAL_INT3_ENABLE_MASK 0x000000000000f7ff
1049 #define SH_LOCAL_INT3_ENABLE_INIT 0x0000000000000000
1051 /* SH_LOCAL_INT3_ENABLE_PI_HW_INT */
1052 /* Description: Enable PI Hardware interrupt */
1053 #define SH_LOCAL_INT3_ENABLE_PI_HW_INT_SHFT 0
1054 #define SH_LOCAL_INT3_ENABLE_PI_HW_INT_MASK 0x0000000000000001
1056 /* SH_LOCAL_INT3_ENABLE_MD_HW_INT */
1057 /* Description: Enable MD Hardware interrupt */
1058 #define SH_LOCAL_INT3_ENABLE_MD_HW_INT_SHFT 1
1059 #define SH_LOCAL_INT3_ENABLE_MD_HW_INT_MASK 0x0000000000000002
1061 /* SH_LOCAL_INT3_ENABLE_XN_HW_INT */
1062 /* Description: Enable XN Hardware interrupt */
1063 #define SH_LOCAL_INT3_ENABLE_XN_HW_INT_SHFT 2
1064 #define SH_LOCAL_INT3_ENABLE_XN_HW_INT_MASK 0x0000000000000004
1066 /* SH_LOCAL_INT3_ENABLE_LB_HW_INT */
1067 /* Description: Enable LB Hardware interrupt */
1068 #define SH_LOCAL_INT3_ENABLE_LB_HW_INT_SHFT 3
1069 #define SH_LOCAL_INT3_ENABLE_LB_HW_INT_MASK 0x0000000000000008
1071 /* SH_LOCAL_INT3_ENABLE_II_HW_INT */
1072 /* Description: Enable II wrapper Hardware interrupt */
1073 #define SH_LOCAL_INT3_ENABLE_II_HW_INT_SHFT 4
1074 #define SH_LOCAL_INT3_ENABLE_II_HW_INT_MASK 0x0000000000000010
1076 /* SH_LOCAL_INT3_ENABLE_PI_CE_INT */
1077 /* Description: Enable PI Correctable Error Interrupt */
1078 #define SH_LOCAL_INT3_ENABLE_PI_CE_INT_SHFT 5
1079 #define SH_LOCAL_INT3_ENABLE_PI_CE_INT_MASK 0x0000000000000020
1081 /* SH_LOCAL_INT3_ENABLE_MD_CE_INT */
1082 /* Description: Enable MD Correctable Error Interrupt */
1083 #define SH_LOCAL_INT3_ENABLE_MD_CE_INT_SHFT 6
1084 #define SH_LOCAL_INT3_ENABLE_MD_CE_INT_MASK 0x0000000000000040
1086 /* SH_LOCAL_INT3_ENABLE_XN_CE_INT */
1087 /* Description: Enable XN Correctable Error Interrupt */
1088 #define SH_LOCAL_INT3_ENABLE_XN_CE_INT_SHFT 7
1089 #define SH_LOCAL_INT3_ENABLE_XN_CE_INT_MASK 0x0000000000000080
1091 /* SH_LOCAL_INT3_ENABLE_PI_UCE_INT */
1092 /* Description: Enable PI Correctable Error Interrupt */
1093 #define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_SHFT 8
1094 #define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_MASK 0x0000000000000100
1096 /* SH_LOCAL_INT3_ENABLE_MD_UCE_INT */
1097 /* Description: Enable MD Correctable Error Interrupt */
1098 #define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_SHFT 9
1099 #define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_MASK 0x0000000000000200
1101 /* SH_LOCAL_INT3_ENABLE_XN_UCE_INT */
1102 /* Description: Enable XN Correctable Error Interrupt */
1103 #define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_SHFT 10
1104 #define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_MASK 0x0000000000000400
1106 /* SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT */
1107 /* Description: Enable System Shutdown Interrupt */
1108 #define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
1109 #define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
1111 /* SH_LOCAL_INT3_ENABLE_UART_INT */
1112 /* Description: Enable Junk Bus UART Interrupt */
1113 #define SH_LOCAL_INT3_ENABLE_UART_INT_SHFT 13
1114 #define SH_LOCAL_INT3_ENABLE_UART_INT_MASK 0x0000000000002000
1116 /* SH_LOCAL_INT3_ENABLE_L1_NMI_INT */
1117 /* Description: Enable L1 Controller NMI Interrupt */
1118 #define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_SHFT 14
1119 #define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_MASK 0x0000000000004000
1121 /* SH_LOCAL_INT3_ENABLE_STOP_CLOCK */
1122 /* Description: Stop Clock Interrupt */
1123 #define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_SHFT 15
1124 #define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_MASK 0x0000000000008000
1126 /* ==================================================================== */
1127 /* Register "SH_LOCAL_INT4_CONFIG" */
1128 /* SHub Local Interrupt 4 Registers */
1129 /* ==================================================================== */
1131 #define SH_LOCAL_INT4_CONFIG 0x0000000110000880
1132 #define SH_LOCAL_INT4_CONFIG_MASK 0x0ff3ffffffefffff
1133 #define SH_LOCAL_INT4_CONFIG_INIT 0x0000000000000000
1135 /* SH_LOCAL_INT4_CONFIG_TYPE */
1136 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1137 #define SH_LOCAL_INT4_CONFIG_TYPE_SHFT 0
1138 #define SH_LOCAL_INT4_CONFIG_TYPE_MASK 0x0000000000000007
1140 /* SH_LOCAL_INT4_CONFIG_AGT */
1141 /* Description: Agent, must be 0 for SHub */
1142 #define SH_LOCAL_INT4_CONFIG_AGT_SHFT 3
1143 #define SH_LOCAL_INT4_CONFIG_AGT_MASK 0x0000000000000008
1145 /* SH_LOCAL_INT4_CONFIG_PID */
1146 /* Description: Processor ID, same setting as on targeted McKinley */
1147 #define SH_LOCAL_INT4_CONFIG_PID_SHFT 4
1148 #define SH_LOCAL_INT4_CONFIG_PID_MASK 0x00000000000ffff0
1150 /* SH_LOCAL_INT4_CONFIG_BASE */
1151 /* Description: Optional interrupt vector area, 2MB aligned */
1152 #define SH_LOCAL_INT4_CONFIG_BASE_SHFT 21
1153 #define SH_LOCAL_INT4_CONFIG_BASE_MASK 0x0003ffffffe00000
1155 /* SH_LOCAL_INT4_CONFIG_IDX */
1156 /* Description: Targeted McKinley interrupt vector */
1157 #define SH_LOCAL_INT4_CONFIG_IDX_SHFT 52
1158 #define SH_LOCAL_INT4_CONFIG_IDX_MASK 0x0ff0000000000000
1160 /* ==================================================================== */
1161 /* Register "SH_LOCAL_INT4_ENABLE" */
1162 /* SHub Local Interrupt 4 Enable */
1163 /* ==================================================================== */
1165 #define SH_LOCAL_INT4_ENABLE 0x0000000110000900
1166 #define SH_LOCAL_INT4_ENABLE_MASK 0x000000000000f7ff
1167 #define SH_LOCAL_INT4_ENABLE_INIT 0x0000000000000000
1169 /* SH_LOCAL_INT4_ENABLE_PI_HW_INT */
1170 /* Description: Enable PI Hardware interrupt */
1171 #define SH_LOCAL_INT4_ENABLE_PI_HW_INT_SHFT 0
1172 #define SH_LOCAL_INT4_ENABLE_PI_HW_INT_MASK 0x0000000000000001
1174 /* SH_LOCAL_INT4_ENABLE_MD_HW_INT */
1175 /* Description: Enable MD Hardware interrupt */
1176 #define SH_LOCAL_INT4_ENABLE_MD_HW_INT_SHFT 1
1177 #define SH_LOCAL_INT4_ENABLE_MD_HW_INT_MASK 0x0000000000000002
1179 /* SH_LOCAL_INT4_ENABLE_XN_HW_INT */
1180 /* Description: Enable XN Hardware interrupt */
1181 #define SH_LOCAL_INT4_ENABLE_XN_HW_INT_SHFT 2
1182 #define SH_LOCAL_INT4_ENABLE_XN_HW_INT_MASK 0x0000000000000004
1184 /* SH_LOCAL_INT4_ENABLE_LB_HW_INT */
1185 /* Description: Enable LB Hardware interrupt */
1186 #define SH_LOCAL_INT4_ENABLE_LB_HW_INT_SHFT 3
1187 #define SH_LOCAL_INT4_ENABLE_LB_HW_INT_MASK 0x0000000000000008
1189 /* SH_LOCAL_INT4_ENABLE_II_HW_INT */
1190 /* Description: Enable II wrapper Hardware interrupt */
1191 #define SH_LOCAL_INT4_ENABLE_II_HW_INT_SHFT 4
1192 #define SH_LOCAL_INT4_ENABLE_II_HW_INT_MASK 0x0000000000000010
1194 /* SH_LOCAL_INT4_ENABLE_PI_CE_INT */
1195 /* Description: Enable PI Correctable Error Interrupt */
1196 #define SH_LOCAL_INT4_ENABLE_PI_CE_INT_SHFT 5
1197 #define SH_LOCAL_INT4_ENABLE_PI_CE_INT_MASK 0x0000000000000020
1199 /* SH_LOCAL_INT4_ENABLE_MD_CE_INT */
1200 /* Description: Enable MD Correctable Error Interrupt */
1201 #define SH_LOCAL_INT4_ENABLE_MD_CE_INT_SHFT 6
1202 #define SH_LOCAL_INT4_ENABLE_MD_CE_INT_MASK 0x0000000000000040
1204 /* SH_LOCAL_INT4_ENABLE_XN_CE_INT */
1205 /* Description: Enable XN Correctable Error Interrupt */
1206 #define SH_LOCAL_INT4_ENABLE_XN_CE_INT_SHFT 7
1207 #define SH_LOCAL_INT4_ENABLE_XN_CE_INT_MASK 0x0000000000000080
1209 /* SH_LOCAL_INT4_ENABLE_PI_UCE_INT */
1210 /* Description: Enable PI Correctable Error Interrupt */
1211 #define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_SHFT 8
1212 #define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_MASK 0x0000000000000100
1214 /* SH_LOCAL_INT4_ENABLE_MD_UCE_INT */
1215 /* Description: Enable MD Correctable Error Interrupt */
1216 #define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_SHFT 9
1217 #define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_MASK 0x0000000000000200
1219 /* SH_LOCAL_INT4_ENABLE_XN_UCE_INT */
1220 /* Description: Enable XN Correctable Error Interrupt */
1221 #define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_SHFT 10
1222 #define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_MASK 0x0000000000000400
1224 /* SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT */
1225 /* Description: Enable System Shutdown Interrupt */
1226 #define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
1227 #define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
1229 /* SH_LOCAL_INT4_ENABLE_UART_INT */
1230 /* Description: Enable Junk Bus UART Interrupt */
1231 #define SH_LOCAL_INT4_ENABLE_UART_INT_SHFT 13
1232 #define SH_LOCAL_INT4_ENABLE_UART_INT_MASK 0x0000000000002000
1234 /* SH_LOCAL_INT4_ENABLE_L1_NMI_INT */
1235 /* Description: Enable L1 Controller NMI Interrupt */
1236 #define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_SHFT 14
1237 #define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_MASK 0x0000000000004000
1239 /* SH_LOCAL_INT4_ENABLE_STOP_CLOCK */
1240 /* Description: Stop Clock Interrupt */
1241 #define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_SHFT 15
1242 #define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_MASK 0x0000000000008000
1244 /* ==================================================================== */
1245 /* Register "SH_LOCAL_INT5_CONFIG" */
1246 /* SHub Local Interrupt 5 Registers */
1247 /* ==================================================================== */
1249 #define SH_LOCAL_INT5_CONFIG 0x0000000110000980
1250 #define SH_LOCAL_INT5_CONFIG_MASK 0x0ff3ffffffefffff
1251 #define SH_LOCAL_INT5_CONFIG_INIT 0x0000000000000000
1253 /* SH_LOCAL_INT5_CONFIG_TYPE */
1254 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1255 #define SH_LOCAL_INT5_CONFIG_TYPE_SHFT 0
1256 #define SH_LOCAL_INT5_CONFIG_TYPE_MASK 0x0000000000000007
1258 /* SH_LOCAL_INT5_CONFIG_AGT */
1259 /* Description: Agent, must be 0 for SHub */
1260 #define SH_LOCAL_INT5_CONFIG_AGT_SHFT 3
1261 #define SH_LOCAL_INT5_CONFIG_AGT_MASK 0x0000000000000008
1263 /* SH_LOCAL_INT5_CONFIG_PID */
1264 /* Description: Processor ID, same setting as on targeted McKinley */
1265 #define SH_LOCAL_INT5_CONFIG_PID_SHFT 4
1266 #define SH_LOCAL_INT5_CONFIG_PID_MASK 0x00000000000ffff0
1268 /* SH_LOCAL_INT5_CONFIG_BASE */
1269 /* Description: Optional interrupt vector area, 2MB aligned */
1270 #define SH_LOCAL_INT5_CONFIG_BASE_SHFT 21
1271 #define SH_LOCAL_INT5_CONFIG_BASE_MASK 0x0003ffffffe00000
1273 /* SH_LOCAL_INT5_CONFIG_IDX */
1274 /* Description: Targeted McKinley interrupt vector */
1275 #define SH_LOCAL_INT5_CONFIG_IDX_SHFT 52
1276 #define SH_LOCAL_INT5_CONFIG_IDX_MASK 0x0ff0000000000000
1278 /* ==================================================================== */
1279 /* Register "SH_LOCAL_INT5_ENABLE" */
1280 /* SHub Local Interrupt 5 Enable */
1281 /* ==================================================================== */
1283 #define SH_LOCAL_INT5_ENABLE 0x0000000110000a00
1284 #define SH_LOCAL_INT5_ENABLE_MASK 0x000000000000f7ff
1285 #define SH_LOCAL_INT5_ENABLE_INIT 0x0000000000000000
1287 /* SH_LOCAL_INT5_ENABLE_PI_HW_INT */
1288 /* Description: Enable PI Hardware interrupt */
1289 #define SH_LOCAL_INT5_ENABLE_PI_HW_INT_SHFT 0
1290 #define SH_LOCAL_INT5_ENABLE_PI_HW_INT_MASK 0x0000000000000001
1292 /* SH_LOCAL_INT5_ENABLE_MD_HW_INT */
1293 /* Description: Enable MD Hardware interrupt */
1294 #define SH_LOCAL_INT5_ENABLE_MD_HW_INT_SHFT 1
1295 #define SH_LOCAL_INT5_ENABLE_MD_HW_INT_MASK 0x0000000000000002
1297 /* SH_LOCAL_INT5_ENABLE_XN_HW_INT */
1298 /* Description: Enable XN Hardware interrupt */
1299 #define SH_LOCAL_INT5_ENABLE_XN_HW_INT_SHFT 2
1300 #define SH_LOCAL_INT5_ENABLE_XN_HW_INT_MASK 0x0000000000000004
1302 /* SH_LOCAL_INT5_ENABLE_LB_HW_INT */
1303 /* Description: Enable LB Hardware interrupt */
1304 #define SH_LOCAL_INT5_ENABLE_LB_HW_INT_SHFT 3
1305 #define SH_LOCAL_INT5_ENABLE_LB_HW_INT_MASK 0x0000000000000008
1307 /* SH_LOCAL_INT5_ENABLE_II_HW_INT */
1308 /* Description: Enable II wrapper Hardware interrupt */
1309 #define SH_LOCAL_INT5_ENABLE_II_HW_INT_SHFT 4
1310 #define SH_LOCAL_INT5_ENABLE_II_HW_INT_MASK 0x0000000000000010
1312 /* SH_LOCAL_INT5_ENABLE_PI_CE_INT */
1313 /* Description: Enable PI Correctable Error Interrupt */
1314 #define SH_LOCAL_INT5_ENABLE_PI_CE_INT_SHFT 5
1315 #define SH_LOCAL_INT5_ENABLE_PI_CE_INT_MASK 0x0000000000000020
1317 /* SH_LOCAL_INT5_ENABLE_MD_CE_INT */
1318 /* Description: Enable MD Correctable Error Interrupt */
1319 #define SH_LOCAL_INT5_ENABLE_MD_CE_INT_SHFT 6
1320 #define SH_LOCAL_INT5_ENABLE_MD_CE_INT_MASK 0x0000000000000040
1322 /* SH_LOCAL_INT5_ENABLE_XN_CE_INT */
1323 /* Description: Enable XN Correctable Error Interrupt */
1324 #define SH_LOCAL_INT5_ENABLE_XN_CE_INT_SHFT 7
1325 #define SH_LOCAL_INT5_ENABLE_XN_CE_INT_MASK 0x0000000000000080
1327 /* SH_LOCAL_INT5_ENABLE_PI_UCE_INT */
1328 /* Description: Enable PI Correctable Error Interrupt */
1329 #define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_SHFT 8
1330 #define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_MASK 0x0000000000000100
1332 /* SH_LOCAL_INT5_ENABLE_MD_UCE_INT */
1333 /* Description: Enable MD Correctable Error Interrupt */
1334 #define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_SHFT 9
1335 #define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_MASK 0x0000000000000200
1337 /* SH_LOCAL_INT5_ENABLE_XN_UCE_INT */
1338 /* Description: Enable XN Correctable Error Interrupt */
1339 #define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_SHFT 10
1340 #define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_MASK 0x0000000000000400
1342 /* SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT */
1343 /* Description: Enable System Shutdown Interrupt */
1344 #define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
1345 #define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
1347 /* SH_LOCAL_INT5_ENABLE_UART_INT */
1348 /* Description: Enable Junk Bus UART Interrupt */
1349 #define SH_LOCAL_INT5_ENABLE_UART_INT_SHFT 13
1350 #define SH_LOCAL_INT5_ENABLE_UART_INT_MASK 0x0000000000002000
1352 /* SH_LOCAL_INT5_ENABLE_L1_NMI_INT */
1353 /* Description: Enable L1 Controller NMI Interrupt */
1354 #define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_SHFT 14
1355 #define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_MASK 0x0000000000004000
1357 /* SH_LOCAL_INT5_ENABLE_STOP_CLOCK */
1358 /* Description: Stop Clock Interrupt */
1359 #define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_SHFT 15
1360 #define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_MASK 0x0000000000008000
1362 /* ==================================================================== */
1363 /* Register "SH_PROC0_ERR_INT_CONFIG" */
1364 /* SHub Processor 0 Error Interrupt Registers */
1365 /* ==================================================================== */
1367 #define SH_PROC0_ERR_INT_CONFIG 0x0000000110000a80
1368 #define SH_PROC0_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff
1369 #define SH_PROC0_ERR_INT_CONFIG_INIT 0x0000000000000000
1371 /* SH_PROC0_ERR_INT_CONFIG_TYPE */
1372 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1373 #define SH_PROC0_ERR_INT_CONFIG_TYPE_SHFT 0
1374 #define SH_PROC0_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007
1376 /* SH_PROC0_ERR_INT_CONFIG_AGT */
1377 /* Description: Agent, must be 0 for SHub */
1378 #define SH_PROC0_ERR_INT_CONFIG_AGT_SHFT 3
1379 #define SH_PROC0_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008
1381 /* SH_PROC0_ERR_INT_CONFIG_PID */
1382 /* Description: Processor ID, same setting as on targeted McKinley */
1383 #define SH_PROC0_ERR_INT_CONFIG_PID_SHFT 4
1384 #define SH_PROC0_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0
1386 /* SH_PROC0_ERR_INT_CONFIG_BASE */
1387 /* Description: Optional interrupt vector area, 2MB aligned */
1388 #define SH_PROC0_ERR_INT_CONFIG_BASE_SHFT 21
1389 #define SH_PROC0_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1391 /* SH_PROC0_ERR_INT_CONFIG_IDX */
1392 /* Description: Targeted McKinley interrupt vector */
1393 #define SH_PROC0_ERR_INT_CONFIG_IDX_SHFT 52
1394 #define SH_PROC0_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1396 /* ==================================================================== */
1397 /* Register "SH_PROC1_ERR_INT_CONFIG" */
1398 /* SHub Processor 1 Error Interrupt Registers */
1399 /* ==================================================================== */
1401 #define SH_PROC1_ERR_INT_CONFIG 0x0000000110000b00
1402 #define SH_PROC1_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff
1403 #define SH_PROC1_ERR_INT_CONFIG_INIT 0x0000000000000000
1405 /* SH_PROC1_ERR_INT_CONFIG_TYPE */
1406 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1407 #define SH_PROC1_ERR_INT_CONFIG_TYPE_SHFT 0
1408 #define SH_PROC1_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007
1410 /* SH_PROC1_ERR_INT_CONFIG_AGT */
1411 /* Description: Agent, must be 0 for SHub */
1412 #define SH_PROC1_ERR_INT_CONFIG_AGT_SHFT 3
1413 #define SH_PROC1_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008
1415 /* SH_PROC1_ERR_INT_CONFIG_PID */
1416 /* Description: Processor ID, same setting as on targeted McKinley */
1417 #define SH_PROC1_ERR_INT_CONFIG_PID_SHFT 4
1418 #define SH_PROC1_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0
1420 /* SH_PROC1_ERR_INT_CONFIG_BASE */
1421 /* Description: Optional interrupt vector area, 2MB aligned */
1422 #define SH_PROC1_ERR_INT_CONFIG_BASE_SHFT 21
1423 #define SH_PROC1_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1425 /* SH_PROC1_ERR_INT_CONFIG_IDX */
1426 /* Description: Targeted McKinley interrupt vector */
1427 #define SH_PROC1_ERR_INT_CONFIG_IDX_SHFT 52
1428 #define SH_PROC1_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1430 /* ==================================================================== */
1431 /* Register "SH_PROC2_ERR_INT_CONFIG" */
1432 /* SHub Processor 2 Error Interrupt Registers */
1433 /* ==================================================================== */
1435 #define SH_PROC2_ERR_INT_CONFIG 0x0000000110000b80
1436 #define SH_PROC2_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff
1437 #define SH_PROC2_ERR_INT_CONFIG_INIT 0x0000000000000000
1439 /* SH_PROC2_ERR_INT_CONFIG_TYPE */
1440 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1441 #define SH_PROC2_ERR_INT_CONFIG_TYPE_SHFT 0
1442 #define SH_PROC2_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007
1444 /* SH_PROC2_ERR_INT_CONFIG_AGT */
1445 /* Description: Agent, must be 0 for SHub */
1446 #define SH_PROC2_ERR_INT_CONFIG_AGT_SHFT 3
1447 #define SH_PROC2_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008
1449 /* SH_PROC2_ERR_INT_CONFIG_PID */
1450 /* Description: Processor ID, same setting as on targeted McKinley */
1451 #define SH_PROC2_ERR_INT_CONFIG_PID_SHFT 4
1452 #define SH_PROC2_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0
1454 /* SH_PROC2_ERR_INT_CONFIG_BASE */
1455 /* Description: Optional interrupt vector area, 2MB aligned */
1456 #define SH_PROC2_ERR_INT_CONFIG_BASE_SHFT 21
1457 #define SH_PROC2_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1459 /* SH_PROC2_ERR_INT_CONFIG_IDX */
1460 /* Description: Targeted McKinley interrupt vector */
1461 #define SH_PROC2_ERR_INT_CONFIG_IDX_SHFT 52
1462 #define SH_PROC2_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1464 /* ==================================================================== */
1465 /* Register "SH_PROC3_ERR_INT_CONFIG" */
1466 /* SHub Processor 3 Error Interrupt Registers */
1467 /* ==================================================================== */
1469 #define SH_PROC3_ERR_INT_CONFIG 0x0000000110000c00
1470 #define SH_PROC3_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff
1471 #define SH_PROC3_ERR_INT_CONFIG_INIT 0x0000000000000000
1473 /* SH_PROC3_ERR_INT_CONFIG_TYPE */
1474 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1475 #define SH_PROC3_ERR_INT_CONFIG_TYPE_SHFT 0
1476 #define SH_PROC3_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007
1478 /* SH_PROC3_ERR_INT_CONFIG_AGT */
1479 /* Description: Agent, must be 0 for SHub */
1480 #define SH_PROC3_ERR_INT_CONFIG_AGT_SHFT 3
1481 #define SH_PROC3_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008
1483 /* SH_PROC3_ERR_INT_CONFIG_PID */
1484 /* Description: Processor ID, same setting as on targeted McKinley */
1485 #define SH_PROC3_ERR_INT_CONFIG_PID_SHFT 4
1486 #define SH_PROC3_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0
1488 /* SH_PROC3_ERR_INT_CONFIG_BASE */
1489 /* Description: Optional interrupt vector area, 2MB aligned */
1490 #define SH_PROC3_ERR_INT_CONFIG_BASE_SHFT 21
1491 #define SH_PROC3_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1493 /* SH_PROC3_ERR_INT_CONFIG_IDX */
1494 /* Description: Targeted McKinley interrupt vector */
1495 #define SH_PROC3_ERR_INT_CONFIG_IDX_SHFT 52
1496 #define SH_PROC3_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1498 /* ==================================================================== */
1499 /* Register "SH_PROC0_ADV_INT_CONFIG" */
1500 /* SHub Processor 0 Advisory Interrupt Registers */
1501 /* ==================================================================== */
1503 #define SH_PROC0_ADV_INT_CONFIG 0x0000000110000c80
1504 #define SH_PROC0_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff
1505 #define SH_PROC0_ADV_INT_CONFIG_INIT 0x0000000000000000
1507 /* SH_PROC0_ADV_INT_CONFIG_TYPE */
1508 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1509 #define SH_PROC0_ADV_INT_CONFIG_TYPE_SHFT 0
1510 #define SH_PROC0_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007
1512 /* SH_PROC0_ADV_INT_CONFIG_AGT */
1513 /* Description: Agent, must be 0 for SHub */
1514 #define SH_PROC0_ADV_INT_CONFIG_AGT_SHFT 3
1515 #define SH_PROC0_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008
1517 /* SH_PROC0_ADV_INT_CONFIG_PID */
1518 /* Description: Processor ID, same setting as on targeted McKinley */
1519 #define SH_PROC0_ADV_INT_CONFIG_PID_SHFT 4
1520 #define SH_PROC0_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0
1522 /* SH_PROC0_ADV_INT_CONFIG_BASE */
1523 /* Description: Optional interrupt vector area, 2MB aligned */
1524 #define SH_PROC0_ADV_INT_CONFIG_BASE_SHFT 21
1525 #define SH_PROC0_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1527 /* SH_PROC0_ADV_INT_CONFIG_IDX */
1528 /* Description: Targeted McKinley interrupt vector */
1529 #define SH_PROC0_ADV_INT_CONFIG_IDX_SHFT 52
1530 #define SH_PROC0_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1532 /* ==================================================================== */
1533 /* Register "SH_PROC1_ADV_INT_CONFIG" */
1534 /* SHub Processor 1 Advisory Interrupt Registers */
1535 /* ==================================================================== */
1537 #define SH_PROC1_ADV_INT_CONFIG 0x0000000110000d00
1538 #define SH_PROC1_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff
1539 #define SH_PROC1_ADV_INT_CONFIG_INIT 0x0000000000000000
1541 /* SH_PROC1_ADV_INT_CONFIG_TYPE */
1542 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1543 #define SH_PROC1_ADV_INT_CONFIG_TYPE_SHFT 0
1544 #define SH_PROC1_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007
1546 /* SH_PROC1_ADV_INT_CONFIG_AGT */
1547 /* Description: Agent, must be 0 for SHub */
1548 #define SH_PROC1_ADV_INT_CONFIG_AGT_SHFT 3
1549 #define SH_PROC1_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008
1551 /* SH_PROC1_ADV_INT_CONFIG_PID */
1552 /* Description: Processor ID, same setting as on targeted McKinley */
1553 #define SH_PROC1_ADV_INT_CONFIG_PID_SHFT 4
1554 #define SH_PROC1_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0
1556 /* SH_PROC1_ADV_INT_CONFIG_BASE */
1557 /* Description: Optional interrupt vector area, 2MB aligned */
1558 #define SH_PROC1_ADV_INT_CONFIG_BASE_SHFT 21
1559 #define SH_PROC1_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1561 /* SH_PROC1_ADV_INT_CONFIG_IDX */
1562 /* Description: Targeted McKinley interrupt vector */
1563 #define SH_PROC1_ADV_INT_CONFIG_IDX_SHFT 52
1564 #define SH_PROC1_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1566 /* ==================================================================== */
1567 /* Register "SH_PROC2_ADV_INT_CONFIG" */
1568 /* SHub Processor 2 Advisory Interrupt Registers */
1569 /* ==================================================================== */
1571 #define SH_PROC2_ADV_INT_CONFIG 0x0000000110000d80
1572 #define SH_PROC2_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff
1573 #define SH_PROC2_ADV_INT_CONFIG_INIT 0x0000000000000000
1575 /* SH_PROC2_ADV_INT_CONFIG_TYPE */
1576 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1577 #define SH_PROC2_ADV_INT_CONFIG_TYPE_SHFT 0
1578 #define SH_PROC2_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007
1580 /* SH_PROC2_ADV_INT_CONFIG_AGT */
1581 /* Description: Agent, must be 0 for SHub */
1582 #define SH_PROC2_ADV_INT_CONFIG_AGT_SHFT 3
1583 #define SH_PROC2_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008
1585 /* SH_PROC2_ADV_INT_CONFIG_PID */
1586 /* Description: Processor ID, same setting as on targeted McKinley */
1587 #define SH_PROC2_ADV_INT_CONFIG_PID_SHFT 4
1588 #define SH_PROC2_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0
1590 /* SH_PROC2_ADV_INT_CONFIG_BASE */
1591 /* Description: Optional interrupt vector area, 2MB aligned */
1592 #define SH_PROC2_ADV_INT_CONFIG_BASE_SHFT 21
1593 #define SH_PROC2_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1595 /* SH_PROC2_ADV_INT_CONFIG_IDX */
1596 /* Description: Targeted McKinley interrupt vector */
1597 #define SH_PROC2_ADV_INT_CONFIG_IDX_SHFT 52
1598 #define SH_PROC2_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1600 /* ==================================================================== */
1601 /* Register "SH_PROC3_ADV_INT_CONFIG" */
1602 /* SHub Processor 3 Advisory Interrupt Registers */
1603 /* ==================================================================== */
1605 #define SH_PROC3_ADV_INT_CONFIG 0x0000000110000e00
1606 #define SH_PROC3_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff
1607 #define SH_PROC3_ADV_INT_CONFIG_INIT 0x0000000000000000
1609 /* SH_PROC3_ADV_INT_CONFIG_TYPE */
1610 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1611 #define SH_PROC3_ADV_INT_CONFIG_TYPE_SHFT 0
1612 #define SH_PROC3_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007
1614 /* SH_PROC3_ADV_INT_CONFIG_AGT */
1615 /* Description: Agent, must be 0 for SHub */
1616 #define SH_PROC3_ADV_INT_CONFIG_AGT_SHFT 3
1617 #define SH_PROC3_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008
1619 /* SH_PROC3_ADV_INT_CONFIG_PID */
1620 /* Description: Processor ID, same setting as on targeted McKinley */
1621 #define SH_PROC3_ADV_INT_CONFIG_PID_SHFT 4
1622 #define SH_PROC3_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0
1624 /* SH_PROC3_ADV_INT_CONFIG_BASE */
1625 /* Description: Optional interrupt vector area, 2MB aligned */
1626 #define SH_PROC3_ADV_INT_CONFIG_BASE_SHFT 21
1627 #define SH_PROC3_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1629 /* SH_PROC3_ADV_INT_CONFIG_IDX */
1630 /* Description: Targeted McKinley interrupt vector */
1631 #define SH_PROC3_ADV_INT_CONFIG_IDX_SHFT 52
1632 #define SH_PROC3_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1634 /* ==================================================================== */
1635 /* Register "SH_PROC0_ERR_INT_ENABLE" */
1636 /* SHub Processor 0 Error Interrupt Enable Registers */
1637 /* ==================================================================== */
1639 #define SH_PROC0_ERR_INT_ENABLE 0x0000000110000e80
1640 #define SH_PROC0_ERR_INT_ENABLE_MASK 0x0000000000000001
1641 #define SH_PROC0_ERR_INT_ENABLE_INIT 0x0000000000000000
1643 /* SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE */
1644 /* Description: Enable Processor 0 Error Interrupt */
1645 #define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_SHFT 0
1646 #define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_MASK 0x0000000000000001
1648 /* ==================================================================== */
1649 /* Register "SH_PROC1_ERR_INT_ENABLE" */
1650 /* SHub Processor 1 Error Interrupt Enable Registers */
1651 /* ==================================================================== */
1653 #define SH_PROC1_ERR_INT_ENABLE 0x0000000110000f00
1654 #define SH_PROC1_ERR_INT_ENABLE_MASK 0x0000000000000001
1655 #define SH_PROC1_ERR_INT_ENABLE_INIT 0x0000000000000000
1657 /* SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE */
1658 /* Description: Enable Processor 1 Error Interrupt */
1659 #define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_SHFT 0
1660 #define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_MASK 0x0000000000000001
1662 /* ==================================================================== */
1663 /* Register "SH_PROC2_ERR_INT_ENABLE" */
1664 /* SHub Processor 2 Error Interrupt Enable Registers */
1665 /* ==================================================================== */
1667 #define SH_PROC2_ERR_INT_ENABLE 0x0000000110000f80
1668 #define SH_PROC2_ERR_INT_ENABLE_MASK 0x0000000000000001
1669 #define SH_PROC2_ERR_INT_ENABLE_INIT 0x0000000000000000
1671 /* SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE */
1672 /* Description: Enable Processor 2 Error Interrupt */
1673 #define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_SHFT 0
1674 #define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_MASK 0x0000000000000001
1676 /* ==================================================================== */
1677 /* Register "SH_PROC3_ERR_INT_ENABLE" */
1678 /* SHub Processor 3 Error Interrupt Enable Registers */
1679 /* ==================================================================== */
1681 #define SH_PROC3_ERR_INT_ENABLE 0x0000000110001000
1682 #define SH_PROC3_ERR_INT_ENABLE_MASK 0x0000000000000001
1683 #define SH_PROC3_ERR_INT_ENABLE_INIT 0x0000000000000000
1685 /* SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE */
1686 /* Description: Enable Processor 3 Error Interrupt */
1687 #define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_SHFT 0
1688 #define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_MASK 0x0000000000000001
1690 /* ==================================================================== */
1691 /* Register "SH_PROC0_ADV_INT_ENABLE" */
1692 /* SHub Processor 0 Advisory Interrupt Enable Registers */
1693 /* ==================================================================== */
1695 #define SH_PROC0_ADV_INT_ENABLE 0x0000000110001080
1696 #define SH_PROC0_ADV_INT_ENABLE_MASK 0x0000000000000001
1697 #define SH_PROC0_ADV_INT_ENABLE_INIT 0x0000000000000000
1699 /* SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE */
1700 /* Description: Enable Processor 0 Advisory Interrupt */
1701 #define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_SHFT 0
1702 #define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_MASK 0x0000000000000001
1704 /* ==================================================================== */
1705 /* Register "SH_PROC1_ADV_INT_ENABLE" */
1706 /* SHub Processor 1 Advisory Interrupt Enable Registers */
1707 /* ==================================================================== */
1709 #define SH_PROC1_ADV_INT_ENABLE 0x0000000110001100
1710 #define SH_PROC1_ADV_INT_ENABLE_MASK 0x0000000000000001
1711 #define SH_PROC1_ADV_INT_ENABLE_INIT 0x0000000000000000
1713 /* SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE */
1714 /* Description: Enable Processor 1 Advisory Interrupt */
1715 #define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_SHFT 0
1716 #define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_MASK 0x0000000000000001
1718 /* ==================================================================== */
1719 /* Register "SH_PROC2_ADV_INT_ENABLE" */
1720 /* SHub Processor 2 Advisory Interrupt Enable Registers */
1721 /* ==================================================================== */
1723 #define SH_PROC2_ADV_INT_ENABLE 0x0000000110001180
1724 #define SH_PROC2_ADV_INT_ENABLE_MASK 0x0000000000000001
1725 #define SH_PROC2_ADV_INT_ENABLE_INIT 0x0000000000000000
1727 /* SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE */
1728 /* Description: Enable Processor 2 Advisory Interrupt */
1729 #define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_SHFT 0
1730 #define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_MASK 0x0000000000000001
1732 /* ==================================================================== */
1733 /* Register "SH_PROC3_ADV_INT_ENABLE" */
1734 /* SHub Processor 3 Advisory Interrupt Enable Registers */
1735 /* ==================================================================== */
1737 #define SH_PROC3_ADV_INT_ENABLE 0x0000000110001200
1738 #define SH_PROC3_ADV_INT_ENABLE_MASK 0x0000000000000001
1739 #define SH_PROC3_ADV_INT_ENABLE_INIT 0x0000000000000000
1741 /* SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE */
1742 /* Description: Enable Processor 3 Advisory Interrupt */
1743 #define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_SHFT 0
1744 #define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_MASK 0x0000000000000001
1746 /* ==================================================================== */
1747 /* Register "SH_PROFILE_INT_CONFIG" */
1748 /* SHub Profile Interrupt Configuration Registers */
1749 /* ==================================================================== */
1751 #define SH_PROFILE_INT_CONFIG 0x0000000110001280
1752 #define SH_PROFILE_INT_CONFIG_MASK 0x0ff3ffffffefffff
1753 #define SH_PROFILE_INT_CONFIG_INIT 0x0000000000000000
1755 /* SH_PROFILE_INT_CONFIG_TYPE */
1756 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1757 #define SH_PROFILE_INT_CONFIG_TYPE_SHFT 0
1758 #define SH_PROFILE_INT_CONFIG_TYPE_MASK 0x0000000000000007
1760 /* SH_PROFILE_INT_CONFIG_AGT */
1761 /* Description: Agent, must be 0 for SHub */
1762 #define SH_PROFILE_INT_CONFIG_AGT_SHFT 3
1763 #define SH_PROFILE_INT_CONFIG_AGT_MASK 0x0000000000000008
1765 /* SH_PROFILE_INT_CONFIG_PID */
1766 /* Description: Processor ID, same setting as on targeted McKinley */
1767 #define SH_PROFILE_INT_CONFIG_PID_SHFT 4
1768 #define SH_PROFILE_INT_CONFIG_PID_MASK 0x00000000000ffff0
1770 /* SH_PROFILE_INT_CONFIG_BASE */
1771 /* Description: Optional interrupt vector area, 2MB aligned */
1772 #define SH_PROFILE_INT_CONFIG_BASE_SHFT 21
1773 #define SH_PROFILE_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1775 /* SH_PROFILE_INT_CONFIG_IDX */
1776 /* Description: Targeted McKinley interrupt vector */
1777 #define SH_PROFILE_INT_CONFIG_IDX_SHFT 52
1778 #define SH_PROFILE_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1780 /* ==================================================================== */
1781 /* Register "SH_PROFILE_INT_ENABLE" */
1782 /* SHub Profile Interrupt Enable Registers */
1783 /* ==================================================================== */
1785 #define SH_PROFILE_INT_ENABLE 0x0000000110001300
1786 #define SH_PROFILE_INT_ENABLE_MASK 0x0000000000000001
1787 #define SH_PROFILE_INT_ENABLE_INIT 0x0000000000000000
1789 /* SH_PROFILE_INT_ENABLE_PROFILE_ENABLE */
1790 /* Description: Enable Profile Interrupt */
1791 #define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_SHFT 0
1792 #define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_MASK 0x0000000000000001
1794 /* ==================================================================== */
1795 /* Register "SH_RTC0_INT_CONFIG" */
1796 /* SHub RTC 0 Interrupt Config Registers */
1797 /* ==================================================================== */
1799 #define SH_RTC0_INT_CONFIG 0x0000000110001380
1800 #define SH_RTC0_INT_CONFIG_MASK 0x0ff3ffffffefffff
1801 #define SH_RTC0_INT_CONFIG_INIT 0x0000000000000000
1803 /* SH_RTC0_INT_CONFIG_TYPE */
1804 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1805 #define SH_RTC0_INT_CONFIG_TYPE_SHFT 0
1806 #define SH_RTC0_INT_CONFIG_TYPE_MASK 0x0000000000000007
1808 /* SH_RTC0_INT_CONFIG_AGT */
1809 /* Description: Agent, must be 0 for SHub */
1810 #define SH_RTC0_INT_CONFIG_AGT_SHFT 3
1811 #define SH_RTC0_INT_CONFIG_AGT_MASK 0x0000000000000008
1813 /* SH_RTC0_INT_CONFIG_PID */
1814 /* Description: Processor ID, same setting as on targeted McKinley */
1815 #define SH_RTC0_INT_CONFIG_PID_SHFT 4
1816 #define SH_RTC0_INT_CONFIG_PID_MASK 0x00000000000ffff0
1818 /* SH_RTC0_INT_CONFIG_BASE */
1819 /* Description: Optional interrupt vector area, 2MB aligned */
1820 #define SH_RTC0_INT_CONFIG_BASE_SHFT 21
1821 #define SH_RTC0_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1823 /* SH_RTC0_INT_CONFIG_IDX */
1824 /* Description: Targeted McKinley interrupt vector */
1825 #define SH_RTC0_INT_CONFIG_IDX_SHFT 52
1826 #define SH_RTC0_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1828 /* ==================================================================== */
1829 /* Register "SH_RTC0_INT_ENABLE" */
1830 /* SHub RTC 0 Interrupt Enable Registers */
1831 /* ==================================================================== */
1833 #define SH_RTC0_INT_ENABLE 0x0000000110001400
1834 #define SH_RTC0_INT_ENABLE_MASK 0x0000000000000001
1835 #define SH_RTC0_INT_ENABLE_INIT 0x0000000000000000
1837 /* SH_RTC0_INT_ENABLE_RTC0_ENABLE */
1838 /* Description: Enable RTC 0 Interrupt */
1839 #define SH_RTC0_INT_ENABLE_RTC0_ENABLE_SHFT 0
1840 #define SH_RTC0_INT_ENABLE_RTC0_ENABLE_MASK 0x0000000000000001
1842 /* ==================================================================== */
1843 /* Register "SH_RTC1_INT_CONFIG" */
1844 /* SHub RTC 1 Interrupt Config Registers */
1845 /* ==================================================================== */
1847 #define SH_RTC1_INT_CONFIG 0x0000000110001480
1848 #define SH_RTC1_INT_CONFIG_MASK 0x0ff3ffffffefffff
1849 #define SH_RTC1_INT_CONFIG_INIT 0x0000000000000000
1851 /* SH_RTC1_INT_CONFIG_TYPE */
1852 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1853 #define SH_RTC1_INT_CONFIG_TYPE_SHFT 0
1854 #define SH_RTC1_INT_CONFIG_TYPE_MASK 0x0000000000000007
1856 /* SH_RTC1_INT_CONFIG_AGT */
1857 /* Description: Agent, must be 0 for SHub */
1858 #define SH_RTC1_INT_CONFIG_AGT_SHFT 3
1859 #define SH_RTC1_INT_CONFIG_AGT_MASK 0x0000000000000008
1861 /* SH_RTC1_INT_CONFIG_PID */
1862 /* Description: Processor ID, same setting as on targeted McKinley */
1863 #define SH_RTC1_INT_CONFIG_PID_SHFT 4
1864 #define SH_RTC1_INT_CONFIG_PID_MASK 0x00000000000ffff0
1866 /* SH_RTC1_INT_CONFIG_BASE */
1867 /* Description: Optional interrupt vector area, 2MB aligned */
1868 #define SH_RTC1_INT_CONFIG_BASE_SHFT 21
1869 #define SH_RTC1_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1871 /* SH_RTC1_INT_CONFIG_IDX */
1872 /* Description: Targeted McKinley interrupt vector */
1873 #define SH_RTC1_INT_CONFIG_IDX_SHFT 52
1874 #define SH_RTC1_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1876 /* ==================================================================== */
1877 /* Register "SH_RTC1_INT_ENABLE" */
1878 /* SHub RTC 1 Interrupt Enable Registers */
1879 /* ==================================================================== */
1881 #define SH_RTC1_INT_ENABLE 0x0000000110001500
1882 #define SH_RTC1_INT_ENABLE_MASK 0x0000000000000001
1883 #define SH_RTC1_INT_ENABLE_INIT 0x0000000000000000
1885 /* SH_RTC1_INT_ENABLE_RTC1_ENABLE */
1886 /* Description: Enable RTC 1 Interrupt */
1887 #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0
1888 #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK 0x0000000000000001
1890 /* ==================================================================== */
1891 /* Register "SH_RTC2_INT_CONFIG" */
1892 /* SHub RTC 2 Interrupt Config Registers */
1893 /* ==================================================================== */
1895 #define SH_RTC2_INT_CONFIG 0x0000000110001580
1896 #define SH_RTC2_INT_CONFIG_MASK 0x0ff3ffffffefffff
1897 #define SH_RTC2_INT_CONFIG_INIT 0x0000000000000000
1899 /* SH_RTC2_INT_CONFIG_TYPE */
1900 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1901 #define SH_RTC2_INT_CONFIG_TYPE_SHFT 0
1902 #define SH_RTC2_INT_CONFIG_TYPE_MASK 0x0000000000000007
1904 /* SH_RTC2_INT_CONFIG_AGT */
1905 /* Description: Agent, must be 0 for SHub */
1906 #define SH_RTC2_INT_CONFIG_AGT_SHFT 3
1907 #define SH_RTC2_INT_CONFIG_AGT_MASK 0x0000000000000008
1909 /* SH_RTC2_INT_CONFIG_PID */
1910 /* Description: Processor ID, same setting as on targeted McKinley */
1911 #define SH_RTC2_INT_CONFIG_PID_SHFT 4
1912 #define SH_RTC2_INT_CONFIG_PID_MASK 0x00000000000ffff0
1914 /* SH_RTC2_INT_CONFIG_BASE */
1915 /* Description: Optional interrupt vector area, 2MB aligned */
1916 #define SH_RTC2_INT_CONFIG_BASE_SHFT 21
1917 #define SH_RTC2_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1919 /* SH_RTC2_INT_CONFIG_IDX */
1920 /* Description: Targeted McKinley interrupt vector */
1921 #define SH_RTC2_INT_CONFIG_IDX_SHFT 52
1922 #define SH_RTC2_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1924 /* ==================================================================== */
1925 /* Register "SH_RTC2_INT_ENABLE" */
1926 /* SHub RTC 2 Interrupt Enable Registers */
1927 /* ==================================================================== */
1929 #define SH_RTC2_INT_ENABLE 0x0000000110001600
1930 #define SH_RTC2_INT_ENABLE_MASK 0x0000000000000001
1931 #define SH_RTC2_INT_ENABLE_INIT 0x0000000000000000
1933 /* SH_RTC2_INT_ENABLE_RTC2_ENABLE */
1934 /* Description: Enable RTC 2 Interrupt */
1935 #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0
1936 #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK 0x0000000000000001
1938 /* ==================================================================== */
1939 /* Register "SH_RTC3_INT_CONFIG" */
1940 /* SHub RTC 3 Interrupt Config Registers */
1941 /* ==================================================================== */
1943 #define SH_RTC3_INT_CONFIG 0x0000000110001680
1944 #define SH_RTC3_INT_CONFIG_MASK 0x0ff3ffffffefffff
1945 #define SH_RTC3_INT_CONFIG_INIT 0x0000000000000000
1947 /* SH_RTC3_INT_CONFIG_TYPE */
1948 /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
1949 #define SH_RTC3_INT_CONFIG_TYPE_SHFT 0
1950 #define SH_RTC3_INT_CONFIG_TYPE_MASK 0x0000000000000007
1952 /* SH_RTC3_INT_CONFIG_AGT */
1953 /* Description: Agent, must be 0 for SHub */
1954 #define SH_RTC3_INT_CONFIG_AGT_SHFT 3
1955 #define SH_RTC3_INT_CONFIG_AGT_MASK 0x0000000000000008
1957 /* SH_RTC3_INT_CONFIG_PID */
1958 /* Description: Processor ID, same setting as on targeted McKinley */
1959 #define SH_RTC3_INT_CONFIG_PID_SHFT 4
1960 #define SH_RTC3_INT_CONFIG_PID_MASK 0x00000000000ffff0
1962 /* SH_RTC3_INT_CONFIG_BASE */
1963 /* Description: Optional interrupt vector area, 2MB aligned */
1964 #define SH_RTC3_INT_CONFIG_BASE_SHFT 21
1965 #define SH_RTC3_INT_CONFIG_BASE_MASK 0x0003ffffffe00000
1967 /* SH_RTC3_INT_CONFIG_IDX */
1968 /* Description: Targeted McKinley interrupt vector */
1969 #define SH_RTC3_INT_CONFIG_IDX_SHFT 52
1970 #define SH_RTC3_INT_CONFIG_IDX_MASK 0x0ff0000000000000
1972 /* ==================================================================== */
1973 /* Register "SH_RTC3_INT_ENABLE" */
1974 /* SHub RTC 3 Interrupt Enable Registers */
1975 /* ==================================================================== */
1977 #define SH_RTC3_INT_ENABLE 0x0000000110001700
1978 #define SH_RTC3_INT_ENABLE_MASK 0x0000000000000001
1979 #define SH_RTC3_INT_ENABLE_INIT 0x0000000000000000
1981 /* SH_RTC3_INT_ENABLE_RTC3_ENABLE */
1982 /* Description: Enable RTC 3 Interrupt */
1983 #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0
1984 #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK 0x0000000000000001
1986 /* ==================================================================== */
1987 /* Register "SH_EVENT_OCCURRED" */
1988 /* SHub Interrupt Event Occurred */
1989 /* ==================================================================== */
1991 #define SH_EVENT_OCCURRED 0x0000000110010000
1992 #define SH_EVENT_OCCURRED_MASK 0x000000007fffffff
1993 #define SH_EVENT_OCCURRED_INIT 0x0000000000000000
1995 /* SH_EVENT_OCCURRED_PI_HW_INT */
1996 /* Description: Pending PI Hardware interrupt */
1997 #define SH_EVENT_OCCURRED_PI_HW_INT_SHFT 0
1998 #define SH_EVENT_OCCURRED_PI_HW_INT_MASK 0x0000000000000001
2000 /* SH_EVENT_OCCURRED_MD_HW_INT */
2001 /* Description: Pending MD Hardware interrupt */
2002 #define SH_EVENT_OCCURRED_MD_HW_INT_SHFT 1
2003 #define SH_EVENT_OCCURRED_MD_HW_INT_MASK 0x0000000000000002
2005 /* SH_EVENT_OCCURRED_XN_HW_INT */
2006 /* Description: Pending XN Hardware interrupt */
2007 #define SH_EVENT_OCCURRED_XN_HW_INT_SHFT 2
2008 #define SH_EVENT_OCCURRED_XN_HW_INT_MASK 0x0000000000000004
2010 /* SH_EVENT_OCCURRED_LB_HW_INT */
2011 /* Description: Pending LB Hardware interrupt */
2012 #define SH_EVENT_OCCURRED_LB_HW_INT_SHFT 3
2013 #define SH_EVENT_OCCURRED_LB_HW_INT_MASK 0x0000000000000008
2015 /* SH_EVENT_OCCURRED_II_HW_INT */
2016 /* Description: Pending II wrapper Hardware interrupt */
2017 #define SH_EVENT_OCCURRED_II_HW_INT_SHFT 4
2018 #define SH_EVENT_OCCURRED_II_HW_INT_MASK 0x0000000000000010
2020 /* SH_EVENT_OCCURRED_PI_CE_INT */
2021 /* Description: Pending PI Correctable Error Interrupt */
2022 #define SH_EVENT_OCCURRED_PI_CE_INT_SHFT 5
2023 #define SH_EVENT_OCCURRED_PI_CE_INT_MASK 0x0000000000000020
2025 /* SH_EVENT_OCCURRED_MD_CE_INT */
2026 /* Description: Pending MD Correctable Error Interrupt */
2027 #define SH_EVENT_OCCURRED_MD_CE_INT_SHFT 6
2028 #define SH_EVENT_OCCURRED_MD_CE_INT_MASK 0x0000000000000040
2030 /* SH_EVENT_OCCURRED_XN_CE_INT */
2031 /* Description: Pending XN Correctable Error Interrupt */
2032 #define SH_EVENT_OCCURRED_XN_CE_INT_SHFT 7
2033 #define SH_EVENT_OCCURRED_XN_CE_INT_MASK 0x0000000000000080
2035 /* SH_EVENT_OCCURRED_PI_UCE_INT */
2036 /* Description: Pending PI Correctable Error Interrupt */
2037 #define SH_EVENT_OCCURRED_PI_UCE_INT_SHFT 8
2038 #define SH_EVENT_OCCURRED_PI_UCE_INT_MASK 0x0000000000000100
2040 /* SH_EVENT_OCCURRED_MD_UCE_INT */
2041 /* Description: Pending MD Correctable Error Interrupt */
2042 #define SH_EVENT_OCCURRED_MD_UCE_INT_SHFT 9
2043 #define SH_EVENT_OCCURRED_MD_UCE_INT_MASK 0x0000000000000200
2045 /* SH_EVENT_OCCURRED_XN_UCE_INT */
2046 /* Description: Pending XN Correctable Error Interrupt */
2047 #define SH_EVENT_OCCURRED_XN_UCE_INT_SHFT 10
2048 #define SH_EVENT_OCCURRED_XN_UCE_INT_MASK 0x0000000000000400
2050 /* SH_EVENT_OCCURRED_PROC0_ADV_INT */
2051 /* Description: Pending Processor 0 Advisory Interrupt */
2052 #define SH_EVENT_OCCURRED_PROC0_ADV_INT_SHFT 11
2053 #define SH_EVENT_OCCURRED_PROC0_ADV_INT_MASK 0x0000000000000800
2055 /* SH_EVENT_OCCURRED_PROC1_ADV_INT */
2056 /* Description: Pending Processor 1 Advisory Interrupt */
2057 #define SH_EVENT_OCCURRED_PROC1_ADV_INT_SHFT 12
2058 #define SH_EVENT_OCCURRED_PROC1_ADV_INT_MASK 0x0000000000001000
2060 /* SH_EVENT_OCCURRED_PROC2_ADV_INT */
2061 /* Description: Pending Processor 2 Advisory Interrupt */
2062 #define SH_EVENT_OCCURRED_PROC2_ADV_INT_SHFT 13
2063 #define SH_EVENT_OCCURRED_PROC2_ADV_INT_MASK 0x0000000000002000
2065 /* SH_EVENT_OCCURRED_PROC3_ADV_INT */
2066 /* Description: Pending Processor 3 Advisory Interrupt */
2067 #define SH_EVENT_OCCURRED_PROC3_ADV_INT_SHFT 14
2068 #define SH_EVENT_OCCURRED_PROC3_ADV_INT_MASK 0x0000000000004000
2070 /* SH_EVENT_OCCURRED_PROC0_ERR_INT */
2071 /* Description: Pending Processor 0 Error Interrupt */
2072 #define SH_EVENT_OCCURRED_PROC0_ERR_INT_SHFT 15
2073 #define SH_EVENT_OCCURRED_PROC0_ERR_INT_MASK 0x0000000000008000
2075 /* SH_EVENT_OCCURRED_PROC1_ERR_INT */
2076 /* Description: Pending Processor 1 Error Interrupt */
2077 #define SH_EVENT_OCCURRED_PROC1_ERR_INT_SHFT 16
2078 #define SH_EVENT_OCCURRED_PROC1_ERR_INT_MASK 0x0000000000010000
2080 /* SH_EVENT_OCCURRED_PROC2_ERR_INT */
2081 /* Description: Pending Processor 2 Error Interrupt */
2082 #define SH_EVENT_OCCURRED_PROC2_ERR_INT_SHFT 17
2083 #define SH_EVENT_OCCURRED_PROC2_ERR_INT_MASK 0x0000000000020000
2085 /* SH_EVENT_OCCURRED_PROC3_ERR_INT */
2086 /* Description: Pending Processor 3 Error Interrupt */
2087 #define SH_EVENT_OCCURRED_PROC3_ERR_INT_SHFT 18
2088 #define SH_EVENT_OCCURRED_PROC3_ERR_INT_MASK 0x0000000000040000
2090 /* SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT */
2091 /* Description: Pending System Shutdown Interrupt */
2092 #define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_SHFT 19
2093 #define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000
2095 /* SH_EVENT_OCCURRED_UART_INT */
2096 /* Description: Pending Junk Bus UART Interrupt */
2097 #define SH_EVENT_OCCURRED_UART_INT_SHFT 20
2098 #define SH_EVENT_OCCURRED_UART_INT_MASK 0x0000000000100000
2100 /* SH_EVENT_OCCURRED_L1_NMI_INT */
2101 /* Description: Pending L1 Controller NMI Interrupt */
2102 #define SH_EVENT_OCCURRED_L1_NMI_INT_SHFT 21
2103 #define SH_EVENT_OCCURRED_L1_NMI_INT_MASK 0x0000000000200000
2105 /* SH_EVENT_OCCURRED_STOP_CLOCK */
2106 /* Description: Pending Stop Clock Interrupt */
2107 #define SH_EVENT_OCCURRED_STOP_CLOCK_SHFT 22
2108 #define SH_EVENT_OCCURRED_STOP_CLOCK_MASK 0x0000000000400000
2110 /* SH_EVENT_OCCURRED_RTC0_INT */
2111 /* Description: Pending RTC 0 Interrupt */
2112 #define SH_EVENT_OCCURRED_RTC0_INT_SHFT 23
2113 #define SH_EVENT_OCCURRED_RTC0_INT_MASK 0x0000000000800000
2115 /* SH_EVENT_OCCURRED_RTC1_INT */
2116 /* Description: Pending RTC 1 Interrupt */
2117 #define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24
2118 #define SH_EVENT_OCCURRED_RTC1_INT_MASK 0x0000000001000000
2120 /* SH_EVENT_OCCURRED_RTC2_INT */
2121 /* Description: Pending RTC 2 Interrupt */
2122 #define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25
2123 #define SH_EVENT_OCCURRED_RTC2_INT_MASK 0x0000000002000000
2125 /* SH_EVENT_OCCURRED_RTC3_INT */
2126 /* Description: Pending RTC 3 Interrupt */
2127 #define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
2128 #define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000
2130 /* SH_EVENT_OCCURRED_PROFILE_INT */
2131 /* Description: Pending Profile Interrupt */
2132 #define SH_EVENT_OCCURRED_PROFILE_INT_SHFT 27
2133 #define SH_EVENT_OCCURRED_PROFILE_INT_MASK 0x0000000008000000
2135 /* SH_EVENT_OCCURRED_IPI_INT */
2136 /* Description: Pending IPI Interrupt */
2137 #define SH_EVENT_OCCURRED_IPI_INT_SHFT 28
2138 #define SH_EVENT_OCCURRED_IPI_INT_MASK 0x0000000010000000
2140 /* SH_EVENT_OCCURRED_II_INT0 */
2141 /* Description: Pending II 0 Interrupt */
2142 #define SH_EVENT_OCCURRED_II_INT0_SHFT 29
2143 #define SH_EVENT_OCCURRED_II_INT0_MASK 0x0000000020000000
2145 /* SH_EVENT_OCCURRED_II_INT1 */
2146 /* Description: Pending II 1 Interrupt */
2147 #define SH_EVENT_OCCURRED_II_INT1_SHFT 30
2148 #define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000
2150 /* ==================================================================== */
2151 /* Register "SH_EVENT_OCCURRED_ALIAS" */
2152 /* SHub Interrupt Event Occurred Alias */
2153 /* ==================================================================== */
2155 #define SH_EVENT_OCCURRED_ALIAS 0x0000000110010008
2157 /* ==================================================================== */
2158 /* Register "SH_EVENT_OVERFLOW" */
2159 /* SHub Interrupt Event Occurred Overflow */
2160 /* ==================================================================== */
2162 #define SH_EVENT_OVERFLOW 0x0000000110010080
2163 #define SH_EVENT_OVERFLOW_MASK 0x000000000fffffff
2164 #define SH_EVENT_OVERFLOW_INIT 0x0000000000000000
2166 /* SH_EVENT_OVERFLOW_PI_HW_INT */
2167 /* Description: Pending PI Hardware interrupt */
2168 #define SH_EVENT_OVERFLOW_PI_HW_INT_SHFT 0
2169 #define SH_EVENT_OVERFLOW_PI_HW_INT_MASK 0x0000000000000001
2171 /* SH_EVENT_OVERFLOW_MD_HW_INT */
2172 /* Description: Pending MD Hardware interrupt */
2173 #define SH_EVENT_OVERFLOW_MD_HW_INT_SHFT 1
2174 #define SH_EVENT_OVERFLOW_MD_HW_INT_MASK 0x0000000000000002
2176 /* SH_EVENT_OVERFLOW_XN_HW_INT */
2177 /* Description: Pending XN Hardware interrupt */
2178 #define SH_EVENT_OVERFLOW_XN_HW_INT_SHFT 2
2179 #define SH_EVENT_OVERFLOW_XN_HW_INT_MASK 0x0000000000000004
2181 /* SH_EVENT_OVERFLOW_LB_HW_INT */
2182 /* Description: Pending LB Hardware interrupt */
2183 #define SH_EVENT_OVERFLOW_LB_HW_INT_SHFT 3
2184 #define SH_EVENT_OVERFLOW_LB_HW_INT_MASK 0x0000000000000008
2186 /* SH_EVENT_OVERFLOW_II_HW_INT */
2187 /* Description: Pending II wrapper Hardware interrupt */
2188 #define SH_EVENT_OVERFLOW_II_HW_INT_SHFT 4
2189 #define SH_EVENT_OVERFLOW_II_HW_INT_MASK 0x0000000000000010
2191 /* SH_EVENT_OVERFLOW_PI_CE_INT */
2192 /* Description: Pending PI Correctable Error Interrupt */
2193 #define SH_EVENT_OVERFLOW_PI_CE_INT_SHFT 5
2194 #define SH_EVENT_OVERFLOW_PI_CE_INT_MASK 0x0000000000000020
2196 /* SH_EVENT_OVERFLOW_MD_CE_INT */
2197 /* Description: Pending MD Correctable Error Interrupt */
2198 #define SH_EVENT_OVERFLOW_MD_CE_INT_SHFT 6
2199 #define SH_EVENT_OVERFLOW_MD_CE_INT_MASK 0x0000000000000040
2201 /* SH_EVENT_OVERFLOW_XN_CE_INT */
2202 /* Description: Pending XN Correctable Error Interrupt */
2203 #define SH_EVENT_OVERFLOW_XN_CE_INT_SHFT 7
2204 #define SH_EVENT_OVERFLOW_XN_CE_INT_MASK 0x0000000000000080
2206 /* SH_EVENT_OVERFLOW_PI_UCE_INT */
2207 /* Description: Pending PI Correctable Error Interrupt */
2208 #define SH_EVENT_OVERFLOW_PI_UCE_INT_SHFT 8
2209 #define SH_EVENT_OVERFLOW_PI_UCE_INT_MASK 0x0000000000000100
2211 /* SH_EVENT_OVERFLOW_MD_UCE_INT */
2212 /* Description: Pending MD Correctable Error Interrupt */
2213 #define SH_EVENT_OVERFLOW_MD_UCE_INT_SHFT 9
2214 #define SH_EVENT_OVERFLOW_MD_UCE_INT_MASK 0x0000000000000200
2216 /* SH_EVENT_OVERFLOW_XN_UCE_INT */
2217 /* Description: Pending XN Correctable Error Interrupt */
2218 #define SH_EVENT_OVERFLOW_XN_UCE_INT_SHFT 10
2219 #define SH_EVENT_OVERFLOW_XN_UCE_INT_MASK 0x0000000000000400
2221 /* SH_EVENT_OVERFLOW_PROC0_ADV_INT */
2222 /* Description: Pending Processor 0 Advisory Interrupt */
2223 #define SH_EVENT_OVERFLOW_PROC0_ADV_INT_SHFT 11
2224 #define SH_EVENT_OVERFLOW_PROC0_ADV_INT_MASK 0x0000000000000800
2226 /* SH_EVENT_OVERFLOW_PROC1_ADV_INT */
2227 /* Description: Pending Processor 1 Advisory Interrupt */
2228 #define SH_EVENT_OVERFLOW_PROC1_ADV_INT_SHFT 12
2229 #define SH_EVENT_OVERFLOW_PROC1_ADV_INT_MASK 0x0000000000001000
2231 /* SH_EVENT_OVERFLOW_PROC2_ADV_INT */
2232 /* Description: Pending Processor 2 Advisory Interrupt */
2233 #define SH_EVENT_OVERFLOW_PROC2_ADV_INT_SHFT 13
2234 #define SH_EVENT_OVERFLOW_PROC2_ADV_INT_MASK 0x0000000000002000
2236 /* SH_EVENT_OVERFLOW_PROC3_ADV_INT */
2237 /* Description: Pending Processor 3 Advisory Interrupt */
2238 #define SH_EVENT_OVERFLOW_PROC3_ADV_INT_SHFT 14
2239 #define SH_EVENT_OVERFLOW_PROC3_ADV_INT_MASK 0x0000000000004000
2241 /* SH_EVENT_OVERFLOW_PROC0_ERR_INT */
2242 /* Description: Pending Processor 0 Error Interrupt */
2243 #define SH_EVENT_OVERFLOW_PROC0_ERR_INT_SHFT 15
2244 #define SH_EVENT_OVERFLOW_PROC0_ERR_INT_MASK 0x0000000000008000
2246 /* SH_EVENT_OVERFLOW_PROC1_ERR_INT */
2247 /* Description: Pending Processor 1 Error Interrupt */
2248 #define SH_EVENT_OVERFLOW_PROC1_ERR_INT_SHFT 16
2249 #define SH_EVENT_OVERFLOW_PROC1_ERR_INT_MASK 0x0000000000010000
2251 /* SH_EVENT_OVERFLOW_PROC2_ERR_INT */
2252 /* Description: Pending Processor 2 Error Interrupt */
2253 #define SH_EVENT_OVERFLOW_PROC2_ERR_INT_SHFT 17
2254 #define SH_EVENT_OVERFLOW_PROC2_ERR_INT_MASK 0x0000000000020000
2256 /* SH_EVENT_OVERFLOW_PROC3_ERR_INT */
2257 /* Description: Pending Processor 3 Error Interrupt */
2258 #define SH_EVENT_OVERFLOW_PROC3_ERR_INT_SHFT 18
2259 #define SH_EVENT_OVERFLOW_PROC3_ERR_INT_MASK 0x0000000000040000
2261 /* SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT */
2262 /* Description: Pending System Shutdown Interrupt */
2263 #define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_SHFT 19
2264 #define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000
2266 /* SH_EVENT_OVERFLOW_UART_INT */
2267 /* Description: Pending Junk Bus UART Interrupt */
2268 #define SH_EVENT_OVERFLOW_UART_INT_SHFT 20
2269 #define SH_EVENT_OVERFLOW_UART_INT_MASK 0x0000000000100000
2271 /* SH_EVENT_OVERFLOW_L1_NMI_INT */
2272 /* Description: Pending L1 Controller NMI Interrupt */
2273 #define SH_EVENT_OVERFLOW_L1_NMI_INT_SHFT 21
2274 #define SH_EVENT_OVERFLOW_L1_NMI_INT_MASK 0x0000000000200000
2276 /* SH_EVENT_OVERFLOW_STOP_CLOCK */
2277 /* Description: Pending Stop Clock Interrupt */
2278 #define SH_EVENT_OVERFLOW_STOP_CLOCK_SHFT 22
2279 #define SH_EVENT_OVERFLOW_STOP_CLOCK_MASK 0x0000000000400000
2281 /* SH_EVENT_OVERFLOW_RTC0_INT */
2282 /* Description: Pending RTC 0 Interrupt */
2283 #define SH_EVENT_OVERFLOW_RTC0_INT_SHFT 23
2284 #define SH_EVENT_OVERFLOW_RTC0_INT_MASK 0x0000000000800000
2286 /* SH_EVENT_OVERFLOW_RTC1_INT */
2287 /* Description: Pending RTC 1 Interrupt */
2288 #define SH_EVENT_OVERFLOW_RTC1_INT_SHFT 24
2289 #define SH_EVENT_OVERFLOW_RTC1_INT_MASK 0x0000000001000000
2291 /* SH_EVENT_OVERFLOW_RTC2_INT */
2292 /* Description: Pending RTC 2 Interrupt */
2293 #define SH_EVENT_OVERFLOW_RTC2_INT_SHFT 25
2294 #define SH_EVENT_OVERFLOW_RTC2_INT_MASK 0x0000000002000000
2296 /* SH_EVENT_OVERFLOW_RTC3_INT */
2297 /* Description: Pending RTC 3 Interrupt */
2298 #define SH_EVENT_OVERFLOW_RTC3_INT_SHFT 26
2299 #define SH_EVENT_OVERFLOW_RTC3_INT_MASK 0x0000000004000000
2301 /* SH_EVENT_OVERFLOW_PROFILE_INT */
2302 /* Description: Pending Profile Interrupt */
2303 #define SH_EVENT_OVERFLOW_PROFILE_INT_SHFT 27
2304 #define SH_EVENT_OVERFLOW_PROFILE_INT_MASK 0x0000000008000000
2306 /* ==================================================================== */
2307 /* Register "SH_EVENT_OVERFLOW_ALIAS" */
2308 /* SHub Interrupt Event Occurred Overflow Alias */
2309 /* ==================================================================== */
2311 #define SH_EVENT_OVERFLOW_ALIAS 0x0000000110010088
2313 /* ==================================================================== */
2314 /* Register "SH_JUNK_BUS_TIME" */
2315 /* Junk Bus Timing */
2316 /* ==================================================================== */
2318 #define SH_JUNK_BUS_TIME 0x0000000110020000
2319 #define SH_JUNK_BUS_TIME_MASK 0x00000000ffffffff
2320 #define SH_JUNK_BUS_TIME_INIT 0x0000000040404040
2322 /* SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD */
2323 /* Description: Fprom_Setup_Hold */
2324 #define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_SHFT 0
2325 #define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_MASK 0x00000000000000ff
2327 /* SH_JUNK_BUS_TIME_FPROM_ENABLE */
2328 /* Description: Fprom_Enable */
2329 #define SH_JUNK_BUS_TIME_FPROM_ENABLE_SHFT 8
2330 #define SH_JUNK_BUS_TIME_FPROM_ENABLE_MASK 0x000000000000ff00
2332 /* SH_JUNK_BUS_TIME_UART_SETUP_HOLD */
2333 /* Description: Uart_Setup_Hold */
2334 #define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_SHFT 16
2335 #define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_MASK 0x0000000000ff0000
2337 /* SH_JUNK_BUS_TIME_UART_ENABLE */
2338 /* Description: Uart_Enable */
2339 #define SH_JUNK_BUS_TIME_UART_ENABLE_SHFT 24
2340 #define SH_JUNK_BUS_TIME_UART_ENABLE_MASK 0x00000000ff000000
2342 /* ==================================================================== */
2343 /* Register "SH_JUNK_LATCH_TIME" */
2344 /* Junk Bus Latch Timing */
2345 /* ==================================================================== */
2347 #define SH_JUNK_LATCH_TIME 0x0000000110020080
2348 #define SH_JUNK_LATCH_TIME_MASK 0x0000000000000007
2349 #define SH_JUNK_LATCH_TIME_INIT 0x0000000000000002
2351 /* SH_JUNK_LATCH_TIME_SETUP_HOLD */
2352 /* Description: Setup and Hold Time */
2353 #define SH_JUNK_LATCH_TIME_SETUP_HOLD_SHFT 0
2354 #define SH_JUNK_LATCH_TIME_SETUP_HOLD_MASK 0x0000000000000007
2356 /* ==================================================================== */
2357 /* Register "SH_JUNK_NACK_RESET" */
2358 /* Junk Bus Nack Counter Reset */
2359 /* ==================================================================== */
2361 #define SH_JUNK_NACK_RESET 0x0000000110020100
2362 #define SH_JUNK_NACK_RESET_MASK 0x0000000000000001
2363 #define SH_JUNK_NACK_RESET_INIT 0x0000000000000000
2365 /* SH_JUNK_NACK_RESET_PULSE */
2366 /* Description: Junk bus nack counter reset */
2367 #define SH_JUNK_NACK_RESET_PULSE_SHFT 0
2368 #define SH_JUNK_NACK_RESET_PULSE_MASK 0x0000000000000001
2370 /* ==================================================================== */
2371 /* Register "SH_JUNK_BUS_LED0" */
2373 /* ==================================================================== */
2375 #define SH_JUNK_BUS_LED0 0x0000000110030000
2376 #define SH_JUNK_BUS_LED0_MASK 0x00000000000000ff
2377 #define SH_JUNK_BUS_LED0_INIT 0x0000000000000000
2379 /* SH_JUNK_BUS_LED0_LED0_DATA */
2380 /* Description: LED0_data */
2381 #define SH_JUNK_BUS_LED0_LED0_DATA_SHFT 0
2382 #define SH_JUNK_BUS_LED0_LED0_DATA_MASK 0x00000000000000ff
2384 /* ==================================================================== */
2385 /* Register "SH_JUNK_BUS_LED1" */
2387 /* ==================================================================== */
2389 #define SH_JUNK_BUS_LED1 0x0000000110030080
2390 #define SH_JUNK_BUS_LED1_MASK 0x00000000000000ff
2391 #define SH_JUNK_BUS_LED1_INIT 0x0000000000000000
2393 /* SH_JUNK_BUS_LED1_LED1_DATA */
2394 /* Description: LED1_data */
2395 #define SH_JUNK_BUS_LED1_LED1_DATA_SHFT 0
2396 #define SH_JUNK_BUS_LED1_LED1_DATA_MASK 0x00000000000000ff
2398 /* ==================================================================== */
2399 /* Register "SH_JUNK_BUS_LED2" */
2401 /* ==================================================================== */
2403 #define SH_JUNK_BUS_LED2 0x0000000110030100
2404 #define SH_JUNK_BUS_LED2_MASK 0x00000000000000ff
2405 #define SH_JUNK_BUS_LED2_INIT 0x0000000000000000
2407 /* SH_JUNK_BUS_LED2_LED2_DATA */
2408 /* Description: LED2_data */
2409 #define SH_JUNK_BUS_LED2_LED2_DATA_SHFT 0
2410 #define SH_JUNK_BUS_LED2_LED2_DATA_MASK 0x00000000000000ff
2412 /* ==================================================================== */
2413 /* Register "SH_JUNK_BUS_LED3" */
2415 /* ==================================================================== */
2417 #define SH_JUNK_BUS_LED3 0x0000000110030180
2418 #define SH_JUNK_BUS_LED3_MASK 0x00000000000000ff
2419 #define SH_JUNK_BUS_LED3_INIT 0x0000000000000000
2421 /* SH_JUNK_BUS_LED3_LED3_DATA */
2422 /* Description: LED3_data */
2423 #define SH_JUNK_BUS_LED3_LED3_DATA_SHFT 0
2424 #define SH_JUNK_BUS_LED3_LED3_DATA_MASK 0x00000000000000ff
2426 /* ==================================================================== */
2427 /* Register "SH_JUNK_ERROR_STATUS" */
2428 /* Junk Bus Error Status */
2429 /* ==================================================================== */
2431 #define SH_JUNK_ERROR_STATUS 0x0000000110030200
2432 #define SH_JUNK_ERROR_STATUS_MASK 0x1fff7fffffffffff
2433 #define SH_JUNK_ERROR_STATUS_INIT 0x0000000000000000
2435 /* SH_JUNK_ERROR_STATUS_ADDRESS */
2436 /* Description: Failing junk bus address */
2437 #define SH_JUNK_ERROR_STATUS_ADDRESS_SHFT 0
2438 #define SH_JUNK_ERROR_STATUS_ADDRESS_MASK 0x00007fffffffffff
2440 /* SH_JUNK_ERROR_STATUS_CMD */
2441 /* Description: Junk bus command */
2442 #define SH_JUNK_ERROR_STATUS_CMD_SHFT 48
2443 #define SH_JUNK_ERROR_STATUS_CMD_MASK 0x00ff000000000000
2445 /* SH_JUNK_ERROR_STATUS_MODE */
2446 /* Description: Mode */
2447 #define SH_JUNK_ERROR_STATUS_MODE_SHFT 56
2448 #define SH_JUNK_ERROR_STATUS_MODE_MASK 0x0100000000000000
2450 /* SH_JUNK_ERROR_STATUS_STATUS */
2451 /* Description: Status */
2452 #define SH_JUNK_ERROR_STATUS_STATUS_SHFT 57
2453 #define SH_JUNK_ERROR_STATUS_STATUS_MASK 0x1e00000000000000
2455 /* ==================================================================== */
2456 /* Register "SH_NI0_LLP_STAT" */
2457 /* This register describes the LLP status. */
2458 /* ==================================================================== */
2460 #define SH_NI0_LLP_STAT 0x0000000150000000
2461 #define SH_NI0_LLP_STAT_MASK 0x000000000000000f
2462 #define SH_NI0_LLP_STAT_INIT 0x0000000000000000
2464 /* SH_NI0_LLP_STAT_LINK_RESET_STATE */
2465 /* Description: Status of LLP link. */
2466 #define SH_NI0_LLP_STAT_LINK_RESET_STATE_SHFT 0
2467 #define SH_NI0_LLP_STAT_LINK_RESET_STATE_MASK 0x000000000000000f
2469 /* ==================================================================== */
2470 /* Register "SH_NI0_LLP_RESET" */
2471 /* Writing issues a reset to the network interface */
2472 /* ==================================================================== */
2474 #define SH_NI0_LLP_RESET 0x0000000150000008
2475 #define SH_NI0_LLP_RESET_MASK 0x0000000000000003
2476 #define SH_NI0_LLP_RESET_INIT 0x0000000000000000
2478 /* SH_NI0_LLP_RESET_LINK */
2479 /* Description: Send Link Reset. Generates a pulse. */
2480 #define SH_NI0_LLP_RESET_LINK_SHFT 0
2481 #define SH_NI0_LLP_RESET_LINK_MASK 0x0000000000000001
2483 /* SH_NI0_LLP_RESET_WARM */
2484 /* Description: Send Warm Reset. Generates a pulse. */
2485 #define SH_NI0_LLP_RESET_WARM_SHFT 1
2486 #define SH_NI0_LLP_RESET_WARM_MASK 0x0000000000000002
2488 /* ==================================================================== */
2489 /* Register "SH_NI0_LLP_RESET_EN" */
2490 /* Controls LLP warm reset propagation */
2491 /* ==================================================================== */
2493 #define SH_NI0_LLP_RESET_EN 0x0000000150000010
2494 #define SH_NI0_LLP_RESET_EN_MASK 0x0000000000000001
2495 #define SH_NI0_LLP_RESET_EN_INIT 0x0000000000000001
2497 /* SH_NI0_LLP_RESET_EN_OK */
2498 /* Description: Allow LLP warm reset to reset SHUB */
2499 #define SH_NI0_LLP_RESET_EN_OK_SHFT 0
2500 #define SH_NI0_LLP_RESET_EN_OK_MASK 0x0000000000000001
2502 /* ==================================================================== */
2503 /* Register "SH_NI0_LLP_CHAN_MODE" */
2504 /* Sets the signaling mode of LLP and channel */
2505 /* ==================================================================== */
2507 #define SH_NI0_LLP_CHAN_MODE 0x0000000150000018
2508 #define SH_NI0_LLP_CHAN_MODE_MASK 0x000000000000001f
2509 #define SH_NI0_LLP_CHAN_MODE_INIT 0x0000000000000000
2511 /* SH_NI0_LLP_CHAN_MODE_BITMODE32 */
2512 /* Description: Enables 32-bit (plus sideband) channel phits */
2513 #define SH_NI0_LLP_CHAN_MODE_BITMODE32_SHFT 0
2514 #define SH_NI0_LLP_CHAN_MODE_BITMODE32_MASK 0x0000000000000001
2516 /* SH_NI0_LLP_CHAN_MODE_AC_ENCODE */
2517 /* Description: Enables nearly dc-free encoding for AC-coupling */
2518 #define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_SHFT 1
2519 #define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_MASK 0x0000000000000002
2521 /* SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING */
2522 /* Description: Enables automatic tuning of channel skew. */
2523 #define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_SHFT 2
2524 #define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_MASK 0x0000000000000004
2526 /* SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD */
2527 /* Description: Enables remote fine tune updates */
2528 #define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3
2529 #define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008
2531 /* SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD */
2532 /* Description: Enables quadrature clock in the pfssd */
2533 #define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4
2534 #define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010
2536 /* ==================================================================== */
2537 /* Register "SH_NI0_LLP_CONFIG" */
2538 /* Sets the configuration of LLP and channel */
2539 /* ==================================================================== */
2541 #define SH_NI0_LLP_CONFIG 0x0000000150000020
2542 #define SH_NI0_LLP_CONFIG_MASK 0x0000003fffffffff
2543 #define SH_NI0_LLP_CONFIG_INIT 0x00000007fc6ffd00
2545 /* SH_NI0_LLP_CONFIG_MAXBURST */
2546 #define SH_NI0_LLP_CONFIG_MAXBURST_SHFT 0
2547 #define SH_NI0_LLP_CONFIG_MAXBURST_MASK 0x00000000000003ff
2549 /* SH_NI0_LLP_CONFIG_MAXRETRY */
2550 #define SH_NI0_LLP_CONFIG_MAXRETRY_SHFT 10
2551 #define SH_NI0_LLP_CONFIG_MAXRETRY_MASK 0x00000000000ffc00
2553 /* SH_NI0_LLP_CONFIG_NULLTIMEOUT */
2554 #define SH_NI0_LLP_CONFIG_NULLTIMEOUT_SHFT 20
2555 #define SH_NI0_LLP_CONFIG_NULLTIMEOUT_MASK 0x0000000003f00000
2557 /* SH_NI0_LLP_CONFIG_FTU_TIME */
2558 #define SH_NI0_LLP_CONFIG_FTU_TIME_SHFT 26
2559 #define SH_NI0_LLP_CONFIG_FTU_TIME_MASK 0x0000003ffc000000
2561 /* ==================================================================== */
2562 /* Register "SH_NI0_LLP_TEST_CTL" */
2563 /* ==================================================================== */
2565 #define SH_NI0_LLP_TEST_CTL 0x0000000150000028
2566 #define SH_NI0_LLP_TEST_CTL_MASK 0x7ff3f3ffffffffff
2567 #define SH_NI0_LLP_TEST_CTL_INIT 0x000000000a5fffff
2569 /* SH_NI0_LLP_TEST_CTL_PATTERN */
2570 /* Description: Send channel data pattern */
2571 #define SH_NI0_LLP_TEST_CTL_PATTERN_SHFT 0
2572 #define SH_NI0_LLP_TEST_CTL_PATTERN_MASK 0x000000ffffffffff
2574 /* SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE */
2575 /* Description: Enables continuous send of data */
2576 #define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_SHFT 40
2577 #define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_MASK 0x0000030000000000
2579 /* SH_NI0_LLP_TEST_CTL_WIRE_SEL */
2580 #define SH_NI0_LLP_TEST_CTL_WIRE_SEL_SHFT 44
2581 #define SH_NI0_LLP_TEST_CTL_WIRE_SEL_MASK 0x0003f00000000000
2583 /* SH_NI0_LLP_TEST_CTL_LFSR_MODE */
2584 #define SH_NI0_LLP_TEST_CTL_LFSR_MODE_SHFT 52
2585 #define SH_NI0_LLP_TEST_CTL_LFSR_MODE_MASK 0x0030000000000000
2587 /* SH_NI0_LLP_TEST_CTL_NOISE_MODE */
2588 #define SH_NI0_LLP_TEST_CTL_NOISE_MODE_SHFT 54
2589 #define SH_NI0_LLP_TEST_CTL_NOISE_MODE_MASK 0x00c0000000000000
2591 /* SH_NI0_LLP_TEST_CTL_ARMCAPTURE */
2592 /* Description: Enable Capture of Next MicroPacket */
2593 #define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_SHFT 56
2594 #define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_MASK 0x0100000000000000
2596 /* SH_NI0_LLP_TEST_CTL_CAPTURECBONLY */
2597 /* Description: Only capture a micropacket with a Check Byte error */
2598 #define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_SHFT 57
2599 #define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_MASK 0x0200000000000000
2601 /* SH_NI0_LLP_TEST_CTL_SENDCBERROR */
2602 /* Description: Sends a single error */
2603 #define SH_NI0_LLP_TEST_CTL_SENDCBERROR_SHFT 58
2604 #define SH_NI0_LLP_TEST_CTL_SENDCBERROR_MASK 0x0400000000000000
2606 /* SH_NI0_LLP_TEST_CTL_SENDSNERROR */
2607 /* Description: Sends a single sequence number error */
2608 #define SH_NI0_LLP_TEST_CTL_SENDSNERROR_SHFT 59
2609 #define SH_NI0_LLP_TEST_CTL_SENDSNERROR_MASK 0x0800000000000000
2611 /* SH_NI0_LLP_TEST_CTL_FAKESNERROR */
2612 /* Description: Causes receiver to pretend it saw a sn error */
2613 #define SH_NI0_LLP_TEST_CTL_FAKESNERROR_SHFT 60
2614 #define SH_NI0_LLP_TEST_CTL_FAKESNERROR_MASK 0x1000000000000000
2616 /* SH_NI0_LLP_TEST_CTL_CAPTURED */
2617 /* Description: Indicates a Valid Micropacket was captured */
2618 #define SH_NI0_LLP_TEST_CTL_CAPTURED_SHFT 61
2619 #define SH_NI0_LLP_TEST_CTL_CAPTURED_MASK 0x2000000000000000
2621 /* SH_NI0_LLP_TEST_CTL_CBERROR */
2622 /* Description: Indicates a Micropacket with a CB error was capture */
2623 #define SH_NI0_LLP_TEST_CTL_CBERROR_SHFT 62
2624 #define SH_NI0_LLP_TEST_CTL_CBERROR_MASK 0x4000000000000000
2626 /* ==================================================================== */
2627 /* Register "SH_NI0_LLP_CAPT_WD1" */
2628 /* low order 64-bit captured word */
2629 /* ==================================================================== */
2631 #define SH_NI0_LLP_CAPT_WD1 0x0000000150000030
2632 #define SH_NI0_LLP_CAPT_WD1_MASK 0xffffffffffffffff
2633 #define SH_NI0_LLP_CAPT_WD1_INIT 0x0000000000000000
2635 /* SH_NI0_LLP_CAPT_WD1_DATA */
2636 /* Description: low order 64-bit captured word */
2637 #define SH_NI0_LLP_CAPT_WD1_DATA_SHFT 0
2638 #define SH_NI0_LLP_CAPT_WD1_DATA_MASK 0xffffffffffffffff
2640 /* ==================================================================== */
2641 /* Register "SH_NI0_LLP_CAPT_WD2" */
2642 /* high order 64-bit captured word */
2643 /* ==================================================================== */
2645 #define SH_NI0_LLP_CAPT_WD2 0x0000000150000038
2646 #define SH_NI0_LLP_CAPT_WD2_MASK 0xffffffffffffffff
2647 #define SH_NI0_LLP_CAPT_WD2_INIT 0x0000000000000000
2649 /* SH_NI0_LLP_CAPT_WD2_DATA */
2650 /* Description: high order 64-bit captured word */
2651 #define SH_NI0_LLP_CAPT_WD2_DATA_SHFT 0
2652 #define SH_NI0_LLP_CAPT_WD2_DATA_MASK 0xffffffffffffffff
2654 /* ==================================================================== */
2655 /* Register "SH_NI0_LLP_CAPT_SBCB" */
2656 /* captured sideband, sequence, and CRC */
2657 /* ==================================================================== */
2659 #define SH_NI0_LLP_CAPT_SBCB 0x0000000150000040
2660 #define SH_NI0_LLP_CAPT_SBCB_MASK 0x0000001fffffffff
2661 #define SH_NI0_LLP_CAPT_SBCB_INIT 0x0000000000000000
2663 /* SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN */
2664 /* Description: sideband and sequence */
2665 #define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0
2666 #define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff
2668 /* SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC */
2669 /* Description: CRC */
2670 #define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16
2671 #define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000
2673 /* SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS */
2674 /* Description: All CB errors have been sent */
2675 #define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32
2676 #define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000
2678 /* SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS */
2679 /* Description: All SN errors have been sent */
2680 #define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33
2681 #define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000
2683 /* SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS */
2684 /* Description: All faked SN errors have been sent */
2685 #define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34
2686 #define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000
2688 /* SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW */
2689 /* Description: wire charge counter overflowed, valid if llp_mode e */
2690 #define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35
2691 #define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000
2693 /* SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW */
2694 /* Description: wire charge counter underflowed, valid if llp_mode */
2696 #define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36
2697 #define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000
2699 /* ==================================================================== */
2700 /* Register "SH_NI0_LLP_ERR" */
2701 /* ==================================================================== */
2703 #define SH_NI0_LLP_ERR 0x0000000150000048
2704 #define SH_NI0_LLP_ERR_MASK 0x001fffffffffffff
2705 #define SH_NI0_LLP_ERR_INIT 0x0000000000000000
2707 /* SH_NI0_LLP_ERR_RX_SN_ERR_COUNT */
2708 /* Description: Counts the sequence number errors received */
2709 #define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_SHFT 0
2710 #define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_MASK 0x00000000000000ff
2712 /* SH_NI0_LLP_ERR_RX_CB_ERR_COUNT */
2713 /* Description: Counts the check byte errors received */
2714 #define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_SHFT 8
2715 #define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_MASK 0x000000000000ff00
2717 /* SH_NI0_LLP_ERR_RETRY_COUNT */
2718 /* Description: Counts the retries */
2719 #define SH_NI0_LLP_ERR_RETRY_COUNT_SHFT 16
2720 #define SH_NI0_LLP_ERR_RETRY_COUNT_MASK 0x0000000000ff0000
2722 /* SH_NI0_LLP_ERR_RETRY_TIMEOUT */
2723 /* Description: Indicates a retry timeout has occurred */
2724 #define SH_NI0_LLP_ERR_RETRY_TIMEOUT_SHFT 24
2725 #define SH_NI0_LLP_ERR_RETRY_TIMEOUT_MASK 0x0000000001000000
2727 /* SH_NI0_LLP_ERR_RCV_LINK_RESET */
2728 /* Description: Indicates a link reset has been received */
2729 #define SH_NI0_LLP_ERR_RCV_LINK_RESET_SHFT 25
2730 #define SH_NI0_LLP_ERR_RCV_LINK_RESET_MASK 0x0000000002000000
2732 /* SH_NI0_LLP_ERR_SQUASH */
2733 /* Description: Indicates a micropacket was squashed */
2734 #define SH_NI0_LLP_ERR_SQUASH_SHFT 26
2735 #define SH_NI0_LLP_ERR_SQUASH_MASK 0x0000000004000000
2737 /* SH_NI0_LLP_ERR_POWER_NOT_OK */
2738 /* Description: Detects and traps a loss of power_OK */
2739 #define SH_NI0_LLP_ERR_POWER_NOT_OK_SHFT 27
2740 #define SH_NI0_LLP_ERR_POWER_NOT_OK_MASK 0x0000000008000000
2742 /* SH_NI0_LLP_ERR_WIRE_CNT */
2743 /* Description: counts the errors detected on a single wire test */
2744 #define SH_NI0_LLP_ERR_WIRE_CNT_SHFT 28
2745 #define SH_NI0_LLP_ERR_WIRE_CNT_MASK 0x000ffffff0000000
2747 /* SH_NI0_LLP_ERR_WIRE_OVERFLOW */
2748 /* Description: wire_error_cnt has overflowed */
2749 #define SH_NI0_LLP_ERR_WIRE_OVERFLOW_SHFT 52
2750 #define SH_NI0_LLP_ERR_WIRE_OVERFLOW_MASK 0x0010000000000000
2752 /* ==================================================================== */
2753 /* Register "SH_NI1_LLP_STAT" */
2754 /* This register describes the LLP status. */
2755 /* ==================================================================== */
2757 #define SH_NI1_LLP_STAT 0x0000000150002000
2758 #define SH_NI1_LLP_STAT_MASK 0x000000000000000f
2759 #define SH_NI1_LLP_STAT_INIT 0x0000000000000000
2761 /* SH_NI1_LLP_STAT_LINK_RESET_STATE */
2762 /* Description: Status of LLP link. */
2763 #define SH_NI1_LLP_STAT_LINK_RESET_STATE_SHFT 0
2764 #define SH_NI1_LLP_STAT_LINK_RESET_STATE_MASK 0x000000000000000f
2766 /* ==================================================================== */
2767 /* Register "SH_NI1_LLP_RESET" */
2768 /* Writing issues a reset to the network interface */
2769 /* ==================================================================== */
2771 #define SH_NI1_LLP_RESET 0x0000000150002008
2772 #define SH_NI1_LLP_RESET_MASK 0x0000000000000003
2773 #define SH_NI1_LLP_RESET_INIT 0x0000000000000000
2775 /* SH_NI1_LLP_RESET_LINK */
2776 /* Description: Send Link Reset. Generates a pulse. */
2777 #define SH_NI1_LLP_RESET_LINK_SHFT 0
2778 #define SH_NI1_LLP_RESET_LINK_MASK 0x0000000000000001
2780 /* SH_NI1_LLP_RESET_WARM */
2781 /* Description: Send Warm Reset. Generates a pulse. */
2782 #define SH_NI1_LLP_RESET_WARM_SHFT 1
2783 #define SH_NI1_LLP_RESET_WARM_MASK 0x0000000000000002
2785 /* ==================================================================== */
2786 /* Register "SH_NI1_LLP_RESET_EN" */
2787 /* Controls LLP warm reset propagation */
2788 /* ==================================================================== */
2790 #define SH_NI1_LLP_RESET_EN 0x0000000150002010
2791 #define SH_NI1_LLP_RESET_EN_MASK 0x0000000000000001
2792 #define SH_NI1_LLP_RESET_EN_INIT 0x0000000000000001
2794 /* SH_NI1_LLP_RESET_EN_OK */
2795 /* Description: Allow LLP warm reset to reset SHUB */
2796 #define SH_NI1_LLP_RESET_EN_OK_SHFT 0
2797 #define SH_NI1_LLP_RESET_EN_OK_MASK 0x0000000000000001
2799 /* ==================================================================== */
2800 /* Register "SH_NI1_LLP_CHAN_MODE" */
2801 /* Sets the signaling mode of LLP and channel */
2802 /* ==================================================================== */
2804 #define SH_NI1_LLP_CHAN_MODE 0x0000000150002018
2805 #define SH_NI1_LLP_CHAN_MODE_MASK 0x000000000000001f
2806 #define SH_NI1_LLP_CHAN_MODE_INIT 0x0000000000000000
2808 /* SH_NI1_LLP_CHAN_MODE_BITMODE32 */
2809 /* Description: Enables 32-bit (plus sideband) channel phits */
2810 #define SH_NI1_LLP_CHAN_MODE_BITMODE32_SHFT 0
2811 #define SH_NI1_LLP_CHAN_MODE_BITMODE32_MASK 0x0000000000000001
2813 /* SH_NI1_LLP_CHAN_MODE_AC_ENCODE */
2814 /* Description: Enables nearly dc-free encoding for AC-coupling */
2815 #define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_SHFT 1
2816 #define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_MASK 0x0000000000000002
2818 /* SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING */
2819 /* Description: Enables automatic tuning of channel skew. */
2820 #define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_SHFT 2
2821 #define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_MASK 0x0000000000000004
2823 /* SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD */
2824 /* Description: Enables remote fine tune updates */
2825 #define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3
2826 #define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008
2828 /* SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD */
2829 /* Description: Enables quadrature clock in the pfssd */
2830 #define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4
2831 #define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010
2833 /* ==================================================================== */
2834 /* Register "SH_NI1_LLP_CONFIG" */
2835 /* Sets the configuration of LLP and channel */
2836 /* ==================================================================== */
2838 #define SH_NI1_LLP_CONFIG 0x0000000150002020
2839 #define SH_NI1_LLP_CONFIG_MASK 0x0000003fffffffff
2840 #define SH_NI1_LLP_CONFIG_INIT 0x00000007fc6ffd00
2842 /* SH_NI1_LLP_CONFIG_MAXBURST */
2843 #define SH_NI1_LLP_CONFIG_MAXBURST_SHFT 0
2844 #define SH_NI1_LLP_CONFIG_MAXBURST_MASK 0x00000000000003ff
2846 /* SH_NI1_LLP_CONFIG_MAXRETRY */
2847 #define SH_NI1_LLP_CONFIG_MAXRETRY_SHFT 10
2848 #define SH_NI1_LLP_CONFIG_MAXRETRY_MASK 0x00000000000ffc00
2850 /* SH_NI1_LLP_CONFIG_NULLTIMEOUT */
2851 #define SH_NI1_LLP_CONFIG_NULLTIMEOUT_SHFT 20
2852 #define SH_NI1_LLP_CONFIG_NULLTIMEOUT_MASK 0x0000000003f00000
2854 /* SH_NI1_LLP_CONFIG_FTU_TIME */
2855 #define SH_NI1_LLP_CONFIG_FTU_TIME_SHFT 26
2856 #define SH_NI1_LLP_CONFIG_FTU_TIME_MASK 0x0000003ffc000000
2858 /* ==================================================================== */
2859 /* Register "SH_NI1_LLP_TEST_CTL" */
2860 /* ==================================================================== */
2862 #define SH_NI1_LLP_TEST_CTL 0x0000000150002028
2863 #define SH_NI1_LLP_TEST_CTL_MASK 0x7ff3f3ffffffffff
2864 #define SH_NI1_LLP_TEST_CTL_INIT 0x000000000a5fffff
2866 /* SH_NI1_LLP_TEST_CTL_PATTERN */
2867 /* Description: Send channel data pattern */
2868 #define SH_NI1_LLP_TEST_CTL_PATTERN_SHFT 0
2869 #define SH_NI1_LLP_TEST_CTL_PATTERN_MASK 0x000000ffffffffff
2871 /* SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE */
2872 /* Description: Enables continuous send of data */
2873 #define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_SHFT 40
2874 #define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_MASK 0x0000030000000000
2876 /* SH_NI1_LLP_TEST_CTL_WIRE_SEL */
2877 #define SH_NI1_LLP_TEST_CTL_WIRE_SEL_SHFT 44
2878 #define SH_NI1_LLP_TEST_CTL_WIRE_SEL_MASK 0x0003f00000000000
2880 /* SH_NI1_LLP_TEST_CTL_LFSR_MODE */
2881 #define SH_NI1_LLP_TEST_CTL_LFSR_MODE_SHFT 52
2882 #define SH_NI1_LLP_TEST_CTL_LFSR_MODE_MASK 0x0030000000000000
2884 /* SH_NI1_LLP_TEST_CTL_NOISE_MODE */
2885 #define SH_NI1_LLP_TEST_CTL_NOISE_MODE_SHFT 54
2886 #define SH_NI1_LLP_TEST_CTL_NOISE_MODE_MASK 0x00c0000000000000
2888 /* SH_NI1_LLP_TEST_CTL_ARMCAPTURE */
2889 /* Description: Enable Capture of Next MicroPacket */
2890 #define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_SHFT 56
2891 #define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_MASK 0x0100000000000000
2893 /* SH_NI1_LLP_TEST_CTL_CAPTURECBONLY */
2894 /* Description: Only capture a micropacket with a Check Byte error */
2895 #define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_SHFT 57
2896 #define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_MASK 0x0200000000000000
2898 /* SH_NI1_LLP_TEST_CTL_SENDCBERROR */
2899 /* Description: Sends a single error */
2900 #define SH_NI1_LLP_TEST_CTL_SENDCBERROR_SHFT 58
2901 #define SH_NI1_LLP_TEST_CTL_SENDCBERROR_MASK 0x0400000000000000
2903 /* SH_NI1_LLP_TEST_CTL_SENDSNERROR */
2904 /* Description: Sends a single sequence number error */
2905 #define SH_NI1_LLP_TEST_CTL_SENDSNERROR_SHFT 59
2906 #define SH_NI1_LLP_TEST_CTL_SENDSNERROR_MASK 0x0800000000000000
2908 /* SH_NI1_LLP_TEST_CTL_FAKESNERROR */
2909 /* Description: Causes receiver to pretend it saw a sn error */
2910 #define SH_NI1_LLP_TEST_CTL_FAKESNERROR_SHFT 60
2911 #define SH_NI1_LLP_TEST_CTL_FAKESNERROR_MASK 0x1000000000000000
2913 /* SH_NI1_LLP_TEST_CTL_CAPTURED */
2914 /* Description: Indicates a Valid Micropacket was captured */
2915 #define SH_NI1_LLP_TEST_CTL_CAPTURED_SHFT 61
2916 #define SH_NI1_LLP_TEST_CTL_CAPTURED_MASK 0x2000000000000000
2918 /* SH_NI1_LLP_TEST_CTL_CBERROR */
2919 /* Description: Indicates a Micropacket with a CB error was capture */
2920 #define SH_NI1_LLP_TEST_CTL_CBERROR_SHFT 62
2921 #define SH_NI1_LLP_TEST_CTL_CBERROR_MASK 0x4000000000000000
2923 /* ==================================================================== */
2924 /* Register "SH_NI1_LLP_CAPT_WD1" */
2925 /* low order 64-bit captured word */
2926 /* ==================================================================== */
2928 #define SH_NI1_LLP_CAPT_WD1 0x0000000150002030
2929 #define SH_NI1_LLP_CAPT_WD1_MASK 0xffffffffffffffff
2930 #define SH_NI1_LLP_CAPT_WD1_INIT 0x0000000000000000
2932 /* SH_NI1_LLP_CAPT_WD1_DATA */
2933 /* Description: low order 64-bit captured word */
2934 #define SH_NI1_LLP_CAPT_WD1_DATA_SHFT 0
2935 #define SH_NI1_LLP_CAPT_WD1_DATA_MASK 0xffffffffffffffff
2937 /* ==================================================================== */
2938 /* Register "SH_NI1_LLP_CAPT_WD2" */
2939 /* high order 64-bit captured word */
2940 /* ==================================================================== */
2942 #define SH_NI1_LLP_CAPT_WD2 0x0000000150002038
2943 #define SH_NI1_LLP_CAPT_WD2_MASK 0xffffffffffffffff
2944 #define SH_NI1_LLP_CAPT_WD2_INIT 0x0000000000000000
2946 /* SH_NI1_LLP_CAPT_WD2_DATA */
2947 /* Description: high order 64-bit captured word */
2948 #define SH_NI1_LLP_CAPT_WD2_DATA_SHFT 0
2949 #define SH_NI1_LLP_CAPT_WD2_DATA_MASK 0xffffffffffffffff
2951 /* ==================================================================== */
2952 /* Register "SH_NI1_LLP_CAPT_SBCB" */
2953 /* captured sideband, sequence, and CRC */
2954 /* ==================================================================== */
2956 #define SH_NI1_LLP_CAPT_SBCB 0x0000000150002040
2957 #define SH_NI1_LLP_CAPT_SBCB_MASK 0x0000001fffffffff
2958 #define SH_NI1_LLP_CAPT_SBCB_INIT 0x0000000000000000
2960 /* SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN */
2961 /* Description: sideband and sequence */
2962 #define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0
2963 #define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff
2965 /* SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC */
2966 /* Description: CRC */
2967 #define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16
2968 #define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000
2970 /* SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS */
2971 /* Description: All CB errors have been sent */
2972 #define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32
2973 #define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000
2975 /* SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS */
2976 /* Description: All SN errors have been sent */
2977 #define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33
2978 #define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000
2980 /* SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS */
2981 /* Description: All faked SN errors have been sent */
2982 #define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34
2983 #define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000
2985 /* SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW */
2986 /* Description: wire charge counter overflowed, valid if llp_mode e */
2987 #define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35
2988 #define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000
2990 /* SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW */
2991 /* Description: wire charge counter underflowed, valid if llp_mode */
2993 #define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36
2994 #define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000
2996 /* ==================================================================== */
2997 /* Register "SH_NI1_LLP_ERR" */
2998 /* ==================================================================== */
3000 #define SH_NI1_LLP_ERR 0x0000000150002048
3001 #define SH_NI1_LLP_ERR_MASK 0x001fffffffffffff
3002 #define SH_NI1_LLP_ERR_INIT 0x0000000000000000
3004 /* SH_NI1_LLP_ERR_RX_SN_ERR_COUNT */
3005 /* Description: Counts the sequence number errors received */
3006 #define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_SHFT 0
3007 #define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_MASK 0x00000000000000ff
3009 /* SH_NI1_LLP_ERR_RX_CB_ERR_COUNT */
3010 /* Description: Counts the check byte errors received */
3011 #define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_SHFT 8
3012 #define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_MASK 0x000000000000ff00
3014 /* SH_NI1_LLP_ERR_RETRY_COUNT */
3015 /* Description: Counts the retries */
3016 #define SH_NI1_LLP_ERR_RETRY_COUNT_SHFT 16
3017 #define SH_NI1_LLP_ERR_RETRY_COUNT_MASK 0x0000000000ff0000
3019 /* SH_NI1_LLP_ERR_RETRY_TIMEOUT */
3020 /* Description: Indicates a retry timeout has occurred */
3021 #define SH_NI1_LLP_ERR_RETRY_TIMEOUT_SHFT 24
3022 #define SH_NI1_LLP_ERR_RETRY_TIMEOUT_MASK 0x0000000001000000
3024 /* SH_NI1_LLP_ERR_RCV_LINK_RESET */
3025 /* Description: Indicates a link reset has been received */
3026 #define SH_NI1_LLP_ERR_RCV_LINK_RESET_SHFT 25
3027 #define SH_NI1_LLP_ERR_RCV_LINK_RESET_MASK 0x0000000002000000
3029 /* SH_NI1_LLP_ERR_SQUASH */
3030 /* Description: Indicates a micropacket was squashed */
3031 #define SH_NI1_LLP_ERR_SQUASH_SHFT 26
3032 #define SH_NI1_LLP_ERR_SQUASH_MASK 0x0000000004000000
3034 /* SH_NI1_LLP_ERR_POWER_NOT_OK */
3035 /* Description: Detects and traps a loss of power_OK */
3036 #define SH_NI1_LLP_ERR_POWER_NOT_OK_SHFT 27
3037 #define SH_NI1_LLP_ERR_POWER_NOT_OK_MASK 0x0000000008000000
3039 /* SH_NI1_LLP_ERR_WIRE_CNT */
3040 /* Description: counts the errors detected on a single wire test */
3041 #define SH_NI1_LLP_ERR_WIRE_CNT_SHFT 28
3042 #define SH_NI1_LLP_ERR_WIRE_CNT_MASK 0x000ffffff0000000
3044 /* SH_NI1_LLP_ERR_WIRE_OVERFLOW */
3045 /* Description: wire_error_cnt has overflowed */
3046 #define SH_NI1_LLP_ERR_WIRE_OVERFLOW_SHFT 52
3047 #define SH_NI1_LLP_ERR_WIRE_OVERFLOW_MASK 0x0010000000000000
3049 /* ==================================================================== */
3050 /* Register "SH_XNNI0_LLP_TO_FIFO02_FLOW" */
3051 /* ==================================================================== */
3053 #define SH_XNNI0_LLP_TO_FIFO02_FLOW 0x0000000150001010
3054 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_MASK 0x3f3f003f3f00bfbf
3055 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_INIT 0x0000000000000000
3057 /* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD */
3058 /* Description: vc0 withhold */
3059 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
3060 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
3062 /* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED */
3063 /* Description: Force Credit on VC0 from debit cntr */
3064 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
3065 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
3067 /* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD */
3068 /* Description: vc2 withhold */
3069 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
3070 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
3072 /* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED */
3073 /* Description: Force Credit on VC2 from debit cntr */
3074 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
3075 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
3077 /* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN */
3078 /* Description: vc0 credit dynamic value */
3079 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24
3080 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
3082 /* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP */
3083 /* Description: vc0 credit captured value */
3084 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32
3085 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
3087 /* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN */
3088 /* Description: vc2 credit dynamic value */
3089 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48
3090 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
3092 /* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP */
3093 /* Description: vc2 credit captured value */
3094 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56
3095 #define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
3097 /* ==================================================================== */
3098 /* Register "SH_XNNI0_LLP_TO_FIFO13_FLOW" */
3099 /* ==================================================================== */
3101 #define SH_XNNI0_LLP_TO_FIFO13_FLOW 0x0000000150001020
3102 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_MASK 0x3f3f003f3f00bfbf
3103 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_INIT 0x0000000000000000
3105 /* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD */
3106 /* Description: vc0 withhold */
3107 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
3108 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
3110 /* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED */
3111 /* Description: Force Credit on VC0 from debit cntr */
3112 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
3113 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
3115 /* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD */
3116 /* Description: vc2 withhold */
3117 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
3118 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
3120 /* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED */
3121 /* Description: Force Credit on VC2 from debit cntr */
3122 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
3123 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
3125 /* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN */
3126 /* Description: vc0 credit dynamic value */
3127 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24
3128 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
3130 /* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP */
3131 /* Description: vc0 credit captured value */
3132 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32
3133 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
3135 /* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN */
3136 /* Description: vc2 credit dynamic value */
3137 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48
3138 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
3140 /* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP */
3141 /* Description: vc2 credit captured value */
3142 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56
3143 #define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
3145 /* ==================================================================== */
3146 /* Register "SH_XNNI0_LLP_DEBIT_FLOW" */
3147 /* ==================================================================== */
3149 #define SH_XNNI0_LLP_DEBIT_FLOW 0x0000000150001030
3150 #define SH_XNNI0_LLP_DEBIT_FLOW_MASK 0x1f1f1f1f1f1f1f1f
3151 #define SH_XNNI0_LLP_DEBIT_FLOW_INIT 0x0000000000000000
3153 /* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN */
3154 /* Description: vc0 debit dynamic value */
3155 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0
3156 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f
3158 /* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP */
3159 /* Description: vc0 debit captured value */
3160 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8
3161 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00
3163 /* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN */
3164 /* Description: vc1 debit dynamic value */
3165 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16
3166 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000
3168 /* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP */
3169 /* Description: vc1 debit captured value */
3170 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24
3171 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000
3173 /* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN */
3174 /* Description: vc2 debit dynamic value */
3175 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32
3176 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000
3178 /* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP */
3179 /* Description: vc2 debit captured value */
3180 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40
3181 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000
3183 /* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN */
3184 /* Description: vc3 debit dynamic value */
3185 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48
3186 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000
3188 /* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP */
3189 /* Description: vc3 debit captured value */
3190 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56
3191 #define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000
3193 /* ==================================================================== */
3194 /* Register "SH_XNNI0_LINK_0_FLOW" */
3195 /* ==================================================================== */
3197 #define SH_XNNI0_LINK_0_FLOW 0x0000000150001040
3198 #define SH_XNNI0_LINK_0_FLOW_MASK 0x000000007f7f7fbf
3199 #define SH_XNNI0_LINK_0_FLOW_INIT 0x0000000000001800
3201 /* SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD */
3202 /* Description: vc0 withhold */
3203 #define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
3204 #define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
3206 /* SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED */
3207 /* Description: Force Credit on vc0 from debit cntr */
3208 #define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
3209 #define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
3211 /* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST */
3212 /* Description: vc0 Limit Test */
3213 #define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8
3214 #define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00
3216 /* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN */
3217 /* Description: Dynamic vc0 credit value */
3218 #define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16
3219 #define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000
3221 /* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP */
3222 /* Description: Captured vc0 credit */
3223 #define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24
3224 #define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000
3226 /* ==================================================================== */
3227 /* Register "SH_XNNI0_LINK_1_FLOW" */
3228 /* ==================================================================== */
3230 #define SH_XNNI0_LINK_1_FLOW 0x0000000150001050
3231 #define SH_XNNI0_LINK_1_FLOW_MASK 0x000000007f7f7fbf
3232 #define SH_XNNI0_LINK_1_FLOW_INIT 0x0000000000001800
3234 /* SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD */
3235 /* Description: vc1 withhold */
3236 #define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
3237 #define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
3239 /* SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED */
3240 /* Description: Force Credit on vc1 from debit cntr */
3241 #define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
3242 #define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
3244 /* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST */
3245 /* Description: vc1 Limit Test */
3246 #define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8
3247 #define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00
3249 /* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN */
3250 /* Description: Dynamic vc1 credit value */
3251 #define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16
3252 #define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000
3254 /* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP */
3255 /* Description: Captured vc1 credit */
3256 #define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24
3257 #define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000
3259 /* ==================================================================== */
3260 /* Register "SH_XNNI0_LINK_2_FLOW" */
3261 /* ==================================================================== */
3263 #define SH_XNNI0_LINK_2_FLOW 0x0000000150001060
3264 #define SH_XNNI0_LINK_2_FLOW_MASK 0x000000007f7f7fbf
3265 #define SH_XNNI0_LINK_2_FLOW_INIT 0x0000000000001800
3267 /* SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD */
3268 /* Description: vc2 withhold */
3269 #define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
3270 #define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
3272 /* SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED */
3273 /* Description: Force Credit on vc2 from debit cntr */
3274 #define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
3275 #define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
3277 /* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST */
3278 /* Description: vc2 Limit Test */
3279 #define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8
3280 #define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00
3282 /* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN */
3283 /* Description: Dynamic vc2 credit value */
3284 #define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16
3285 #define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000
3287 /* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP */
3288 /* Description: Captured vc2 credit */
3289 #define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24
3290 #define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000
3292 /* ==================================================================== */
3293 /* Register "SH_XNNI0_LINK_3_FLOW" */
3294 /* ==================================================================== */
3296 #define SH_XNNI0_LINK_3_FLOW 0x0000000150001070
3297 #define SH_XNNI0_LINK_3_FLOW_MASK 0x000000007f7f7fbf
3298 #define SH_XNNI0_LINK_3_FLOW_INIT 0x0000000000001800
3300 /* SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD */
3301 /* Description: vc3 withhold */
3302 #define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
3303 #define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
3305 /* SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED */
3306 /* Description: Force Credit on vc3 from debit cntr */
3307 #define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
3308 #define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
3310 /* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST */
3311 /* Description: vc3 Limit Test */
3312 #define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8
3313 #define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00
3315 /* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN */
3316 /* Description: Dynamic vc3 credit value */
3317 #define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16
3318 #define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000
3320 /* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP */
3321 /* Description: Captured vc3 credit */
3322 #define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24
3323 #define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000
3325 /* ==================================================================== */
3326 /* Register "SH_XNNI1_LLP_TO_FIFO02_FLOW" */
3327 /* ==================================================================== */
3329 #define SH_XNNI1_LLP_TO_FIFO02_FLOW 0x0000000150003010
3330 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_MASK 0x3f3f003f3f00bfbf
3331 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_INIT 0x0000000000000000
3333 /* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD */
3334 /* Description: vc0 withhold */
3335 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
3336 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
3338 /* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED */
3339 /* Description: Force Credit on VC0 from debit cntr */
3340 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
3341 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
3343 /* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD */
3344 /* Description: vc2 withhold */
3345 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
3346 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
3348 /* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED */
3349 /* Description: Force Credit on VC2 from debit cntr */
3350 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
3351 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
3353 /* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN */
3354 /* Description: vc0 credit dynamic value */
3355 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24
3356 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
3358 /* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP */
3359 /* Description: vc0 credit captured value */
3360 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32
3361 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
3363 /* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN */
3364 /* Description: vc2 credit dynamic value */
3365 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48
3366 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
3368 /* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP */
3369 /* Description: vc2 credit captured value */
3370 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56
3371 #define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
3373 /* ==================================================================== */
3374 /* Register "SH_XNNI1_LLP_TO_FIFO13_FLOW" */
3375 /* ==================================================================== */
3377 #define SH_XNNI1_LLP_TO_FIFO13_FLOW 0x0000000150003020
3378 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_MASK 0x3f3f003f3f00bfbf
3379 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_INIT 0x0000000000000000
3381 /* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD */
3382 /* Description: vc0 withhold */
3383 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
3384 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
3386 /* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED */
3387 /* Description: Force Credit on VC0 from debit cntr */
3388 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
3389 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
3391 /* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD */
3392 /* Description: vc2 withhold */
3393 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
3394 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
3396 /* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED */
3397 /* Description: Force Credit on VC2 from debit cntr */
3398 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
3399 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
3401 /* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN */
3402 /* Description: vc0 credit dynamic value */
3403 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24
3404 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
3406 /* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP */
3407 /* Description: vc0 credit captured value */
3408 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32
3409 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
3411 /* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN */
3412 /* Description: vc2 credit dynamic value */
3413 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48
3414 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
3416 /* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP */
3417 /* Description: vc2 credit captured value */
3418 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56
3419 #define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
3421 /* ==================================================================== */
3422 /* Register "SH_XNNI1_LLP_DEBIT_FLOW" */
3423 /* ==================================================================== */
3425 #define SH_XNNI1_LLP_DEBIT_FLOW 0x0000000150003030
3426 #define SH_XNNI1_LLP_DEBIT_FLOW_MASK 0x1f1f1f1f1f1f1f1f
3427 #define SH_XNNI1_LLP_DEBIT_FLOW_INIT 0x0000000000000000
3429 /* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN */
3430 /* Description: vc0 debit dynamic value */
3431 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0
3432 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f
3434 /* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP */
3435 /* Description: vc0 debit captured value */
3436 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8
3437 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00
3439 /* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN */
3440 /* Description: vc1 debit dynamic value */
3441 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16
3442 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000
3444 /* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP */
3445 /* Description: vc1 debit captured value */
3446 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24
3447 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000
3449 /* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN */
3450 /* Description: vc2 debit dynamic value */
3451 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32
3452 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000
3454 /* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP */
3455 /* Description: vc2 debit captured value */
3456 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40
3457 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000
3459 /* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN */
3460 /* Description: vc3 debit dynamic value */
3461 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48
3462 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000
3464 /* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP */
3465 /* Description: vc3 debit captured value */
3466 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56
3467 #define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000
3469 /* ==================================================================== */
3470 /* Register "SH_XNNI1_LINK_0_FLOW" */
3471 /* ==================================================================== */
3473 #define SH_XNNI1_LINK_0_FLOW 0x0000000150003040
3474 #define SH_XNNI1_LINK_0_FLOW_MASK 0x000000007f7f7fbf
3475 #define SH_XNNI1_LINK_0_FLOW_INIT 0x0000000000001800
3477 /* SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD */
3478 /* Description: vc0 withhold */
3479 #define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
3480 #define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
3482 /* SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED */
3483 /* Description: Force Credit on vc0 from debit cntr */
3484 #define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
3485 #define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
3487 /* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST */
3488 /* Description: vc0 Limit Test */
3489 #define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8
3490 #define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00
3492 /* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN */
3493 /* Description: Dynamic vc0 credit value */
3494 #define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16
3495 #define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000
3497 /* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP */
3498 /* Description: Captured vc0 credit */
3499 #define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24
3500 #define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000
3502 /* ==================================================================== */
3503 /* Register "SH_XNNI1_LINK_1_FLOW" */
3504 /* ==================================================================== */
3506 #define SH_XNNI1_LINK_1_FLOW 0x0000000150003050
3507 #define SH_XNNI1_LINK_1_FLOW_MASK 0x000000007f7f7fbf
3508 #define SH_XNNI1_LINK_1_FLOW_INIT 0x0000000000001800
3510 /* SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD */
3511 /* Description: vc1 withhold */
3512 #define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
3513 #define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
3515 /* SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED */
3516 /* Description: Force Credit on vc1 from debit cntr */
3517 #define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
3518 #define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
3520 /* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST */
3521 /* Description: vc1 Limit Test */
3522 #define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8
3523 #define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00
3525 /* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN */
3526 /* Description: Dynamic vc1 credit value */
3527 #define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16
3528 #define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000
3530 /* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP */
3531 /* Description: Captured vc1 credit */
3532 #define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24
3533 #define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000
3535 /* ==================================================================== */
3536 /* Register "SH_XNNI1_LINK_2_FLOW" */
3537 /* ==================================================================== */
3539 #define SH_XNNI1_LINK_2_FLOW 0x0000000150003060
3540 #define SH_XNNI1_LINK_2_FLOW_MASK 0x000000007f7f7fbf
3541 #define SH_XNNI1_LINK_2_FLOW_INIT 0x0000000000001800
3543 /* SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD */
3544 /* Description: vc2 withhold */
3545 #define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
3546 #define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
3548 /* SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED */
3549 /* Description: Force Credit on vc2 from debit cntr */
3550 #define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
3551 #define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
3553 /* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST */
3554 /* Description: vc2 Limit Test */
3555 #define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8
3556 #define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00
3558 /* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN */
3559 /* Description: Dynamic vc2 credit value */
3560 #define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16
3561 #define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000
3563 /* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP */
3564 /* Description: Captured vc2 credit */
3565 #define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24
3566 #define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000
3568 /* ==================================================================== */
3569 /* Register "SH_XNNI1_LINK_3_FLOW" */
3570 /* ==================================================================== */
3572 #define SH_XNNI1_LINK_3_FLOW 0x0000000150003070
3573 #define SH_XNNI1_LINK_3_FLOW_MASK 0x000000007f7f7fbf
3574 #define SH_XNNI1_LINK_3_FLOW_INIT 0x0000000000001800
3576 /* SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD */
3577 /* Description: vc3 withhold */
3578 #define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
3579 #define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
3581 /* SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED */
3582 /* Description: Force Credit on vc3 from debit cntr */
3583 #define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
3584 #define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
3586 /* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST */
3587 /* Description: vc3 Limit Test */
3588 #define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8
3589 #define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00
3591 /* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN */
3592 /* Description: Dynamic vc3 credit value */
3593 #define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16
3594 #define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000
3596 /* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP */
3597 /* Description: Captured vc3 credit */
3598 #define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24
3599 #define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000
3601 /* ==================================================================== */
3602 /* Register "SH_IILB_LOCAL_TABLE" */
3603 /* local lookup table */
3604 /* ==================================================================== */
3606 #define SH_IILB_LOCAL_TABLE 0x0000000150020000
3607 #define SH_IILB_LOCAL_TABLE_MASK 0x800000000000003f
3608 #define SH_IILB_LOCAL_TABLE_MEMDEPTH 128
3609 #define SH_IILB_LOCAL_TABLE_INIT 0x0000000000000000
3611 /* SH_IILB_LOCAL_TABLE_DIR0 */
3612 /* Description: Direction field for next chip */
3613 #define SH_IILB_LOCAL_TABLE_DIR0_SHFT 0
3614 #define SH_IILB_LOCAL_TABLE_DIR0_MASK 0x000000000000000f
3616 /* SH_IILB_LOCAL_TABLE_V0 */
3617 /* Description: Low bit of virtual channel for next chip */
3618 #define SH_IILB_LOCAL_TABLE_V0_SHFT 4
3619 #define SH_IILB_LOCAL_TABLE_V0_MASK 0x0000000000000010
3621 /* SH_IILB_LOCAL_TABLE_NI_SEL0 */
3622 /* Description: ni select for requests */
3623 #define SH_IILB_LOCAL_TABLE_NI_SEL0_SHFT 5
3624 #define SH_IILB_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020
3626 /* SH_IILB_LOCAL_TABLE_VALID */
3627 /* Description: Indicates that this entry is valid */
3628 #define SH_IILB_LOCAL_TABLE_VALID_SHFT 63
3629 #define SH_IILB_LOCAL_TABLE_VALID_MASK 0x8000000000000000
3631 /* ==================================================================== */
3632 /* Register "SH_IILB_GLOBAL_TABLE" */
3633 /* global lookup table */
3634 /* ==================================================================== */
3636 #define SH_IILB_GLOBAL_TABLE 0x0000000150020400
3637 #define SH_IILB_GLOBAL_TABLE_MASK 0x800000000000003f
3638 #define SH_IILB_GLOBAL_TABLE_MEMDEPTH 16
3639 #define SH_IILB_GLOBAL_TABLE_INIT 0x0000000000000000
3641 /* SH_IILB_GLOBAL_TABLE_DIR0 */
3642 /* Description: Direction field for next chip */
3643 #define SH_IILB_GLOBAL_TABLE_DIR0_SHFT 0
3644 #define SH_IILB_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f
3646 /* SH_IILB_GLOBAL_TABLE_V0 */
3647 /* Description: Low bit of virtual channel for next chip */
3648 #define SH_IILB_GLOBAL_TABLE_V0_SHFT 4
3649 #define SH_IILB_GLOBAL_TABLE_V0_MASK 0x0000000000000010
3651 /* SH_IILB_GLOBAL_TABLE_NI_SEL0 */
3652 /* Description: ni select for requests */
3653 #define SH_IILB_GLOBAL_TABLE_NI_SEL0_SHFT 5
3654 #define SH_IILB_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020
3656 /* SH_IILB_GLOBAL_TABLE_VALID */
3657 /* Description: Indicates that this entry is valid */
3658 #define SH_IILB_GLOBAL_TABLE_VALID_SHFT 63
3659 #define SH_IILB_GLOBAL_TABLE_VALID_MASK 0x8000000000000000
3661 /* ==================================================================== */
3662 /* Register "SH_IILB_OVER_RIDE_TABLE" */
3663 /* If enabled, bypass the Global/Local tables */
3664 /* ==================================================================== */
3666 #define SH_IILB_OVER_RIDE_TABLE 0x0000000150020480
3667 #define SH_IILB_OVER_RIDE_TABLE_MASK 0x800000000000003f
3668 #define SH_IILB_OVER_RIDE_TABLE_INIT 0x8000000000000000
3670 /* SH_IILB_OVER_RIDE_TABLE_DIR0 */
3671 /* Description: Direction field for next chip */
3672 #define SH_IILB_OVER_RIDE_TABLE_DIR0_SHFT 0
3673 #define SH_IILB_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f
3675 /* SH_IILB_OVER_RIDE_TABLE_V0 */
3676 /* Description: Low bit of virtual channel for next chip */
3677 #define SH_IILB_OVER_RIDE_TABLE_V0_SHFT 4
3678 #define SH_IILB_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010
3680 /* SH_IILB_OVER_RIDE_TABLE_NI_SEL0 */
3681 /* Description: ni select */
3682 #define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_SHFT 5
3683 #define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020
3685 /* SH_IILB_OVER_RIDE_TABLE_ENABLE */
3686 /* Description: Indicates that this entry is enabled */
3687 #define SH_IILB_OVER_RIDE_TABLE_ENABLE_SHFT 63
3688 #define SH_IILB_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000
3690 /* ==================================================================== */
3691 /* Register "SH_IILB_RSP_PLANE_HINT" */
3692 /* If enabled, invert incoming response only plane hint bit before lo */
3693 /* ==================================================================== */
3695 #define SH_IILB_RSP_PLANE_HINT 0x0000000150020488
3696 #define SH_IILB_RSP_PLANE_HINT_MASK 0x0000000000000000
3697 #define SH_IILB_RSP_PLANE_HINT_INIT 0x0000000000000000
3699 /* ==================================================================== */
3700 /* Register "SH_PI_LOCAL_TABLE" */
3701 /* local lookup table */
3702 /* ==================================================================== */
3704 #define SH_PI_LOCAL_TABLE 0x0000000150021000
3705 #define SH_PI_LOCAL_TABLE_MASK 0x8000000000003f3f
3706 #define SH_PI_LOCAL_TABLE_MEMDEPTH 128
3707 #define SH_PI_LOCAL_TABLE_INIT 0x0000000000000000
3709 /* SH_PI_LOCAL_TABLE_DIR0 */
3710 /* Description: Direction field for next chip */
3711 #define SH_PI_LOCAL_TABLE_DIR0_SHFT 0
3712 #define SH_PI_LOCAL_TABLE_DIR0_MASK 0x000000000000000f
3714 /* SH_PI_LOCAL_TABLE_V0 */
3715 /* Description: Low bit of virtual channel for next chip */
3716 #define SH_PI_LOCAL_TABLE_V0_SHFT 4
3717 #define SH_PI_LOCAL_TABLE_V0_MASK 0x0000000000000010
3719 /* SH_PI_LOCAL_TABLE_NI_SEL0 */
3720 /* Description: ni select for requests */
3721 #define SH_PI_LOCAL_TABLE_NI_SEL0_SHFT 5
3722 #define SH_PI_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020
3724 /* SH_PI_LOCAL_TABLE_DIR1 */
3725 #define SH_PI_LOCAL_TABLE_DIR1_SHFT 8
3726 #define SH_PI_LOCAL_TABLE_DIR1_MASK 0x0000000000000f00
3728 /* SH_PI_LOCAL_TABLE_V1 */
3729 /* Description: Low bit of virtual channel for next chip */
3730 #define SH_PI_LOCAL_TABLE_V1_SHFT 12
3731 #define SH_PI_LOCAL_TABLE_V1_MASK 0x0000000000001000
3733 /* SH_PI_LOCAL_TABLE_NI_SEL1 */
3734 /* Description: ni select for plane-hint 1 */
3735 #define SH_PI_LOCAL_TABLE_NI_SEL1_SHFT 13
3736 #define SH_PI_LOCAL_TABLE_NI_SEL1_MASK 0x0000000000002000
3738 /* SH_PI_LOCAL_TABLE_VALID */
3739 /* Description: Indicates that this entry is valid */
3740 #define SH_PI_LOCAL_TABLE_VALID_SHFT 63
3741 #define SH_PI_LOCAL_TABLE_VALID_MASK 0x8000000000000000
3743 /* ==================================================================== */
3744 /* Register "SH_PI_GLOBAL_TABLE" */
3745 /* global lookup table */
3746 /* ==================================================================== */
3748 #define SH_PI_GLOBAL_TABLE 0x0000000150021400
3749 #define SH_PI_GLOBAL_TABLE_MASK 0x8000000000003f3f
3750 #define SH_PI_GLOBAL_TABLE_MEMDEPTH 16
3751 #define SH_PI_GLOBAL_TABLE_INIT 0x0000000000000000
3753 /* SH_PI_GLOBAL_TABLE_DIR0 */
3754 /* Description: Direction field for next chip */
3755 #define SH_PI_GLOBAL_TABLE_DIR0_SHFT 0
3756 #define SH_PI_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f
3758 /* SH_PI_GLOBAL_TABLE_V0 */
3759 /* Description: Low bit of virtual channel for next chip */
3760 #define SH_PI_GLOBAL_TABLE_V0_SHFT 4
3761 #define SH_PI_GLOBAL_TABLE_V0_MASK 0x0000000000000010
3763 /* SH_PI_GLOBAL_TABLE_NI_SEL0 */
3764 /* Description: ni select for requests */
3765 #define SH_PI_GLOBAL_TABLE_NI_SEL0_SHFT 5
3766 #define SH_PI_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020
3768 /* SH_PI_GLOBAL_TABLE_DIR1 */
3769 #define SH_PI_GLOBAL_TABLE_DIR1_SHFT 8
3770 #define SH_PI_GLOBAL_TABLE_DIR1_MASK 0x0000000000000f00
3772 /* SH_PI_GLOBAL_TABLE_V1 */
3773 /* Description: Low bit of virtual channel for next chip */
3774 #define SH_PI_GLOBAL_TABLE_V1_SHFT 12
3775 #define SH_PI_GLOBAL_TABLE_V1_MASK 0x0000000000001000
3777 /* SH_PI_GLOBAL_TABLE_NI_SEL1 */
3778 /* Description: ni select for plane-hint 1 */
3779 #define SH_PI_GLOBAL_TABLE_NI_SEL1_SHFT 13
3780 #define SH_PI_GLOBAL_TABLE_NI_SEL1_MASK 0x0000000000002000
3782 /* SH_PI_GLOBAL_TABLE_VALID */
3783 /* Description: Indicates that this entry is valid */
3784 #define SH_PI_GLOBAL_TABLE_VALID_SHFT 63
3785 #define SH_PI_GLOBAL_TABLE_VALID_MASK 0x8000000000000000
3787 /* ==================================================================== */
3788 /* Register "SH_PI_OVER_RIDE_TABLE" */
3789 /* If enabled, bypass the Global/Local tables */
3790 /* ==================================================================== */
3792 #define SH_PI_OVER_RIDE_TABLE 0x0000000150021480
3793 #define SH_PI_OVER_RIDE_TABLE_MASK 0x8000000000003f3f
3794 #define SH_PI_OVER_RIDE_TABLE_INIT 0x8000000000002000
3796 /* SH_PI_OVER_RIDE_TABLE_DIR0 */
3797 /* Description: Direction field for next chip */
3798 #define SH_PI_OVER_RIDE_TABLE_DIR0_SHFT 0
3799 #define SH_PI_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f
3801 /* SH_PI_OVER_RIDE_TABLE_V0 */
3802 /* Description: Low bit of virtual channel for next chip */
3803 #define SH_PI_OVER_RIDE_TABLE_V0_SHFT 4
3804 #define SH_PI_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010
3806 /* SH_PI_OVER_RIDE_TABLE_NI_SEL0 */
3807 /* Description: ni select */
3808 #define SH_PI_OVER_RIDE_TABLE_NI_SEL0_SHFT 5
3809 #define SH_PI_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020
3811 /* SH_PI_OVER_RIDE_TABLE_DIR1 */
3812 #define SH_PI_OVER_RIDE_TABLE_DIR1_SHFT 8
3813 #define SH_PI_OVER_RIDE_TABLE_DIR1_MASK 0x0000000000000f00
3815 /* SH_PI_OVER_RIDE_TABLE_V1 */
3816 /* Description: Low bit of virtual channel for next chip */
3817 #define SH_PI_OVER_RIDE_TABLE_V1_SHFT 12
3818 #define SH_PI_OVER_RIDE_TABLE_V1_MASK 0x0000000000001000
3820 /* SH_PI_OVER_RIDE_TABLE_NI_SEL1 */
3821 /* Description: ni select */
3822 #define SH_PI_OVER_RIDE_TABLE_NI_SEL1_SHFT 13
3823 #define SH_PI_OVER_RIDE_TABLE_NI_SEL1_MASK 0x0000000000002000
3825 /* SH_PI_OVER_RIDE_TABLE_ENABLE */
3826 /* Description: Indicates that this entry is enabled */
3827 #define SH_PI_OVER_RIDE_TABLE_ENABLE_SHFT 63
3828 #define SH_PI_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000
3830 /* ==================================================================== */
3831 /* Register "SH_PI_RSP_PLANE_HINT" */
3832 /* If enabled, invert incoming response only plane hint bit before lo */
3833 /* ==================================================================== */
3835 #define SH_PI_RSP_PLANE_HINT 0x0000000150021488
3836 #define SH_PI_RSP_PLANE_HINT_MASK 0x0000000000000001
3837 #define SH_PI_RSP_PLANE_HINT_INIT 0x0000000000000000
3839 /* SH_PI_RSP_PLANE_HINT_INVERT */
3840 /* Description: Invert Response Plane Hint */
3841 #define SH_PI_RSP_PLANE_HINT_INVERT_SHFT 0
3842 #define SH_PI_RSP_PLANE_HINT_INVERT_MASK 0x0000000000000001
3844 /* ==================================================================== */
3845 /* Register "SH_NI0_LOCAL_TABLE" */
3846 /* local lookup table */
3847 /* ==================================================================== */
3849 #define SH_NI0_LOCAL_TABLE 0x0000000150022000
3850 #define SH_NI0_LOCAL_TABLE_MASK 0x800000000000001f
3851 #define SH_NI0_LOCAL_TABLE_MEMDEPTH 128
3852 #define SH_NI0_LOCAL_TABLE_INIT 0x0000000000000000
3854 /* SH_NI0_LOCAL_TABLE_DIR0 */
3855 /* Description: Direction field for next chip */
3856 #define SH_NI0_LOCAL_TABLE_DIR0_SHFT 0
3857 #define SH_NI0_LOCAL_TABLE_DIR0_MASK 0x000000000000000f
3859 /* SH_NI0_LOCAL_TABLE_V0 */
3860 /* Description: Low bit of virtual channel for next chip */
3861 #define SH_NI0_LOCAL_TABLE_V0_SHFT 4
3862 #define SH_NI0_LOCAL_TABLE_V0_MASK 0x0000000000000010
3864 /* SH_NI0_LOCAL_TABLE_VALID */
3865 /* Description: Indicates that this entry is valid */
3866 #define SH_NI0_LOCAL_TABLE_VALID_SHFT 63
3867 #define SH_NI0_LOCAL_TABLE_VALID_MASK 0x8000000000000000
3869 /* ==================================================================== */
3870 /* Register "SH_NI0_GLOBAL_TABLE" */
3871 /* global lookup table */
3872 /* ==================================================================== */
3874 #define SH_NI0_GLOBAL_TABLE 0x0000000150022400
3875 #define SH_NI0_GLOBAL_TABLE_MASK 0x800000000000001f
3876 #define SH_NI0_GLOBAL_TABLE_MEMDEPTH 16
3877 #define SH_NI0_GLOBAL_TABLE_INIT 0x0000000000000000
3879 /* SH_NI0_GLOBAL_TABLE_DIR0 */
3880 /* Description: Direction field for next chip */
3881 #define SH_NI0_GLOBAL_TABLE_DIR0_SHFT 0
3882 #define SH_NI0_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f
3884 /* SH_NI0_GLOBAL_TABLE_V0 */
3885 /* Description: Low bit of virtual channel for next chip */
3886 #define SH_NI0_GLOBAL_TABLE_V0_SHFT 4
3887 #define SH_NI0_GLOBAL_TABLE_V0_MASK 0x0000000000000010
3889 /* SH_NI0_GLOBAL_TABLE_VALID */
3890 /* Description: Indicates that this entry is valid */
3891 #define SH_NI0_GLOBAL_TABLE_VALID_SHFT 63
3892 #define SH_NI0_GLOBAL_TABLE_VALID_MASK 0x8000000000000000
3894 /* ==================================================================== */
3895 /* Register "SH_NI0_OVER_RIDE_TABLE" */
3896 /* If enabled, bypass the Global/Local tables */
3897 /* ==================================================================== */
3899 #define SH_NI0_OVER_RIDE_TABLE 0x0000000150022480
3900 #define SH_NI0_OVER_RIDE_TABLE_MASK 0x800000000000001f
3901 #define SH_NI0_OVER_RIDE_TABLE_INIT 0x8000000000000000
3903 /* SH_NI0_OVER_RIDE_TABLE_DIR0 */
3904 /* Description: Direction field for next chip */
3905 #define SH_NI0_OVER_RIDE_TABLE_DIR0_SHFT 0
3906 #define SH_NI0_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f
3908 /* SH_NI0_OVER_RIDE_TABLE_V0 */
3909 /* Description: Low bit of virtual channel for next chip */
3910 #define SH_NI0_OVER_RIDE_TABLE_V0_SHFT 4
3911 #define SH_NI0_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010
3913 /* SH_NI0_OVER_RIDE_TABLE_ENABLE */
3914 /* Description: Indicates that this entry is enabled */
3915 #define SH_NI0_OVER_RIDE_TABLE_ENABLE_SHFT 63
3916 #define SH_NI0_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000
3918 /* ==================================================================== */
3919 /* Register "SH_NI0_RSP_PLANE_HINT" */
3920 /* If enabled, invert incoming response only plane hint bit before lo */
3921 /* ==================================================================== */
3923 #define SH_NI0_RSP_PLANE_HINT 0x0000000150022488
3924 #define SH_NI0_RSP_PLANE_HINT_MASK 0x0000000000000000
3925 #define SH_NI0_RSP_PLANE_HINT_INIT 0x0000000000000000
3927 /* ==================================================================== */
3928 /* Register "SH_NI1_LOCAL_TABLE" */
3929 /* local lookup table */
3930 /* ==================================================================== */
3932 #define SH_NI1_LOCAL_TABLE 0x0000000150023000
3933 #define SH_NI1_LOCAL_TABLE_MASK 0x800000000000001f
3934 #define SH_NI1_LOCAL_TABLE_MEMDEPTH 128
3935 #define SH_NI1_LOCAL_TABLE_INIT 0x0000000000000000
3937 /* SH_NI1_LOCAL_TABLE_DIR0 */
3938 /* Description: Direction field for next chip */
3939 #define SH_NI1_LOCAL_TABLE_DIR0_SHFT 0
3940 #define SH_NI1_LOCAL_TABLE_DIR0_MASK 0x000000000000000f
3942 /* SH_NI1_LOCAL_TABLE_V0 */
3943 /* Description: Low bit of virtual channel for next chip */
3944 #define SH_NI1_LOCAL_TABLE_V0_SHFT 4
3945 #define SH_NI1_LOCAL_TABLE_V0_MASK 0x0000000000000010
3947 /* SH_NI1_LOCAL_TABLE_VALID */
3948 /* Description: Indicates that this entry is valid */
3949 #define SH_NI1_LOCAL_TABLE_VALID_SHFT 63
3950 #define SH_NI1_LOCAL_TABLE_VALID_MASK 0x8000000000000000
3952 /* ==================================================================== */
3953 /* Register "SH_NI1_GLOBAL_TABLE" */
3954 /* global lookup table */
3955 /* ==================================================================== */
3957 #define SH_NI1_GLOBAL_TABLE 0x0000000150023400
3958 #define SH_NI1_GLOBAL_TABLE_MASK 0x800000000000001f
3959 #define SH_NI1_GLOBAL_TABLE_MEMDEPTH 16
3960 #define SH_NI1_GLOBAL_TABLE_INIT 0x0000000000000000
3962 /* SH_NI1_GLOBAL_TABLE_DIR0 */
3963 /* Description: Direction field for next chip */
3964 #define SH_NI1_GLOBAL_TABLE_DIR0_SHFT 0
3965 #define SH_NI1_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f
3967 /* SH_NI1_GLOBAL_TABLE_V0 */
3968 /* Description: Low bit of virtual channel for next chip */
3969 #define SH_NI1_GLOBAL_TABLE_V0_SHFT 4
3970 #define SH_NI1_GLOBAL_TABLE_V0_MASK 0x0000000000000010
3972 /* SH_NI1_GLOBAL_TABLE_VALID */
3973 /* Description: Indicates that this entry is valid */
3974 #define SH_NI1_GLOBAL_TABLE_VALID_SHFT 63
3975 #define SH_NI1_GLOBAL_TABLE_VALID_MASK 0x8000000000000000
3977 /* ==================================================================== */
3978 /* Register "SH_NI1_OVER_RIDE_TABLE" */
3979 /* If enabled, bypass the Global/Local tables */
3980 /* ==================================================================== */
3982 #define SH_NI1_OVER_RIDE_TABLE 0x0000000150023480
3983 #define SH_NI1_OVER_RIDE_TABLE_MASK 0x800000000000001f
3984 #define SH_NI1_OVER_RIDE_TABLE_INIT 0x8000000000000000
3986 /* SH_NI1_OVER_RIDE_TABLE_DIR0 */
3987 /* Description: Direction field for next chip */
3988 #define SH_NI1_OVER_RIDE_TABLE_DIR0_SHFT 0
3989 #define SH_NI1_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f
3991 /* SH_NI1_OVER_RIDE_TABLE_V0 */
3992 /* Description: Low bit of virtual channel for next chip */
3993 #define SH_NI1_OVER_RIDE_TABLE_V0_SHFT 4
3994 #define SH_NI1_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010
3996 /* SH_NI1_OVER_RIDE_TABLE_ENABLE */
3997 /* Description: Indicates that this entry is enabled */
3998 #define SH_NI1_OVER_RIDE_TABLE_ENABLE_SHFT 63
3999 #define SH_NI1_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000
4001 /* ==================================================================== */
4002 /* Register "SH_NI1_RSP_PLANE_HINT" */
4003 /* If enabled, invert incoming response only plane hint bit before lo */
4004 /* ==================================================================== */
4006 #define SH_NI1_RSP_PLANE_HINT 0x0000000150023488
4007 #define SH_NI1_RSP_PLANE_HINT_MASK 0x0000000000000000
4008 #define SH_NI1_RSP_PLANE_HINT_INIT 0x0000000000000000
4010 /* ==================================================================== */
4011 /* Register "SH_MD_LOCAL_TABLE" */
4012 /* local lookup table */
4013 /* ==================================================================== */
4015 #define SH_MD_LOCAL_TABLE 0x0000000150024000
4016 #define SH_MD_LOCAL_TABLE_MASK 0x8000000000003f3f
4017 #define SH_MD_LOCAL_TABLE_MEMDEPTH 128
4018 #define SH_MD_LOCAL_TABLE_INIT 0x0000000000000000
4020 /* SH_MD_LOCAL_TABLE_DIR0 */
4021 /* Description: Direction field for next chip */
4022 #define SH_MD_LOCAL_TABLE_DIR0_SHFT 0
4023 #define SH_MD_LOCAL_TABLE_DIR0_MASK 0x000000000000000f
4025 /* SH_MD_LOCAL_TABLE_V0 */
4026 /* Description: Low bit of virtual channel for next chip */
4027 #define SH_MD_LOCAL_TABLE_V0_SHFT 4
4028 #define SH_MD_LOCAL_TABLE_V0_MASK 0x0000000000000010
4030 /* SH_MD_LOCAL_TABLE_NI_SEL0 */
4031 /* Description: ni select for requests */
4032 #define SH_MD_LOCAL_TABLE_NI_SEL0_SHFT 5
4033 #define SH_MD_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020
4035 /* SH_MD_LOCAL_TABLE_DIR1 */
4036 #define SH_MD_LOCAL_TABLE_DIR1_SHFT 8
4037 #define SH_MD_LOCAL_TABLE_DIR1_MASK 0x0000000000000f00
4039 /* SH_MD_LOCAL_TABLE_V1 */
4040 /* Description: Low bit of virtual channel for next chip */
4041 #define SH_MD_LOCAL_TABLE_V1_SHFT 12
4042 #define SH_MD_LOCAL_TABLE_V1_MASK 0x0000000000001000
4044 /* SH_MD_LOCAL_TABLE_NI_SEL1 */
4045 /* Description: ni select for plane-hint 1 */
4046 #define SH_MD_LOCAL_TABLE_NI_SEL1_SHFT 13
4047 #define SH_MD_LOCAL_TABLE_NI_SEL1_MASK 0x0000000000002000
4049 /* SH_MD_LOCAL_TABLE_VALID */
4050 /* Description: Indicates that this entry is valid */
4051 #define SH_MD_LOCAL_TABLE_VALID_SHFT 63
4052 #define SH_MD_LOCAL_TABLE_VALID_MASK 0x8000000000000000
4054 /* ==================================================================== */
4055 /* Register "SH_MD_GLOBAL_TABLE" */
4056 /* global lookup table */
4057 /* ==================================================================== */
4059 #define SH_MD_GLOBAL_TABLE 0x0000000150024400
4060 #define SH_MD_GLOBAL_TABLE_MASK 0x8000000000003f3f
4061 #define SH_MD_GLOBAL_TABLE_MEMDEPTH 16
4062 #define SH_MD_GLOBAL_TABLE_INIT 0x0000000000000000
4064 /* SH_MD_GLOBAL_TABLE_DIR0 */
4065 /* Description: Direction field for next chip */
4066 #define SH_MD_GLOBAL_TABLE_DIR0_SHFT 0
4067 #define SH_MD_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f
4069 /* SH_MD_GLOBAL_TABLE_V0 */
4070 /* Description: Low bit of virtual channel for next chip */
4071 #define SH_MD_GLOBAL_TABLE_V0_SHFT 4
4072 #define SH_MD_GLOBAL_TABLE_V0_MASK 0x0000000000000010
4074 /* SH_MD_GLOBAL_TABLE_NI_SEL0 */
4075 /* Description: ni select for requests */
4076 #define SH_MD_GLOBAL_TABLE_NI_SEL0_SHFT 5
4077 #define SH_MD_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020
4079 /* SH_MD_GLOBAL_TABLE_DIR1 */
4080 #define SH_MD_GLOBAL_TABLE_DIR1_SHFT 8
4081 #define SH_MD_GLOBAL_TABLE_DIR1_MASK 0x0000000000000f00
4083 /* SH_MD_GLOBAL_TABLE_V1 */
4084 /* Description: Low bit of virtual channel for next chip */
4085 #define SH_MD_GLOBAL_TABLE_V1_SHFT 12
4086 #define SH_MD_GLOBAL_TABLE_V1_MASK 0x0000000000001000
4088 /* SH_MD_GLOBAL_TABLE_NI_SEL1 */
4089 /* Description: ni select for plane-hint 1 */
4090 #define SH_MD_GLOBAL_TABLE_NI_SEL1_SHFT 13
4091 #define SH_MD_GLOBAL_TABLE_NI_SEL1_MASK 0x0000000000002000
4093 /* SH_MD_GLOBAL_TABLE_VALID */
4094 /* Description: Indicates that this entry is valid */
4095 #define SH_MD_GLOBAL_TABLE_VALID_SHFT 63
4096 #define SH_MD_GLOBAL_TABLE_VALID_MASK 0x8000000000000000
4098 /* ==================================================================== */
4099 /* Register "SH_MD_OVER_RIDE_TABLE" */
4100 /* If enabled, bypass the Global/Local tables */
4101 /* ==================================================================== */
4103 #define SH_MD_OVER_RIDE_TABLE 0x0000000150024480
4104 #define SH_MD_OVER_RIDE_TABLE_MASK 0x8000000000003f3f
4105 #define SH_MD_OVER_RIDE_TABLE_INIT 0x8000000000002000
4107 /* SH_MD_OVER_RIDE_TABLE_DIR0 */
4108 /* Description: Direction field for next chip */
4109 #define SH_MD_OVER_RIDE_TABLE_DIR0_SHFT 0
4110 #define SH_MD_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f
4112 /* SH_MD_OVER_RIDE_TABLE_V0 */
4113 /* Description: Low bit of virtual channel for next chip */
4114 #define SH_MD_OVER_RIDE_TABLE_V0_SHFT 4
4115 #define SH_MD_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010
4117 /* SH_MD_OVER_RIDE_TABLE_NI_SEL0 */
4118 /* Description: ni select */
4119 #define SH_MD_OVER_RIDE_TABLE_NI_SEL0_SHFT 5
4120 #define SH_MD_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020
4122 /* SH_MD_OVER_RIDE_TABLE_DIR1 */
4123 #define SH_MD_OVER_RIDE_TABLE_DIR1_SHFT 8
4124 #define SH_MD_OVER_RIDE_TABLE_DIR1_MASK 0x0000000000000f00
4126 /* SH_MD_OVER_RIDE_TABLE_V1 */
4127 /* Description: Low bit of virtual channel for next chip */
4128 #define SH_MD_OVER_RIDE_TABLE_V1_SHFT 12
4129 #define SH_MD_OVER_RIDE_TABLE_V1_MASK 0x0000000000001000
4131 /* SH_MD_OVER_RIDE_TABLE_NI_SEL1 */
4132 /* Description: ni select */
4133 #define SH_MD_OVER_RIDE_TABLE_NI_SEL1_SHFT 13
4134 #define SH_MD_OVER_RIDE_TABLE_NI_SEL1_MASK 0x0000000000002000
4136 /* SH_MD_OVER_RIDE_TABLE_ENABLE */
4137 /* Description: Indicates that this entry is enabled */
4138 #define SH_MD_OVER_RIDE_TABLE_ENABLE_SHFT 63
4139 #define SH_MD_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000
4141 /* ==================================================================== */
4142 /* Register "SH_MD_RSP_PLANE_HINT" */
4143 /* If enabled, invert incoming response only plane hint bit before lo */
4144 /* ==================================================================== */
4146 #define SH_MD_RSP_PLANE_HINT 0x0000000150024488
4147 #define SH_MD_RSP_PLANE_HINT_MASK 0x0000000000000001
4148 #define SH_MD_RSP_PLANE_HINT_INIT 0x0000000000000000
4150 /* SH_MD_RSP_PLANE_HINT_INVERT */
4151 /* Description: Invert Response Plane Hint */
4152 #define SH_MD_RSP_PLANE_HINT_INVERT_SHFT 0
4153 #define SH_MD_RSP_PLANE_HINT_INVERT_MASK 0x0000000000000001
4155 /* ==================================================================== */
4156 /* Register "SH_LB_LIQ_CTL" */
4157 /* Local Block LIQ Control */
4158 /* ==================================================================== */
4160 #define SH_LB_LIQ_CTL 0x0000000110040000
4161 #define SH_LB_LIQ_CTL_MASK 0x0000000000070f1f
4162 #define SH_LB_LIQ_CTL_INIT 0x0000000000000000
4164 /* SH_LB_LIQ_CTL_LIQ_REQ_CTL */
4165 /* Description: LIQ Request Control */
4166 #define SH_LB_LIQ_CTL_LIQ_REQ_CTL_SHFT 0
4167 #define SH_LB_LIQ_CTL_LIQ_REQ_CTL_MASK 0x000000000000001f
4169 /* SH_LB_LIQ_CTL_LIQ_RPL_CTL */
4170 /* Description: LIQ Reply Control */
4171 #define SH_LB_LIQ_CTL_LIQ_RPL_CTL_SHFT 8
4172 #define SH_LB_LIQ_CTL_LIQ_RPL_CTL_MASK 0x0000000000000f00
4174 /* SH_LB_LIQ_CTL_FORCE_RQ_CREDIT */
4175 /* Description: Force request credit */
4176 #define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_SHFT 16
4177 #define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_MASK 0x0000000000010000
4179 /* SH_LB_LIQ_CTL_FORCE_RP_CREDIT */
4180 /* Description: Force reply credit */
4181 #define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_SHFT 17
4182 #define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_MASK 0x0000000000020000
4184 /* SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT */
4185 /* Description: Force linvv credit */
4186 #define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_SHFT 18
4187 #define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_MASK 0x0000000000040000
4189 /* ==================================================================== */
4190 /* Register "SH_LB_LOQ_CTL" */
4191 /* Local Block LOQ Control */
4192 /* ==================================================================== */
4194 #define SH_LB_LOQ_CTL 0x0000000110040080
4195 #define SH_LB_LOQ_CTL_MASK 0x0000000000000003
4196 #define SH_LB_LOQ_CTL_INIT 0x0000000000000000
4198 /* SH_LB_LOQ_CTL_LOQ_REQ_CTL */
4199 /* Description: LOQ Request Control */
4200 #define SH_LB_LOQ_CTL_LOQ_REQ_CTL_SHFT 0
4201 #define SH_LB_LOQ_CTL_LOQ_REQ_CTL_MASK 0x0000000000000001
4203 /* SH_LB_LOQ_CTL_LOQ_RPL_CTL */
4204 /* Description: LOQ Reply Control */
4205 #define SH_LB_LOQ_CTL_LOQ_RPL_CTL_SHFT 1
4206 #define SH_LB_LOQ_CTL_LOQ_RPL_CTL_MASK 0x0000000000000002
4208 /* ==================================================================== */
4209 /* Register "SH_LB_MAX_REP_CREDIT_CNT" */
4210 /* Maximum number of reply credits from XN */
4211 /* ==================================================================== */
4213 #define SH_LB_MAX_REP_CREDIT_CNT 0x0000000110040100
4214 #define SH_LB_MAX_REP_CREDIT_CNT_MASK 0x000000000000001f
4215 #define SH_LB_MAX_REP_CREDIT_CNT_INIT 0x000000000000001f
4217 /* SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT */
4218 /* Description: Max reply credits */
4219 #define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_SHFT 0
4220 #define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_MASK 0x000000000000001f
4222 /* ==================================================================== */
4223 /* Register "SH_LB_MAX_REQ_CREDIT_CNT" */
4224 /* Maximum number of request credits from XN */
4225 /* ==================================================================== */
4227 #define SH_LB_MAX_REQ_CREDIT_CNT 0x0000000110040180
4228 #define SH_LB_MAX_REQ_CREDIT_CNT_MASK 0x000000000000001f
4229 #define SH_LB_MAX_REQ_CREDIT_CNT_INIT 0x000000000000001f
4231 /* SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT */
4232 /* Description: Max request credits */
4233 #define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_SHFT 0
4234 #define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_MASK 0x000000000000001f
4236 /* ==================================================================== */
4237 /* Register "SH_PIO_TIME_OUT" */
4238 /* Local Block PIO time out value */
4239 /* ==================================================================== */
4241 #define SH_PIO_TIME_OUT 0x0000000110040200
4242 #define SH_PIO_TIME_OUT_MASK 0x000000000000ffff
4243 #define SH_PIO_TIME_OUT_INIT 0x0000000000000400
4245 /* SH_PIO_TIME_OUT_VALUE */
4246 /* Description: PIO time out value */
4247 #define SH_PIO_TIME_OUT_VALUE_SHFT 0
4248 #define SH_PIO_TIME_OUT_VALUE_MASK 0x000000000000ffff
4250 /* ==================================================================== */
4251 /* Register "SH_PIO_NACK_RESET" */
4252 /* Local Block PIO Reset for nack counters */
4253 /* ==================================================================== */
4255 #define SH_PIO_NACK_RESET 0x0000000110040280
4256 #define SH_PIO_NACK_RESET_MASK 0x0000000000000001
4257 #define SH_PIO_NACK_RESET_INIT 0x0000000000000000
4259 /* SH_PIO_NACK_RESET_PULSE */
4260 /* Description: PIO nack counter reset */
4261 #define SH_PIO_NACK_RESET_PULSE_SHFT 0
4262 #define SH_PIO_NACK_RESET_PULSE_MASK 0x0000000000000001
4264 /* ==================================================================== */
4265 /* Register "SH_CONVEYOR_BELT_TIME_OUT" */
4266 /* Local Block conveyor belt time out value */
4267 /* ==================================================================== */
4269 #define SH_CONVEYOR_BELT_TIME_OUT 0x0000000110040300
4270 #define SH_CONVEYOR_BELT_TIME_OUT_MASK 0x0000000000000fff
4271 #define SH_CONVEYOR_BELT_TIME_OUT_INIT 0x0000000000000000
4273 /* SH_CONVEYOR_BELT_TIME_OUT_VALUE */
4274 /* Description: Conveyor belt time out value */
4275 #define SH_CONVEYOR_BELT_TIME_OUT_VALUE_SHFT 0
4276 #define SH_CONVEYOR_BELT_TIME_OUT_VALUE_MASK 0x0000000000000fff
4278 /* ==================================================================== */
4279 /* Register "SH_LB_CREDIT_STATUS" */
4280 /* Credit Counter Status Register */
4281 /* ==================================================================== */
4283 #define SH_LB_CREDIT_STATUS 0x0000000110050000
4284 #define SH_LB_CREDIT_STATUS_MASK 0x000000000ffff3df
4285 #define SH_LB_CREDIT_STATUS_INIT 0x0000000000000000
4287 /* SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT */
4288 /* Description: LIQ request queue credit counter */
4289 #define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_SHFT 0
4290 #define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_MASK 0x000000000000001f
4292 /* SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT */
4293 /* Description: LIQ reply queue credit counter */
4294 #define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_SHFT 6
4295 #define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_MASK 0x00000000000003c0
4297 /* SH_LB_CREDIT_STATUS_LINVV_CREDIT */
4298 /* Description: LINVV credit counter */
4299 #define SH_LB_CREDIT_STATUS_LINVV_CREDIT_SHFT 12
4300 #define SH_LB_CREDIT_STATUS_LINVV_CREDIT_MASK 0x000000000003f000
4302 /* SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT */
4303 /* Description: LOQ request queue credit counter */
4304 #define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_SHFT 18
4305 #define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_MASK 0x00000000007c0000
4307 /* SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT */
4308 /* Description: LOQ reply queue credit counter */
4309 #define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_SHFT 23
4310 #define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_MASK 0x000000000f800000
4312 /* ==================================================================== */
4313 /* Register "SH_LB_DEBUG_LOCAL_SEL" */
4314 /* LB Debug Port Select */
4315 /* ==================================================================== */
4317 #define SH_LB_DEBUG_LOCAL_SEL 0x0000000110050080
4318 #define SH_LB_DEBUG_LOCAL_SEL_MASK 0xf777777777777777
4319 #define SH_LB_DEBUG_LOCAL_SEL_INIT 0x0000000000000000
4321 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL */
4322 /* Description: Nibble 0 Chiplet select */
4323 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0
4324 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
4326 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL */
4327 /* Description: Nibble 0 Nibble select */
4328 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
4329 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
4331 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL */
4332 /* Description: Nibble 1 Chiplet select */
4333 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8
4334 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
4336 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL */
4337 /* Description: Nibble 1 Nibble select */
4338 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
4339 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
4341 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL */
4342 /* Description: Nibble 2 Chiplet select */
4343 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16
4344 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
4346 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL */
4347 /* Description: Nibble 2 Nibble select */
4348 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
4349 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
4351 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL */
4352 /* Description: Nibble 3 Chiplet select */
4353 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24
4354 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
4356 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL */
4357 /* Description: Nibble 3 Nibble select */
4358 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
4359 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
4361 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL */
4362 /* Description: Nibble 4 Chiplet select */
4363 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32
4364 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
4366 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL */
4367 /* Description: Nibble 4 Nibble select */
4368 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
4369 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
4371 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL */
4372 /* Description: Nibble 5 Chiplet select */
4373 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40
4374 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
4376 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL */
4377 /* Description: Nibble 5 Nibble select */
4378 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
4379 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
4381 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL */
4382 /* Description: Nibble 6 Chiplet select */
4383 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48
4384 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
4386 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL */
4387 /* Description: Nibble 6 Nibble select */
4388 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
4389 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
4391 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL */
4392 /* Description: Nibble 7 Chiplet select */
4393 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56
4394 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
4396 /* SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL */
4397 /* Description: Nibble 7 Nibble select */
4398 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
4399 #define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
4401 /* SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE */
4402 /* Description: Enable trigger on bit 32 of Analyzer data */
4403 #define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_SHFT 63
4404 #define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_MASK 0x8000000000000000
4406 /* ==================================================================== */
4407 /* Register "SH_LB_DEBUG_PERF_SEL" */
4408 /* LB Debug Port Performance Select */
4409 /* ==================================================================== */
4411 #define SH_LB_DEBUG_PERF_SEL 0x0000000110050100
4412 #define SH_LB_DEBUG_PERF_SEL_MASK 0x7777777777777777
4413 #define SH_LB_DEBUG_PERF_SEL_INIT 0x0000000000000000
4415 /* SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL */
4416 /* Description: Nibble 0 Chiplet select */
4417 #define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0
4418 #define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
4420 /* SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL */
4421 /* Description: Nibble 0 Nibble select */
4422 #define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
4423 #define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
4425 /* SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL */
4426 /* Description: Nibble 1 Chiplet select */
4427 #define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8
4428 #define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
4430 /* SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL */
4431 /* Description: Nibble 1 Nibble select */
4432 #define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
4433 #define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
4435 /* SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL */
4436 /* Description: Nibble 2 Chiplet select */
4437 #define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16
4438 #define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
4440 /* SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL */
4441 /* Description: Nibble 2 Nibble select */
4442 #define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
4443 #define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
4445 /* SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL */
4446 /* Description: Nibble 3 Chiplet select */
4447 #define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24
4448 #define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
4450 /* SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL */
4451 /* Description: Nibble 3 Nibble select */
4452 #define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
4453 #define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
4455 /* SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL */
4456 /* Description: Nibble 4 Chiplet select */
4457 #define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32
4458 #define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
4460 /* SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL */
4461 /* Description: Nibble 4 Nibble select */
4462 #define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
4463 #define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
4465 /* SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL */
4466 /* Description: Nibble 5 Chiplet select */
4467 #define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40
4468 #define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
4470 /* SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL */
4471 /* Description: Nibble 5 Nibble select */
4472 #define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
4473 #define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
4475 /* SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL */
4476 /* Description: Nibble 6 Chiplet select */
4477 #define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48
4478 #define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
4480 /* SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL */
4481 /* Description: Nibble 6 Nibble select */
4482 #define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
4483 #define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
4485 /* SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL */
4486 /* Description: Nibble 7 Chiplet select */
4487 #define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56
4488 #define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
4490 /* SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL */
4491 /* Description: Nibble 7 Nibble select */
4492 #define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
4493 #define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
4495 /* ==================================================================== */
4496 /* Register "SH_LB_DEBUG_TRIG_SEL" */
4497 /* LB Debug Trigger Select */
4498 /* ==================================================================== */
4500 #define SH_LB_DEBUG_TRIG_SEL 0x0000000110050180
4501 #define SH_LB_DEBUG_TRIG_SEL_MASK 0x7777777777777777
4502 #define SH_LB_DEBUG_TRIG_SEL_INIT 0x0000000000000000
4504 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL */
4505 /* Description: Nibble 0 Chiplet select */
4506 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_SHFT 0
4507 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
4509 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL */
4510 /* Description: Nibble 0 Nibble select */
4511 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4
4512 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
4514 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL */
4515 /* Description: Nibble 1 Chiplet select */
4516 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_SHFT 8
4517 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
4519 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL */
4520 /* Description: Nibble 1 Nibble select */
4521 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12
4522 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
4524 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL */
4525 /* Description: Nibble 2 Chiplet select */
4526 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_SHFT 16
4527 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
4529 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL */
4530 /* Description: Nibble 2 Nibble select */
4531 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20
4532 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
4534 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL */
4535 /* Description: Nibble 3 Chiplet select */
4536 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_SHFT 24
4537 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
4539 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL */
4540 /* Description: Nibble 3 Nibble select */
4541 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28
4542 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
4544 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL */
4545 /* Description: Nibble 4 Chiplet select */
4546 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_SHFT 32
4547 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
4549 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL */
4550 /* Description: Nibble 4 Nibble select */
4551 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36
4552 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
4554 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL */
4555 /* Description: Nibble 5 Chiplet select */
4556 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_SHFT 40
4557 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
4559 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL */
4560 /* Description: Nibble 5 Nibble select */
4561 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44
4562 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
4564 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL */
4565 /* Description: Nibble 6 Chiplet select */
4566 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_SHFT 48
4567 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
4569 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL */
4570 /* Description: Nibble 6 Nibble select */
4571 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52
4572 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
4574 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL */
4575 /* Description: Nibble 7 Chiplet select */
4576 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_SHFT 56
4577 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
4579 /* SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL */
4580 /* Description: Nibble 7 Nibble select */
4581 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60
4582 #define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
4584 /* ==================================================================== */
4585 /* Register "SH_LB_ERROR_DETAIL_1" */
4586 /* LB Error capture information: HDR1 */
4587 /* ==================================================================== */
4589 #define SH_LB_ERROR_DETAIL_1 0x0000000110050200
4590 #define SH_LB_ERROR_DETAIL_1_MASK 0x8003073fff3fffff
4591 #define SH_LB_ERROR_DETAIL_1_INIT 0x0000000000000000
4593 /* SH_LB_ERROR_DETAIL_1_COMMAND */
4594 /* Description: COMMAND */
4595 #define SH_LB_ERROR_DETAIL_1_COMMAND_SHFT 0
4596 #define SH_LB_ERROR_DETAIL_1_COMMAND_MASK 0x00000000000000ff
4598 /* SH_LB_ERROR_DETAIL_1_SUPPL */
4599 /* Description: SUPPLMENTAL */
4600 #define SH_LB_ERROR_DETAIL_1_SUPPL_SHFT 8
4601 #define SH_LB_ERROR_DETAIL_1_SUPPL_MASK 0x00000000003fff00
4603 /* SH_LB_ERROR_DETAIL_1_SOURCE */
4604 /* Description: SOURCE */
4605 #define SH_LB_ERROR_DETAIL_1_SOURCE_SHFT 24
4606 #define SH_LB_ERROR_DETAIL_1_SOURCE_MASK 0x0000003fff000000
4608 /* SH_LB_ERROR_DETAIL_1_DEST */
4609 /* Description: DEST */
4610 #define SH_LB_ERROR_DETAIL_1_DEST_SHFT 40
4611 #define SH_LB_ERROR_DETAIL_1_DEST_MASK 0x0000070000000000
4613 /* SH_LB_ERROR_DETAIL_1_HDR_ERR */
4614 /* Description: HDR_ERR */
4615 #define SH_LB_ERROR_DETAIL_1_HDR_ERR_SHFT 48
4616 #define SH_LB_ERROR_DETAIL_1_HDR_ERR_MASK 0x0001000000000000
4618 /* SH_LB_ERROR_DETAIL_1_DATA_ERR */
4619 /* Description: DATA_ERR */
4620 #define SH_LB_ERROR_DETAIL_1_DATA_ERR_SHFT 49
4621 #define SH_LB_ERROR_DETAIL_1_DATA_ERR_MASK 0x0002000000000000
4623 /* SH_LB_ERROR_DETAIL_1_VALID */
4624 /* Description: VALID */
4625 #define SH_LB_ERROR_DETAIL_1_VALID_SHFT 63
4626 #define SH_LB_ERROR_DETAIL_1_VALID_MASK 0x8000000000000000
4628 /* ==================================================================== */
4629 /* Register "SH_LB_ERROR_DETAIL_2" */
4631 /* ==================================================================== */
4633 #define SH_LB_ERROR_DETAIL_2 0x0000000110050280
4634 #define SH_LB_ERROR_DETAIL_2_MASK 0x00007fffffffffff
4635 #define SH_LB_ERROR_DETAIL_2_INIT 0x0000000000000000
4637 /* SH_LB_ERROR_DETAIL_2_ADDRESS */
4638 /* Description: ADDRESS */
4639 #define SH_LB_ERROR_DETAIL_2_ADDRESS_SHFT 0
4640 #define SH_LB_ERROR_DETAIL_2_ADDRESS_MASK 0x00007fffffffffff
4642 /* ==================================================================== */
4643 /* Register "SH_LB_ERROR_DETAIL_3" */
4645 /* ==================================================================== */
4647 #define SH_LB_ERROR_DETAIL_3 0x0000000110050300
4648 #define SH_LB_ERROR_DETAIL_3_MASK 0xffffffffffffffff
4649 #define SH_LB_ERROR_DETAIL_3_INIT 0x0000000000000000
4651 /* SH_LB_ERROR_DETAIL_3_DATA */
4652 /* Description: DATA */
4653 #define SH_LB_ERROR_DETAIL_3_DATA_SHFT 0
4654 #define SH_LB_ERROR_DETAIL_3_DATA_MASK 0xffffffffffffffff
4656 /* ==================================================================== */
4657 /* Register "SH_LB_ERROR_DETAIL_4" */
4659 /* ==================================================================== */
4661 #define SH_LB_ERROR_DETAIL_4 0x0000000110050380
4662 #define SH_LB_ERROR_DETAIL_4_MASK 0xffffffffffffffff
4663 #define SH_LB_ERROR_DETAIL_4_INIT 0x0000000000000000
4665 /* SH_LB_ERROR_DETAIL_4_ROUTE */
4666 /* Description: ROUTE */
4667 #define SH_LB_ERROR_DETAIL_4_ROUTE_SHFT 0
4668 #define SH_LB_ERROR_DETAIL_4_ROUTE_MASK 0xffffffffffffffff
4670 /* ==================================================================== */
4671 /* Register "SH_LB_ERROR_DETAIL_5" */
4673 /* ==================================================================== */
4675 #define SH_LB_ERROR_DETAIL_5 0x0000000110050400
4676 #define SH_LB_ERROR_DETAIL_5_MASK 0x000000000000007f
4677 #define SH_LB_ERROR_DETAIL_5_INIT 0x0000000000000000
4679 /* SH_LB_ERROR_DETAIL_5_READ_RETRY */
4680 /* Description: Read retry error */
4681 #define SH_LB_ERROR_DETAIL_5_READ_RETRY_SHFT 0
4682 #define SH_LB_ERROR_DETAIL_5_READ_RETRY_MASK 0x0000000000000001
4684 /* SH_LB_ERROR_DETAIL_5_PTC1_WRITE */
4685 /* Description: PTC1 write error */
4686 #define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_SHFT 1
4687 #define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_MASK 0x0000000000000002
4689 /* SH_LB_ERROR_DETAIL_5_WRITE_RETRY */
4690 /* Description: Write retry error */
4691 #define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_SHFT 2
4692 #define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_MASK 0x0000000000000004
4694 /* SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW */
4695 /* Description: Nack A counter overflow error */
4696 #define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_SHFT 3
4697 #define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_MASK 0x0000000000000008
4699 /* SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW */
4700 /* Description: Nack B counter overflow error */
4701 #define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_SHFT 4
4702 #define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_MASK 0x0000000000000010
4704 /* SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT */
4705 /* Description: Nack A counter timeout error */
4706 #define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_SHFT 5
4707 #define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_MASK 0x0000000000000020
4709 /* SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT */
4710 /* Description: Nack B counter timeout error */
4711 #define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_SHFT 6
4712 #define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_MASK 0x0000000000000040
4714 /* ==================================================================== */
4715 /* Register "SH_LB_ERROR_MASK" */
4717 /* ==================================================================== */
4719 #define SH_LB_ERROR_MASK 0x0000000110050480
4720 #define SH_LB_ERROR_MASK_MASK 0x00000000007fffff
4721 #define SH_LB_ERROR_MASK_INIT 0x00000000007fffff
4723 /* SH_LB_ERROR_MASK_RQ_BAD_CMD */
4724 /* Description: RQ_BAD_CMD */
4725 #define SH_LB_ERROR_MASK_RQ_BAD_CMD_SHFT 0
4726 #define SH_LB_ERROR_MASK_RQ_BAD_CMD_MASK 0x0000000000000001
4728 /* SH_LB_ERROR_MASK_RP_BAD_CMD */
4729 /* Description: RP_BAD_CMD */
4730 #define SH_LB_ERROR_MASK_RP_BAD_CMD_SHFT 1
4731 #define SH_LB_ERROR_MASK_RP_BAD_CMD_MASK 0x0000000000000002
4733 /* SH_LB_ERROR_MASK_RQ_SHORT */
4734 /* Description: RQ_SHORT */
4735 #define SH_LB_ERROR_MASK_RQ_SHORT_SHFT 2
4736 #define SH_LB_ERROR_MASK_RQ_SHORT_MASK 0x0000000000000004
4738 /* SH_LB_ERROR_MASK_RP_SHORT */
4739 /* Description: RP_SHORT */
4740 #define SH_LB_ERROR_MASK_RP_SHORT_SHFT 3
4741 #define SH_LB_ERROR_MASK_RP_SHORT_MASK 0x0000000000000008
4743 /* SH_LB_ERROR_MASK_RQ_LONG */
4744 /* Description: RQ_LONG */
4745 #define SH_LB_ERROR_MASK_RQ_LONG_SHFT 4
4746 #define SH_LB_ERROR_MASK_RQ_LONG_MASK 0x0000000000000010
4748 /* SH_LB_ERROR_MASK_RP_LONG */
4749 /* Description: RP_LONG */
4750 #define SH_LB_ERROR_MASK_RP_LONG_SHFT 5
4751 #define SH_LB_ERROR_MASK_RP_LONG_MASK 0x0000000000000020
4753 /* SH_LB_ERROR_MASK_RQ_BAD_DATA */
4754 /* Description: RQ_BAD_DATA */
4755 #define SH_LB_ERROR_MASK_RQ_BAD_DATA_SHFT 6
4756 #define SH_LB_ERROR_MASK_RQ_BAD_DATA_MASK 0x0000000000000040
4758 /* SH_LB_ERROR_MASK_RP_BAD_DATA */
4759 /* Description: RP_BAD_DATA */
4760 #define SH_LB_ERROR_MASK_RP_BAD_DATA_SHFT 7
4761 #define SH_LB_ERROR_MASK_RP_BAD_DATA_MASK 0x0000000000000080
4763 /* SH_LB_ERROR_MASK_RQ_BAD_ADDR */
4764 /* Description: RQ_BAD_ADDR */
4765 #define SH_LB_ERROR_MASK_RQ_BAD_ADDR_SHFT 8
4766 #define SH_LB_ERROR_MASK_RQ_BAD_ADDR_MASK 0x0000000000000100
4768 /* SH_LB_ERROR_MASK_RQ_TIME_OUT */
4769 /* Description: RQ_TIME_OUT */
4770 #define SH_LB_ERROR_MASK_RQ_TIME_OUT_SHFT 9
4771 #define SH_LB_ERROR_MASK_RQ_TIME_OUT_MASK 0x0000000000000200
4773 /* SH_LB_ERROR_MASK_LINVV_OVERFLOW */
4774 /* Description: LINVV_OVERFLOW */
4775 #define SH_LB_ERROR_MASK_LINVV_OVERFLOW_SHFT 10
4776 #define SH_LB_ERROR_MASK_LINVV_OVERFLOW_MASK 0x0000000000000400
4778 /* SH_LB_ERROR_MASK_UNEXPECTED_LINV */
4779 /* Description: UNEXPECTED_LINV */
4780 #define SH_LB_ERROR_MASK_UNEXPECTED_LINV_SHFT 11
4781 #define SH_LB_ERROR_MASK_UNEXPECTED_LINV_MASK 0x0000000000000800
4783 /* SH_LB_ERROR_MASK_PTC_1_TIMEOUT */
4784 /* Description: PTC_1 Time out */
4785 #define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_SHFT 12
4786 #define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_MASK 0x0000000000001000
4788 /* SH_LB_ERROR_MASK_JUNK_BUS_ERR */
4789 /* Description: Junk Bus error */
4790 #define SH_LB_ERROR_MASK_JUNK_BUS_ERR_SHFT 13
4791 #define SH_LB_ERROR_MASK_JUNK_BUS_ERR_MASK 0x0000000000002000
4793 /* SH_LB_ERROR_MASK_PIO_CB_ERR */
4794 /* Description: PIO Conveyor Belt operation error */
4795 #define SH_LB_ERROR_MASK_PIO_CB_ERR_SHFT 14
4796 #define SH_LB_ERROR_MASK_PIO_CB_ERR_MASK 0x0000000000004000
4798 /* SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR */
4799 /* Description: Vector request Route data was invalid */
4800 #define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_SHFT 15
4801 #define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000
4803 /* SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR */
4804 /* Description: Vector reply Route data was invalid */
4805 #define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_SHFT 16
4806 #define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000
4808 /* SH_LB_ERROR_MASK_GCLK_DROP */
4809 /* Description: Gclk drop error */
4810 #define SH_LB_ERROR_MASK_GCLK_DROP_SHFT 17
4811 #define SH_LB_ERROR_MASK_GCLK_DROP_MASK 0x0000000000020000
4813 /* SH_LB_ERROR_MASK_RQ_FIFO_ERROR */
4814 /* Description: Request queue FIFO error */
4815 #define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_SHFT 18
4816 #define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_MASK 0x0000000000040000
4818 /* SH_LB_ERROR_MASK_RP_FIFO_ERROR */
4819 /* Description: Reply queue FIFO error */
4820 #define SH_LB_ERROR_MASK_RP_FIFO_ERROR_SHFT 19
4821 #define SH_LB_ERROR_MASK_RP_FIFO_ERROR_MASK 0x0000000000080000
4823 /* SH_LB_ERROR_MASK_UNEXP_VALID */
4824 /* Description: Unexpected valid error */
4825 #define SH_LB_ERROR_MASK_UNEXP_VALID_SHFT 20
4826 #define SH_LB_ERROR_MASK_UNEXP_VALID_MASK 0x0000000000100000
4828 /* SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW */
4829 /* Description: Request queue credit overflow */
4830 #define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_SHFT 21
4831 #define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000
4833 /* SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW */
4834 /* Description: Reply queue credit overflow */
4835 #define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_SHFT 22
4836 #define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000
4838 /* ==================================================================== */
4839 /* Register "SH_LB_ERROR_OVERFLOW" */
4840 /* LB Error Overflow */
4841 /* ==================================================================== */
4843 #define SH_LB_ERROR_OVERFLOW 0x0000000110050500
4844 #define SH_LB_ERROR_OVERFLOW_MASK 0x00000000007fffff
4845 #define SH_LB_ERROR_OVERFLOW_INIT 0x0000000000000000
4847 /* SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL */
4848 /* Description: RQ_BAD_CMD_OVRFL */
4849 #define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_SHFT 0
4850 #define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_MASK 0x0000000000000001
4852 /* SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL */
4853 /* Description: RP_BAD_CMD_OVRFL */
4854 #define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_SHFT 1
4855 #define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_MASK 0x0000000000000002
4857 /* SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL */
4858 /* Description: RQ_SHORT_OVRFL */
4859 #define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_SHFT 2
4860 #define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_MASK 0x0000000000000004
4862 /* SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL */
4863 /* Description: RP_SHORT_OVRFL */
4864 #define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_SHFT 3
4865 #define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_MASK 0x0000000000000008
4867 /* SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL */
4868 /* Description: RQ_LONG_OVRFL */
4869 #define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_SHFT 4
4870 #define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_MASK 0x0000000000000010
4872 /* SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL */
4873 /* Description: RP_LONG_OVRFL */
4874 #define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_SHFT 5
4875 #define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_MASK 0x0000000000000020
4877 /* SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL */
4878 /* Description: RQ_BAD_DATA_OVRFL */
4879 #define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_SHFT 6
4880 #define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_MASK 0x0000000000000040
4882 /* SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL */
4883 /* Description: RP_BAD_DATA_OVRFL */
4884 #define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_SHFT 7
4885 #define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_MASK 0x0000000000000080
4887 /* SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL */
4888 /* Description: RQ_BAD_ADDR_OVRFL */
4889 #define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_SHFT 8
4890 #define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_MASK 0x0000000000000100
4892 /* SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL */
4893 /* Description: RQ_TIME_OUT_OVRFL */
4894 #define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_SHFT 9
4895 #define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_MASK 0x0000000000000200
4897 /* SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL */
4898 /* Description: LINVV_OVERFLOW_OVRFL */
4899 #define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_SHFT 10
4900 #define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_MASK 0x0000000000000400
4902 /* SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL */
4903 /* Description: UNEXPECTED_LINV_OVRFL */
4904 #define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_SHFT 11
4905 #define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_MASK 0x0000000000000800
4907 /* SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL */
4908 /* Description: PTC_1 Time out overflow */
4909 #define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_SHFT 12
4910 #define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_MASK 0x0000000000001000
4912 /* SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL */
4913 /* Description: Junk Bus error overflow */
4914 #define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_SHFT 13
4915 #define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_MASK 0x0000000000002000
4917 /* SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL */
4918 /* Description: PIO Conveyor Belt operation error overflow */
4919 #define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_SHFT 14
4920 #define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_MASK 0x0000000000004000
4922 /* SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL */
4923 /* Description: Vector request Route data was invalid overflow */
4924 #define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_SHFT 15
4925 #define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_MASK 0x0000000000008000
4927 /* SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL */
4928 /* Description: Vector reply Route data was invalid overflow */
4929 #define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_SHFT 16
4930 #define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_MASK 0x0000000000010000
4932 /* SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL */
4933 /* Description: Gclk drop error overflow */
4934 #define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_SHFT 17
4935 #define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_MASK 0x0000000000020000
4937 /* SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL */
4938 /* Description: Request queue FIFO error overflow */
4939 #define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_SHFT 18
4940 #define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_MASK 0x0000000000040000
4942 /* SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL */
4943 /* Description: Reply queue FIFO error overflow */
4944 #define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_SHFT 19
4945 #define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_MASK 0x0000000000080000
4947 /* SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL */
4948 /* Description: Unexpected valid error overflow */
4949 #define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_SHFT 20
4950 #define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_MASK 0x0000000000100000
4952 /* SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL */
4953 /* Description: Request queue credit overflow */
4954 #define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_SHFT 21
4955 #define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000200000
4957 /* SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL */
4958 /* Description: Reply queue credit overflow */
4959 #define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_SHFT 22
4960 #define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000400000
4962 /* ==================================================================== */
4963 /* Register "SH_LB_ERROR_OVERFLOW_ALIAS" */
4964 /* LB Error Overflow */
4965 /* ==================================================================== */
4967 #define SH_LB_ERROR_OVERFLOW_ALIAS 0x0000000110050508
4969 /* ==================================================================== */
4970 /* Register "SH_LB_ERROR_SUMMARY" */
4972 /* ==================================================================== */
4974 #define SH_LB_ERROR_SUMMARY 0x0000000110050580
4975 #define SH_LB_ERROR_SUMMARY_MASK 0x00000000007fffff
4976 #define SH_LB_ERROR_SUMMARY_INIT 0x0000000000000000
4978 /* SH_LB_ERROR_SUMMARY_RQ_BAD_CMD */
4979 /* Description: RQ_BAD_CMD */
4980 #define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_SHFT 0
4981 #define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_MASK 0x0000000000000001
4983 /* SH_LB_ERROR_SUMMARY_RP_BAD_CMD */
4984 /* Description: RP_BAD_CMD */
4985 #define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_SHFT 1
4986 #define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_MASK 0x0000000000000002
4988 /* SH_LB_ERROR_SUMMARY_RQ_SHORT */
4989 /* Description: RQ_SHORT */
4990 #define SH_LB_ERROR_SUMMARY_RQ_SHORT_SHFT 2
4991 #define SH_LB_ERROR_SUMMARY_RQ_SHORT_MASK 0x0000000000000004
4993 /* SH_LB_ERROR_SUMMARY_RP_SHORT */
4994 /* Description: RP_SHORT */
4995 #define SH_LB_ERROR_SUMMARY_RP_SHORT_SHFT 3
4996 #define SH_LB_ERROR_SUMMARY_RP_SHORT_MASK 0x0000000000000008
4998 /* SH_LB_ERROR_SUMMARY_RQ_LONG */
4999 /* Description: RQ_LONG */
5000 #define SH_LB_ERROR_SUMMARY_RQ_LONG_SHFT 4
5001 #define SH_LB_ERROR_SUMMARY_RQ_LONG_MASK 0x0000000000000010
5003 /* SH_LB_ERROR_SUMMARY_RP_LONG */
5004 /* Description: RP_LONG */
5005 #define SH_LB_ERROR_SUMMARY_RP_LONG_SHFT 5
5006 #define SH_LB_ERROR_SUMMARY_RP_LONG_MASK 0x0000000000000020
5008 /* SH_LB_ERROR_SUMMARY_RQ_BAD_DATA */
5009 /* Description: RQ_BAD_DATA */
5010 #define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_SHFT 6
5011 #define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_MASK 0x0000000000000040
5013 /* SH_LB_ERROR_SUMMARY_RP_BAD_DATA */
5014 /* Description: RP_BAD_DATA */
5015 #define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_SHFT 7
5016 #define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_MASK 0x0000000000000080
5018 /* SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR */
5019 /* Description: RQ_BAD_ADDR */
5020 #define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_SHFT 8
5021 #define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_MASK 0x0000000000000100
5023 /* SH_LB_ERROR_SUMMARY_RQ_TIME_OUT */
5024 /* Description: RQ_TIME_OUT */
5025 #define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_SHFT 9
5026 #define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_MASK 0x0000000000000200
5028 /* SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW */
5029 /* Description: LINVV_OVERFLOW */
5030 #define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_SHFT 10
5031 #define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_MASK 0x0000000000000400
5033 /* SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV */
5034 /* Description: UNEXPECTED_LINV */
5035 #define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_SHFT 11
5036 #define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_MASK 0x0000000000000800
5038 /* SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT */
5039 /* Description: PTC_1 Time out */
5040 #define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_SHFT 12
5041 #define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_MASK 0x0000000000001000
5043 /* SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR */
5044 /* Description: Junk Bus error */
5045 #define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_SHFT 13
5046 #define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_MASK 0x0000000000002000
5048 /* SH_LB_ERROR_SUMMARY_PIO_CB_ERR */
5049 /* Description: PIO Conveyor Belt operation error */
5050 #define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_SHFT 14
5051 #define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_MASK 0x0000000000004000
5053 /* SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR */
5054 /* Description: Vector request Route data was invalid */
5055 #define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_SHFT 15
5056 #define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000
5058 /* SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR */
5059 /* Description: Vector reply Route data was invalid */
5060 #define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_SHFT 16
5061 #define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000
5063 /* SH_LB_ERROR_SUMMARY_GCLK_DROP */
5064 /* Description: Gclk drop error */
5065 #define SH_LB_ERROR_SUMMARY_GCLK_DROP_SHFT 17
5066 #define SH_LB_ERROR_SUMMARY_GCLK_DROP_MASK 0x0000000000020000
5068 /* SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR */
5069 /* Description: Request queue FIFO error */
5070 #define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_SHFT 18
5071 #define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_MASK 0x0000000000040000
5073 /* SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR */
5074 /* Description: Reply queue FIFO error */
5075 #define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_SHFT 19
5076 #define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_MASK 0x0000000000080000
5078 /* SH_LB_ERROR_SUMMARY_UNEXP_VALID */
5079 /* Description: Unexpected valid error */
5080 #define SH_LB_ERROR_SUMMARY_UNEXP_VALID_SHFT 20
5081 #define SH_LB_ERROR_SUMMARY_UNEXP_VALID_MASK 0x0000000000100000
5083 /* SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW */
5084 /* Description: Request queue credit overflow */
5085 #define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_SHFT 21
5086 #define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000
5088 /* SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW */
5089 /* Description: Reply queue credit overflow */
5090 #define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_SHFT 22
5091 #define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000
5093 /* ==================================================================== */
5094 /* Register "SH_LB_ERROR_SUMMARY_ALIAS" */
5095 /* LB Error Bits Alias */
5096 /* ==================================================================== */
5098 #define SH_LB_ERROR_SUMMARY_ALIAS 0x0000000110050588
5100 /* ==================================================================== */
5101 /* Register "SH_LB_FIRST_ERROR" */
5102 /* LB First Error */
5103 /* ==================================================================== */
5105 #define SH_LB_FIRST_ERROR 0x0000000110050600
5106 #define SH_LB_FIRST_ERROR_MASK 0x00000000007fffff
5107 #define SH_LB_FIRST_ERROR_INIT 0x0000000000000000
5109 /* SH_LB_FIRST_ERROR_RQ_BAD_CMD */
5110 /* Description: RQ_BAD_CMD */
5111 #define SH_LB_FIRST_ERROR_RQ_BAD_CMD_SHFT 0
5112 #define SH_LB_FIRST_ERROR_RQ_BAD_CMD_MASK 0x0000000000000001
5114 /* SH_LB_FIRST_ERROR_RP_BAD_CMD */
5115 /* Description: RP_BAD_CMD */
5116 #define SH_LB_FIRST_ERROR_RP_BAD_CMD_SHFT 1
5117 #define SH_LB_FIRST_ERROR_RP_BAD_CMD_MASK 0x0000000000000002
5119 /* SH_LB_FIRST_ERROR_RQ_SHORT */
5120 /* Description: RQ_SHORT */
5121 #define SH_LB_FIRST_ERROR_RQ_SHORT_SHFT 2
5122 #define SH_LB_FIRST_ERROR_RQ_SHORT_MASK 0x0000000000000004
5124 /* SH_LB_FIRST_ERROR_RP_SHORT */
5125 /* Description: RP_SHORT */
5126 #define SH_LB_FIRST_ERROR_RP_SHORT_SHFT 3
5127 #define SH_LB_FIRST_ERROR_RP_SHORT_MASK 0x0000000000000008
5129 /* SH_LB_FIRST_ERROR_RQ_LONG */
5130 /* Description: RQ_LONG */
5131 #define SH_LB_FIRST_ERROR_RQ_LONG_SHFT 4
5132 #define SH_LB_FIRST_ERROR_RQ_LONG_MASK 0x0000000000000010
5134 /* SH_LB_FIRST_ERROR_RP_LONG */
5135 /* Description: RP_LONG */
5136 #define SH_LB_FIRST_ERROR_RP_LONG_SHFT 5
5137 #define SH_LB_FIRST_ERROR_RP_LONG_MASK 0x0000000000000020
5139 /* SH_LB_FIRST_ERROR_RQ_BAD_DATA */
5140 /* Description: RQ_BAD_DATA */
5141 #define SH_LB_FIRST_ERROR_RQ_BAD_DATA_SHFT 6
5142 #define SH_LB_FIRST_ERROR_RQ_BAD_DATA_MASK 0x0000000000000040
5144 /* SH_LB_FIRST_ERROR_RP_BAD_DATA */
5145 /* Description: RP_BAD_DATA */
5146 #define SH_LB_FIRST_ERROR_RP_BAD_DATA_SHFT 7
5147 #define SH_LB_FIRST_ERROR_RP_BAD_DATA_MASK 0x0000000000000080
5149 /* SH_LB_FIRST_ERROR_RQ_BAD_ADDR */
5150 /* Description: RQ_BAD_ADDR */
5151 #define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_SHFT 8
5152 #define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_MASK 0x0000000000000100
5154 /* SH_LB_FIRST_ERROR_RQ_TIME_OUT */
5155 /* Description: RQ_TIME_OUT */
5156 #define SH_LB_FIRST_ERROR_RQ_TIME_OUT_SHFT 9
5157 #define SH_LB_FIRST_ERROR_RQ_TIME_OUT_MASK 0x0000000000000200
5159 /* SH_LB_FIRST_ERROR_LINVV_OVERFLOW */
5160 /* Description: LINVV_OVERFLOW */
5161 #define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_SHFT 10
5162 #define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_MASK 0x0000000000000400
5164 /* SH_LB_FIRST_ERROR_UNEXPECTED_LINV */
5165 /* Description: UNEXPECTED_LINV */
5166 #define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_SHFT 11
5167 #define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_MASK 0x0000000000000800
5169 /* SH_LB_FIRST_ERROR_PTC_1_TIMEOUT */
5170 /* Description: PTC_1 Time out */
5171 #define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_SHFT 12
5172 #define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_MASK 0x0000000000001000
5174 /* SH_LB_FIRST_ERROR_JUNK_BUS_ERR */
5175 /* Description: Junk Bus error */
5176 #define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_SHFT 13
5177 #define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_MASK 0x0000000000002000
5179 /* SH_LB_FIRST_ERROR_PIO_CB_ERR */
5180 /* Description: PIO Conveyor Belt operation error */
5181 #define SH_LB_FIRST_ERROR_PIO_CB_ERR_SHFT 14
5182 #define SH_LB_FIRST_ERROR_PIO_CB_ERR_MASK 0x0000000000004000
5184 /* SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR */
5185 /* Description: Vector request Route data was invalid */
5186 #define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_SHFT 15
5187 #define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000
5189 /* SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR */
5190 /* Description: Vector reply Route data was invalid */
5191 #define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_SHFT 16
5192 #define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000
5194 /* SH_LB_FIRST_ERROR_GCLK_DROP */
5195 /* Description: Gclk drop error */
5196 #define SH_LB_FIRST_ERROR_GCLK_DROP_SHFT 17
5197 #define SH_LB_FIRST_ERROR_GCLK_DROP_MASK 0x0000000000020000
5199 /* SH_LB_FIRST_ERROR_RQ_FIFO_ERROR */
5200 /* Description: Request queue FIFO error */
5201 #define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_SHFT 18
5202 #define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_MASK 0x0000000000040000
5204 /* SH_LB_FIRST_ERROR_RP_FIFO_ERROR */
5205 /* Description: Reply queue FIFO error */
5206 #define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_SHFT 19
5207 #define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_MASK 0x0000000000080000
5209 /* SH_LB_FIRST_ERROR_UNEXP_VALID */
5210 /* Description: Unexpected valid error */
5211 #define SH_LB_FIRST_ERROR_UNEXP_VALID_SHFT 20
5212 #define SH_LB_FIRST_ERROR_UNEXP_VALID_MASK 0x0000000000100000
5214 /* SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW */
5215 /* Description: Request queue credit overflow */
5216 #define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_SHFT 21
5217 #define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000
5219 /* SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW */
5220 /* Description: Reply queue credit overflow */
5221 #define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_SHFT 22
5222 #define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000
5224 /* ==================================================================== */
5225 /* Register "SH_LB_LAST_CREDIT" */
5226 /* Credit counter status register */
5227 /* ==================================================================== */
5229 #define SH_LB_LAST_CREDIT 0x0000000110050680
5230 #define SH_LB_LAST_CREDIT_MASK 0x000000000ffff3df
5231 #define SH_LB_LAST_CREDIT_INIT 0x0000000000000000
5233 /* SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT */
5234 /* Description: LIQ request queue credit counter */
5235 #define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_SHFT 0
5236 #define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_MASK 0x000000000000001f
5238 /* SH_LB_LAST_CREDIT_LIQ_RP_CREDIT */
5239 /* Description: LIQ reply queue credit counter */
5240 #define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_SHFT 6
5241 #define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_MASK 0x00000000000003c0
5243 /* SH_LB_LAST_CREDIT_LINVV_CREDIT */
5244 /* Description: LINVV credit counter */
5245 #define SH_LB_LAST_CREDIT_LINVV_CREDIT_SHFT 12
5246 #define SH_LB_LAST_CREDIT_LINVV_CREDIT_MASK 0x000000000003f000
5248 /* SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT */
5249 /* Description: LOQ request queue credit counter */
5250 #define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_SHFT 18
5251 #define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_MASK 0x00000000007c0000
5253 /* SH_LB_LAST_CREDIT_LOQ_RP_CREDIT */
5254 /* Description: LOQ reply queue credit counter */
5255 #define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_SHFT 23
5256 #define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_MASK 0x000000000f800000
5258 /* ==================================================================== */
5259 /* Register "SH_LB_NACK_STATUS" */
5260 /* Nack Counter Status Register */
5261 /* ==================================================================== */
5263 #define SH_LB_NACK_STATUS 0x0000000110050700
5264 #define SH_LB_NACK_STATUS_MASK 0x3fffffff0fff0fff
5265 #define SH_LB_NACK_STATUS_INIT 0x0000000000000000
5267 /* SH_LB_NACK_STATUS_PIO_NACK_A */
5268 /* Description: PIO nackA counter */
5269 #define SH_LB_NACK_STATUS_PIO_NACK_A_SHFT 0
5270 #define SH_LB_NACK_STATUS_PIO_NACK_A_MASK 0x0000000000000fff
5272 /* SH_LB_NACK_STATUS_PIO_NACK_B */
5273 /* Description: PIO nackA counter */
5274 #define SH_LB_NACK_STATUS_PIO_NACK_B_SHFT 16
5275 #define SH_LB_NACK_STATUS_PIO_NACK_B_MASK 0x000000000fff0000
5277 /* SH_LB_NACK_STATUS_JUNK_NACK */
5278 /* Description: Junk bus nack counter */
5279 #define SH_LB_NACK_STATUS_JUNK_NACK_SHFT 32
5280 #define SH_LB_NACK_STATUS_JUNK_NACK_MASK 0x0000ffff00000000
5282 /* SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT */
5283 /* Description: Conveyor belt time out counter */
5284 #define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_SHFT 48
5285 #define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_MASK 0x0fff000000000000
5287 /* SH_LB_NACK_STATUS_CB_STATE */
5288 /* Description: Conveyor belt state */
5289 #define SH_LB_NACK_STATUS_CB_STATE_SHFT 60
5290 #define SH_LB_NACK_STATUS_CB_STATE_MASK 0x3000000000000000
5292 /* ==================================================================== */
5293 /* Register "SH_LB_TRIGGER_COMPARE" */
5294 /* LB Test-point Trigger Compare */
5295 /* ==================================================================== */
5297 #define SH_LB_TRIGGER_COMPARE 0x0000000110050780
5298 #define SH_LB_TRIGGER_COMPARE_MASK 0x00000000ffffffff
5299 #define SH_LB_TRIGGER_COMPARE_INIT 0x0000000000000000
5301 /* SH_LB_TRIGGER_COMPARE_MASK */
5302 /* Description: Mask to select Debug bits for trigger generation */
5303 #define SH_LB_TRIGGER_COMPARE_MASK_SHFT 0
5304 #define SH_LB_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff
5306 /* ==================================================================== */
5307 /* Register "SH_LB_TRIGGER_DATA" */
5308 /* LB Test-point Trigger Compare Data */
5309 /* ==================================================================== */
5311 #define SH_LB_TRIGGER_DATA 0x0000000110050800
5312 #define SH_LB_TRIGGER_DATA_MASK 0x00000000ffffffff
5313 #define SH_LB_TRIGGER_DATA_INIT 0x00000000ffffffff
5315 /* SH_LB_TRIGGER_DATA_COMPARE_PATTERN */
5316 /* Description: debug bit pattern for trigger generation */
5317 #define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_SHFT 0
5318 #define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_MASK 0x00000000ffffffff
5320 /* ==================================================================== */
5321 /* Register "SH_PI_AEC_CONFIG" */
5322 /* PI Adaptive Error Correction Configuration */
5323 /* ==================================================================== */
5325 #define SH_PI_AEC_CONFIG 0x0000000120050000
5326 #define SH_PI_AEC_CONFIG_MASK 0x0000000000000007
5327 #define SH_PI_AEC_CONFIG_INIT 0x0000000000000000
5329 /* SH_PI_AEC_CONFIG_MODE */
5330 /* Description: AEC Operation Mode */
5331 #define SH_PI_AEC_CONFIG_MODE_SHFT 0
5332 #define SH_PI_AEC_CONFIG_MODE_MASK 0x0000000000000007
5334 /* ==================================================================== */
5335 /* Register "SH_PI_AFI_ERROR_MASK" */
5336 /* PI AFI Error Mask */
5337 /* ==================================================================== */
5339 #define SH_PI_AFI_ERROR_MASK 0x0000000120050080
5340 #define SH_PI_AFI_ERROR_MASK_MASK 0x00000007ffe00000
5341 #define SH_PI_AFI_ERROR_MASK_INIT 0x00000007ffe00000
5343 /* SH_PI_AFI_ERROR_MASK_HUNG_BUS */
5344 /* Description: FSB is hung */
5345 #define SH_PI_AFI_ERROR_MASK_HUNG_BUS_SHFT 21
5346 #define SH_PI_AFI_ERROR_MASK_HUNG_BUS_MASK 0x0000000000200000
5348 /* SH_PI_AFI_ERROR_MASK_RSP_PARITY */
5349 /* Description: Parity error detecte during response phase */
5350 #define SH_PI_AFI_ERROR_MASK_RSP_PARITY_SHFT 22
5351 #define SH_PI_AFI_ERROR_MASK_RSP_PARITY_MASK 0x0000000000400000
5353 /* SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN */
5354 /* Description: Over run error detected on IOQ */
5355 #define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_SHFT 23
5356 #define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_MASK 0x0000000000800000
5358 /* SH_PI_AFI_ERROR_MASK_REQ_FORMAT */
5359 /* Description: FSB request format not supported */
5360 #define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_SHFT 24
5361 #define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_MASK 0x0000000001000000
5363 /* SH_PI_AFI_ERROR_MASK_ADDR_ACCESS */
5364 /* Description: Access to Address is not supported */
5365 #define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_SHFT 25
5366 #define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_MASK 0x0000000002000000
5368 /* SH_PI_AFI_ERROR_MASK_REQ_PARITY */
5369 /* Description: Parity error detected during request phase */
5370 #define SH_PI_AFI_ERROR_MASK_REQ_PARITY_SHFT 26
5371 #define SH_PI_AFI_ERROR_MASK_REQ_PARITY_MASK 0x0000000004000000
5373 /* SH_PI_AFI_ERROR_MASK_ADDR_PARITY */
5374 /* Description: Parity error detected on address */
5375 #define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_SHFT 27
5376 #define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_MASK 0x0000000008000000
5378 /* SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE */
5379 /* Description: SHUB_FSB_DQE */
5380 #define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_SHFT 28
5381 #define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_MASK 0x0000000010000000
5383 /* SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE */
5384 /* Description: An un-correctable ECC error was detected */
5385 #define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_SHFT 29
5386 #define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_MASK 0x0000000020000000
5388 /* SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE */
5389 /* Description: An correctable ECC error was detected */
5390 #define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_SHFT 30
5391 #define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_MASK 0x0000000040000000
5393 /* SH_PI_AFI_ERROR_MASK_LIVELOCK */
5394 /* Description: AFI livelock error was detected */
5395 #define SH_PI_AFI_ERROR_MASK_LIVELOCK_SHFT 31
5396 #define SH_PI_AFI_ERROR_MASK_LIVELOCK_MASK 0x0000000080000000
5398 /* SH_PI_AFI_ERROR_MASK_BAD_SNOOP */
5399 /* Description: AFI bad snoop error was detected */
5400 #define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_SHFT 32
5401 #define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_MASK 0x0000000100000000
5403 /* SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS */
5404 /* Description: AFI FSB request table miss error was detected */
5405 #define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_SHFT 33
5406 #define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_MASK 0x0000000200000000
5408 /* SH_PI_AFI_ERROR_MASK_MSG_LEN */
5409 /* Description: Runt or Obese message received from SIC */
5410 #define SH_PI_AFI_ERROR_MASK_MSG_LEN_SHFT 34
5411 #define SH_PI_AFI_ERROR_MASK_MSG_LEN_MASK 0x0000000400000000
5413 /* ==================================================================== */
5414 /* Register "SH_PI_AFI_TEST_POINT_COMPARE" */
5415 /* PI AFI Test Point Compare */
5416 /* ==================================================================== */
5418 #define SH_PI_AFI_TEST_POINT_COMPARE 0x0000000120050100
5419 #define SH_PI_AFI_TEST_POINT_COMPARE_MASK 0xffffffffffffffff
5420 #define SH_PI_AFI_TEST_POINT_COMPARE_INIT 0xffffffff00000000
5422 /* SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK */
5423 /* Description: Mask to select Debug bits for trigger generation */
5424 #define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
5425 #define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
5427 /* SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN */
5428 /* Description: debug bit pattern for trigger generation */
5429 #define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
5430 #define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
5432 /* ==================================================================== */
5433 /* Register "SH_PI_AFI_TEST_POINT_SELECT" */
5434 /* PI AFI Test Point Select */
5435 /* ==================================================================== */
5437 #define SH_PI_AFI_TEST_POINT_SELECT 0x0000000120050180
5438 #define SH_PI_AFI_TEST_POINT_SELECT_MASK 0xff7f7f7f7f7f7f7f
5439 #define SH_PI_AFI_TEST_POINT_SELECT_INIT 0x0000000000000000
5441 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */
5442 /* Description: Nibble 0: Word Select */
5443 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
5444 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x000000000000000f
5446 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */
5447 /* Description: Nibble 0: Nibble Select */
5448 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
5449 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
5451 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */
5452 /* Description: Nibble 1: Word Select */
5453 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
5454 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000f00
5456 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */
5457 /* Description: Nibble 1: Nibble Select */
5458 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
5459 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
5461 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */
5462 /* Description: Nibble 2: Word Select */
5463 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
5464 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x00000000000f0000
5466 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */
5467 /* Description: Nibble 2: Nibble Select */
5468 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
5469 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
5471 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */
5472 /* Description: Nibble 3: Word Select */
5473 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
5474 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x000000000f000000
5476 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */
5477 /* Description: Nibble 3: Nibble Select */
5478 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
5479 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
5481 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */
5482 /* Description: Nibble 4: Word Select */
5483 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
5484 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000f00000000
5486 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */
5487 /* Description: Nibble 4: Nibble Select */
5488 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
5489 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
5491 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */
5492 /* Description: Nibble 5: Word Select */
5493 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
5494 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x00000f0000000000
5496 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */
5497 /* Description: Nibble 5: Nibble Select */
5498 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
5499 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
5501 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */
5502 /* Description: Nibble 6: Word Select */
5503 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
5504 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x000f000000000000
5506 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */
5507 /* Description: Nibble 6: Nibble Select */
5508 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
5509 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
5511 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */
5512 /* Description: Nibble 7: Word Select */
5513 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
5514 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0f00000000000000
5516 /* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */
5517 /* Description: Nibble 7: Nibble Select */
5518 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
5519 #define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
5521 /* SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE */
5522 /* Description: Trigger Enabled */
5523 #define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
5524 #define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
5526 /* ==================================================================== */
5527 /* Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT" */
5528 /* PI CRBC Test Point Trigger Select */
5529 /* ==================================================================== */
5531 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT 0x0000000120050200
5532 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_MASK 0x7f7f7f7f7f7f7f7f
5533 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000
5535 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */
5536 /* Description: Nibble 0 Chiplet select */
5537 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
5538 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x000000000000000f
5540 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */
5541 /* Description: Nibble 0 Nibble select */
5542 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
5543 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
5545 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */
5546 /* Description: Nibble 1 Chiplet select */
5547 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
5548 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000f00
5550 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */
5551 /* Description: Nibble 1 Nibble select */
5552 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
5553 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
5555 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */
5556 /* Description: Nibble 2 Chiplet select */
5557 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
5558 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x00000000000f0000
5560 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */
5561 /* Description: Nibble 2 Nibble select */
5562 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
5563 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
5565 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */
5566 /* Description: Nibble 3 Chiplet select */
5567 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
5568 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x000000000f000000
5570 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */
5571 /* Description: Nibble 3 Nibble select */
5572 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
5573 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
5575 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */
5576 /* Description: Nibble 4 Chiplet select */
5577 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
5578 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000f00000000
5580 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */
5581 /* Description: Nibble 4 Nibble select */
5582 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
5583 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
5585 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */
5586 /* Description: Nibble 5 Chiplet select */
5587 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
5588 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x00000f0000000000
5590 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */
5591 /* Description: Nibble 5 Nibble select */
5592 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
5593 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
5595 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */
5596 /* Description: Nibble 6 Chiplet select */
5597 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
5598 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x000f000000000000
5600 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */
5601 /* Description: Nibble 6 Nibble select */
5602 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
5603 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
5605 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */
5606 /* Description: Nibble 7 Chiplet select */
5607 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
5608 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0f00000000000000
5610 /* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */
5611 /* Description: Nibble 7 Nibble select */
5612 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
5613 #define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
5615 /* ==================================================================== */
5616 /* Register "SH_PI_AUTO_REPLY_ENABLE" */
5617 /* PI Auto Reply Enable */
5618 /* ==================================================================== */
5620 #define SH_PI_AUTO_REPLY_ENABLE 0x0000000120050280
5621 #define SH_PI_AUTO_REPLY_ENABLE_MASK 0x0000000000000001
5622 #define SH_PI_AUTO_REPLY_ENABLE_INIT 0x0000000000000000
5624 /* SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE */
5625 /* Description: Auto Reply Enabled */
5626 #define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_SHFT 0
5627 #define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_MASK 0x0000000000000001
5629 /* ==================================================================== */
5630 /* Register "SH_PI_CAM_CONTROL" */
5631 /* CRB CAM MMR Access Control */
5632 /* ==================================================================== */
5634 #define SH_PI_CAM_CONTROL 0x0000000120050300
5635 #define SH_PI_CAM_CONTROL_MASK 0x800000000000037f
5636 #define SH_PI_CAM_CONTROL_INIT 0x0000000000000000
5638 /* SH_PI_CAM_CONTROL_CAM_INDX */
5639 /* Description: CRB CAM Index to perform read/write on. */
5640 #define SH_PI_CAM_CONTROL_CAM_INDX_SHFT 0
5641 #define SH_PI_CAM_CONTROL_CAM_INDX_MASK 0x000000000000007f
5643 /* SH_PI_CAM_CONTROL_CAM_WRITE */
5644 /* Description: Is CRB CAM MMR function a write. */
5645 #define SH_PI_CAM_CONTROL_CAM_WRITE_SHFT 8
5646 #define SH_PI_CAM_CONTROL_CAM_WRITE_MASK 0x0000000000000100
5648 /* SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR */
5649 /* Description: Clear RRB read tranfer pending. */
5650 #define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_SHFT 9
5651 #define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_MASK 0x0000000000000200
5653 /* SH_PI_CAM_CONTROL_START */
5654 /* Description: Start CRB CAM read/write operation */
5655 #define SH_PI_CAM_CONTROL_START_SHFT 63
5656 #define SH_PI_CAM_CONTROL_START_MASK 0x8000000000000000
5658 /* ==================================================================== */
5659 /* Register "SH_PI_CRBC_TEST_POINT_COMPARE" */
5660 /* PI CRBC Test Point Compare */
5661 /* ==================================================================== */
5663 #define SH_PI_CRBC_TEST_POINT_COMPARE 0x0000000120050380
5664 #define SH_PI_CRBC_TEST_POINT_COMPARE_MASK 0xffffffffffffffff
5665 #define SH_PI_CRBC_TEST_POINT_COMPARE_INIT 0xffffffff00000000
5667 /* SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK */
5668 /* Description: Mask to select Debug bits for trigger generation */
5669 #define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
5670 #define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
5672 /* SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN */
5673 /* Description: debug bit pattern for trigger generation */
5674 #define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
5675 #define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
5677 /* ==================================================================== */
5678 /* Register "SH_PI_CRBC_TEST_POINT_SELECT" */
5679 /* PI CRBC Test Point Select */
5680 /* ==================================================================== */
5682 #define SH_PI_CRBC_TEST_POINT_SELECT 0x0000000120050400
5683 #define SH_PI_CRBC_TEST_POINT_SELECT_MASK 0xf777777777777777
5684 #define SH_PI_CRBC_TEST_POINT_SELECT_INIT 0x0000000000000000
5686 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */
5687 /* Description: Nibble 0 Chiplet select */
5688 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
5689 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
5691 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */
5692 /* Description: Nibble 0 Nibble select */
5693 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
5694 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
5696 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */
5697 /* Description: Nibble 1 Chiplet select */
5698 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
5699 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
5701 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */
5702 /* Description: Nibble 1 Nibble select */
5703 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
5704 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
5706 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */
5707 /* Description: Nibble 2 Chiplet select */
5708 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
5709 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
5711 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */
5712 /* Description: Nibble 2 Nibble select */
5713 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
5714 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
5716 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */
5717 /* Description: Nibble 3 Chiplet select */
5718 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
5719 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
5721 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */
5722 /* Description: Nibble 3 Nibble select */
5723 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
5724 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
5726 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */
5727 /* Description: Nibble 4 Chiplet select */
5728 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
5729 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
5731 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */
5732 /* Description: Nibble 4 Nibble select */
5733 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
5734 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
5736 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */
5737 /* Description: Nibble 5 Chiplet select */
5738 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
5739 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
5741 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */
5742 /* Description: Nibble 5 Nibble select */
5743 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
5744 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
5746 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */
5747 /* Description: Nibble 6 Chiplet select */
5748 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
5749 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
5751 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */
5752 /* Description: Nibble 6 Nibble select */
5753 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
5754 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
5756 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */
5757 /* Description: Nibble 7 Chiplet select */
5758 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
5759 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
5761 /* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */
5762 /* Description: Nibble 7 Nibble select */
5763 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
5764 #define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
5766 /* SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE */
5767 /* Description: Enable trigger on bit 32 of Analyzer data */
5768 #define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
5769 #define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
5771 /* ==================================================================== */
5772 /* Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT" */
5773 /* PI CRBC Test Point Trigger Select */
5774 /* ==================================================================== */
5776 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT 0x0000000120050480
5777 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777
5778 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000
5780 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */
5781 /* Description: Nibble 0 Chiplet select */
5782 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
5783 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
5785 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */
5786 /* Description: Nibble 0 Nibble select */
5787 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
5788 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
5790 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */
5791 /* Description: Nibble 1 Chiplet select */
5792 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
5793 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
5795 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */
5796 /* Description: Nibble 1 Nibble select */
5797 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
5798 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
5800 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */
5801 /* Description: Nibble 2 Chiplet select */
5802 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
5803 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
5805 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */
5806 /* Description: Nibble 2 Nibble select */
5807 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
5808 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
5810 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */
5811 /* Description: Nibble 3 Chiplet select */
5812 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
5813 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
5815 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */
5816 /* Description: Nibble 3 Nibble select */
5817 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
5818 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
5820 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */
5821 /* Description: Nibble 4 Chiplet select */
5822 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
5823 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
5825 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */
5826 /* Description: Nibble 4 Nibble select */
5827 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
5828 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
5830 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */
5831 /* Description: Nibble 5 Chiplet select */
5832 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
5833 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
5835 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */
5836 /* Description: Nibble 5 Nibble select */
5837 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
5838 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
5840 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */
5841 /* Description: Nibble 6 Chiplet select */
5842 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
5843 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
5845 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */
5846 /* Description: Nibble 6 Nibble select */
5847 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
5848 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
5850 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */
5851 /* Description: Nibble 7 Chiplet select */
5852 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
5853 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
5855 /* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */
5856 /* Description: Nibble 7 Nibble select */
5857 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
5858 #define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
5860 /* ==================================================================== */
5861 /* Register "SH_PI_CRBP_ERROR_MASK" */
5862 /* PI CRBP Error Mask */
5863 /* ==================================================================== */
5865 #define SH_PI_CRBP_ERROR_MASK 0x0000000120050500
5866 #define SH_PI_CRBP_ERROR_MASK_MASK 0x00000000001fffff
5867 #define SH_PI_CRBP_ERROR_MASK_INIT 0x00000000001fffff
5869 /* SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR */
5870 /* Description: Mask detection internal protocol table misses */
5871 #define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_SHFT 0
5872 #define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_MASK 0x0000000000000001
5874 /* SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR */
5875 /* Description: Mask graphic reply error detection */
5876 #define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_SHFT 1
5877 #define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_MASK 0x0000000000000002
5879 /* SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR */
5880 /* Description: Mask detection of external protocol table misses */
5881 #define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_SHFT 2
5882 #define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_MASK 0x0000000000000004
5884 /* SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR */
5885 /* Description: Mask memory error reply message detection */
5886 #define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_SHFT 3
5887 #define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_MASK 0x0000000000000008
5889 /* SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR */
5890 /* Description: Mask PIO reply error message detection */
5891 #define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_SHFT 4
5892 #define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_MASK 0x0000000000000010
5894 /* SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR */
5895 /* Description: Mask memory time-out detection */
5896 #define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_SHFT 5
5897 #define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_MASK 0x0000000000000020
5899 /* SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR */
5900 /* Description: Mask PIO time-out detection */
5901 #define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_SHFT 6
5902 #define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_MASK 0x0000000000000040
5904 /* SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE */
5905 /* Description: Mask un-correctable ECC error detection */
5906 #define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_SHFT 7
5907 #define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_MASK 0x0000000000000080
5909 /* SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE */
5910 /* Description: Mask correctable ECC error detection */
5911 #define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_SHFT 8
5912 #define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_MASK 0x0000000000000100
5914 /* SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR */
5915 /* Description: Mask detection of color errors */
5916 #define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_SHFT 9
5917 #define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_MASK 0x0000000000000200
5919 /* SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW */
5920 /* Description: Mask MD Request input buffer over flow error */
5921 #define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT 10
5922 #define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_MASK 0x0000000000000400
5924 /* SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW */
5925 /* Description: Mask MD Reply input buffer over flow error */
5926 #define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_SHFT 11
5927 #define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_MASK 0x0000000000000800
5929 /* SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW */
5930 /* Description: Mask XN Request input buffer over flow error */
5931 #define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT 12
5932 #define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_MASK 0x0000000000001000
5934 /* SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW */
5935 /* Description: Mask XN Reply input buffer over flow error */
5936 #define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_SHFT 13
5937 #define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_MASK 0x0000000000002000
5939 /* SH_PI_CRBP_ERROR_MASK_NACK_OFLOW */
5940 /* Description: Mask NACK over flow error */
5941 #define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_SHFT 14
5942 #define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_MASK 0x0000000000004000
5944 /* SH_PI_CRBP_ERROR_MASK_GFX_INT_0 */
5945 /* Description: Mask GFX transfer interrupt for CPU 0 */
5946 #define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_SHFT 15
5947 #define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_MASK 0x0000000000008000
5949 /* SH_PI_CRBP_ERROR_MASK_GFX_INT_1 */
5950 /* Description: Mask GFX transfer interrupt for CPU 1 */
5951 #define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_SHFT 16
5952 #define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_MASK 0x0000000000010000
5954 /* SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW */
5955 /* Description: Mask MD Request Credit Overflow Error */
5956 #define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT 17
5957 #define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
5959 /* SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW */
5960 /* Description: Mask MD Reply Credit Overflow Error */
5961 #define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT 18
5962 #define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
5964 /* SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW */
5965 /* Description: Mask XN Request Credit Overflow Error */
5966 #define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT 19
5967 #define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
5969 /* SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW */
5970 /* Description: Mask XN Reply Credit Overflow Error */
5971 #define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT 20
5972 #define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
5974 /* ==================================================================== */
5975 /* Register "SH_PI_CRBP_FSB_PIPE_COMPARE" */
5976 /* CRBP FSB Pipe Compare */
5977 /* ==================================================================== */
5979 #define SH_PI_CRBP_FSB_PIPE_COMPARE 0x0000000120050580
5980 #define SH_PI_CRBP_FSB_PIPE_COMPARE_MASK 0x001fffffffffffff
5981 #define SH_PI_CRBP_FSB_PIPE_COMPARE_INIT 0x0000000000000000
5983 /* SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS */
5984 /* Description: Address A or B to compare against */
5985 #define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_SHFT 0
5986 #define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_MASK 0x00007fffffffffff
5988 /* SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ */
5989 /* Description: REQa or REQb value to compare against */
5990 #define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_SHFT 47
5991 #define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_MASK 0x001f800000000000
5993 /* ==================================================================== */
5994 /* Register "SH_PI_CRBP_FSB_PIPE_MASK" */
5995 /* CRBP Compare Mask */
5996 /* ==================================================================== */
5998 #define SH_PI_CRBP_FSB_PIPE_MASK 0x0000000120050600
5999 #define SH_PI_CRBP_FSB_PIPE_MASK_MASK 0x001fffffffffffff
6000 #define SH_PI_CRBP_FSB_PIPE_MASK_INIT 0x0000000000000000
6002 /* SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK */
6003 /* Description: Address A or B mask values */
6004 #define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_SHFT 0
6005 #define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff
6007 /* SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK */
6008 /* Description: REQa or REQb mask values */
6009 #define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_SHFT 47
6010 #define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_MASK 0x001f800000000000
6012 /* ==================================================================== */
6013 /* Register "SH_PI_CRBP_TEST_POINT_COMPARE" */
6014 /* PI CRBP Test Point Compare */
6015 /* ==================================================================== */
6017 #define SH_PI_CRBP_TEST_POINT_COMPARE 0x0000000120050680
6018 #define SH_PI_CRBP_TEST_POINT_COMPARE_MASK 0xffffffffffffffff
6019 #define SH_PI_CRBP_TEST_POINT_COMPARE_INIT 0xffffffff00000000
6021 /* SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK */
6022 /* Description: Mask to select Debug bits for trigger generation */
6023 #define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
6024 #define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
6026 /* SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN */
6027 /* Description: debug bit pattern for trigger generation */
6028 #define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
6029 #define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
6031 /* ==================================================================== */
6032 /* Register "SH_PI_CRBP_TEST_POINT_SELECT" */
6033 /* PI CRBP Test Point Select */
6034 /* ==================================================================== */
6036 #define SH_PI_CRBP_TEST_POINT_SELECT 0x0000000120050700
6037 #define SH_PI_CRBP_TEST_POINT_SELECT_MASK 0xf777777777777777
6038 #define SH_PI_CRBP_TEST_POINT_SELECT_INIT 0x0000000000000000
6040 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */
6041 /* Description: Nibble 0 Chiplet select */
6042 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
6043 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
6045 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */
6046 /* Description: Nibble 0 Nibble select */
6047 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
6048 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
6050 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */
6051 /* Description: Nibble 1 Chiplet select */
6052 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
6053 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
6055 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */
6056 /* Description: Nibble 1 Nibble select */
6057 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
6058 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
6060 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */
6061 /* Description: Nibble 2 Chiplet select */
6062 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
6063 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
6065 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */
6066 /* Description: Nibble 2 Nibble select */
6067 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
6068 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
6070 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */
6071 /* Description: Nibble 3 Chiplet select */
6072 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
6073 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
6075 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */
6076 /* Description: Nibble 3 Nibble select */
6077 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
6078 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
6080 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */
6081 /* Description: Nibble 4 Chiplet select */
6082 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
6083 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
6085 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */
6086 /* Description: Nibble 4 Nibble select */
6087 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
6088 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
6090 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */
6091 /* Description: Nibble 5 Chiplet select */
6092 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
6093 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
6095 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */
6096 /* Description: Nibble 5 Nibble select */
6097 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
6098 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
6100 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */
6101 /* Description: Nibble 6 Chiplet select */
6102 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
6103 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
6105 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */
6106 /* Description: Nibble 6 Nibble select */
6107 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
6108 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
6110 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */
6111 /* Description: Nibble 7 Chiplet select */
6112 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
6113 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
6115 /* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */
6116 /* Description: Nibble 7 Nibble select */
6117 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
6118 #define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
6120 /* SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE */
6121 /* Description: Enable trigger on bit 32 of Analyzer data */
6122 #define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
6123 #define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
6125 /* ==================================================================== */
6126 /* Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT" */
6127 /* PI CRBP Test Point Trigger Select */
6128 /* ==================================================================== */
6130 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT 0x0000000120050780
6131 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777
6132 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000
6134 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */
6135 /* Description: Nibble 0 Chiplet select */
6136 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
6137 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
6139 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */
6140 /* Description: Nibble 0 Nibble select */
6141 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
6142 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
6144 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */
6145 /* Description: Nibble 1 Chiplet select */
6146 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
6147 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
6149 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */
6150 /* Description: Nibble 1 Nibble select */
6151 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
6152 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
6154 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */
6155 /* Description: Nibble 2 Chiplet select */
6156 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
6157 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
6159 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */
6160 /* Description: Nibble 2 Nibble select */
6161 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
6162 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
6164 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */
6165 /* Description: Nibble 3 Chiplet select */
6166 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
6167 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
6169 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */
6170 /* Description: Nibble 3 Nibble select */
6171 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
6172 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
6174 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */
6175 /* Description: Nibble 4 Chiplet select */
6176 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
6177 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
6179 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */
6180 /* Description: Nibble 4 Nibble select */
6181 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
6182 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
6184 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */
6185 /* Description: Nibble 5 Chiplet select */
6186 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
6187 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
6189 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */
6190 /* Description: Nibble 5 Nibble select */
6191 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
6192 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
6194 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */
6195 /* Description: Nibble 6 Chiplet select */
6196 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
6197 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
6199 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */
6200 /* Description: Nibble 6 Nibble select */
6201 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
6202 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
6204 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */
6205 /* Description: Nibble 7 Chiplet select */
6206 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
6207 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
6209 /* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */
6210 /* Description: Nibble 7 Nibble select */
6211 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
6212 #define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
6214 /* ==================================================================== */
6215 /* Register "SH_PI_CRBP_XB_PIPE_COMPARE_0" */
6216 /* CRBP XB Pipe Compare */
6217 /* ==================================================================== */
6219 #define SH_PI_CRBP_XB_PIPE_COMPARE_0 0x0000000120050800
6220 #define SH_PI_CRBP_XB_PIPE_COMPARE_0_MASK 0x007fffffffffffff
6221 #define SH_PI_CRBP_XB_PIPE_COMPARE_0_INIT 0x0000000000000000
6223 /* SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS */
6224 /* Description: Address to compare against */
6225 #define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_SHFT 0
6226 #define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_MASK 0x00007fffffffffff
6228 /* SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND */
6229 /* Description: SN2NET Command to compare against */
6230 #define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_SHFT 47
6231 #define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_MASK 0x007f800000000000
6233 /* ==================================================================== */
6234 /* Register "SH_PI_CRBP_XB_PIPE_COMPARE_1" */
6235 /* CRBP XB Pipe Compare */
6236 /* ==================================================================== */
6238 #define SH_PI_CRBP_XB_PIPE_COMPARE_1 0x0000000120050880
6239 #define SH_PI_CRBP_XB_PIPE_COMPARE_1_MASK 0x000001ff3fff3fff
6240 #define SH_PI_CRBP_XB_PIPE_COMPARE_1_INIT 0x0000000000000000
6242 /* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE */
6243 /* Description: Source to compare against */
6244 #define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_SHFT 0
6245 #define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_MASK 0x0000000000003fff
6247 /* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL */
6248 /* Description: Supplemental to compare against */
6249 #define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_SHFT 16
6250 #define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_MASK 0x000000003fff0000
6252 /* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO */
6253 /* Description: Echo to compare against */
6254 #define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_SHFT 32
6255 #define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_MASK 0x000001ff00000000
6257 /* ==================================================================== */
6258 /* Register "SH_PI_CRBP_XB_PIPE_MASK_0" */
6259 /* CRBP Compare Mask Register 1 */
6260 /* ==================================================================== */
6262 #define SH_PI_CRBP_XB_PIPE_MASK_0 0x0000000120050900
6263 #define SH_PI_CRBP_XB_PIPE_MASK_0_MASK 0x007fffffffffffff
6264 #define SH_PI_CRBP_XB_PIPE_MASK_0_INIT 0x0000000000000000
6266 /* SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK */
6267 /* Description: Address to compare against */
6268 #define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_SHFT 0
6269 #define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff
6271 /* SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK */
6272 /* Description: SN2NET Command to compare against */
6273 #define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_SHFT 47
6274 #define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_MASK 0x007f800000000000
6276 /* ==================================================================== */
6277 /* Register "SH_PI_CRBP_XB_PIPE_MASK_1" */
6278 /* CRBP XB Pipe Compare Mask Register 1 */
6279 /* ==================================================================== */
6281 #define SH_PI_CRBP_XB_PIPE_MASK_1 0x0000000120050980
6282 #define SH_PI_CRBP_XB_PIPE_MASK_1_MASK 0x000001ff3fff3fff
6283 #define SH_PI_CRBP_XB_PIPE_MASK_1_INIT 0x0000000000000000
6285 /* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK */
6286 /* Description: Source to compare against */
6287 #define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_SHFT 0
6288 #define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_MASK 0x0000000000003fff
6290 /* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK */
6291 /* Description: Supplemental to compare against */
6292 #define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_SHFT 16
6293 #define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_MASK 0x000000003fff0000
6295 /* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK */
6296 /* Description: Echo to compare against */
6297 #define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_SHFT 32
6298 #define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_MASK 0x000001ff00000000
6300 /* ==================================================================== */
6301 /* Register "SH_PI_DPC_QUEUE_CONFIG" */
6302 /* DPC Queue Configuration */
6303 /* ==================================================================== */
6305 #define SH_PI_DPC_QUEUE_CONFIG 0x0000000120050a00
6306 #define SH_PI_DPC_QUEUE_CONFIG_MASK 0x000000001f1f1f1f
6307 #define SH_PI_DPC_QUEUE_CONFIG_INIT 0x000000000c010c01
6309 /* SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL */
6310 /* Description: DXB WTL Command Queue Almost Empty Level */
6311 #define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_SHFT 0
6312 #define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_MASK 0x000000000000001f
6314 /* SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH */
6315 /* Description: DXB WTL Command Queue Almost Full Threshold */
6316 #define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_SHFT 8
6317 #define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_MASK 0x0000000000001f00
6319 /* SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL */
6320 /* Description: FSB WTL Command Queue Almost Empty Level */
6321 #define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_SHFT 16
6322 #define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_MASK 0x00000000001f0000
6324 /* SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH */
6325 /* Description: FSB WTL Command Queue Almost Full Threshold */
6326 #define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_SHFT 24
6327 #define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_MASK 0x000000001f000000
6329 /* ==================================================================== */
6330 /* Register "SH_PI_ERROR_MASK" */
6332 /* ==================================================================== */
6334 #define SH_PI_ERROR_MASK 0x0000000120050a80
6335 #define SH_PI_ERROR_MASK_MASK 0x00000007ffffffff
6336 #define SH_PI_ERROR_MASK_INIT 0x00000007ffffffff
6338 /* SH_PI_ERROR_MASK_FSB_PROTO_ERR */
6339 /* Description: Mask detection of internal protocol table misses */
6340 #define SH_PI_ERROR_MASK_FSB_PROTO_ERR_SHFT 0
6341 #define SH_PI_ERROR_MASK_FSB_PROTO_ERR_MASK 0x0000000000000001
6343 /* SH_PI_ERROR_MASK_GFX_RP_ERR */
6344 /* Description: Mask graphic reply error message error detection */
6345 #define SH_PI_ERROR_MASK_GFX_RP_ERR_SHFT 1
6346 #define SH_PI_ERROR_MASK_GFX_RP_ERR_MASK 0x0000000000000002
6348 /* SH_PI_ERROR_MASK_XB_PROTO_ERR */
6349 /* Description: Mask detection of external protocol table misses */
6350 #define SH_PI_ERROR_MASK_XB_PROTO_ERR_SHFT 2
6351 #define SH_PI_ERROR_MASK_XB_PROTO_ERR_MASK 0x0000000000000004
6353 /* SH_PI_ERROR_MASK_MEM_RP_ERR */
6354 /* Description: Mask memory reply error detection */
6355 #define SH_PI_ERROR_MASK_MEM_RP_ERR_SHFT 3
6356 #define SH_PI_ERROR_MASK_MEM_RP_ERR_MASK 0x0000000000000008
6358 /* SH_PI_ERROR_MASK_PIO_RP_ERR */
6359 /* Description: Mask PIO reply error detection */
6360 #define SH_PI_ERROR_MASK_PIO_RP_ERR_SHFT 4
6361 #define SH_PI_ERROR_MASK_PIO_RP_ERR_MASK 0x0000000000000010
6363 /* SH_PI_ERROR_MASK_MEM_TO_ERR */
6364 /* Description: Mask CRB time-out errors */
6365 #define SH_PI_ERROR_MASK_MEM_TO_ERR_SHFT 5
6366 #define SH_PI_ERROR_MASK_MEM_TO_ERR_MASK 0x0000000000000020
6368 /* SH_PI_ERROR_MASK_PIO_TO_ERR */
6369 /* Description: Mask PIO time-out errors */
6370 #define SH_PI_ERROR_MASK_PIO_TO_ERR_SHFT 6
6371 #define SH_PI_ERROR_MASK_PIO_TO_ERR_MASK 0x0000000000000040
6373 /* SH_PI_ERROR_MASK_FSB_SHUB_UCE */
6374 /* Description: Mask un-correctable ECC error detection */
6375 #define SH_PI_ERROR_MASK_FSB_SHUB_UCE_SHFT 7
6376 #define SH_PI_ERROR_MASK_FSB_SHUB_UCE_MASK 0x0000000000000080
6378 /* SH_PI_ERROR_MASK_FSB_SHUB_CE */
6379 /* Description: Mask correctable ECC error detection */
6380 #define SH_PI_ERROR_MASK_FSB_SHUB_CE_SHFT 8
6381 #define SH_PI_ERROR_MASK_FSB_SHUB_CE_MASK 0x0000000000000100
6383 /* SH_PI_ERROR_MASK_MSG_COLOR_ERR */
6384 /* Description: Mask message color error detection */
6385 #define SH_PI_ERROR_MASK_MSG_COLOR_ERR_SHFT 9
6386 #define SH_PI_ERROR_MASK_MSG_COLOR_ERR_MASK 0x0000000000000200
6388 /* SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW */
6389 /* Description: Mask MD Request input buffer over flow error */
6390 #define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT 10
6391 #define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_MASK 0x0000000000000400
6393 /* SH_PI_ERROR_MASK_MD_RP_Q_OFLOW */
6394 /* Description: Mask MD Reply input buffer over flow error */
6395 #define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_SHFT 11
6396 #define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_MASK 0x0000000000000800
6398 /* SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW */
6399 /* Description: Mask XN Request input buffer over flow error */
6400 #define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT 12
6401 #define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_MASK 0x0000000000001000
6403 /* SH_PI_ERROR_MASK_XN_RP_Q_OFLOW */
6404 /* Description: Mask XN Reply input buffer over flow error */
6405 #define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_SHFT 13
6406 #define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_MASK 0x0000000000002000
6408 /* SH_PI_ERROR_MASK_NACK_OFLOW */
6409 /* Description: Mask NACK over flow error */
6410 #define SH_PI_ERROR_MASK_NACK_OFLOW_SHFT 14
6411 #define SH_PI_ERROR_MASK_NACK_OFLOW_MASK 0x0000000000004000
6413 /* SH_PI_ERROR_MASK_GFX_INT_0 */
6414 /* Description: Mask GFX transfer interrupt for CPU 0 */
6415 #define SH_PI_ERROR_MASK_GFX_INT_0_SHFT 15
6416 #define SH_PI_ERROR_MASK_GFX_INT_0_MASK 0x0000000000008000
6418 /* SH_PI_ERROR_MASK_GFX_INT_1 */
6419 /* Description: Mask GFX transfer interrupt for CPU 1 */
6420 #define SH_PI_ERROR_MASK_GFX_INT_1_SHFT 16
6421 #define SH_PI_ERROR_MASK_GFX_INT_1_MASK 0x0000000000010000
6423 /* SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW */
6424 /* Description: Mask MD Request Credit Overflow Error */
6425 #define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT 17
6426 #define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
6428 /* SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW */
6429 /* Description: Mask MD Reply Credit Overflow Error */
6430 #define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT 18
6431 #define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
6433 /* SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW */
6434 /* Description: Mask XN Request Credit Overflow Error */
6435 #define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT 19
6436 #define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
6438 /* SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW */
6439 /* Description: Mask XN Reply Credit Overflow Error */
6440 #define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT 20
6441 #define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
6443 /* SH_PI_ERROR_MASK_HUNG_BUS */
6444 /* Description: Mask FSB hung error */
6445 #define SH_PI_ERROR_MASK_HUNG_BUS_SHFT 21
6446 #define SH_PI_ERROR_MASK_HUNG_BUS_MASK 0x0000000000200000
6448 /* SH_PI_ERROR_MASK_RSP_PARITY */
6449 /* Description: Parity error detecte during response phase */
6450 #define SH_PI_ERROR_MASK_RSP_PARITY_SHFT 22
6451 #define SH_PI_ERROR_MASK_RSP_PARITY_MASK 0x0000000000400000
6453 /* SH_PI_ERROR_MASK_IOQ_OVERRUN */
6454 /* Description: Over run error detected on IOQ */
6455 #define SH_PI_ERROR_MASK_IOQ_OVERRUN_SHFT 23
6456 #define SH_PI_ERROR_MASK_IOQ_OVERRUN_MASK 0x0000000000800000
6458 /* SH_PI_ERROR_MASK_REQ_FORMAT */
6459 /* Description: FSB request format not supported */
6460 #define SH_PI_ERROR_MASK_REQ_FORMAT_SHFT 24
6461 #define SH_PI_ERROR_MASK_REQ_FORMAT_MASK 0x0000000001000000
6463 /* SH_PI_ERROR_MASK_ADDR_ACCESS */
6464 /* Description: Access to Address is not supported */
6465 #define SH_PI_ERROR_MASK_ADDR_ACCESS_SHFT 25
6466 #define SH_PI_ERROR_MASK_ADDR_ACCESS_MASK 0x0000000002000000
6468 /* SH_PI_ERROR_MASK_REQ_PARITY */
6469 /* Description: Parity error detected during request phase */
6470 #define SH_PI_ERROR_MASK_REQ_PARITY_SHFT 26
6471 #define SH_PI_ERROR_MASK_REQ_PARITY_MASK 0x0000000004000000
6473 /* SH_PI_ERROR_MASK_ADDR_PARITY */
6474 /* Description: Parity error detected on address */
6475 #define SH_PI_ERROR_MASK_ADDR_PARITY_SHFT 27
6476 #define SH_PI_ERROR_MASK_ADDR_PARITY_MASK 0x0000000008000000
6478 /* SH_PI_ERROR_MASK_SHUB_FSB_DQE */
6479 /* Description: SHUB_FSB_DQE */
6480 #define SH_PI_ERROR_MASK_SHUB_FSB_DQE_SHFT 28
6481 #define SH_PI_ERROR_MASK_SHUB_FSB_DQE_MASK 0x0000000010000000
6483 /* SH_PI_ERROR_MASK_SHUB_FSB_UCE */
6484 /* Description: An un-correctable ECC error was detected */
6485 #define SH_PI_ERROR_MASK_SHUB_FSB_UCE_SHFT 29
6486 #define SH_PI_ERROR_MASK_SHUB_FSB_UCE_MASK 0x0000000020000000
6488 /* SH_PI_ERROR_MASK_SHUB_FSB_CE */
6489 /* Description: An correctable ECC error was detected */
6490 #define SH_PI_ERROR_MASK_SHUB_FSB_CE_SHFT 30
6491 #define SH_PI_ERROR_MASK_SHUB_FSB_CE_MASK 0x0000000040000000
6493 /* SH_PI_ERROR_MASK_LIVELOCK */
6494 /* Description: AFI livelock error was detected */
6495 #define SH_PI_ERROR_MASK_LIVELOCK_SHFT 31
6496 #define SH_PI_ERROR_MASK_LIVELOCK_MASK 0x0000000080000000
6498 /* SH_PI_ERROR_MASK_BAD_SNOOP */
6499 /* Description: AFI bad snoop error was detected */
6500 #define SH_PI_ERROR_MASK_BAD_SNOOP_SHFT 32
6501 #define SH_PI_ERROR_MASK_BAD_SNOOP_MASK 0x0000000100000000
6503 /* SH_PI_ERROR_MASK_FSB_TBL_MISS */
6504 /* Description: AFI FSB request table miss error was detected */
6505 #define SH_PI_ERROR_MASK_FSB_TBL_MISS_SHFT 33
6506 #define SH_PI_ERROR_MASK_FSB_TBL_MISS_MASK 0x0000000200000000
6508 /* SH_PI_ERROR_MASK_MSG_LENGTH */
6509 /* Description: Message length error on received message from SIC */
6510 #define SH_PI_ERROR_MASK_MSG_LENGTH_SHFT 34
6511 #define SH_PI_ERROR_MASK_MSG_LENGTH_MASK 0x0000000400000000
6513 /* ==================================================================== */
6514 /* Register "SH_PI_EXPRESS_REPLY_CONFIG" */
6515 /* PI Express Reply Configuration */
6516 /* ==================================================================== */
6518 #define SH_PI_EXPRESS_REPLY_CONFIG 0x0000000120050b00
6519 #define SH_PI_EXPRESS_REPLY_CONFIG_MASK 0x0000000000000007
6520 #define SH_PI_EXPRESS_REPLY_CONFIG_INIT 0x0000000000000001
6522 /* SH_PI_EXPRESS_REPLY_CONFIG_MODE */
6523 /* Description: Express Reply Mode */
6524 #define SH_PI_EXPRESS_REPLY_CONFIG_MODE_SHFT 0
6525 #define SH_PI_EXPRESS_REPLY_CONFIG_MODE_MASK 0x0000000000000007
6527 /* ==================================================================== */
6528 /* Register "SH_PI_FSB_COMPARE_VALUE" */
6529 /* FSB Compare Value */
6530 /* ==================================================================== */
6532 #define SH_PI_FSB_COMPARE_VALUE 0x0000000120050c00
6533 #define SH_PI_FSB_COMPARE_VALUE_MASK 0xffffffffffffffff
6534 #define SH_PI_FSB_COMPARE_VALUE_INIT 0x0000000000000000
6536 /* SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE */
6537 /* Description: Compare value */
6538 #define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_SHFT 0
6539 #define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_MASK 0xffffffffffffffff
6541 /* ==================================================================== */
6542 /* Register "SH_PI_FSB_COMPARE_MASK" */
6543 /* FSB Compare Mask */
6544 /* ==================================================================== */
6546 #define SH_PI_FSB_COMPARE_MASK 0x0000000120050b80
6547 #define SH_PI_FSB_COMPARE_MASK_MASK 0xffffffffffffffff
6548 #define SH_PI_FSB_COMPARE_MASK_INIT 0x0000000000000000
6550 /* SH_PI_FSB_COMPARE_MASK_MASK_VALUE */
6551 /* Description: Mask value */
6552 #define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_SHFT 0
6553 #define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_MASK 0xffffffffffffffff
6555 /* ==================================================================== */
6556 /* Register "SH_PI_FSB_ERROR_INJECTION" */
6557 /* Inject an Error onto the FSB */
6558 /* ==================================================================== */
6560 #define SH_PI_FSB_ERROR_INJECTION 0x0000000120050c80
6561 #define SH_PI_FSB_ERROR_INJECTION_MASK 0x000000070fff03ff
6562 #define SH_PI_FSB_ERROR_INJECTION_INIT 0x0000000000000000
6564 /* SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB */
6565 /* Description: Inject a RP# Parity Error onto the FSB */
6566 #define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_SHFT 0
6567 #define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_MASK 0x0000000000000001
6569 /* SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB */
6570 /* Description: Inject an AP[0]# Parity Error onto the FSB */
6571 #define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_SHFT 1
6572 #define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_MASK 0x0000000000000002
6574 /* SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB */
6575 /* Description: Inject an AP[1]# Parity Error onto the FSB */
6576 #define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_SHFT 2
6577 #define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_MASK 0x0000000000000004
6579 /* SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB */
6580 /* Description: Inject a RSP# Parity Error onto the FSB */
6581 #define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_SHFT 3
6582 #define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_MASK 0x0000000000000008
6584 /* SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB */
6585 /* Description: Inject a Correctable Error in Doubleword 0 onto the */
6586 #define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_SHFT 4
6587 #define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_MASK 0x0000000000000010
6589 /* SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB */
6590 /* Description: Inject an Uncorrectable Error in Doubleword 0 onto */
6592 #define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_SHFT 5
6593 #define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_MASK 0x0000000000000020
6595 /* SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB */
6596 /* Description: Inject a Correctable Error in Doubleword 1 onto the */
6597 #define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_SHFT 6
6598 #define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_MASK 0x0000000000000040
6600 /* SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB */
6601 /* Description: Inject an Uncorrectable Error in Doubleword 1 onto */
6603 #define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_SHFT 7
6604 #define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_MASK 0x0000000000000080
6606 /* SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB */
6607 /* Description: Inject an IP[0]# Parity Error onto the FSB */
6608 #define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_SHFT 8
6609 #define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_MASK 0x0000000000000100
6611 /* SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB */
6612 /* Description: Inject an IP[1]# Parity Error onto the FSB */
6613 #define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_SHFT 9
6614 #define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_MASK 0x0000000000000200
6616 /* SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB */
6617 /* Description: Inject a RP# Parity Error When Sampling the FSB */
6618 #define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_SHFT 16
6619 #define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_MASK 0x0000000000010000
6621 /* SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB */
6622 /* Description: Inject an AP[0]# Parity Error When Sampling the FSB */
6623 #define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_SHFT 17
6624 #define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_MASK 0x0000000000020000
6626 /* SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB */
6627 /* Description: Inject an AP[1]# Parity Error When Sampling the FSB */
6628 #define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_SHFT 18
6629 #define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_MASK 0x0000000000040000
6631 /* SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB */
6632 /* Description: Inject a RSP# Parity Error When Sampling the FSB */
6633 #define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_SHFT 19
6634 #define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_MASK 0x0000000000080000
6636 /* SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB */
6637 /* Description: Inject a Correctable Error in Doubleword 0 of SIC D */
6639 #define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_SHFT 20
6640 #define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_MASK 0x0000000000100000
6642 /* SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB */
6643 /* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */
6645 #define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_SHFT 21
6646 #define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_MASK 0x0000000000200000
6648 /* SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB */
6649 /* Description: Inject a Correctable Error in Doubleword 0 of SIC D */
6651 #define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_SHFT 22
6652 #define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_MASK 0x0000000000400000
6654 /* SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB */
6655 /* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */
6657 #define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_SHFT 23
6658 #define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_MASK 0x0000000000800000
6660 /* SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB */
6661 /* Description: Inject a Correctable Error in Doubleword 0 of SIC D */
6663 #define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_SHFT 24
6664 #define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_MASK 0x0000000001000000
6666 /* SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB */
6667 /* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */
6669 #define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_SHFT 25
6670 #define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_MASK 0x0000000002000000
6672 /* SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB */
6673 /* Description: Inject a Correctable Error in Doubleword 0 of SIC D */
6675 #define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_SHFT 26
6676 #define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_MASK 0x0000000004000000
6678 /* SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB */
6679 /* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */
6681 #define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_SHFT 27
6682 #define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_MASK 0x0000000008000000
6684 /* SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN */
6685 /* Description: Inject an ioq overrun Error on the FSB */
6686 #define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_SHFT 32
6687 #define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_MASK 0x0000000100000000
6689 /* SH_PI_FSB_ERROR_INJECTION_LIVELOCK */
6690 /* Description: Inject a livelock Error on the FSB */
6691 #define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_SHFT 33
6692 #define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_MASK 0x0000000200000000
6694 /* SH_PI_FSB_ERROR_INJECTION_BUS_HANG */
6695 /* Description: Inject an bus hang on the FSB */
6696 #define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_SHFT 34
6697 #define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_MASK 0x0000000400000000
6699 /* ==================================================================== */
6700 /* Register "SH_PI_MD2PI_REPLY_VC_CONFIG" */
6701 /* MD-to-PI Reply Virtual Channel Configuration */
6702 /* ==================================================================== */
6704 #define SH_PI_MD2PI_REPLY_VC_CONFIG 0x0000000120050d00
6705 #define SH_PI_MD2PI_REPLY_VC_CONFIG_MASK 0xc000000000003fff
6706 #define SH_PI_MD2PI_REPLY_VC_CONFIG_INIT 0x000000000000088c
6708 /* SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH */
6709 /* Description: Depth of header Buffer */
6710 #define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0
6711 #define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
6713 /* SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH */
6714 /* Description: Number of data buffers Available */
6715 #define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4
6716 #define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
6718 /* SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS */
6719 /* Description: Maximum credits from sender */
6720 #define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8
6721 #define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
6723 /* SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT */
6724 /* Description: Send an extra credit to sender */
6725 #define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62
6726 #define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
6728 /* SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS */
6729 /* Description: Capture credit and status information */
6730 #define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
6731 #define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
6733 /* ==================================================================== */
6734 /* Register "SH_PI_MD2PI_REQUEST_VC_CONFIG" */
6735 /* MD-to-PI Request Virtual Channel Configuration */
6736 /* ==================================================================== */
6738 #define SH_PI_MD2PI_REQUEST_VC_CONFIG 0x0000000120050d80
6739 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_MASK 0xc000000000003fff
6740 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_INIT 0x000000000000088c
6742 /* SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH */
6743 /* Description: Depth of header Buffer */
6744 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0
6745 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
6747 /* SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH */
6748 /* Description: Number of data buffers Available */
6749 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4
6750 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
6752 /* SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS */
6753 /* Description: Maximum credits from sender */
6754 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8
6755 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
6757 /* SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT */
6758 /* Description: Send an extra credit to sender */
6759 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62
6760 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
6762 /* SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS */
6763 /* Description: Capture credit and status information */
6764 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
6765 #define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
6767 /* ==================================================================== */
6768 /* Register "SH_PI_QUEUE_ERROR_INJECTION" */
6769 /* PI Queue Error Injection */
6770 /* ==================================================================== */
6772 #define SH_PI_QUEUE_ERROR_INJECTION 0x0000000120050e00
6773 #define SH_PI_QUEUE_ERROR_INJECTION_MASK 0x00000000000000ff
6774 #define SH_PI_QUEUE_ERROR_INJECTION_INIT 0x0000000000000000
6776 /* SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q */
6777 #define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_SHFT 0
6778 #define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_MASK 0x0000000000000001
6780 /* SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q */
6781 #define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_SHFT 1
6782 #define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_MASK 0x0000000000000002
6784 /* SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q */
6785 #define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_SHFT 2
6786 #define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_MASK 0x0000000000000004
6788 /* SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR */
6789 #define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_SHFT 3
6790 #define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_MASK 0x0000000000000008
6792 /* SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR */
6793 #define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_SHFT 4
6794 #define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_MASK 0x0000000000000010
6796 /* SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q */
6797 #define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_SHFT 5
6798 #define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_MASK 0x0000000000000020
6800 /* SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q */
6801 #define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_SHFT 6
6802 #define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_MASK 0x0000000000000040
6804 /* SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR */
6805 #define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_SHFT 7
6806 #define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_MASK 0x0000000000000080
6808 /* ==================================================================== */
6809 /* Register "SH_PI_TEST_POINT_COMPARE" */
6810 /* PI Test Point Compare */
6811 /* ==================================================================== */
6813 #define SH_PI_TEST_POINT_COMPARE 0x0000000120050e80
6814 #define SH_PI_TEST_POINT_COMPARE_MASK 0xffffffffffffffff
6815 #define SH_PI_TEST_POINT_COMPARE_INIT 0xffffffff00000000
6817 /* SH_PI_TEST_POINT_COMPARE_COMPARE_MASK */
6818 /* Description: Mask to select test point data for trigger generati */
6819 #define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
6820 #define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
6822 /* SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN */
6823 /* Description: Pattern of test point data to cause trigger */
6824 #define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
6825 #define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
6827 /* ==================================================================== */
6828 /* Register "SH_PI_TEST_POINT_SELECT" */
6829 /* PI Test Point Select */
6830 /* ==================================================================== */
6832 #define SH_PI_TEST_POINT_SELECT 0x0000000120050f00
6833 #define SH_PI_TEST_POINT_SELECT_MASK 0xf777777777777777
6834 #define SH_PI_TEST_POINT_SELECT_INIT 0x0000000000000000
6836 /* SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */
6837 /* Description: Nibble 0 data is from Chiplet X */
6838 #define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
6839 #define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
6841 /* SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */
6842 /* Description: Nibble X is routed to Nibble 0 */
6843 #define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
6844 #define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
6846 /* SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */
6847 /* Description: Nibble 1 data is from Chiplet X */
6848 #define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
6849 #define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
6851 /* SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */
6852 /* Description: Nibble X is routed to Nibble 1 */
6853 #define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
6854 #define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
6856 /* SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */
6857 /* Description: Nibble 2 data is from Chiplet X */
6858 #define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
6859 #define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
6861 /* SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */
6862 /* Description: Nibble X is routed to Nibble 2 */
6863 #define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
6864 #define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
6866 /* SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */
6867 /* Description: Nibble 3 data is from Chiplet X */
6868 #define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
6869 #define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
6871 /* SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */
6872 /* Description: Nibble X is routed to Nibble 3 */
6873 #define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
6874 #define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
6876 /* SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */
6877 /* Description: Nibble 4 data is from Chiplet X */
6878 #define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
6879 #define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
6881 /* SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */
6882 /* Description: Nibble X is routed to Nibble 4 */
6883 #define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
6884 #define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
6886 /* SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */
6887 /* Description: Nibble 5 data is from Chiplet X */
6888 #define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
6889 #define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
6891 /* SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */
6892 /* Description: Nibble X is routed to Nibble 5 */
6893 #define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
6894 #define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
6896 /* SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */
6897 /* Description: Nibble 6 data is from Chiplet X */
6898 #define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
6899 #define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
6901 /* SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */
6902 /* Description: Nibble X is routed to Nibble 6 */
6903 #define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
6904 #define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
6906 /* SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */
6907 /* Description: Nibble 7 data is from Chiplet X */
6908 #define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
6909 #define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
6911 /* SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */
6912 /* Description: Nibble X is routed to Nibble 7 */
6913 #define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
6914 #define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
6916 /* SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE */
6917 /* Description: Enable trigger on bit 32 of Analyzer data */
6918 #define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
6919 #define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
6921 /* ==================================================================== */
6922 /* Register "SH_PI_TEST_POINT_TRIGGER_SELECT" */
6923 /* PI Test Point Trigger Select */
6924 /* ==================================================================== */
6926 #define SH_PI_TEST_POINT_TRIGGER_SELECT 0x0000000120050f80
6927 #define SH_PI_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777
6928 #define SH_PI_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000
6930 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */
6931 /* Description: Nibble 0 Chiplet select */
6932 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
6933 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
6935 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */
6936 /* Description: Nibble 0 Nibble select */
6937 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
6938 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
6940 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */
6941 /* Description: Nibble 1 Chiplet select */
6942 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
6943 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
6945 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */
6946 /* Description: Nibble 1 Nibble select */
6947 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
6948 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
6950 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */
6951 /* Description: Nibble 2 Chiplet select */
6952 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
6953 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
6955 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */
6956 /* Description: Nibble 2 Nibble select */
6957 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
6958 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
6960 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */
6961 /* Description: Nibble 3 Chiplet select */
6962 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
6963 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
6965 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */
6966 /* Description: Nibble 3 Nibble select */
6967 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
6968 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
6970 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */
6971 /* Description: Nibble 4 Chiplet select */
6972 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
6973 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
6975 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */
6976 /* Description: Nibble 4 Nibble select */
6977 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
6978 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
6980 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */
6981 /* Description: Nibble 5 Chiplet select */
6982 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
6983 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
6985 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */
6986 /* Description: Nibble 5 Nibble select */
6987 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
6988 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
6990 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */
6991 /* Description: Nibble 6 Chiplet select */
6992 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
6993 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
6995 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */
6996 /* Description: Nibble 6 Nibble select */
6997 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
6998 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
7000 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */
7001 /* Description: Nibble 7 Chiplet select */
7002 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
7003 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
7005 /* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */
7006 /* Description: Nibble 7 Nibble select */
7007 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
7008 #define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
7010 /* ==================================================================== */
7011 /* Register "SH_PI_XN2PI_REPLY_VC_CONFIG" */
7012 /* XN-to-PI Reply Virtual Channel Configuration */
7013 /* ==================================================================== */
7015 #define SH_PI_XN2PI_REPLY_VC_CONFIG 0x0000000120051000
7016 #define SH_PI_XN2PI_REPLY_VC_CONFIG_MASK 0xc000000000003fff
7017 #define SH_PI_XN2PI_REPLY_VC_CONFIG_INIT 0x000000000000068c
7019 /* SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH */
7020 /* Description: Depth of header Buffer */
7021 #define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0
7022 #define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
7024 /* SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH */
7025 /* Description: Number of data buffers Available */
7026 #define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4
7027 #define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
7029 /* SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS */
7030 /* Description: Maximum credits from sender */
7031 #define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8
7032 #define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
7034 /* SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT */
7035 /* Description: Send an extra credit to sender */
7036 #define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62
7037 #define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
7039 /* SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS */
7040 /* Description: Capture credit and status information */
7041 #define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
7042 #define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
7044 /* ==================================================================== */
7045 /* Register "SH_PI_XN2PI_REQUEST_VC_CONFIG" */
7046 /* XN-to-PI Request Virtual Channel Configuration */
7047 /* ==================================================================== */
7049 #define SH_PI_XN2PI_REQUEST_VC_CONFIG 0x0000000120051080
7050 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_MASK 0xc000000000003fff
7051 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_INIT 0x000000000000068c
7053 /* SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH */
7054 /* Description: Depth of header Buffer */
7055 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0
7056 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
7058 /* SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH */
7059 /* Description: Number of data buffers Available */
7060 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4
7061 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
7063 /* SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS */
7064 /* Description: Maximum credits from sender */
7065 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8
7066 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
7068 /* SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT */
7069 /* Description: Send an extra credit to sender */
7070 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62
7071 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
7073 /* SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS */
7074 /* Description: Capture credit and status information */
7075 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
7076 #define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
7078 /* ==================================================================== */
7079 /* Register "SH_PI_AEC_STATUS" */
7080 /* PI Adaptive Error Correction Status */
7081 /* ==================================================================== */
7083 #define SH_PI_AEC_STATUS 0x0000000120060000
7084 #define SH_PI_AEC_STATUS_MASK 0x0000000000000007
7085 #define SH_PI_AEC_STATUS_INIT 0x0000000000000000
7087 /* SH_PI_AEC_STATUS_STATE */
7088 /* Description: AEC State */
7089 #define SH_PI_AEC_STATUS_STATE_SHFT 0
7090 #define SH_PI_AEC_STATUS_STATE_MASK 0x0000000000000007
7092 /* ==================================================================== */
7093 /* Register "SH_PI_AFI_FIRST_ERROR" */
7094 /* PI AFI First Error */
7095 /* ==================================================================== */
7097 #define SH_PI_AFI_FIRST_ERROR 0x0000000120060080
7098 #define SH_PI_AFI_FIRST_ERROR_MASK 0x00000007ffe00180
7099 #define SH_PI_AFI_FIRST_ERROR_INIT 0x0000000000000000
7101 /* SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE */
7102 /* Description: An un-correctable ECC error was detected */
7103 #define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7
7104 #define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080
7106 /* SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE */
7107 /* Description: A correctable ECC error was detected */
7108 #define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_SHFT 8
7109 #define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100
7111 /* SH_PI_AFI_FIRST_ERROR_HUNG_BUS */
7112 /* Description: FSB is hung */
7113 #define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_SHFT 21
7114 #define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_MASK 0x0000000000200000
7116 /* SH_PI_AFI_FIRST_ERROR_RSP_PARITY */
7117 /* Description: Parity error detecte during response phase */
7118 #define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_SHFT 22
7119 #define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_MASK 0x0000000000400000
7121 /* SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN */
7122 /* Description: Over run error detected on IOQ */
7123 #define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_SHFT 23
7124 #define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_MASK 0x0000000000800000
7126 /* SH_PI_AFI_FIRST_ERROR_REQ_FORMAT */
7127 /* Description: FSB request format not supported */
7128 #define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_SHFT 24
7129 #define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_MASK 0x0000000001000000
7131 /* SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS */
7132 /* Description: Access to Address is not supported */
7133 #define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_SHFT 25
7134 #define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_MASK 0x0000000002000000
7136 /* SH_PI_AFI_FIRST_ERROR_REQ_PARITY */
7137 /* Description: Parity error detected during request phase */
7138 #define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_SHFT 26
7139 #define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_MASK 0x0000000004000000
7141 /* SH_PI_AFI_FIRST_ERROR_ADDR_PARITY */
7142 /* Description: Parity error detected on address */
7143 #define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_SHFT 27
7144 #define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_MASK 0x0000000008000000
7146 /* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE */
7147 /* Description: SHUB_FSB_DQE */
7148 #define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_SHFT 28
7149 #define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_MASK 0x0000000010000000
7151 /* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE */
7152 /* Description: An un-correctable ECC error was detected */
7153 #define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_SHFT 29
7154 #define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_MASK 0x0000000020000000
7156 /* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE */
7157 /* Description: An correctable ECC error was detected */
7158 #define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_SHFT 30
7159 #define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_MASK 0x0000000040000000
7161 /* SH_PI_AFI_FIRST_ERROR_LIVELOCK */
7162 /* Description: AFI livelock error was detected */
7163 #define SH_PI_AFI_FIRST_ERROR_LIVELOCK_SHFT 31
7164 #define SH_PI_AFI_FIRST_ERROR_LIVELOCK_MASK 0x0000000080000000
7166 /* SH_PI_AFI_FIRST_ERROR_BAD_SNOOP */
7167 /* Description: AFI bad snoop error was detected */
7168 #define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_SHFT 32
7169 #define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_MASK 0x0000000100000000
7171 /* SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS */
7172 /* Description: AFI FSB request table miss error was detected */
7173 #define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_SHFT 33
7174 #define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_MASK 0x0000000200000000
7176 /* SH_PI_AFI_FIRST_ERROR_MSG_LEN */
7177 /* Description: Runt or Obese message received from SIC */
7178 #define SH_PI_AFI_FIRST_ERROR_MSG_LEN_SHFT 34
7179 #define SH_PI_AFI_FIRST_ERROR_MSG_LEN_MASK 0x0000000400000000
7181 /* ==================================================================== */
7182 /* Register "SH_PI_CAM_ADDRESS_READ_DATA" */
7183 /* CRB CAM MMR Address Read Data */
7184 /* ==================================================================== */
7186 #define SH_PI_CAM_ADDRESS_READ_DATA 0x0000000120060100
7187 #define SH_PI_CAM_ADDRESS_READ_DATA_MASK 0x8000ffffffffffff
7188 #define SH_PI_CAM_ADDRESS_READ_DATA_INIT 0x0000000000000000
7190 /* SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR */
7191 /* Description: CRB CAM Address Read Data. */
7192 #define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_SHFT 0
7193 #define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_MASK 0x0000ffffffffffff
7195 /* SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL */
7196 /* Description: CRB CAM Address Read Data Valid. */
7197 #define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_SHFT 63
7198 #define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_MASK 0x8000000000000000
7200 /* ==================================================================== */
7201 /* Register "SH_PI_CAM_LPRA_READ_DATA" */
7202 /* CRB CAM MMR LPRA Read Data */
7203 /* ==================================================================== */
7205 #define SH_PI_CAM_LPRA_READ_DATA 0x0000000120060180
7206 #define SH_PI_CAM_LPRA_READ_DATA_MASK 0xffffffffffffffff
7207 #define SH_PI_CAM_LPRA_READ_DATA_INIT 0x0000000000000000
7209 /* SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA */
7210 /* Description: CRB CAM LPRA read data. */
7211 #define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_SHFT 0
7212 #define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_MASK 0xffffffffffffffff
7214 /* ==================================================================== */
7215 /* Register "SH_PI_CAM_STATE_READ_DATA" */
7216 /* CRB CAM MMR State Read Data */
7217 /* ==================================================================== */
7219 #define SH_PI_CAM_STATE_READ_DATA 0x0000000120060200
7220 #define SH_PI_CAM_STATE_READ_DATA_MASK 0x8003ffff0000003f
7221 #define SH_PI_CAM_STATE_READ_DATA_INIT 0x0000000000000000
7223 /* SH_PI_CAM_STATE_READ_DATA_CAM_STATE */
7224 /* Description: CRB CAM State read data. */
7225 #define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_SHFT 0
7226 #define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_MASK 0x000000000000000f
7228 /* SH_PI_CAM_STATE_READ_DATA_CAM_TO */
7229 /* Description: CRB CAM Time-out Status. */
7230 #define SH_PI_CAM_STATE_READ_DATA_CAM_TO_SHFT 4
7231 #define SH_PI_CAM_STATE_READ_DATA_CAM_TO_MASK 0x0000000000000010
7233 /* SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND */
7234 /* Description: CRB CAM State Read Pending. */
7235 #define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_SHFT 5
7236 #define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_MASK 0x0000000000000020
7238 /* SH_PI_CAM_STATE_READ_DATA_CAM_LPRA */
7239 /* Description: CRB LPRA Overflow Data. */
7240 #define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_SHFT 32
7241 #define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_MASK 0x0003ffff00000000
7243 /* SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL */
7244 /* Description: CRB CAM MMR read data is valid. */
7245 #define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_SHFT 63
7246 #define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_MASK 0x8000000000000000
7248 /* ==================================================================== */
7249 /* Register "SH_PI_CORRECTED_DETAIL_1" */
7250 /* PI Corrected Error Detail */
7251 /* ==================================================================== */
7253 #define SH_PI_CORRECTED_DETAIL_1 0x0000000120060280
7254 #define SH_PI_CORRECTED_DETAIL_1_MASK 0xffffffffffffffff
7255 #define SH_PI_CORRECTED_DETAIL_1_INIT 0x0000000000000000
7257 /* SH_PI_CORRECTED_DETAIL_1_ADDRESS */
7258 /* Description: Address of Message that logged Correctable Error */
7259 #define SH_PI_CORRECTED_DETAIL_1_ADDRESS_SHFT 0
7260 #define SH_PI_CORRECTED_DETAIL_1_ADDRESS_MASK 0x0000ffffffffffff
7262 /* SH_PI_CORRECTED_DETAIL_1_SYNDROME */
7263 /* Description: Syndrome for double word data with Correctable Erro */
7264 #define SH_PI_CORRECTED_DETAIL_1_SYNDROME_SHFT 48
7265 #define SH_PI_CORRECTED_DETAIL_1_SYNDROME_MASK 0x00ff000000000000
7267 /* SH_PI_CORRECTED_DETAIL_1_DEP */
7268 /* Description: DEP code for Double word in error */
7269 #define SH_PI_CORRECTED_DETAIL_1_DEP_SHFT 56
7270 #define SH_PI_CORRECTED_DETAIL_1_DEP_MASK 0xff00000000000000
7272 /* ==================================================================== */
7273 /* Register "SH_PI_CORRECTED_DETAIL_2" */
7274 /* PI Corrected Error Detail 2 */
7275 /* ==================================================================== */
7277 #define SH_PI_CORRECTED_DETAIL_2 0x0000000120060300
7278 #define SH_PI_CORRECTED_DETAIL_2_MASK 0xffffffffffffffff
7279 #define SH_PI_CORRECTED_DETAIL_2_INIT 0x0000000000000000
7281 /* SH_PI_CORRECTED_DETAIL_2_DATA */
7282 /* Description: Double word data in error */
7283 #define SH_PI_CORRECTED_DETAIL_2_DATA_SHFT 0
7284 #define SH_PI_CORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff
7286 /* ==================================================================== */
7287 /* Register "SH_PI_CORRECTED_DETAIL_3" */
7288 /* PI Corrected Error Detail 3 */
7289 /* ==================================================================== */
7291 #define SH_PI_CORRECTED_DETAIL_3 0x0000000120060380
7292 #define SH_PI_CORRECTED_DETAIL_3_MASK 0xffffffffffffffff
7293 #define SH_PI_CORRECTED_DETAIL_3_INIT 0x0000000000000000
7295 /* SH_PI_CORRECTED_DETAIL_3_ADDRESS */
7296 /* Description: Address of Message that logged Correctable Error */
7297 #define SH_PI_CORRECTED_DETAIL_3_ADDRESS_SHFT 0
7298 #define SH_PI_CORRECTED_DETAIL_3_ADDRESS_MASK 0x0000ffffffffffff
7300 /* SH_PI_CORRECTED_DETAIL_3_SYNDROME */
7301 /* Description: Syndrome for double word data with Correctable Erro */
7302 #define SH_PI_CORRECTED_DETAIL_3_SYNDROME_SHFT 48
7303 #define SH_PI_CORRECTED_DETAIL_3_SYNDROME_MASK 0x00ff000000000000
7305 /* SH_PI_CORRECTED_DETAIL_3_DEP */
7306 /* Description: DEP code for Double word in error */
7307 #define SH_PI_CORRECTED_DETAIL_3_DEP_SHFT 56
7308 #define SH_PI_CORRECTED_DETAIL_3_DEP_MASK 0xff00000000000000
7310 /* ==================================================================== */
7311 /* Register "SH_PI_CORRECTED_DETAIL_4" */
7312 /* PI Corrected Error Detail 4 */
7313 /* ==================================================================== */
7315 #define SH_PI_CORRECTED_DETAIL_4 0x0000000120060400
7316 #define SH_PI_CORRECTED_DETAIL_4_MASK 0xffffffffffffffff
7317 #define SH_PI_CORRECTED_DETAIL_4_INIT 0x0000000000000000
7319 /* SH_PI_CORRECTED_DETAIL_4_DATA */
7320 /* Description: Double word data in error */
7321 #define SH_PI_CORRECTED_DETAIL_4_DATA_SHFT 0
7322 #define SH_PI_CORRECTED_DETAIL_4_DATA_MASK 0xffffffffffffffff
7324 /* ==================================================================== */
7325 /* Register "SH_PI_CRBP_FIRST_ERROR" */
7326 /* PI CRBP First Error */
7327 /* ==================================================================== */
7329 #define SH_PI_CRBP_FIRST_ERROR 0x0000000120060480
7330 #define SH_PI_CRBP_FIRST_ERROR_MASK 0x00000000001fffff
7331 #define SH_PI_CRBP_FIRST_ERROR_INIT 0x0000000000000000
7333 /* SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR */
7334 /* Description: CRB's FSB pipe detected protocol table miss */
7335 #define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_SHFT 0
7336 #define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_MASK 0x0000000000000001
7338 /* SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR */
7339 /* Description: CRB's XB pipe received a GFX error reply */
7340 #define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_SHFT 1
7341 #define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_MASK 0x0000000000000002
7343 /* SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR */
7344 /* Description: CRB's XB pipe detected protocol table miss */
7345 #define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_SHFT 2
7346 #define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_MASK 0x0000000000000004
7348 /* SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR */
7349 /* Description: CRB's XB pipe received a memory error reply message */
7350 #define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_SHFT 3
7351 #define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_MASK 0x0000000000000008
7353 /* SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR */
7354 /* Description: CRB's XB pipe received a PIO error reply message */
7355 #define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_SHFT 4
7356 #define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_MASK 0x0000000000000010
7358 /* SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR */
7359 /* Description: CRB's XB pipe detected a CRB time-out */
7360 #define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_SHFT 5
7361 #define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_MASK 0x0000000000000020
7363 /* SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR */
7364 /* Description: CRB's XB pipe detected a PIO time-out */
7365 #define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_SHFT 6
7366 #define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_MASK 0x0000000000000040
7368 /* SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE */
7369 /* Description: An un-correctable ECC error was detected */
7370 #define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7
7371 #define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080
7373 /* SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE */
7374 /* Description: A correctable ECC error was detected */
7375 #define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_SHFT 8
7376 #define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100
7378 /* SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR */
7379 /* Description: Message color was wrong */
7380 #define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_SHFT 9
7381 #define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_MASK 0x0000000000000200
7383 /* SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW */
7384 /* Description: MD Request input buffer over flow error */
7385 #define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT 10
7386 #define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK 0x0000000000000400
7388 /* SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW */
7389 /* Description: MD Reply input buffer over flow error */
7390 #define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT 11
7391 #define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_MASK 0x0000000000000800
7393 /* SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW */
7394 /* Description: XN Request input buffer over flow error */
7395 #define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT 12
7396 #define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK 0x0000000000001000
7398 /* SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW */
7399 /* Description: XN Reply input buffer over flow error */
7400 #define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT 13
7401 #define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_MASK 0x0000000000002000
7403 /* SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW */
7404 /* Description: NACK over flow error */
7405 #define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_SHFT 14
7406 #define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_MASK 0x0000000000004000
7408 /* SH_PI_CRBP_FIRST_ERROR_GFX_INT_0 */
7409 /* Description: GFX transfer interrupt for CPU 0 */
7410 #define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_SHFT 15
7411 #define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_MASK 0x0000000000008000
7413 /* SH_PI_CRBP_FIRST_ERROR_GFX_INT_1 */
7414 /* Description: GFX transfer interrupt for CPU 1 */
7415 #define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_SHFT 16
7416 #define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_MASK 0x0000000000010000
7418 /* SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW */
7419 /* Description: MD Request Credit Overflow Error */
7420 #define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT 17
7421 #define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
7423 /* SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW */
7424 /* Description: MD Reply Credit Overflow Error */
7425 #define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT 18
7426 #define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
7428 /* SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW */
7429 /* Description: XN Request Credit Overflow Error */
7430 #define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT 19
7431 #define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
7433 /* SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW */
7434 /* Description: XN Reply Credit Overflow Error */
7435 #define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT 20
7436 #define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
7438 /* ==================================================================== */
7439 /* Register "SH_PI_ERROR_DETAIL_1" */
7440 /* PI Error Detail 1 */
7441 /* ==================================================================== */
7443 #define SH_PI_ERROR_DETAIL_1 0x0000000120060500
7444 #define SH_PI_ERROR_DETAIL_1_MASK 0xffffffffffffffff
7445 #define SH_PI_ERROR_DETAIL_1_INIT 0x0000000000000000
7447 /* SH_PI_ERROR_DETAIL_1_STATUS */
7448 /* Description: Error Detail 1 */
7449 #define SH_PI_ERROR_DETAIL_1_STATUS_SHFT 0
7450 #define SH_PI_ERROR_DETAIL_1_STATUS_MASK 0xffffffffffffffff
7452 /* ==================================================================== */
7453 /* Register "SH_PI_ERROR_DETAIL_2" */
7454 /* PI Error Detail 2 */
7455 /* ==================================================================== */
7457 #define SH_PI_ERROR_DETAIL_2 0x0000000120060580
7458 #define SH_PI_ERROR_DETAIL_2_MASK 0xffffffffffffffff
7459 #define SH_PI_ERROR_DETAIL_2_INIT 0x0000000000000000
7461 /* SH_PI_ERROR_DETAIL_2_STATUS */
7462 /* Description: Error Status */
7463 #define SH_PI_ERROR_DETAIL_2_STATUS_SHFT 0
7464 #define SH_PI_ERROR_DETAIL_2_STATUS_MASK 0xffffffffffffffff
7466 /* ==================================================================== */
7467 /* Register "SH_PI_ERROR_OVERFLOW" */
7468 /* PI Error Overflow */
7469 /* ==================================================================== */
7471 #define SH_PI_ERROR_OVERFLOW 0x0000000120060600
7472 #define SH_PI_ERROR_OVERFLOW_MASK 0x00000007ffffffff
7473 #define SH_PI_ERROR_OVERFLOW_INIT 0x0000000000000000
7475 /* SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR */
7476 /* Description: CRB's FSB pipe detected protocol table miss */
7477 #define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_SHFT 0
7478 #define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_MASK 0x0000000000000001
7480 /* SH_PI_ERROR_OVERFLOW_GFX_RP_ERR */
7481 /* Description: CRB's XB pipe received another GFX reply error mess */
7482 #define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_SHFT 1
7483 #define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_MASK 0x0000000000000002
7485 /* SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR */
7486 /* Description: CRB's XB pipe detected another protocol table miss */
7487 #define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_SHFT 2
7488 #define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_MASK 0x0000000000000004
7490 /* SH_PI_ERROR_OVERFLOW_MEM_RP_ERR */
7491 /* Description: CRB's XB pipe received another memory reply error m */
7492 #define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_SHFT 3
7493 #define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_MASK 0x0000000000000008
7495 /* SH_PI_ERROR_OVERFLOW_PIO_RP_ERR */
7496 /* Description: CRB's XB pipe received another PIO reply error mess */
7497 #define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_SHFT 4
7498 #define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_MASK 0x0000000000000010
7500 /* SH_PI_ERROR_OVERFLOW_MEM_TO_ERR */
7501 /* Description: CRB's XB pipe detected a CRB time-out */
7502 #define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_SHFT 5
7503 #define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_MASK 0x0000000000000020
7505 /* SH_PI_ERROR_OVERFLOW_PIO_TO_ERR */
7506 /* Description: CRB's XB pipe detected a PIO time-out */
7507 #define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_SHFT 6
7508 #define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_MASK 0x0000000000000040
7510 /* SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE */
7511 /* Description: An un-correctable ECC error was detected */
7512 #define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_SHFT 7
7513 #define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_MASK 0x0000000000000080
7515 /* SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE */
7516 /* Description: An correctable ECC error was detected */
7517 #define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_SHFT 8
7518 #define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_MASK 0x0000000000000100
7520 /* SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR */
7521 /* Description: Message color was not correct */
7522 #define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_SHFT 9
7523 #define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_MASK 0x0000000000000200
7525 /* SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW */
7526 /* Description: MD Request input buffer over flow error */
7527 #define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_SHFT 10
7528 #define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_MASK 0x0000000000000400
7530 /* SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW */
7531 /* Description: MD Reply input buffer over flow error */
7532 #define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_SHFT 11
7533 #define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_MASK 0x0000000000000800
7535 /* SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW */
7536 /* Description: XN Request input buffer over flow error */
7537 #define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_SHFT 12
7538 #define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_MASK 0x0000000000001000
7540 /* SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW */
7541 /* Description: XN Reply input buffer over flow error */
7542 #define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_SHFT 13
7543 #define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_MASK 0x0000000000002000
7545 /* SH_PI_ERROR_OVERFLOW_NACK_OFLOW */
7546 /* Description: NACK over flow error */
7547 #define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_SHFT 14
7548 #define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_MASK 0x0000000000004000
7550 /* SH_PI_ERROR_OVERFLOW_GFX_INT_0 */
7551 /* Description: GFX transfer interrupt for CPU 0 */
7552 #define SH_PI_ERROR_OVERFLOW_GFX_INT_0_SHFT 15
7553 #define SH_PI_ERROR_OVERFLOW_GFX_INT_0_MASK 0x0000000000008000
7555 /* SH_PI_ERROR_OVERFLOW_GFX_INT_1 */
7556 /* Description: GFX transfer interrupt for CPU 1 */
7557 #define SH_PI_ERROR_OVERFLOW_GFX_INT_1_SHFT 16
7558 #define SH_PI_ERROR_OVERFLOW_GFX_INT_1_MASK 0x0000000000010000
7560 /* SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW */
7561 /* Description: MD Request Credit Overflow Error */
7562 #define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_SHFT 17
7563 #define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
7565 /* SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW */
7566 /* Description: MD Reply Credit Overflow Error */
7567 #define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_SHFT 18
7568 #define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
7570 /* SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW */
7571 /* Description: XN Request Credit Overflow Error */
7572 #define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_SHFT 19
7573 #define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
7575 /* SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW */
7576 /* Description: XN Reply Credit Overflow Error */
7577 #define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_SHFT 20
7578 #define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
7580 /* SH_PI_ERROR_OVERFLOW_HUNG_BUS */
7581 /* Description: FSB is hung */
7582 #define SH_PI_ERROR_OVERFLOW_HUNG_BUS_SHFT 21
7583 #define SH_PI_ERROR_OVERFLOW_HUNG_BUS_MASK 0x0000000000200000
7585 /* SH_PI_ERROR_OVERFLOW_RSP_PARITY */
7586 /* Description: Parity error detecte during response phase */
7587 #define SH_PI_ERROR_OVERFLOW_RSP_PARITY_SHFT 22
7588 #define SH_PI_ERROR_OVERFLOW_RSP_PARITY_MASK 0x0000000000400000
7590 /* SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN */
7591 /* Description: Over run error detected on IOQ */
7592 #define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_SHFT 23
7593 #define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_MASK 0x0000000000800000
7595 /* SH_PI_ERROR_OVERFLOW_REQ_FORMAT */
7596 /* Description: FSB request format not supported */
7597 #define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_SHFT 24
7598 #define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_MASK 0x0000000001000000
7600 /* SH_PI_ERROR_OVERFLOW_ADDR_ACCESS */
7601 /* Description: Access to Address is not supported */
7602 #define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_SHFT 25
7603 #define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_MASK 0x0000000002000000
7605 /* SH_PI_ERROR_OVERFLOW_REQ_PARITY */
7606 /* Description: Parity error detected during request phase */
7607 #define SH_PI_ERROR_OVERFLOW_REQ_PARITY_SHFT 26
7608 #define SH_PI_ERROR_OVERFLOW_REQ_PARITY_MASK 0x0000000004000000
7610 /* SH_PI_ERROR_OVERFLOW_ADDR_PARITY */
7611 /* Description: Parity error detected on address */
7612 #define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_SHFT 27
7613 #define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_MASK 0x0000000008000000
7615 /* SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE */
7616 /* Description: SHUB_FSB_DQE */
7617 #define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_SHFT 28
7618 #define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_MASK 0x0000000010000000
7620 /* SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE */
7621 /* Description: An un-correctable ECC error was detected */
7622 #define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_SHFT 29
7623 #define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_MASK 0x0000000020000000
7625 /* SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE */
7626 /* Description: An correctable ECC error was detected */
7627 #define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_SHFT 30
7628 #define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_MASK 0x0000000040000000
7630 /* SH_PI_ERROR_OVERFLOW_LIVELOCK */
7631 /* Description: AFI livelock error was detected */
7632 #define SH_PI_ERROR_OVERFLOW_LIVELOCK_SHFT 31
7633 #define SH_PI_ERROR_OVERFLOW_LIVELOCK_MASK 0x0000000080000000
7635 /* SH_PI_ERROR_OVERFLOW_BAD_SNOOP */
7636 /* Description: AFI bad snoop error was detected */
7637 #define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_SHFT 32
7638 #define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_MASK 0x0000000100000000
7640 /* SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS */
7641 /* Description: AFI FSB request table miss error was detected */
7642 #define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_SHFT 33
7643 #define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_MASK 0x0000000200000000
7645 /* SH_PI_ERROR_OVERFLOW_MSG_LENGTH */
7646 /* Description: Message length error on received message from SIC */
7647 #define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_SHFT 34
7648 #define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_MASK 0x0000000400000000
7650 /* ==================================================================== */
7651 /* Register "SH_PI_ERROR_OVERFLOW_ALIAS" */
7652 /* PI Error Overflow Alias */
7653 /* ==================================================================== */
7655 #define SH_PI_ERROR_OVERFLOW_ALIAS 0x0000000120060608
7657 /* ==================================================================== */
7658 /* Register "SH_PI_ERROR_SUMMARY" */
7659 /* PI Error Summary */
7660 /* ==================================================================== */
7662 #define SH_PI_ERROR_SUMMARY 0x0000000120060680
7663 #define SH_PI_ERROR_SUMMARY_MASK 0x00000007ffffffff
7664 #define SH_PI_ERROR_SUMMARY_INIT 0x0000000000000000
7666 /* SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR */
7667 /* Description: CRB's FSB pipe detected protocol table miss */
7668 #define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_SHFT 0
7669 #define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_MASK 0x0000000000000001
7671 /* SH_PI_ERROR_SUMMARY_GFX_RP_ERR */
7672 /* Description: Graphic reply error message received */
7673 #define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_SHFT 1
7674 #define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_MASK 0x0000000000000002
7676 /* SH_PI_ERROR_SUMMARY_XB_PROTO_ERR */
7677 /* Description: CRB's XB pipe detected protocol table miss */
7678 #define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_SHFT 2
7679 #define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_MASK 0x0000000000000004
7681 /* SH_PI_ERROR_SUMMARY_MEM_RP_ERR */
7682 /* Description: Memory reply error message received */
7683 #define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_SHFT 3
7684 #define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_MASK 0x0000000000000008
7686 /* SH_PI_ERROR_SUMMARY_PIO_RP_ERR */
7687 /* Description: PIO error reply message received */
7688 #define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_SHFT 4
7689 #define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_MASK 0x0000000000000010
7691 /* SH_PI_ERROR_SUMMARY_MEM_TO_ERR */
7692 /* Description: CRB's XB pipe detected a CRB time-out */
7693 #define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_SHFT 5
7694 #define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_MASK 0x0000000000000020
7696 /* SH_PI_ERROR_SUMMARY_PIO_TO_ERR */
7697 /* Description: CRB's XB pipe detected a PIO time-out */
7698 #define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_SHFT 6
7699 #define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_MASK 0x0000000000000040
7701 /* SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE */
7702 /* Description: An un-correctable ECC error was detected */
7703 #define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_SHFT 7
7704 #define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_MASK 0x0000000000000080
7706 /* SH_PI_ERROR_SUMMARY_FSB_SHUB_CE */
7707 /* Description: An correctable ECC error was detected */
7708 #define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_SHFT 8
7709 #define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_MASK 0x0000000000000100
7711 /* SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR */
7712 /* Description: Message color was wrong */
7713 #define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_SHFT 9
7714 #define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_MASK 0x0000000000000200
7716 /* SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW */
7717 /* Description: MD Request input buffer over flow error */
7718 #define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_SHFT 10
7719 #define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_MASK 0x0000000000000400
7721 /* SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW */
7722 /* Description: MD Reply input buffer over flow error */
7723 #define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_SHFT 11
7724 #define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_MASK 0x0000000000000800
7726 /* SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW */
7727 /* Description: XN Request input buffer over flow error */
7728 #define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_SHFT 12
7729 #define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_MASK 0x0000000000001000
7731 /* SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW */
7732 /* Description: XN Reply input buffer over flow error */
7733 #define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_SHFT 13
7734 #define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_MASK 0x0000000000002000
7736 /* SH_PI_ERROR_SUMMARY_NACK_OFLOW */
7737 /* Description: NACK over flow error */
7738 #define SH_PI_ERROR_SUMMARY_NACK_OFLOW_SHFT 14
7739 #define SH_PI_ERROR_SUMMARY_NACK_OFLOW_MASK 0x0000000000004000
7741 /* SH_PI_ERROR_SUMMARY_GFX_INT_0 */
7742 /* Description: GFX transfer interrupt for CPU 0 */
7743 #define SH_PI_ERROR_SUMMARY_GFX_INT_0_SHFT 15
7744 #define SH_PI_ERROR_SUMMARY_GFX_INT_0_MASK 0x0000000000008000
7746 /* SH_PI_ERROR_SUMMARY_GFX_INT_1 */
7747 /* Description: GFX transfer interrupt for CPU 1 */
7748 #define SH_PI_ERROR_SUMMARY_GFX_INT_1_SHFT 16
7749 #define SH_PI_ERROR_SUMMARY_GFX_INT_1_MASK 0x0000000000010000
7751 /* SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW */
7752 /* Description: MD Request Credit Overflow Error */
7753 #define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_SHFT 17
7754 #define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
7756 /* SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW */
7757 /* Description: MD Reply Credit Overflow Error */
7758 #define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_SHFT 18
7759 #define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
7761 /* SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW */
7762 /* Description: XN Request Credit Overflow Error */
7763 #define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_SHFT 19
7764 #define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
7766 /* SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW */
7767 /* Description: XN Reply Credit Overflow Error */
7768 #define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_SHFT 20
7769 #define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
7771 /* SH_PI_ERROR_SUMMARY_HUNG_BUS */
7772 /* Description: FSB is hung */
7773 #define SH_PI_ERROR_SUMMARY_HUNG_BUS_SHFT 21
7774 #define SH_PI_ERROR_SUMMARY_HUNG_BUS_MASK 0x0000000000200000
7776 /* SH_PI_ERROR_SUMMARY_RSP_PARITY */
7777 /* Description: Parity error detecte during response phase */
7778 #define SH_PI_ERROR_SUMMARY_RSP_PARITY_SHFT 22
7779 #define SH_PI_ERROR_SUMMARY_RSP_PARITY_MASK 0x0000000000400000
7781 /* SH_PI_ERROR_SUMMARY_IOQ_OVERRUN */
7782 /* Description: Over run error detected on IOQ */
7783 #define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_SHFT 23
7784 #define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_MASK 0x0000000000800000
7786 /* SH_PI_ERROR_SUMMARY_REQ_FORMAT */
7787 /* Description: FSB request format not supported */
7788 #define SH_PI_ERROR_SUMMARY_REQ_FORMAT_SHFT 24
7789 #define SH_PI_ERROR_SUMMARY_REQ_FORMAT_MASK 0x0000000001000000
7791 /* SH_PI_ERROR_SUMMARY_ADDR_ACCESS */
7792 /* Description: Access to Address is not supported */
7793 #define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_SHFT 25
7794 #define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_MASK 0x0000000002000000
7796 /* SH_PI_ERROR_SUMMARY_REQ_PARITY */
7797 /* Description: Parity error detected during request phase */
7798 #define SH_PI_ERROR_SUMMARY_REQ_PARITY_SHFT 26
7799 #define SH_PI_ERROR_SUMMARY_REQ_PARITY_MASK 0x0000000004000000
7801 /* SH_PI_ERROR_SUMMARY_ADDR_PARITY */
7802 /* Description: Parity error detected on address */
7803 #define SH_PI_ERROR_SUMMARY_ADDR_PARITY_SHFT 27
7804 #define SH_PI_ERROR_SUMMARY_ADDR_PARITY_MASK 0x0000000008000000
7806 /* SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE */
7807 /* Description: SHUB_FSB_DQE error */
7808 #define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_SHFT 28
7809 #define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_MASK 0x0000000010000000
7811 /* SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE */
7812 /* Description: An un-correctable ECC error was detected */
7813 #define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_SHFT 29
7814 #define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_MASK 0x0000000020000000
7816 /* SH_PI_ERROR_SUMMARY_SHUB_FSB_CE */
7817 /* Description: An correctable ECC error was detected */
7818 #define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_SHFT 30
7819 #define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_MASK 0x0000000040000000
7821 /* SH_PI_ERROR_SUMMARY_LIVELOCK */
7822 /* Description: AFI livelock error was detected */
7823 #define SH_PI_ERROR_SUMMARY_LIVELOCK_SHFT 31
7824 #define SH_PI_ERROR_SUMMARY_LIVELOCK_MASK 0x0000000080000000
7826 /* SH_PI_ERROR_SUMMARY_BAD_SNOOP */
7827 /* Description: AFI bad snoop error was detected */
7828 #define SH_PI_ERROR_SUMMARY_BAD_SNOOP_SHFT 32
7829 #define SH_PI_ERROR_SUMMARY_BAD_SNOOP_MASK 0x0000000100000000
7831 /* SH_PI_ERROR_SUMMARY_FSB_TBL_MISS */
7832 /* Description: AFI FSB request table miss error was detected */
7833 #define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_SHFT 33
7834 #define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_MASK 0x0000000200000000
7836 /* SH_PI_ERROR_SUMMARY_MSG_LENGTH */
7837 /* Description: Message length error on received message from SIC */
7838 #define SH_PI_ERROR_SUMMARY_MSG_LENGTH_SHFT 34
7839 #define SH_PI_ERROR_SUMMARY_MSG_LENGTH_MASK 0x0000000400000000
7841 /* ==================================================================== */
7842 /* Register "SH_PI_ERROR_SUMMARY_ALIAS" */
7843 /* PI Error Summary Alias */
7844 /* ==================================================================== */
7846 #define SH_PI_ERROR_SUMMARY_ALIAS 0x0000000120060688
7848 /* ==================================================================== */
7849 /* Register "SH_PI_EXPRESS_REPLY_STATUS" */
7850 /* PI Express Reply Status */
7851 /* ==================================================================== */
7853 #define SH_PI_EXPRESS_REPLY_STATUS 0x0000000120060700
7854 #define SH_PI_EXPRESS_REPLY_STATUS_MASK 0x0000000000000007
7855 #define SH_PI_EXPRESS_REPLY_STATUS_INIT 0x0000000000000000
7857 /* SH_PI_EXPRESS_REPLY_STATUS_STATE */
7858 /* Description: Express Reply State */
7859 #define SH_PI_EXPRESS_REPLY_STATUS_STATE_SHFT 0
7860 #define SH_PI_EXPRESS_REPLY_STATUS_STATE_MASK 0x0000000000000007
7862 /* ==================================================================== */
7863 /* Register "SH_PI_FIRST_ERROR" */
7864 /* PI First Error */
7865 /* ==================================================================== */
7867 #define SH_PI_FIRST_ERROR 0x0000000120060780
7868 #define SH_PI_FIRST_ERROR_MASK 0x00000007ffffffff
7869 #define SH_PI_FIRST_ERROR_INIT 0x0000000000000000
7871 /* SH_PI_FIRST_ERROR_FSB_PROTO_ERR */
7872 /* Description: CRB's FSB pipe detected protocol table miss */
7873 #define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_SHFT 0
7874 #define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_MASK 0x0000000000000001
7876 /* SH_PI_FIRST_ERROR_GFX_RP_ERR */
7877 /* Description: Graphics error reply message received */
7878 #define SH_PI_FIRST_ERROR_GFX_RP_ERR_SHFT 1
7879 #define SH_PI_FIRST_ERROR_GFX_RP_ERR_MASK 0x0000000000000002
7881 /* SH_PI_FIRST_ERROR_XB_PROTO_ERR */
7882 /* Description: CRB's XB pipe detected protocol table miss */
7883 #define SH_PI_FIRST_ERROR_XB_PROTO_ERR_SHFT 2
7884 #define SH_PI_FIRST_ERROR_XB_PROTO_ERR_MASK 0x0000000000000004
7886 /* SH_PI_FIRST_ERROR_MEM_RP_ERR */
7887 /* Description: Memory reply error message received */
7888 #define SH_PI_FIRST_ERROR_MEM_RP_ERR_SHFT 3
7889 #define SH_PI_FIRST_ERROR_MEM_RP_ERR_MASK 0x0000000000000008
7891 /* SH_PI_FIRST_ERROR_PIO_RP_ERR */
7892 /* Description: PIO reply error message received */
7893 #define SH_PI_FIRST_ERROR_PIO_RP_ERR_SHFT 4
7894 #define SH_PI_FIRST_ERROR_PIO_RP_ERR_MASK 0x0000000000000010
7896 /* SH_PI_FIRST_ERROR_MEM_TO_ERR */
7897 /* Description: CRB's XB pipe detected a CRB time-out */
7898 #define SH_PI_FIRST_ERROR_MEM_TO_ERR_SHFT 5
7899 #define SH_PI_FIRST_ERROR_MEM_TO_ERR_MASK 0x0000000000000020
7901 /* SH_PI_FIRST_ERROR_PIO_TO_ERR */
7902 /* Description: CRB's XB pipe detected a PIO time-out */
7903 #define SH_PI_FIRST_ERROR_PIO_TO_ERR_SHFT 6
7904 #define SH_PI_FIRST_ERROR_PIO_TO_ERR_MASK 0x0000000000000040
7906 /* SH_PI_FIRST_ERROR_FSB_SHUB_UCE */
7907 /* Description: An un-correctable ECC error was detected */
7908 #define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7
7909 #define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080
7911 /* SH_PI_FIRST_ERROR_FSB_SHUB_CE */
7912 /* Description: A correctable ECC error was detected */
7913 #define SH_PI_FIRST_ERROR_FSB_SHUB_CE_SHFT 8
7914 #define SH_PI_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100
7916 /* SH_PI_FIRST_ERROR_MSG_COLOR_ERR */
7917 /* Description: Message color was wrong */
7918 #define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_SHFT 9
7919 #define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_MASK 0x0000000000000200
7921 /* SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW */
7922 /* Description: MD Request input buffer over flow error */
7923 #define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT 10
7924 #define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK 0x0000000000000400
7926 /* SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW */
7927 /* Description: MD Reply input buffer over flow error */
7928 #define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT 11
7929 #define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_MASK 0x0000000000000800
7931 /* SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW */
7932 /* Description: XN Request input buffer over flow error */
7933 #define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT 12
7934 #define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK 0x0000000000001000
7936 /* SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW */
7937 /* Description: XN Reply input buffer over flow error */
7938 #define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT 13
7939 #define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_MASK 0x0000000000002000
7941 /* SH_PI_FIRST_ERROR_NACK_OFLOW */
7942 /* Description: NACK over flow error */
7943 #define SH_PI_FIRST_ERROR_NACK_OFLOW_SHFT 14
7944 #define SH_PI_FIRST_ERROR_NACK_OFLOW_MASK 0x0000000000004000
7946 /* SH_PI_FIRST_ERROR_GFX_INT_0 */
7947 /* Description: GFX transfer interrupt for CPU 0 */
7948 #define SH_PI_FIRST_ERROR_GFX_INT_0_SHFT 15
7949 #define SH_PI_FIRST_ERROR_GFX_INT_0_MASK 0x0000000000008000
7951 /* SH_PI_FIRST_ERROR_GFX_INT_1 */
7952 /* Description: GFX transfer interrupt for CPU 1 */
7953 #define SH_PI_FIRST_ERROR_GFX_INT_1_SHFT 16
7954 #define SH_PI_FIRST_ERROR_GFX_INT_1_MASK 0x0000000000010000
7956 /* SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW */
7957 /* Description: MD Request Credit Overflow Error */
7958 #define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT 17
7959 #define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
7961 /* SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW */
7962 /* Description: MD Reply Credit Overflow Error */
7963 #define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT 18
7964 #define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
7966 /* SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW */
7967 /* Description: XN Request Credit Overflow Error */
7968 #define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT 19
7969 #define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
7971 /* SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW */
7972 /* Description: XN Reply Credit Overflow Error */
7973 #define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT 20
7974 #define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
7976 /* SH_PI_FIRST_ERROR_HUNG_BUS */
7977 /* Description: FSB is hung */
7978 #define SH_PI_FIRST_ERROR_HUNG_BUS_SHFT 21
7979 #define SH_PI_FIRST_ERROR_HUNG_BUS_MASK 0x0000000000200000
7981 /* SH_PI_FIRST_ERROR_RSP_PARITY */
7982 /* Description: Parity error detecte during response phase */
7983 #define SH_PI_FIRST_ERROR_RSP_PARITY_SHFT 22
7984 #define SH_PI_FIRST_ERROR_RSP_PARITY_MASK 0x0000000000400000
7986 /* SH_PI_FIRST_ERROR_IOQ_OVERRUN */
7987 /* Description: Over run error detected on IOQ */
7988 #define SH_PI_FIRST_ERROR_IOQ_OVERRUN_SHFT 23
7989 #define SH_PI_FIRST_ERROR_IOQ_OVERRUN_MASK 0x0000000000800000
7991 /* SH_PI_FIRST_ERROR_REQ_FORMAT */
7992 /* Description: FSB request format not supported */
7993 #define SH_PI_FIRST_ERROR_REQ_FORMAT_SHFT 24
7994 #define SH_PI_FIRST_ERROR_REQ_FORMAT_MASK 0x0000000001000000
7996 /* SH_PI_FIRST_ERROR_ADDR_ACCESS */
7997 /* Description: Access to Address is not supported */
7998 #define SH_PI_FIRST_ERROR_ADDR_ACCESS_SHFT 25
7999 #define SH_PI_FIRST_ERROR_ADDR_ACCESS_MASK 0x0000000002000000
8001 /* SH_PI_FIRST_ERROR_REQ_PARITY */
8002 /* Description: Parity error detected during request phase */
8003 #define SH_PI_FIRST_ERROR_REQ_PARITY_SHFT 26
8004 #define SH_PI_FIRST_ERROR_REQ_PARITY_MASK 0x0000000004000000
8006 /* SH_PI_FIRST_ERROR_ADDR_PARITY */
8007 /* Description: Parity error detected on address */
8008 #define SH_PI_FIRST_ERROR_ADDR_PARITY_SHFT 27
8009 #define SH_PI_FIRST_ERROR_ADDR_PARITY_MASK 0x0000000008000000
8011 /* SH_PI_FIRST_ERROR_SHUB_FSB_DQE */
8012 /* Description: SHUB_FSB_DQE */
8013 #define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_SHFT 28
8014 #define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_MASK 0x0000000010000000
8016 /* SH_PI_FIRST_ERROR_SHUB_FSB_UCE */
8017 /* Description: An un-correctable ECC error was detected */
8018 #define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_SHFT 29
8019 #define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_MASK 0x0000000020000000
8021 /* SH_PI_FIRST_ERROR_SHUB_FSB_CE */
8022 /* Description: An correctable ECC error was detected */
8023 #define SH_PI_FIRST_ERROR_SHUB_FSB_CE_SHFT 30
8024 #define SH_PI_FIRST_ERROR_SHUB_FSB_CE_MASK 0x0000000040000000
8026 /* SH_PI_FIRST_ERROR_LIVELOCK */
8027 /* Description: AFI livelock error was detected */
8028 #define SH_PI_FIRST_ERROR_LIVELOCK_SHFT 31
8029 #define SH_PI_FIRST_ERROR_LIVELOCK_MASK 0x0000000080000000
8031 /* SH_PI_FIRST_ERROR_BAD_SNOOP */
8032 /* Description: AFI bad snoop error was detected */
8033 #define SH_PI_FIRST_ERROR_BAD_SNOOP_SHFT 32
8034 #define SH_PI_FIRST_ERROR_BAD_SNOOP_MASK 0x0000000100000000
8036 /* SH_PI_FIRST_ERROR_FSB_TBL_MISS */
8037 /* Description: AFI FSB request table miss error was detected */
8038 #define SH_PI_FIRST_ERROR_FSB_TBL_MISS_SHFT 33
8039 #define SH_PI_FIRST_ERROR_FSB_TBL_MISS_MASK 0x0000000200000000
8041 /* SH_PI_FIRST_ERROR_MSG_LENGTH */
8042 /* Description: Message length error on received message from SIC */
8043 #define SH_PI_FIRST_ERROR_MSG_LENGTH_SHFT 34
8044 #define SH_PI_FIRST_ERROR_MSG_LENGTH_MASK 0x0000000400000000
8046 /* ==================================================================== */
8047 /* Register "SH_PI_FIRST_ERROR_ALIAS" */
8048 /* PI First Error Alias */
8049 /* ==================================================================== */
8051 #define SH_PI_FIRST_ERROR_ALIAS 0x0000000120060788
8053 /* ==================================================================== */
8054 /* Register "SH_PI_PI2MD_REPLY_VC_STATUS" */
8055 /* PI-to-MD Reply Virtual Channel Status */
8056 /* ==================================================================== */
8058 #define SH_PI_PI2MD_REPLY_VC_STATUS 0x0000000120060900
8059 #define SH_PI_PI2MD_REPLY_VC_STATUS_MASK 0x000000000000003f
8060 #define SH_PI_PI2MD_REPLY_VC_STATUS_INIT 0x0000000000000000
8062 /* SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT */
8063 /* Description: Status of output credits */
8064 #define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
8065 #define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
8067 /* ==================================================================== */
8068 /* Register "SH_PI_PI2MD_REQUEST_VC_STATUS" */
8069 /* PI-to-MD Request Virtual Channel Status */
8070 /* ==================================================================== */
8072 #define SH_PI_PI2MD_REQUEST_VC_STATUS 0x0000000120060980
8073 #define SH_PI_PI2MD_REQUEST_VC_STATUS_MASK 0x000000000000003f
8074 #define SH_PI_PI2MD_REQUEST_VC_STATUS_INIT 0x0000000000000000
8076 /* SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT */
8077 /* Description: Status of output credits */
8078 #define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
8079 #define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
8081 /* ==================================================================== */
8082 /* Register "SH_PI_PI2XN_REPLY_VC_STATUS" */
8083 /* PI-to-XN Reply Virtual Channel Status */
8084 /* ==================================================================== */
8086 #define SH_PI_PI2XN_REPLY_VC_STATUS 0x0000000120060a00
8087 #define SH_PI_PI2XN_REPLY_VC_STATUS_MASK 0x000000000000003f
8088 #define SH_PI_PI2XN_REPLY_VC_STATUS_INIT 0x0000000000000000
8090 /* SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT */
8091 /* Description: Status of output credits */
8092 #define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
8093 #define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
8095 /* ==================================================================== */
8096 /* Register "SH_PI_PI2XN_REQUEST_VC_STATUS" */
8097 /* PI-to-XN Request Virtual Channel Status */
8098 /* ==================================================================== */
8100 #define SH_PI_PI2XN_REQUEST_VC_STATUS 0x0000000120060a80
8101 #define SH_PI_PI2XN_REQUEST_VC_STATUS_MASK 0x000000000000003f
8102 #define SH_PI_PI2XN_REQUEST_VC_STATUS_INIT 0x0000000000000000
8104 /* SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT */
8105 /* Description: Status of output credits */
8106 #define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
8107 #define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
8109 /* ==================================================================== */
8110 /* Register "SH_PI_UNCORRECTED_DETAIL_1" */
8111 /* PI Uncorrected Error Detail 1 */
8112 /* ==================================================================== */
8114 #define SH_PI_UNCORRECTED_DETAIL_1 0x0000000120060b00
8115 #define SH_PI_UNCORRECTED_DETAIL_1_MASK 0xffffffffffffffff
8116 #define SH_PI_UNCORRECTED_DETAIL_1_INIT 0x0000000000000000
8118 /* SH_PI_UNCORRECTED_DETAIL_1_ADDRESS */
8119 /* Description: Address of Message that logged Uncorrectable Error */
8120 #define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_SHFT 0
8121 #define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_MASK 0x0000ffffffffffff
8123 /* SH_PI_UNCORRECTED_DETAIL_1_SYNDROME */
8124 /* Description: Syndrome for double word data with Uncorrectable Er */
8125 #define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_SHFT 48
8126 #define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_MASK 0x00ff000000000000
8128 /* SH_PI_UNCORRECTED_DETAIL_1_DEP */
8129 /* Description: DEP for Double word in error */
8130 #define SH_PI_UNCORRECTED_DETAIL_1_DEP_SHFT 56
8131 #define SH_PI_UNCORRECTED_DETAIL_1_DEP_MASK 0xff00000000000000
8133 /* ==================================================================== */
8134 /* Register "SH_PI_UNCORRECTED_DETAIL_2" */
8135 /* PI Uncorrected Error Detail 2 */
8136 /* ==================================================================== */
8138 #define SH_PI_UNCORRECTED_DETAIL_2 0x0000000120060b80
8139 #define SH_PI_UNCORRECTED_DETAIL_2_MASK 0xffffffffffffffff
8140 #define SH_PI_UNCORRECTED_DETAIL_2_INIT 0x0000000000000000
8142 /* SH_PI_UNCORRECTED_DETAIL_2_DATA */
8143 /* Description: Double word data in error */
8144 #define SH_PI_UNCORRECTED_DETAIL_2_DATA_SHFT 0
8145 #define SH_PI_UNCORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff
8147 /* ==================================================================== */
8148 /* Register "SH_PI_UNCORRECTED_DETAIL_3" */
8149 /* PI Uncorrected Error Detail 3 */
8150 /* ==================================================================== */
8152 #define SH_PI_UNCORRECTED_DETAIL_3 0x0000000120060c00
8153 #define SH_PI_UNCORRECTED_DETAIL_3_MASK 0xffffffffffffffff
8154 #define SH_PI_UNCORRECTED_DETAIL_3_INIT 0x0000000000000000
8156 /* SH_PI_UNCORRECTED_DETAIL_3_ADDRESS */
8157 /* Description: Address of Message that logged Uncorrectable Error */
8158 #define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_SHFT 0
8159 #define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_MASK 0x0000ffffffffffff
8161 /* SH_PI_UNCORRECTED_DETAIL_3_SYNDROME */
8162 /* Description: Syndrome for double word data with Uncorrectable Er */
8163 #define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_SHFT 48
8164 #define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_MASK 0x00ff000000000000
8166 /* SH_PI_UNCORRECTED_DETAIL_3_DEP */
8167 /* Description: DCP for Double word in error */
8168 #define SH_PI_UNCORRECTED_DETAIL_3_DEP_SHFT 56
8169 #define SH_PI_UNCORRECTED_DETAIL_3_DEP_MASK 0xff00000000000000
8171 /* ==================================================================== */
8172 /* Register "SH_PI_UNCORRECTED_DETAIL_4" */
8173 /* PI Uncorrected Error Detail 4 */
8174 /* ==================================================================== */
8176 #define SH_PI_UNCORRECTED_DETAIL_4 0x0000000120060c80
8177 #define SH_PI_UNCORRECTED_DETAIL_4_MASK 0xffffffffffffffff
8178 #define SH_PI_UNCORRECTED_DETAIL_4_INIT 0x0000000000000000
8180 /* SH_PI_UNCORRECTED_DETAIL_4_DATA */
8181 /* Description: Double word data in error */
8182 #define SH_PI_UNCORRECTED_DETAIL_4_DATA_SHFT 0
8183 #define SH_PI_UNCORRECTED_DETAIL_4_DATA_MASK 0xffffffffffffffff
8185 /* ==================================================================== */
8186 /* Register "SH_PI_MD2PI_REPLY_VC_STATUS" */
8187 /* MD-to-PI Reply Virtual Channel Status */
8188 /* ==================================================================== */
8190 #define SH_PI_MD2PI_REPLY_VC_STATUS 0x0000000120060800
8191 #define SH_PI_MD2PI_REPLY_VC_STATUS_MASK 0x0000000000000fff
8192 #define SH_PI_MD2PI_REPLY_VC_STATUS_INIT 0x0000000000000000
8194 /* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT */
8195 /* Description: Status of input header credits */
8196 #define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
8197 #define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
8199 /* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT */
8200 /* Description: Status of data credits */
8201 #define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
8202 #define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
8204 /* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT */
8205 /* Description: Status of MD Reply Input Queue */
8206 #define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
8207 #define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
8209 /* ==================================================================== */
8210 /* Register "SH_PI_MD2PI_REQUEST_VC_STATUS" */
8211 /* MD-to-PI Request Virtual Channel Status */
8212 /* ==================================================================== */
8214 #define SH_PI_MD2PI_REQUEST_VC_STATUS 0x0000000120060880
8215 #define SH_PI_MD2PI_REQUEST_VC_STATUS_MASK 0x0000000000000fff
8216 #define SH_PI_MD2PI_REQUEST_VC_STATUS_INIT 0x0000000000000000
8218 /* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT */
8219 /* Description: Status of input header credits */
8220 #define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
8221 #define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
8223 /* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT */
8224 /* Description: Status of input data credits */
8225 #define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
8226 #define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
8228 /* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT */
8229 /* Description: Status of MD Request Input Queue */
8230 #define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
8231 #define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
8233 /* ==================================================================== */
8234 /* Register "SH_PI_XN2PI_REPLY_VC_STATUS" */
8235 /* XN-to-PI Reply Virtual Channel Status */
8236 /* ==================================================================== */
8238 #define SH_PI_XN2PI_REPLY_VC_STATUS 0x0000000120060d00
8239 #define SH_PI_XN2PI_REPLY_VC_STATUS_MASK 0x0000000000000fff
8240 #define SH_PI_XN2PI_REPLY_VC_STATUS_INIT 0x0000000000000000
8242 /* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT */
8243 /* Description: Status of input header credits */
8244 #define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
8245 #define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
8247 /* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT */
8248 /* Description: Status of input data credits */
8249 #define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
8250 #define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
8252 /* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT */
8253 /* Description: Status of XN Reply Input Queue */
8254 #define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
8255 #define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
8257 /* ==================================================================== */
8258 /* Register "SH_PI_XN2PI_REQUEST_VC_STATUS" */
8259 /* XN-to-PI Request Virtual Channel Status */
8260 /* ==================================================================== */
8262 #define SH_PI_XN2PI_REQUEST_VC_STATUS 0x0000000120060d80
8263 #define SH_PI_XN2PI_REQUEST_VC_STATUS_MASK 0x0000000000000fff
8264 #define SH_PI_XN2PI_REQUEST_VC_STATUS_INIT 0x0000000000000000
8266 /* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT */
8267 /* Description: Status of input header credits */
8268 #define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
8269 #define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
8271 /* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT */
8272 /* Description: Status of input data credits */
8273 #define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
8274 #define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
8276 /* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT */
8277 /* Description: Status of XN Request Input Queue */
8278 #define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
8279 #define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
8281 /* ==================================================================== */
8282 /* Register "SH_XNPI_SIC_FLOW" */
8283 /* ==================================================================== */
8285 #define SH_XNPI_SIC_FLOW 0x0000000150030000
8286 #define SH_XNPI_SIC_FLOW_MASK 0x9f1f1f1f1f1f9f9f
8287 #define SH_XNPI_SIC_FLOW_INIT 0x0000080000080000
8289 /* SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD */
8290 /* Description: vc0 withhold */
8291 #define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
8292 #define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f
8294 /* SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED */
8295 /* Description: Force Credit on VC0 from debit cntr */
8296 #define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
8297 #define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
8299 /* SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD */
8300 /* Description: vc2 withhold */
8301 #define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
8302 #define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00
8304 /* SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED */
8305 /* Description: Force Credit on VC2 from debit cntr */
8306 #define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
8307 #define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
8309 /* SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST */
8310 /* Description: vc0 credit_test */
8311 #define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_SHFT 16
8312 #define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_MASK 0x00000000001f0000
8314 /* SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN */
8315 /* Description: vc0 credit dynamic value */
8316 #define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_SHFT 24
8317 #define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_MASK 0x000000001f000000
8319 /* SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP */
8320 /* Description: vc0 credit captured value */
8321 #define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_SHFT 32
8322 #define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_MASK 0x0000001f00000000
8324 /* SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST */
8325 /* Description: vc2 credit_test */
8326 #define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_SHFT 40
8327 #define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_MASK 0x00001f0000000000
8329 /* SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN */
8330 /* Description: vc2 credit dynamic value */
8331 #define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_SHFT 48
8332 #define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_MASK 0x001f000000000000
8334 /* SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP */
8335 /* Description: vc2 credit captured value */
8336 #define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_SHFT 56
8337 #define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_MASK 0x1f00000000000000
8339 /* SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT */
8340 #define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63
8341 #define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000
8343 /* ==================================================================== */
8344 /* Register "SH_XNPI_TO_NI0_PORT_FLOW" */
8345 /* ==================================================================== */
8347 #define SH_XNPI_TO_NI0_PORT_FLOW 0x0000000150030010
8348 #define SH_XNPI_TO_NI0_PORT_FLOW_MASK 0x3f3f003f3f00bfbf
8349 #define SH_XNPI_TO_NI0_PORT_FLOW_INIT 0x0000000000000000
8351 /* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD */
8352 /* Description: vc0 withhold */
8353 #define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
8354 #define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
8356 /* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED */
8357 /* Description: Force Credit on VC0 from debit cntr */
8358 #define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
8359 #define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
8361 /* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD */
8362 /* Description: vc2 withhold */
8363 #define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
8364 #define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
8366 /* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED */
8367 /* Description: Force Credit on VC2 from debit cntr */
8368 #define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
8369 #define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
8371 /* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN */
8372 /* Description: vc0 credit dynamic value */
8373 #define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
8374 #define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
8376 /* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP */
8377 /* Description: vc0 credit captured value */
8378 #define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
8379 #define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
8381 /* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN */
8382 /* Description: vc2 credit dynamic value */
8383 #define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
8384 #define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
8386 /* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP */
8387 /* Description: vc2 credit captured value */
8388 #define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
8389 #define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
8391 /* ==================================================================== */
8392 /* Register "SH_XNPI_TO_NI1_PORT_FLOW" */
8393 /* ==================================================================== */
8395 #define SH_XNPI_TO_NI1_PORT_FLOW 0x0000000150030020
8396 #define SH_XNPI_TO_NI1_PORT_FLOW_MASK 0x3f3f003f3f00bfbf
8397 #define SH_XNPI_TO_NI1_PORT_FLOW_INIT 0x0000000000000000
8399 /* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD */
8400 /* Description: vc0 withhold */
8401 #define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
8402 #define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
8404 /* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED */
8405 /* Description: Force Credit on VC0 from debit cntr */
8406 #define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
8407 #define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
8409 /* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD */
8410 /* Description: vc2 withhold */
8411 #define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
8412 #define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
8414 /* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED */
8415 /* Description: Force Credit on VC2 from debit cntr */
8416 #define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
8417 #define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
8419 /* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN */
8420 /* Description: vc0 credit dynamic value */
8421 #define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
8422 #define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
8424 /* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP */
8425 /* Description: vc0 credit captured value */
8426 #define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
8427 #define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
8429 /* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN */
8430 /* Description: vc2 credit dynamic value */
8431 #define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
8432 #define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
8434 /* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP */
8435 /* Description: vc2 credit captured value */
8436 #define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
8437 #define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
8439 /* ==================================================================== */
8440 /* Register "SH_XNPI_TO_IILB_PORT_FLOW" */
8441 /* ==================================================================== */
8443 #define SH_XNPI_TO_IILB_PORT_FLOW 0x0000000150030030
8444 #define SH_XNPI_TO_IILB_PORT_FLOW_MASK 0x3f3f003f3f00bfbf
8445 #define SH_XNPI_TO_IILB_PORT_FLOW_INIT 0x0000000000000000
8447 /* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD */
8448 /* Description: vc0 withhold */
8449 #define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
8450 #define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
8452 /* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED */
8453 /* Description: Force Credit on VC0 from debit cntr */
8454 #define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
8455 #define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
8457 /* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD */
8458 /* Description: vc2 withhold */
8459 #define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
8460 #define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
8462 /* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED */
8463 /* Description: Force Credit on VC2 from debit cntr */
8464 #define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
8465 #define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
8467 /* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN */
8468 /* Description: vc0 credit dynamic value */
8469 #define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
8470 #define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
8472 /* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP */
8473 /* Description: vc0 credit captured value */
8474 #define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
8475 #define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
8477 /* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN */
8478 /* Description: vc2 credit dynamic value */
8479 #define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
8480 #define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
8482 /* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP */
8483 /* Description: vc2 credit captured value */
8484 #define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
8485 #define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
8487 /* ==================================================================== */
8488 /* Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO" */
8489 /* ==================================================================== */
8491 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO 0x0000000150030040
8492 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f
8493 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_INIT 0x00000c0c00000000
8495 /* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN */
8496 /* Description: vc0 fifo entry dynamic value */
8497 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
8498 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
8500 /* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP */
8501 /* Description: vc0 fifo entry captured value */
8502 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
8503 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
8505 /* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN */
8506 /* Description: vc2 fifo entry dynamic value */
8507 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
8508 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
8510 /* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP */
8511 /* Description: vc2 fifo entry captured value */
8512 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
8513 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
8515 /* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST */
8516 /* Description: vc0 test credits limit */
8517 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
8518 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
8520 /* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST */
8521 /* Description: vc2 test credits limit */
8522 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
8523 #define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
8525 /* ==================================================================== */
8526 /* Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO" */
8527 /* ==================================================================== */
8529 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO 0x0000000150030050
8530 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f
8531 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_INIT 0x00000c0c00000000
8533 /* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN */
8534 /* Description: vc0 fifo entry dynamic value */
8535 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
8536 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
8538 /* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP */
8539 /* Description: vc0 fifo entry captured value */
8540 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
8541 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
8543 /* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN */
8544 /* Description: vc2 fifo entry dynamic value */
8545 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
8546 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
8548 /* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP */
8549 /* Description: vc2 fifo entry captured value */
8550 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
8551 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
8553 /* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST */
8554 /* Description: vc0 test credits limit */
8555 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
8556 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
8558 /* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST */
8559 /* Description: vc2 test credits limit */
8560 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
8561 #define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
8563 /* ==================================================================== */
8564 /* Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO" */
8565 /* ==================================================================== */
8567 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO 0x0000000150030060
8568 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f
8569 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_INIT 0x00000c0c00000000
8571 /* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN */
8572 /* Description: vc0 fifo entry dynamic value */
8573 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
8574 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
8576 /* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP */
8577 /* Description: vc0 fifo entry captured value */
8578 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
8579 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
8581 /* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN */
8582 /* Description: vc2 fifo entry dynamic value */
8583 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
8584 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
8586 /* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP */
8587 /* Description: vc2 fifo entry captured value */
8588 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
8589 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
8591 /* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST */
8592 /* Description: vc0 test credits limit */
8593 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
8594 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
8596 /* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST */
8597 /* Description: vc2 test credits limit */
8598 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
8599 #define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
8601 /* ==================================================================== */
8602 /* Register "SH_XNMD_SIC_FLOW" */
8603 /* ==================================================================== */
8605 #define SH_XNMD_SIC_FLOW 0x0000000150030100
8606 #define SH_XNMD_SIC_FLOW_MASK 0x9f1f1f1f1f1f9f9f
8607 #define SH_XNMD_SIC_FLOW_INIT 0x0000090000090000
8609 /* SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD */
8610 /* Description: vc0 withhold */
8611 #define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
8612 #define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f
8614 /* SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED */
8615 /* Description: Force Credit on VC0 from debit cntr */
8616 #define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
8617 #define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
8619 /* SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD */
8620 /* Description: vc2 withhold */
8621 #define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
8622 #define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00
8624 /* SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED */
8625 /* Description: Force Credit on VC2 from debit cntr */
8626 #define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
8627 #define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
8629 /* SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST */
8630 /* Description: vc0 credit_test */
8631 #define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_SHFT 16
8632 #define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_MASK 0x00000000001f0000
8634 /* SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN */
8635 /* Description: vc0 credit dynamic value */
8636 #define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_SHFT 24
8637 #define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_MASK 0x000000001f000000
8639 /* SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP */
8640 /* Description: vc0 credit captured value */
8641 #define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_SHFT 32
8642 #define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_MASK 0x0000001f00000000
8644 /* SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST */
8645 /* Description: vc2 credit_test */
8646 #define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_SHFT 40
8647 #define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_MASK 0x00001f0000000000
8649 /* SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN */
8650 /* Description: vc2 credit dynamic value */
8651 #define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_SHFT 48
8652 #define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_MASK 0x001f000000000000
8654 /* SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP */
8655 /* Description: vc2 credit captured value */
8656 #define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_SHFT 56
8657 #define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_MASK 0x1f00000000000000
8659 /* SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT */
8660 #define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63
8661 #define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000
8663 /* ==================================================================== */
8664 /* Register "SH_XNMD_TO_NI0_PORT_FLOW" */
8665 /* ==================================================================== */
8667 #define SH_XNMD_TO_NI0_PORT_FLOW 0x0000000150030110
8668 #define SH_XNMD_TO_NI0_PORT_FLOW_MASK 0x3f3f003f3f00bfbf
8669 #define SH_XNMD_TO_NI0_PORT_FLOW_INIT 0x0000000000000000
8671 /* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD */
8672 /* Description: vc0 withhold */
8673 #define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
8674 #define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
8676 /* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED */
8677 /* Description: Force Credit on VC0 from debit cntr */
8678 #define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
8679 #define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
8681 /* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD */
8682 /* Description: vc2 withhold */
8683 #define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
8684 #define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
8686 /* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED */
8687 /* Description: Force Credit on VC2 from debit cntr */
8688 #define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
8689 #define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
8691 /* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN */
8692 /* Description: vc0 credit dynamic value */
8693 #define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
8694 #define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
8696 /* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP */
8697 /* Description: vc0 credit captured value */
8698 #define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
8699 #define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
8701 /* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN */
8702 /* Description: vc2 credit dynamic value */
8703 #define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
8704 #define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
8706 /* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP */
8707 /* Description: vc2 credit captured value */
8708 #define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
8709 #define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
8711 /* ==================================================================== */
8712 /* Register "SH_XNMD_TO_NI1_PORT_FLOW" */
8713 /* ==================================================================== */
8715 #define SH_XNMD_TO_NI1_PORT_FLOW 0x0000000150030120
8716 #define SH_XNMD_TO_NI1_PORT_FLOW_MASK 0x3f3f003f3f00bfbf
8717 #define SH_XNMD_TO_NI1_PORT_FLOW_INIT 0x0000000000000000
8719 /* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD */
8720 /* Description: vc0 withhold */
8721 #define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
8722 #define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
8724 /* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED */
8725 /* Description: Force Credit on VC0 from debit cntr */
8726 #define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
8727 #define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
8729 /* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD */
8730 /* Description: vc2 withhold */
8731 #define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
8732 #define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
8734 /* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED */
8735 /* Description: Force Credit on VC2 from debit cntr */
8736 #define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
8737 #define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
8739 /* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN */
8740 /* Description: vc0 credit dynamic value */
8741 #define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
8742 #define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
8744 /* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP */
8745 /* Description: vc0 credit captured value */
8746 #define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
8747 #define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
8749 /* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN */
8750 /* Description: vc2 credit dynamic value */
8751 #define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
8752 #define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
8754 /* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP */
8755 /* Description: vc2 credit captured value */
8756 #define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
8757 #define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
8759 /* ==================================================================== */
8760 /* Register "SH_XNMD_TO_IILB_PORT_FLOW" */
8761 /* ==================================================================== */
8763 #define SH_XNMD_TO_IILB_PORT_FLOW 0x0000000150030130
8764 #define SH_XNMD_TO_IILB_PORT_FLOW_MASK 0x3f3f003f3f00bfbf
8765 #define SH_XNMD_TO_IILB_PORT_FLOW_INIT 0x0000000000000000
8767 /* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD */
8768 /* Description: vc0 withhold */
8769 #define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
8770 #define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
8772 /* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED */
8773 /* Description: Force Credit on VC0 from debit cntr */
8774 #define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
8775 #define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
8777 /* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD */
8778 /* Description: vc2 withhold */
8779 #define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
8780 #define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
8782 /* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED */
8783 /* Description: Force Credit on VC2 from debit cntr */
8784 #define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
8785 #define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
8787 /* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN */
8788 /* Description: vc0 credit dynamic value */
8789 #define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
8790 #define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
8792 /* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP */
8793 /* Description: vc0 credit captured value */
8794 #define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
8795 #define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
8797 /* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN */
8798 /* Description: vc2 credit dynamic value */
8799 #define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
8800 #define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
8802 /* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP */
8803 /* Description: vc2 credit captured value */
8804 #define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
8805 #define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
8807 /* ==================================================================== */
8808 /* Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO" */
8809 /* ==================================================================== */
8811 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO 0x0000000150030140
8812 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f
8813 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_INIT 0x00000c0c00000000
8815 /* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN */
8816 /* Description: vc0 fifo entry dynamic value */
8817 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
8818 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
8820 /* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP */
8821 /* Description: vc0 fifo entry captured value */
8822 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
8823 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
8825 /* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN */
8826 /* Description: vc2 fifo entry dynamic value */
8827 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
8828 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
8830 /* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP */
8831 /* Description: vc2 fifo entry captured value */
8832 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
8833 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
8835 /* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST */
8836 /* Description: vc0 test credits limit */
8837 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
8838 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
8840 /* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST */
8841 /* Description: vc2 test credits limit */
8842 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
8843 #define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
8845 /* ==================================================================== */
8846 /* Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO" */
8847 /* ==================================================================== */
8849 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO 0x0000000150030150
8850 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f
8851 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_INIT 0x00000c0c00000000
8853 /* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN */
8854 /* Description: vc0 fifo entry dynamic value */
8855 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
8856 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
8858 /* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP */
8859 /* Description: vc0 fifo entry captured value */
8860 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
8861 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
8863 /* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN */
8864 /* Description: vc2 fifo entry dynamic value */
8865 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
8866 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
8868 /* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP */
8869 /* Description: vc2 fifo entry captured value */
8870 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
8871 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
8873 /* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST */
8874 /* Description: vc0 test credits limit */
8875 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
8876 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
8878 /* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST */
8879 /* Description: vc2 test credits limit */
8880 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
8881 #define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
8883 /* ==================================================================== */
8884 /* Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO" */
8885 /* ==================================================================== */
8887 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO 0x0000000150030160
8888 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f
8889 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_INIT 0x00000c0c00000000
8891 /* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN */
8892 /* Description: vc0 fifo entry dynamic value */
8893 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
8894 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
8896 /* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP */
8897 /* Description: vc0 fifo entry captured value */
8898 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
8899 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
8901 /* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN */
8902 /* Description: vc2 fifo entry dynamic value */
8903 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
8904 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
8906 /* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP */
8907 /* Description: vc2 fifo entry captured value */
8908 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
8909 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
8911 /* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST */
8912 /* Description: vc0 test credits limit */
8913 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
8914 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
8916 /* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST */
8917 /* Description: vc2 test credits limit */
8918 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
8919 #define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
8921 /* ==================================================================== */
8922 /* Register "SH_XNII_INTRA_FLOW" */
8923 /* ==================================================================== */
8925 #define SH_XNII_INTRA_FLOW 0x0000000150030200
8926 #define SH_XNII_INTRA_FLOW_MASK 0x7f7f7f7f7f7fbfbf
8927 #define SH_XNII_INTRA_FLOW_INIT 0x00003f00003f0000
8929 /* SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
8930 /* Description: vc0 withhold */
8931 #define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
8932 #define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
8934 /* SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
8935 /* Description: Force Credit on VC0 from debit cntr */
8936 #define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
8937 #define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
8939 /* SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
8940 /* Description: vc2 withhold */
8941 #define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
8942 #define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
8944 /* SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
8945 /* Description: Force Credit on VC2 from debit cntr */
8946 #define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
8947 #define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
8949 /* SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST */
8950 /* Description: vc0 credit_test */
8951 #define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 16
8952 #define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x00000000007f0000
8954 /* SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN */
8955 /* Description: vc0 credit dynamic value */
8956 #define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 24
8957 #define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x000000007f000000
8959 /* SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP */
8960 /* Description: vc0 credit captured value */
8961 #define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 32
8962 #define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x0000007f00000000
8964 /* SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST */
8965 /* Description: vc2 credit_test */
8966 #define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 40
8967 #define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x00007f0000000000
8969 /* SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN */
8970 /* Description: vc2 credit dynamic value */
8971 #define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 48
8972 #define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x007f000000000000
8974 /* SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP */
8975 /* Description: vc2 credit captured value */
8976 #define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 56
8977 #define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x7f00000000000000
8979 /* ==================================================================== */
8980 /* Register "SH_XNLB_INTRA_FLOW" */
8981 /* ==================================================================== */
8983 #define SH_XNLB_INTRA_FLOW 0x0000000150030210
8984 #define SH_XNLB_INTRA_FLOW_MASK 0xff7f7f7f7f7fbfbf
8985 #define SH_XNLB_INTRA_FLOW_INIT 0x0000080000100000
8987 /* SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
8988 /* Description: vc0 withhold */
8989 #define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
8990 #define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
8992 /* SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
8993 /* Description: Force Credit on VC0 from debit cntr */
8994 #define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
8995 #define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
8997 /* SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
8998 /* Description: vc2 withhold */
8999 #define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
9000 #define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
9002 /* SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
9003 /* Description: Force Credit on VC2 from debit cntr */
9004 #define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
9005 #define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
9007 /* SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST */
9008 /* Description: vc0 credit_test */
9009 #define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 16
9010 #define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x00000000007f0000
9012 /* SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN */
9013 /* Description: vc0 credit dynamic value */
9014 #define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 24
9015 #define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x000000007f000000
9017 /* SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP */
9018 /* Description: vc0 credit captured value */
9019 #define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 32
9020 #define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x0000007f00000000
9022 /* SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST */
9023 /* Description: vc2 credit_test */
9024 #define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 40
9025 #define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x00007f0000000000
9027 /* SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN */
9028 /* Description: vc2 credit dynamic value */
9029 #define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 48
9030 #define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x007f000000000000
9032 /* SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP */
9033 /* Description: vc2 credit captured value */
9034 #define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 56
9035 #define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x7f00000000000000
9037 /* SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN */
9038 #define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_SHFT 63
9039 #define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_MASK 0x8000000000000000
9041 /* ==================================================================== */
9042 /* Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT" */
9043 /* ==================================================================== */
9045 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT 0x0000000150030220
9046 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf
9047 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_INIT 0x0000000000000000
9049 /* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
9050 /* Description: vc0 withhold */
9051 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
9052 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
9054 /* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
9055 /* Description: Force Credit on VC0 from debit cntr */
9056 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
9057 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
9059 /* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
9060 /* Description: vc2 withhold */
9061 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
9062 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
9064 /* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
9065 /* Description: Force Credit on VC2 from debit cntr */
9066 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
9067 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
9069 /* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN */
9070 /* Description: vc0 debit dynamic value */
9071 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
9072 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
9074 /* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP */
9075 /* Description: vc0 debit captured value */
9076 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
9077 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
9079 /* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN */
9080 /* Description: vc2 debit dynamic value */
9081 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
9082 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
9084 /* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP */
9085 /* Description: vc2 debit captured value */
9086 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
9087 #define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
9089 /* ==================================================================== */
9090 /* Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT" */
9091 /* ==================================================================== */
9093 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT 0x0000000150030230
9094 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf
9095 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_INIT 0x0000000000000000
9097 /* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
9098 /* Description: vc0 withhold */
9099 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
9100 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
9102 /* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
9103 /* Description: Force Credit on VC0 from debit cntr */
9104 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
9105 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
9107 /* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
9108 /* Description: vc2 withhold */
9109 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
9110 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
9112 /* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
9113 /* Description: Force Credit on VC2 from debit cntr */
9114 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
9115 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
9117 /* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN */
9118 /* Description: vc0 debit dynamic value */
9119 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
9120 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
9122 /* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP */
9123 /* Description: vc0 debit captured value */
9124 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
9125 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
9127 /* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN */
9128 /* Description: vc2 debit dynamic value */
9129 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
9130 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
9132 /* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP */
9133 /* Description: vc2 debit captured value */
9134 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
9135 #define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
9137 /* ==================================================================== */
9138 /* Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT" */
9139 /* ==================================================================== */
9141 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030240
9142 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf
9143 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000
9145 /* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
9146 /* Description: vc0 withhold */
9147 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
9148 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
9150 /* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
9151 /* Description: Force Credit on VC0 from debit cntr */
9152 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
9153 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
9155 /* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
9156 /* Description: vc2 withhold */
9157 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
9158 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
9160 /* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
9161 /* Description: Force Credit on VC2 from debit cntr */
9162 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
9163 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
9165 /* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */
9166 /* Description: vc0 debit dynamic value */
9167 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
9168 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
9170 /* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */
9171 /* Description: vc0 debit captured value */
9172 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
9173 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
9175 /* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */
9176 /* Description: vc2 debit dynamic value */
9177 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
9178 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
9180 /* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */
9181 /* Description: vc2 debit captured value */
9182 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
9183 #define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
9185 /* ==================================================================== */
9186 /* Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT" */
9187 /* ==================================================================== */
9189 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030250
9190 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf
9191 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000
9193 /* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
9194 /* Description: vc0 withhold */
9195 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
9196 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
9198 /* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
9199 /* Description: Force Credit on VC0 from debit cntr */
9200 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
9201 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
9203 /* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
9204 /* Description: vc2 withhold */
9205 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
9206 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
9208 /* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
9209 /* Description: Force Credit on VC2 from debit cntr */
9210 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
9211 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
9213 /* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */
9214 /* Description: vc0 debit dynamic value */
9215 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
9216 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
9218 /* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */
9219 /* Description: vc0 debit captured value */
9220 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
9221 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
9223 /* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */
9224 /* Description: vc2 debit dynamic value */
9225 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
9226 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
9228 /* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */
9229 /* Description: vc2 debit captured value */
9230 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
9231 #define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
9233 /* ==================================================================== */
9234 /* Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT" */
9235 /* ==================================================================== */
9237 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030260
9238 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf
9239 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000
9241 /* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
9242 /* Description: vc0 withhold */
9243 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
9244 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
9246 /* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
9247 /* Description: Force Credit on VC0 from debit cntr */
9248 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
9249 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
9251 /* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
9252 /* Description: vc2 withhold */
9253 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
9254 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
9256 /* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
9257 /* Description: Force Credit on VC2 from debit cntr */
9258 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
9259 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
9261 /* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */
9262 /* Description: vc0 debit dynamic value */
9263 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
9264 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
9266 /* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */
9267 /* Description: vc0 debit captured value */
9268 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
9269 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
9271 /* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */
9272 /* Description: vc2 debit dynamic value */
9273 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
9274 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
9276 /* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */
9277 /* Description: vc2 debit captured value */
9278 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
9279 #define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
9281 /* ==================================================================== */
9282 /* Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT" */
9283 /* ==================================================================== */
9285 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT 0x0000000150030270
9286 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
9287 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
9289 /* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST */
9290 /* Description: vc0 credit_test */
9291 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
9292 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
9294 /* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN */
9295 /* Description: vc0 credit dynamic value */
9296 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
9297 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
9299 /* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP */
9300 /* Description: vc0 credit captured value */
9301 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
9302 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
9304 /* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST */
9305 /* Description: vc2 credit_test */
9306 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
9307 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
9309 /* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN */
9310 /* Description: vc2 credit dynamic value */
9311 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
9312 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
9314 /* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP */
9315 /* Description: vc2 credit captured value */
9316 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
9317 #define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
9319 /* ==================================================================== */
9320 /* Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT" */
9321 /* ==================================================================== */
9323 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT 0x0000000150030280
9324 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
9325 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
9327 /* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST */
9328 /* Description: vc0 credit_test */
9329 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
9330 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
9332 /* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN */
9333 /* Description: vc0 credit dynamic value */
9334 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
9335 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
9337 /* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP */
9338 /* Description: vc0 credit captured value */
9339 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
9340 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
9342 /* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST */
9343 /* Description: vc2 credit_test */
9344 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
9345 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
9347 /* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN */
9348 /* Description: vc2 credit dynamic value */
9349 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
9350 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
9352 /* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP */
9353 /* Description: vc2 credit captured value */
9354 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
9355 #define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
9357 /* ==================================================================== */
9358 /* Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT" */
9359 /* ==================================================================== */
9361 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030290
9362 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
9363 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
9365 /* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */
9366 /* Description: vc0 credit_test */
9367 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
9368 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
9370 /* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */
9371 /* Description: vc0 credit dynamic value */
9372 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
9373 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
9375 /* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */
9376 /* Description: vc0 credit captured value */
9377 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
9378 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
9380 /* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */
9381 /* Description: vc2 credit_test */
9382 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
9383 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
9385 /* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */
9386 /* Description: vc2 credit dynamic value */
9387 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
9388 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
9390 /* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */
9391 /* Description: vc2 credit captured value */
9392 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
9393 #define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
9395 /* ==================================================================== */
9396 /* Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT" */
9397 /* ==================================================================== */
9399 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT 0x00000001500302a0
9400 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
9401 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
9403 /* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */
9404 /* Description: vc0 credit_test */
9405 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
9406 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
9408 /* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */
9409 /* Description: vc0 credit dynamic value */
9410 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
9411 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
9413 /* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */
9414 /* Description: vc0 credit captured value */
9415 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
9416 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
9418 /* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */
9419 /* Description: vc2 credit_test */
9420 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
9421 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
9423 /* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */
9424 /* Description: vc2 credit dynamic value */
9425 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
9426 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
9428 /* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */
9429 /* Description: vc2 credit captured value */
9430 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
9431 #define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
9433 /* ==================================================================== */
9434 /* Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT" */
9435 /* ==================================================================== */
9437 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT 0x00000001500302b0
9438 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
9439 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
9441 /* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */
9442 /* Description: vc0 credit_test */
9443 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
9444 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
9446 /* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */
9447 /* Description: vc0 credit dynamic value */
9448 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
9449 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
9451 /* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */
9452 /* Description: vc0 credit captured value */
9453 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
9454 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
9456 /* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */
9457 /* Description: vc2 credit_test */
9458 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
9459 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
9461 /* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */
9462 /* Description: vc2 credit dynamic value */
9463 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
9464 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
9466 /* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */
9467 /* Description: vc2 credit captured value */
9468 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
9469 #define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
9471 /* ==================================================================== */
9472 /* Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT" */
9473 /* ==================================================================== */
9475 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030300
9476 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf
9477 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000
9479 /* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
9480 /* Description: vc0 withhold */
9481 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
9482 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
9484 /* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
9485 /* Description: Force Credit on VC0 from debit cntr */
9486 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
9487 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
9489 /* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
9490 /* Description: vc2 withhold */
9491 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
9492 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
9494 /* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
9495 /* Description: Force Credit on VC2 from debit cntr */
9496 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
9497 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
9499 /* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */
9500 /* Description: vc0 debit dynamic value */
9501 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
9502 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
9504 /* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */
9505 /* Description: vc0 debit captured value */
9506 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
9507 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
9509 /* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */
9510 /* Description: vc2 debit dynamic value */
9511 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
9512 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
9514 /* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */
9515 /* Description: vc2 debit captured value */
9516 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
9517 #define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
9519 /* ==================================================================== */
9520 /* Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT" */
9521 /* ==================================================================== */
9523 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030310
9524 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf
9525 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000
9527 /* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
9528 /* Description: vc0 withhold */
9529 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
9530 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
9532 /* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
9533 /* Description: Force Credit on VC0 from debit cntr */
9534 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
9535 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
9537 /* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
9538 /* Description: vc2 withhold */
9539 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
9540 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
9542 /* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
9543 /* Description: Force Credit on VC2 from debit cntr */
9544 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
9545 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
9547 /* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */
9548 /* Description: vc0 debit dynamic value */
9549 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
9550 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
9552 /* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */
9553 /* Description: vc0 debit captured value */
9554 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
9555 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
9557 /* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */
9558 /* Description: vc2 debit dynamic value */
9559 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
9560 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
9562 /* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */
9563 /* Description: vc2 debit captured value */
9564 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
9565 #define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
9567 /* ==================================================================== */
9568 /* Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT" */
9569 /* ==================================================================== */
9571 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030320
9572 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf
9573 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000
9575 /* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
9576 /* Description: vc0 withhold */
9577 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
9578 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
9580 /* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
9581 /* Description: Force Credit on VC0 from debit cntr */
9582 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
9583 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
9585 /* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
9586 /* Description: vc2 withhold */
9587 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
9588 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
9590 /* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
9591 /* Description: Force Credit on VC2 from debit cntr */
9592 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
9593 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
9595 /* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */
9596 /* Description: vc0 debit dynamic value */
9597 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
9598 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
9600 /* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */
9601 /* Description: vc0 debit captured value */
9602 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
9603 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
9605 /* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */
9606 /* Description: vc2 debit dynamic value */
9607 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
9608 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
9610 /* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */
9611 /* Description: vc2 debit captured value */
9612 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
9613 #define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
9615 /* ==================================================================== */
9616 /* Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT" */
9617 /* ==================================================================== */
9619 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT 0x0000000150030330
9620 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
9621 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
9623 /* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */
9624 /* Description: vc0 credit_test */
9625 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
9626 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
9628 /* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */
9629 /* Description: vc0 credit dynamic value */
9630 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
9631 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
9633 /* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */
9634 /* Description: vc0 credit captured value */
9635 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
9636 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
9638 /* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */
9639 /* Description: vc2 credit_test */
9640 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
9641 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
9643 /* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */
9644 /* Description: vc2 credit dynamic value */
9645 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
9646 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
9648 /* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */
9649 /* Description: vc2 credit captured value */
9650 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
9651 #define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
9653 /* ==================================================================== */
9654 /* Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT" */
9655 /* ==================================================================== */
9657 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030340
9658 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
9659 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
9661 /* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */
9662 /* Description: vc0 credit_test */
9663 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
9664 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
9666 /* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */
9667 /* Description: vc0 credit dynamic value */
9668 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
9669 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
9671 /* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */
9672 /* Description: vc0 credit captured value */
9673 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
9674 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
9676 /* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */
9677 /* Description: vc2 credit_test */
9678 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
9679 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
9681 /* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */
9682 /* Description: vc2 credit dynamic value */
9683 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
9684 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
9686 /* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */
9687 /* Description: vc2 credit captured value */
9688 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
9689 #define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
9691 /* ==================================================================== */
9692 /* Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT" */
9693 /* ==================================================================== */
9695 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT 0x0000000150030350
9696 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
9697 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
9699 /* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */
9700 /* Description: vc0 credit_test */
9701 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
9702 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
9704 /* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */
9705 /* Description: vc0 credit dynamic value */
9706 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
9707 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
9709 /* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */
9710 /* Description: vc0 credit captured value */
9711 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
9712 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
9714 /* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */
9715 /* Description: vc2 credit_test */
9716 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
9717 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
9719 /* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */
9720 /* Description: vc2 credit dynamic value */
9721 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
9722 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
9724 /* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */
9725 /* Description: vc2 credit captured value */
9726 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
9727 #define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
9729 /* ==================================================================== */
9730 /* Register "SH_XNNI0_0_INTRANI_FLOW" */
9731 /* ==================================================================== */
9733 #define SH_XNNI0_0_INTRANI_FLOW 0x0000000150030360
9734 #define SH_XNNI0_0_INTRANI_FLOW_MASK 0x00000000000000bf
9735 #define SH_XNNI0_0_INTRANI_FLOW_INIT 0x0000000000000000
9737 /* SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD */
9738 /* Description: vc0 withhold */
9739 #define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
9740 #define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
9742 /* SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED */
9743 /* Description: Force Credit on VC0 from debit cntr */
9744 #define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
9745 #define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
9747 /* ==================================================================== */
9748 /* Register "SH_XNNI0_1_INTRANI_FLOW" */
9749 /* ==================================================================== */
9751 #define SH_XNNI0_1_INTRANI_FLOW 0x0000000150030370
9752 #define SH_XNNI0_1_INTRANI_FLOW_MASK 0x00000000000000bf
9753 #define SH_XNNI0_1_INTRANI_FLOW_INIT 0x0000000000000000
9755 /* SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD */
9756 /* Description: vc1 withhold */
9757 #define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
9758 #define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
9760 /* SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED */
9761 /* Description: Force Credit on VC1 from debit cntr */
9762 #define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
9763 #define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
9765 /* ==================================================================== */
9766 /* Register "SH_XNNI0_2_INTRANI_FLOW" */
9767 /* ==================================================================== */
9769 #define SH_XNNI0_2_INTRANI_FLOW 0x0000000150030380
9770 #define SH_XNNI0_2_INTRANI_FLOW_MASK 0x00000000000000bf
9771 #define SH_XNNI0_2_INTRANI_FLOW_INIT 0x0000000000000000
9773 /* SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD */
9774 /* Description: vc2 withhold */
9775 #define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
9776 #define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
9778 /* SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED */
9779 /* Description: Force Credit on VC2 from debit cntr */
9780 #define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
9781 #define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
9783 /* ==================================================================== */
9784 /* Register "SH_XNNI0_3_INTRANI_FLOW" */
9785 /* ==================================================================== */
9787 #define SH_XNNI0_3_INTRANI_FLOW 0x0000000150030390
9788 #define SH_XNNI0_3_INTRANI_FLOW_MASK 0x00000000000000bf
9789 #define SH_XNNI0_3_INTRANI_FLOW_INIT 0x0000000000000000
9791 /* SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD */
9792 /* Description: vc3 withhold */
9793 #define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
9794 #define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
9796 /* SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED */
9797 /* Description: Force Credit on VC3 from debit cntr */
9798 #define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
9799 #define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
9801 /* ==================================================================== */
9802 /* Register "SH_XNNI0_VCSWITCH_FLOW" */
9803 /* ==================================================================== */
9805 #define SH_XNNI0_VCSWITCH_FLOW 0x00000001500303a0
9806 #define SH_XNNI0_VCSWITCH_FLOW_MASK 0x0000000701010101
9807 #define SH_XNNI0_VCSWITCH_FLOW_INIT 0x0000000000000000
9809 /* SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH */
9810 /* Description: Swap VC0/2 with VC1/3 */
9811 #define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0
9812 #define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001
9814 /* SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH */
9815 /* Description: Swap VC0/2 with VC1/3 */
9816 #define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8
9817 #define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100
9819 /* SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH */
9820 /* Description: Swap VC0/2 with VC1/3 */
9821 #define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16
9822 #define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000
9824 /* SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH */
9825 /* Description: Swap VC0/2 with VC1/3 */
9826 #define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24
9827 #define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000
9829 /* SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN */
9830 #define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32
9831 #define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000
9833 /* SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT */
9834 #define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33
9835 #define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000
9837 /* SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES */
9838 #define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34
9839 #define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000
9841 /* ==================================================================== */
9842 /* Register "SH_XNNI0_TIMER_REG" */
9843 /* ==================================================================== */
9845 #define SH_XNNI0_TIMER_REG 0x00000001500303b0
9846 #define SH_XNNI0_TIMER_REG_MASK 0x0000000100ffffff
9847 #define SH_XNNI0_TIMER_REG_INIT 0x0000000000ffffff
9849 /* SH_XNNI0_TIMER_REG_TIMEOUT_REG */
9850 /* Description: Master Timeout Counter */
9851 #define SH_XNNI0_TIMER_REG_TIMEOUT_REG_SHFT 0
9852 #define SH_XNNI0_TIMER_REG_TIMEOUT_REG_MASK 0x0000000000ffffff
9854 /* SH_XNNI0_TIMER_REG_LINKCLEANUP_REG */
9855 /* Description: Link Clean Up */
9856 #define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_SHFT 32
9857 #define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_MASK 0x0000000100000000
9859 /* ==================================================================== */
9860 /* Register "SH_XNNI0_FIFO02_FLOW" */
9861 /* ==================================================================== */
9863 #define SH_XNNI0_FIFO02_FLOW 0x00000001500303c0
9864 #define SH_XNNI0_FIFO02_FLOW_MASK 0x00000f0f0f0f0f0f
9865 #define SH_XNNI0_FIFO02_FLOW_INIT 0x0000000000000000
9867 /* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT */
9868 /* Description: limit reg zero disables functionality */
9869 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0
9870 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f
9872 /* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN */
9873 /* Description: dynamic counter value */
9874 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_SHFT 8
9875 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_MASK 0x0000000000000f00
9877 /* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP */
9878 /* Description: captured counter value */
9879 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_SHFT 16
9880 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_MASK 0x00000000000f0000
9882 /* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT */
9883 /* Description: limit reg zero disables functionality */
9884 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24
9885 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000
9887 /* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN */
9888 /* Description: counter dynamic value */
9889 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_SHFT 32
9890 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_MASK 0x0000000f00000000
9892 /* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP */
9893 /* Description: captured counter value */
9894 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_SHFT 40
9895 #define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_MASK 0x00000f0000000000
9897 /* ==================================================================== */
9898 /* Register "SH_XNNI0_FIFO13_FLOW" */
9899 /* ==================================================================== */
9901 #define SH_XNNI0_FIFO13_FLOW 0x00000001500303d0
9902 #define SH_XNNI0_FIFO13_FLOW_MASK 0x00000f0f0f0f0f0f
9903 #define SH_XNNI0_FIFO13_FLOW_INIT 0x0000000000000000
9905 /* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT */
9906 /* Description: limit reg zero disables functionality */
9907 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0
9908 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f
9910 /* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN */
9911 /* Description: dynamic counter value */
9912 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_SHFT 8
9913 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_MASK 0x0000000000000f00
9915 /* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP */
9916 /* Description: captured counter value */
9917 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_SHFT 16
9918 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_MASK 0x00000000000f0000
9920 /* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT */
9921 /* Description: limit reg zero disables functionality */
9922 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24
9923 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000
9925 /* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN */
9926 /* Description: counter dynamic value */
9927 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_SHFT 32
9928 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_MASK 0x0000000f00000000
9930 /* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP */
9931 /* Description: captured counter value */
9932 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_SHFT 40
9933 #define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_MASK 0x00000f0000000000
9935 /* ==================================================================== */
9936 /* Register "SH_XNNI0_NI_FLOW" */
9937 /* ==================================================================== */
9939 #define SH_XNNI0_NI_FLOW 0x00000001500303e0
9940 #define SH_XNNI0_NI_FLOW_MASK 0xff0fff0fff0fff0f
9941 #define SH_XNNI0_NI_FLOW_INIT 0x0000000000000000
9943 /* SH_XNNI0_NI_FLOW_VC0_LIMIT */
9944 /* Description: vc0 limit reg, zero disables functionality */
9945 #define SH_XNNI0_NI_FLOW_VC0_LIMIT_SHFT 0
9946 #define SH_XNNI0_NI_FLOW_VC0_LIMIT_MASK 0x000000000000000f
9948 /* SH_XNNI0_NI_FLOW_VC0_DYN */
9949 /* Description: vc0 counter dynamic value */
9950 #define SH_XNNI0_NI_FLOW_VC0_DYN_SHFT 8
9951 #define SH_XNNI0_NI_FLOW_VC0_DYN_MASK 0x0000000000000f00
9953 /* SH_XNNI0_NI_FLOW_VC0_CAP */
9954 /* Description: vc0 counter captured value */
9955 #define SH_XNNI0_NI_FLOW_VC0_CAP_SHFT 12
9956 #define SH_XNNI0_NI_FLOW_VC0_CAP_MASK 0x000000000000f000
9958 /* SH_XNNI0_NI_FLOW_VC1_LIMIT */
9959 /* Description: vc1 limit reg, zero disables functionality */
9960 #define SH_XNNI0_NI_FLOW_VC1_LIMIT_SHFT 16
9961 #define SH_XNNI0_NI_FLOW_VC1_LIMIT_MASK 0x00000000000f0000
9963 /* SH_XNNI0_NI_FLOW_VC1_DYN */
9964 /* Description: vc1 counter dynamic value */
9965 #define SH_XNNI0_NI_FLOW_VC1_DYN_SHFT 24
9966 #define SH_XNNI0_NI_FLOW_VC1_DYN_MASK 0x000000000f000000
9968 /* SH_XNNI0_NI_FLOW_VC1_CAP */
9969 /* Description: vc1 counter captured value */
9970 #define SH_XNNI0_NI_FLOW_VC1_CAP_SHFT 28
9971 #define SH_XNNI0_NI_FLOW_VC1_CAP_MASK 0x00000000f0000000
9973 /* SH_XNNI0_NI_FLOW_VC2_LIMIT */
9974 /* Description: vc2 limit reg, zero disables functionality */
9975 #define SH_XNNI0_NI_FLOW_VC2_LIMIT_SHFT 32
9976 #define SH_XNNI0_NI_FLOW_VC2_LIMIT_MASK 0x0000000f00000000
9978 /* SH_XNNI0_NI_FLOW_VC2_DYN */
9979 /* Description: vc2 counter dynamic value */
9980 #define SH_XNNI0_NI_FLOW_VC2_DYN_SHFT 40
9981 #define SH_XNNI0_NI_FLOW_VC2_DYN_MASK 0x00000f0000000000
9983 /* SH_XNNI0_NI_FLOW_VC2_CAP */
9984 /* Description: vc2 counter captured value */
9985 #define SH_XNNI0_NI_FLOW_VC2_CAP_SHFT 44
9986 #define SH_XNNI0_NI_FLOW_VC2_CAP_MASK 0x0000f00000000000
9988 /* SH_XNNI0_NI_FLOW_VC3_LIMIT */
9989 /* Description: vc3 limit reg, zero disables functionality */
9990 #define SH_XNNI0_NI_FLOW_VC3_LIMIT_SHFT 48
9991 #define SH_XNNI0_NI_FLOW_VC3_LIMIT_MASK 0x000f000000000000
9993 /* SH_XNNI0_NI_FLOW_VC3_DYN */
9994 /* Description: vc3 counter dynamic value */
9995 #define SH_XNNI0_NI_FLOW_VC3_DYN_SHFT 56
9996 #define SH_XNNI0_NI_FLOW_VC3_DYN_MASK 0x0f00000000000000
9998 /* SH_XNNI0_NI_FLOW_VC3_CAP */
9999 /* Description: vc3 counter captured value */
10000 #define SH_XNNI0_NI_FLOW_VC3_CAP_SHFT 60
10001 #define SH_XNNI0_NI_FLOW_VC3_CAP_MASK 0xf000000000000000
10003 /* ==================================================================== */
10004 /* Register "SH_XNNI0_DEAD_FLOW" */
10005 /* ==================================================================== */
10007 #define SH_XNNI0_DEAD_FLOW 0x00000001500303f0
10008 #define SH_XNNI0_DEAD_FLOW_MASK 0xff0fff0fff0fff0f
10009 #define SH_XNNI0_DEAD_FLOW_INIT 0x0000000000000000
10011 /* SH_XNNI0_DEAD_FLOW_VC0_LIMIT */
10012 /* Description: vc0 limit reg, zero disables functionality */
10013 #define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_SHFT 0
10014 #define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_MASK 0x000000000000000f
10016 /* SH_XNNI0_DEAD_FLOW_VC0_DYN */
10017 /* Description: vc0 counter dynamic value */
10018 #define SH_XNNI0_DEAD_FLOW_VC0_DYN_SHFT 8
10019 #define SH_XNNI0_DEAD_FLOW_VC0_DYN_MASK 0x0000000000000f00
10021 /* SH_XNNI0_DEAD_FLOW_VC0_CAP */
10022 /* Description: vc0 counter captured value */
10023 #define SH_XNNI0_DEAD_FLOW_VC0_CAP_SHFT 12
10024 #define SH_XNNI0_DEAD_FLOW_VC0_CAP_MASK 0x000000000000f000
10026 /* SH_XNNI0_DEAD_FLOW_VC1_LIMIT */
10027 /* Description: vc1 limit reg, zero disables functionality */
10028 #define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_SHFT 16
10029 #define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_MASK 0x00000000000f0000
10031 /* SH_XNNI0_DEAD_FLOW_VC1_DYN */
10032 /* Description: vc1 counter dynamic value */
10033 #define SH_XNNI0_DEAD_FLOW_VC1_DYN_SHFT 24
10034 #define SH_XNNI0_DEAD_FLOW_VC1_DYN_MASK 0x000000000f000000
10036 /* SH_XNNI0_DEAD_FLOW_VC1_CAP */
10037 /* Description: vc1 counter captured value */
10038 #define SH_XNNI0_DEAD_FLOW_VC1_CAP_SHFT 28
10039 #define SH_XNNI0_DEAD_FLOW_VC1_CAP_MASK 0x00000000f0000000
10041 /* SH_XNNI0_DEAD_FLOW_VC2_LIMIT */
10042 /* Description: vc2 limit reg, zero disables functionality */
10043 #define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_SHFT 32
10044 #define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_MASK 0x0000000f00000000
10046 /* SH_XNNI0_DEAD_FLOW_VC2_DYN */
10047 /* Description: vc2 counter dynamic value */
10048 #define SH_XNNI0_DEAD_FLOW_VC2_DYN_SHFT 40
10049 #define SH_XNNI0_DEAD_FLOW_VC2_DYN_MASK 0x00000f0000000000
10051 /* SH_XNNI0_DEAD_FLOW_VC2_CAP */
10052 /* Description: vc2 counter captured value */
10053 #define SH_XNNI0_DEAD_FLOW_VC2_CAP_SHFT 44
10054 #define SH_XNNI0_DEAD_FLOW_VC2_CAP_MASK 0x0000f00000000000
10056 /* SH_XNNI0_DEAD_FLOW_VC3_LIMIT */
10057 /* Description: vc3 limit reg, zero disables functionality */
10058 #define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_SHFT 48
10059 #define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_MASK 0x000f000000000000
10061 /* SH_XNNI0_DEAD_FLOW_VC3_DYN */
10062 /* Description: vc3 counter dynamic value */
10063 #define SH_XNNI0_DEAD_FLOW_VC3_DYN_SHFT 56
10064 #define SH_XNNI0_DEAD_FLOW_VC3_DYN_MASK 0x0f00000000000000
10066 /* SH_XNNI0_DEAD_FLOW_VC3_CAP */
10067 /* Description: vc3 counter captured value */
10068 #define SH_XNNI0_DEAD_FLOW_VC3_CAP_SHFT 60
10069 #define SH_XNNI0_DEAD_FLOW_VC3_CAP_MASK 0xf000000000000000
10071 /* ==================================================================== */
10072 /* Register "SH_XNNI0_INJECT_AGE" */
10073 /* ==================================================================== */
10075 #define SH_XNNI0_INJECT_AGE 0x0000000150030400
10076 #define SH_XNNI0_INJECT_AGE_MASK 0x000000000000ffff
10077 #define SH_XNNI0_INJECT_AGE_INIT 0x0000000000000000
10079 /* SH_XNNI0_INJECT_AGE_REQUEST_INJECT */
10080 /* Description: Value of AGE field for outgoing requests */
10081 #define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_SHFT 0
10082 #define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_MASK 0x00000000000000ff
10084 /* SH_XNNI0_INJECT_AGE_REPLY_INJECT */
10085 /* Description: Value of AGE field for outgoing replies */
10086 #define SH_XNNI0_INJECT_AGE_REPLY_INJECT_SHFT 8
10087 #define SH_XNNI0_INJECT_AGE_REPLY_INJECT_MASK 0x000000000000ff00
10089 /* ==================================================================== */
10090 /* Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT" */
10091 /* ==================================================================== */
10093 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030500
10094 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf
10095 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000
10097 /* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
10098 /* Description: vc0 withhold */
10099 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
10100 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
10102 /* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
10103 /* Description: Force Credit on VC0 from debit cntr */
10104 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
10105 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
10107 /* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
10108 /* Description: vc2 withhold */
10109 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
10110 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
10112 /* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
10113 /* Description: Force Credit on VC2 from debit cntr */
10114 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
10115 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
10117 /* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */
10118 /* Description: vc0 debit dynamic value */
10119 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
10120 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
10122 /* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */
10123 /* Description: vc0 debit captured value */
10124 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
10125 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
10127 /* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */
10128 /* Description: vc2 debit dynamic value */
10129 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
10130 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
10132 /* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */
10133 /* Description: vc2 debit captured value */
10134 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
10135 #define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
10137 /* ==================================================================== */
10138 /* Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT" */
10139 /* ==================================================================== */
10141 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030510
10142 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf
10143 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000
10145 /* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
10146 /* Description: vc0 withhold */
10147 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
10148 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
10150 /* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
10151 /* Description: Force Credit on VC0 from debit cntr */
10152 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
10153 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
10155 /* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
10156 /* Description: vc2 withhold */
10157 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
10158 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
10160 /* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
10161 /* Description: Force Credit on VC2 from debit cntr */
10162 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
10163 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
10165 /* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */
10166 /* Description: vc0 debit dynamic value */
10167 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
10168 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
10170 /* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */
10171 /* Description: vc0 debit captured value */
10172 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
10173 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
10175 /* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */
10176 /* Description: vc2 debit dynamic value */
10177 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
10178 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
10180 /* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */
10181 /* Description: vc2 debit captured value */
10182 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
10183 #define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
10185 /* ==================================================================== */
10186 /* Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT" */
10187 /* ==================================================================== */
10189 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030520
10190 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf
10191 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000
10193 /* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */
10194 /* Description: vc0 withhold */
10195 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
10196 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
10198 /* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */
10199 /* Description: Force Credit on VC0 from debit cntr */
10200 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
10201 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
10203 /* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */
10204 /* Description: vc2 withhold */
10205 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
10206 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
10208 /* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */
10209 /* Description: Force Credit on VC2 from debit cntr */
10210 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
10211 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
10213 /* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */
10214 /* Description: vc0 debit dynamic value */
10215 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
10216 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
10218 /* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */
10219 /* Description: vc0 debit captured value */
10220 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
10221 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
10223 /* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */
10224 /* Description: vc2 debit dynamic value */
10225 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
10226 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
10228 /* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */
10229 /* Description: vc2 debit captured value */
10230 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
10231 #define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
10233 /* ==================================================================== */
10234 /* Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT" */
10235 /* ==================================================================== */
10237 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT 0x0000000150030530
10238 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
10239 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
10241 /* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */
10242 /* Description: vc0 credit_test */
10243 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
10244 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
10246 /* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */
10247 /* Description: vc0 credit dynamic value */
10248 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
10249 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
10251 /* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */
10252 /* Description: vc0 credit captured value */
10253 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
10254 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
10256 /* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */
10257 /* Description: vc2 credit_test */
10258 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
10259 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
10261 /* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */
10262 /* Description: vc2 credit dynamic value */
10263 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
10264 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
10266 /* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */
10267 /* Description: vc2 credit captured value */
10268 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
10269 #define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
10271 /* ==================================================================== */
10272 /* Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT" */
10273 /* ==================================================================== */
10275 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030540
10276 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
10277 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
10279 /* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */
10280 /* Description: vc0 credit_test */
10281 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
10282 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
10284 /* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */
10285 /* Description: vc0 credit dynamic value */
10286 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
10287 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
10289 /* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */
10290 /* Description: vc0 credit captured value */
10291 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
10292 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
10294 /* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */
10295 /* Description: vc2 credit_test */
10296 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
10297 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
10299 /* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */
10300 /* Description: vc2 credit dynamic value */
10301 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
10302 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
10304 /* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */
10305 /* Description: vc2 credit captured value */
10306 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
10307 #define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
10309 /* ==================================================================== */
10310 /* Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT" */
10311 /* ==================================================================== */
10313 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT 0x0000000150030550
10314 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
10315 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
10317 /* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */
10318 /* Description: vc0 credit_test */
10319 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
10320 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
10322 /* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */
10323 /* Description: vc0 credit dynamic value */
10324 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
10325 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
10327 /* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */
10328 /* Description: vc0 credit captured value */
10329 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
10330 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
10332 /* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */
10333 /* Description: vc2 credit_test */
10334 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
10335 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
10337 /* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */
10338 /* Description: vc2 credit dynamic value */
10339 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
10340 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
10342 /* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */
10343 /* Description: vc2 credit captured value */
10344 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
10345 #define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
10347 /* ==================================================================== */
10348 /* Register "SH_XNNI1_0_INTRANI_FLOW" */
10349 /* ==================================================================== */
10351 #define SH_XNNI1_0_INTRANI_FLOW 0x0000000150030560
10352 #define SH_XNNI1_0_INTRANI_FLOW_MASK 0x00000000000000bf
10353 #define SH_XNNI1_0_INTRANI_FLOW_INIT 0x0000000000000000
10355 /* SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD */
10356 /* Description: vc0 withhold */
10357 #define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
10358 #define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
10360 /* SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED */
10361 /* Description: Force Credit on VC0 from debit cntr */
10362 #define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
10363 #define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
10365 /* ==================================================================== */
10366 /* Register "SH_XNNI1_1_INTRANI_FLOW" */
10367 /* ==================================================================== */
10369 #define SH_XNNI1_1_INTRANI_FLOW 0x0000000150030570
10370 #define SH_XNNI1_1_INTRANI_FLOW_MASK 0x00000000000000bf
10371 #define SH_XNNI1_1_INTRANI_FLOW_INIT 0x0000000000000000
10373 /* SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD */
10374 /* Description: vc1 withhold */
10375 #define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
10376 #define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
10378 /* SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED */
10379 /* Description: Force Credit on VC1 from debit cntr */
10380 #define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
10381 #define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
10383 /* ==================================================================== */
10384 /* Register "SH_XNNI1_2_INTRANI_FLOW" */
10385 /* ==================================================================== */
10387 #define SH_XNNI1_2_INTRANI_FLOW 0x0000000150030580
10388 #define SH_XNNI1_2_INTRANI_FLOW_MASK 0x00000000000000bf
10389 #define SH_XNNI1_2_INTRANI_FLOW_INIT 0x0000000000000000
10391 /* SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD */
10392 /* Description: vc2 withhold */
10393 #define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
10394 #define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
10396 /* SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED */
10397 /* Description: Force Credit on VC2 from debit cntr */
10398 #define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
10399 #define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
10401 /* ==================================================================== */
10402 /* Register "SH_XNNI1_3_INTRANI_FLOW" */
10403 /* ==================================================================== */
10405 #define SH_XNNI1_3_INTRANI_FLOW 0x0000000150030590
10406 #define SH_XNNI1_3_INTRANI_FLOW_MASK 0x00000000000000bf
10407 #define SH_XNNI1_3_INTRANI_FLOW_INIT 0x0000000000000000
10409 /* SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD */
10410 /* Description: vc3 withhold */
10411 #define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
10412 #define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
10414 /* SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED */
10415 /* Description: Force Credit on VC3 from debit cntr */
10416 #define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
10417 #define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
10419 /* ==================================================================== */
10420 /* Register "SH_XNNI1_VCSWITCH_FLOW" */
10421 /* ==================================================================== */
10423 #define SH_XNNI1_VCSWITCH_FLOW 0x00000001500305a0
10424 #define SH_XNNI1_VCSWITCH_FLOW_MASK 0x0000000701010101
10425 #define SH_XNNI1_VCSWITCH_FLOW_INIT 0x0000000000000000
10427 /* SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH */
10428 /* Description: Swap VC0/2 with VC1/3 */
10429 #define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0
10430 #define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001
10432 /* SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH */
10433 /* Description: Swap VC0/2 with VC1/3 */
10434 #define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8
10435 #define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100
10437 /* SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH */
10438 /* Description: Swap VC0/2 with VC1/3 */
10439 #define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16
10440 #define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000
10442 /* SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH */
10443 /* Description: Swap VC0/2 with VC1/3 */
10444 #define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24
10445 #define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000
10447 /* SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN */
10448 #define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32
10449 #define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000
10451 /* SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT */
10452 #define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33
10453 #define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000
10455 /* SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES */
10456 #define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34
10457 #define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000
10459 /* ==================================================================== */
10460 /* Register "SH_XNNI1_TIMER_REG" */
10461 /* ==================================================================== */
10463 #define SH_XNNI1_TIMER_REG 0x00000001500305b0
10464 #define SH_XNNI1_TIMER_REG_MASK 0x0000000100ffffff
10465 #define SH_XNNI1_TIMER_REG_INIT 0x0000000000ffffff
10467 /* SH_XNNI1_TIMER_REG_TIMEOUT_REG */
10468 /* Description: Master Timeout Counter */
10469 #define SH_XNNI1_TIMER_REG_TIMEOUT_REG_SHFT 0
10470 #define SH_XNNI1_TIMER_REG_TIMEOUT_REG_MASK 0x0000000000ffffff
10472 /* SH_XNNI1_TIMER_REG_LINKCLEANUP_REG */
10473 /* Description: Link Clean Up */
10474 #define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_SHFT 32
10475 #define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_MASK 0x0000000100000000
10477 /* ==================================================================== */
10478 /* Register "SH_XNNI1_FIFO02_FLOW" */
10479 /* ==================================================================== */
10481 #define SH_XNNI1_FIFO02_FLOW 0x00000001500305c0
10482 #define SH_XNNI1_FIFO02_FLOW_MASK 0x00000f0f0f0f0f0f
10483 #define SH_XNNI1_FIFO02_FLOW_INIT 0x0000000000000000
10485 /* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT */
10486 /* Description: limit reg zero disables functionality */
10487 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0
10488 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f
10490 /* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN */
10491 /* Description: dynamic counter value */
10492 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_SHFT 8
10493 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_MASK 0x0000000000000f00
10495 /* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP */
10496 /* Description: captured counter value */
10497 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_SHFT 16
10498 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_MASK 0x00000000000f0000
10500 /* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT */
10501 /* Description: limit reg zero disables functionality */
10502 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24
10503 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000
10505 /* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN */
10506 /* Description: counter dynamic value */
10507 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_SHFT 32
10508 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_MASK 0x0000000f00000000
10510 /* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP */
10511 /* Description: captured counter value */
10512 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_SHFT 40
10513 #define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_MASK 0x00000f0000000000
10515 /* ==================================================================== */
10516 /* Register "SH_XNNI1_FIFO13_FLOW" */
10517 /* ==================================================================== */
10519 #define SH_XNNI1_FIFO13_FLOW 0x00000001500305d0
10520 #define SH_XNNI1_FIFO13_FLOW_MASK 0x00000f0f0f0f0f0f
10521 #define SH_XNNI1_FIFO13_FLOW_INIT 0x0000000000000000
10523 /* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT */
10524 /* Description: limit reg zero disables functionality */
10525 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0
10526 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f
10528 /* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN */
10529 /* Description: dynamic counter value */
10530 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_SHFT 8
10531 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_MASK 0x0000000000000f00
10533 /* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP */
10534 /* Description: captured counter value */
10535 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_SHFT 16
10536 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_MASK 0x00000000000f0000
10538 /* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT */
10539 /* Description: limit reg zero disables functionality */
10540 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24
10541 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000
10543 /* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN */
10544 /* Description: counter dynamic value */
10545 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_SHFT 32
10546 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_MASK 0x0000000f00000000
10548 /* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP */
10549 /* Description: captured counter value */
10550 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_SHFT 40
10551 #define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_MASK 0x00000f0000000000
10553 /* ==================================================================== */
10554 /* Register "SH_XNNI1_NI_FLOW" */
10555 /* ==================================================================== */
10557 #define SH_XNNI1_NI_FLOW 0x00000001500305e0
10558 #define SH_XNNI1_NI_FLOW_MASK 0xff0fff0fff0fff0f
10559 #define SH_XNNI1_NI_FLOW_INIT 0x0000000000000000
10561 /* SH_XNNI1_NI_FLOW_VC0_LIMIT */
10562 /* Description: vc0 limit reg, zero disables functionality */
10563 #define SH_XNNI1_NI_FLOW_VC0_LIMIT_SHFT 0
10564 #define SH_XNNI1_NI_FLOW_VC0_LIMIT_MASK 0x000000000000000f
10566 /* SH_XNNI1_NI_FLOW_VC0_DYN */
10567 /* Description: vc0 counter dynamic value */
10568 #define SH_XNNI1_NI_FLOW_VC0_DYN_SHFT 8
10569 #define SH_XNNI1_NI_FLOW_VC0_DYN_MASK 0x0000000000000f00
10571 /* SH_XNNI1_NI_FLOW_VC0_CAP */
10572 /* Description: vc0 counter captured value */
10573 #define SH_XNNI1_NI_FLOW_VC0_CAP_SHFT 12
10574 #define SH_XNNI1_NI_FLOW_VC0_CAP_MASK 0x000000000000f000
10576 /* SH_XNNI1_NI_FLOW_VC1_LIMIT */
10577 /* Description: vc1 limit reg, zero disables functionality */
10578 #define SH_XNNI1_NI_FLOW_VC1_LIMIT_SHFT 16
10579 #define SH_XNNI1_NI_FLOW_VC1_LIMIT_MASK 0x00000000000f0000
10581 /* SH_XNNI1_NI_FLOW_VC1_DYN */
10582 /* Description: vc1 counter dynamic value */
10583 #define SH_XNNI1_NI_FLOW_VC1_DYN_SHFT 24
10584 #define SH_XNNI1_NI_FLOW_VC1_DYN_MASK 0x000000000f000000
10586 /* SH_XNNI1_NI_FLOW_VC1_CAP */
10587 /* Description: vc1 counter captured value */
10588 #define SH_XNNI1_NI_FLOW_VC1_CAP_SHFT 28
10589 #define SH_XNNI1_NI_FLOW_VC1_CAP_MASK 0x00000000f0000000
10591 /* SH_XNNI1_NI_FLOW_VC2_LIMIT */
10592 /* Description: vc2 limit reg, zero disables functionality */
10593 #define SH_XNNI1_NI_FLOW_VC2_LIMIT_SHFT 32
10594 #define SH_XNNI1_NI_FLOW_VC2_LIMIT_MASK 0x0000000f00000000
10596 /* SH_XNNI1_NI_FLOW_VC2_DYN */
10597 /* Description: vc2 counter dynamic value */
10598 #define SH_XNNI1_NI_FLOW_VC2_DYN_SHFT 40
10599 #define SH_XNNI1_NI_FLOW_VC2_DYN_MASK 0x00000f0000000000
10601 /* SH_XNNI1_NI_FLOW_VC2_CAP */
10602 /* Description: vc2 counter captured value */
10603 #define SH_XNNI1_NI_FLOW_VC2_CAP_SHFT 44
10604 #define SH_XNNI1_NI_FLOW_VC2_CAP_MASK 0x0000f00000000000
10606 /* SH_XNNI1_NI_FLOW_VC3_LIMIT */
10607 /* Description: vc3 limit reg, zero disables functionality */
10608 #define SH_XNNI1_NI_FLOW_VC3_LIMIT_SHFT 48
10609 #define SH_XNNI1_NI_FLOW_VC3_LIMIT_MASK 0x000f000000000000
10611 /* SH_XNNI1_NI_FLOW_VC3_DYN */
10612 /* Description: vc3 counter dynamic value */
10613 #define SH_XNNI1_NI_FLOW_VC3_DYN_SHFT 56
10614 #define SH_XNNI1_NI_FLOW_VC3_DYN_MASK 0x0f00000000000000
10616 /* SH_XNNI1_NI_FLOW_VC3_CAP */
10617 /* Description: vc3 counter captured value */
10618 #define SH_XNNI1_NI_FLOW_VC3_CAP_SHFT 60
10619 #define SH_XNNI1_NI_FLOW_VC3_CAP_MASK 0xf000000000000000
10621 /* ==================================================================== */
10622 /* Register "SH_XNNI1_DEAD_FLOW" */
10623 /* ==================================================================== */
10625 #define SH_XNNI1_DEAD_FLOW 0x00000001500305f0
10626 #define SH_XNNI1_DEAD_FLOW_MASK 0xff0fff0fff0fff0f
10627 #define SH_XNNI1_DEAD_FLOW_INIT 0x0000000000000000
10629 /* SH_XNNI1_DEAD_FLOW_VC0_LIMIT */
10630 /* Description: vc0 limit reg, zero disables functionality */
10631 #define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_SHFT 0
10632 #define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_MASK 0x000000000000000f
10634 /* SH_XNNI1_DEAD_FLOW_VC0_DYN */
10635 /* Description: vc0 counter dynamic value */
10636 #define SH_XNNI1_DEAD_FLOW_VC0_DYN_SHFT 8
10637 #define SH_XNNI1_DEAD_FLOW_VC0_DYN_MASK 0x0000000000000f00
10639 /* SH_XNNI1_DEAD_FLOW_VC0_CAP */
10640 /* Description: vc0 counter captured value */
10641 #define SH_XNNI1_DEAD_FLOW_VC0_CAP_SHFT 12
10642 #define SH_XNNI1_DEAD_FLOW_VC0_CAP_MASK 0x000000000000f000
10644 /* SH_XNNI1_DEAD_FLOW_VC1_LIMIT */
10645 /* Description: vc1 limit reg, zero disables functionality */
10646 #define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_SHFT 16
10647 #define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_MASK 0x00000000000f0000
10649 /* SH_XNNI1_DEAD_FLOW_VC1_DYN */
10650 /* Description: vc1 counter dynamic value */
10651 #define SH_XNNI1_DEAD_FLOW_VC1_DYN_SHFT 24
10652 #define SH_XNNI1_DEAD_FLOW_VC1_DYN_MASK 0x000000000f000000
10654 /* SH_XNNI1_DEAD_FLOW_VC1_CAP */
10655 /* Description: vc1 counter captured value */
10656 #define SH_XNNI1_DEAD_FLOW_VC1_CAP_SHFT 28
10657 #define SH_XNNI1_DEAD_FLOW_VC1_CAP_MASK 0x00000000f0000000
10659 /* SH_XNNI1_DEAD_FLOW_VC2_LIMIT */
10660 /* Description: vc2 limit reg, zero disables functionality */
10661 #define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_SHFT 32
10662 #define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_MASK 0x0000000f00000000
10664 /* SH_XNNI1_DEAD_FLOW_VC2_DYN */
10665 /* Description: vc2 counter dynamic value */
10666 #define SH_XNNI1_DEAD_FLOW_VC2_DYN_SHFT 40
10667 #define SH_XNNI1_DEAD_FLOW_VC2_DYN_MASK 0x00000f0000000000
10669 /* SH_XNNI1_DEAD_FLOW_VC2_CAP */
10670 /* Description: vc2 counter captured value */
10671 #define SH_XNNI1_DEAD_FLOW_VC2_CAP_SHFT 44
10672 #define SH_XNNI1_DEAD_FLOW_VC2_CAP_MASK 0x0000f00000000000
10674 /* SH_XNNI1_DEAD_FLOW_VC3_LIMIT */
10675 /* Description: vc3 limit reg, zero disables functionality */
10676 #define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_SHFT 48
10677 #define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_MASK 0x000f000000000000
10679 /* SH_XNNI1_DEAD_FLOW_VC3_DYN */
10680 /* Description: vc3 counter dynamic value */
10681 #define SH_XNNI1_DEAD_FLOW_VC3_DYN_SHFT 56
10682 #define SH_XNNI1_DEAD_FLOW_VC3_DYN_MASK 0x0f00000000000000
10684 /* SH_XNNI1_DEAD_FLOW_VC3_CAP */
10685 /* Description: vc3 counter captured value */
10686 #define SH_XNNI1_DEAD_FLOW_VC3_CAP_SHFT 60
10687 #define SH_XNNI1_DEAD_FLOW_VC3_CAP_MASK 0xf000000000000000
10689 /* ==================================================================== */
10690 /* Register "SH_XNNI1_INJECT_AGE" */
10691 /* ==================================================================== */
10693 #define SH_XNNI1_INJECT_AGE 0x0000000150030600
10694 #define SH_XNNI1_INJECT_AGE_MASK 0x000000000000ffff
10695 #define SH_XNNI1_INJECT_AGE_INIT 0x0000000000000000
10697 /* SH_XNNI1_INJECT_AGE_REQUEST_INJECT */
10698 /* Description: Value of AGE field for outgoing requests */
10699 #define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_SHFT 0
10700 #define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_MASK 0x00000000000000ff
10702 /* SH_XNNI1_INJECT_AGE_REPLY_INJECT */
10703 /* Description: Value of AGE field for outgoing replies */
10704 #define SH_XNNI1_INJECT_AGE_REPLY_INJECT_SHFT 8
10705 #define SH_XNNI1_INJECT_AGE_REPLY_INJECT_MASK 0x000000000000ff00
10707 /* ==================================================================== */
10708 /* Register "SH_XN_DEBUG_SEL" */
10709 /* XN Debug Port Select */
10710 /* ==================================================================== */
10712 #define SH_XN_DEBUG_SEL 0x0000000150031000
10713 #define SH_XN_DEBUG_SEL_MASK 0xf777777777777777
10714 #define SH_XN_DEBUG_SEL_INIT 0x0000000000000000
10716 /* SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL */
10717 /* Description: Nibble 0 RLM select */
10718 #define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_SHFT 0
10719 #define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_MASK 0x0000000000000007
10721 /* SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */
10722 /* Description: Nibble 0 Nibble select */
10723 #define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
10724 #define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
10726 /* SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL */
10727 /* Description: Nibble 1 RLM select */
10728 #define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_SHFT 8
10729 #define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_MASK 0x0000000000000700
10731 /* SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */
10732 /* Description: Nibble 1 Nibble select */
10733 #define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
10734 #define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
10736 /* SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL */
10737 /* Description: Nibble 2 RLM select */
10738 #define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_SHFT 16
10739 #define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_MASK 0x0000000000070000
10741 /* SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */
10742 /* Description: Nibble 2 Nibble select */
10743 #define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
10744 #define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
10746 /* SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL */
10747 /* Description: Nibble 3 RLM select */
10748 #define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_SHFT 24
10749 #define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_MASK 0x0000000007000000
10751 /* SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */
10752 /* Description: Nibble 3 Nibble select */
10753 #define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
10754 #define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
10756 /* SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL */
10757 /* Description: Nibble 4 RLM select */
10758 #define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_SHFT 32
10759 #define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_MASK 0x0000000700000000
10761 /* SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */
10762 /* Description: Nibble 4 Nibble select */
10763 #define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
10764 #define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
10766 /* SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL */
10767 /* Description: Nibble 5 RLM select */
10768 #define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_SHFT 40
10769 #define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_MASK 0x0000070000000000
10771 /* SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */
10772 /* Description: Nibble 5 Nibble select */
10773 #define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
10774 #define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
10776 /* SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL */
10777 /* Description: Nibble 6 RLM select */
10778 #define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_SHFT 48
10779 #define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_MASK 0x0007000000000000
10781 /* SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */
10782 /* Description: Nibble 6 Nibble select */
10783 #define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
10784 #define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
10786 /* SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL */
10787 /* Description: Nibble 7 RLM select */
10788 #define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_SHFT 56
10789 #define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_MASK 0x0700000000000000
10791 /* SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */
10792 /* Description: Nibble 7 Nibble select */
10793 #define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
10794 #define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
10796 /* SH_XN_DEBUG_SEL_TRIGGER_ENABLE */
10797 /* Description: Enable trigger on bit 32 of Analyzer data */
10798 #define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_SHFT 63
10799 #define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_MASK 0x8000000000000000
10801 /* ==================================================================== */
10802 /* Register "SH_XN_DEBUG_TRIG_SEL" */
10803 /* XN Debug trigger Select */
10804 /* ==================================================================== */
10806 #define SH_XN_DEBUG_TRIG_SEL 0x0000000150031020
10807 #define SH_XN_DEBUG_TRIG_SEL_MASK 0x7777777777777777
10808 #define SH_XN_DEBUG_TRIG_SEL_INIT 0x0000000000000000
10810 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL */
10811 /* Description: Nibble 0 RLM select */
10812 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_SHFT 0
10813 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_MASK 0x0000000000000007
10815 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL */
10816 /* Description: Nibble 0 Nibble select */
10817 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4
10818 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
10820 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL */
10821 /* Description: Nibble 1 RLM select */
10822 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_SHFT 8
10823 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_MASK 0x0000000000000700
10825 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL */
10826 /* Description: Nibble 1 Nibble select */
10827 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12
10828 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
10830 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL */
10831 /* Description: Nibble 2 RLM select */
10832 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_SHFT 16
10833 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_MASK 0x0000000000070000
10835 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL */
10836 /* Description: Nibble 2 Nibble select */
10837 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20
10838 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
10840 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL */
10841 /* Description: Nibble 3 RLM select */
10842 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_SHFT 24
10843 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_MASK 0x0000000007000000
10845 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL */
10846 /* Description: Nibble 3 Nibble select */
10847 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28
10848 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
10850 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL */
10851 /* Description: Nibble 4 RLM select */
10852 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_SHFT 32
10853 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_MASK 0x0000000700000000
10855 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL */
10856 /* Description: Nibble 4 Nibble select */
10857 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36
10858 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
10860 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL */
10861 /* Description: Nibble 5 RLM select */
10862 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_SHFT 40
10863 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_MASK 0x0000070000000000
10865 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL */
10866 /* Description: Nibble 5 Nibble select */
10867 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44
10868 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
10870 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL */
10871 /* Description: Nibble 6 RLM select */
10872 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_SHFT 48
10873 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_MASK 0x0007000000000000
10875 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL */
10876 /* Description: Nibble 6 Nibble select */
10877 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52
10878 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
10880 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL */
10881 /* Description: Nibble 7 RLM select */
10882 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_SHFT 56
10883 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_MASK 0x0700000000000000
10885 /* SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL */
10886 /* Description: Nibble 7 Nibble select */
10887 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60
10888 #define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
10890 /* ==================================================================== */
10891 /* Register "SH_XN_TRIGGER_COMPARE" */
10892 /* XN Debug Compare */
10893 /* ==================================================================== */
10895 #define SH_XN_TRIGGER_COMPARE 0x0000000150031040
10896 #define SH_XN_TRIGGER_COMPARE_MASK 0x00000000ffffffff
10897 #define SH_XN_TRIGGER_COMPARE_INIT 0x0000000000000000
10899 /* SH_XN_TRIGGER_COMPARE_MASK */
10900 /* Description: Mask to select Debug bits for trigger generation */
10901 #define SH_XN_TRIGGER_COMPARE_MASK_SHFT 0
10902 #define SH_XN_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff
10904 /* ==================================================================== */
10905 /* Register "SH_XN_TRIGGER_DATA" */
10906 /* XN Debug Compare Data */
10907 /* ==================================================================== */
10909 #define SH_XN_TRIGGER_DATA 0x0000000150031050
10910 #define SH_XN_TRIGGER_DATA_MASK 0x00000000ffffffff
10911 #define SH_XN_TRIGGER_DATA_INIT 0x00000000ffffffff
10913 /* SH_XN_TRIGGER_DATA_COMPARE_PATTERN */
10914 /* Description: debug bit pattern for trigger generation */
10915 #define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_SHFT 0
10916 #define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_MASK 0x00000000ffffffff
10918 /* ==================================================================== */
10919 /* Register "SH_XN_IILB_DEBUG_SEL" */
10920 /* XN IILB Debug Port Select */
10921 /* ==================================================================== */
10923 #define SH_XN_IILB_DEBUG_SEL 0x0000000150031060
10924 #define SH_XN_IILB_DEBUG_SEL_MASK 0x7777777777777777
10925 #define SH_XN_IILB_DEBUG_SEL_INIT 0x0000000000000000
10927 /* SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL */
10928 /* Description: Nibble 0 input select */
10929 #define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
10930 #define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
10932 /* SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */
10933 /* Description: Nibble 0 Nibble select */
10934 #define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
10935 #define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
10937 /* SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL */
10938 /* Description: Nibble 1 input select */
10939 #define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
10940 #define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
10942 /* SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */
10943 /* Description: Nibble 1 Nibble select */
10944 #define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
10945 #define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
10947 /* SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL */
10948 /* Description: Nibble 2 input select */
10949 #define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
10950 #define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
10952 /* SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */
10953 /* Description: Nibble 2 Nibble select */
10954 #define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
10955 #define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
10957 /* SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL */
10958 /* Description: Nibble 3 input select */
10959 #define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
10960 #define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
10962 /* SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */
10963 /* Description: Nibble 3 Nibble select */
10964 #define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
10965 #define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
10967 /* SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL */
10968 /* Description: Nibble 4 input select */
10969 #define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
10970 #define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
10972 /* SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */
10973 /* Description: Nibble 4 Nibble select */
10974 #define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
10975 #define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
10977 /* SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL */
10978 /* Description: Nibble 5 input select */
10979 #define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
10980 #define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
10982 /* SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */
10983 /* Description: Nibble 5 Nibble select */
10984 #define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
10985 #define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
10987 /* SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL */
10988 /* Description: Nibble 6 input select */
10989 #define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
10990 #define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
10992 /* SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */
10993 /* Description: Nibble 6 Nibble select */
10994 #define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
10995 #define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
10997 /* SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL */
10998 /* Description: Nibble 7 input select */
10999 #define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
11000 #define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
11002 /* SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */
11003 /* Description: Nibble 7 Nibble select */
11004 #define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
11005 #define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
11007 /* ==================================================================== */
11008 /* Register "SH_XN_PI_DEBUG_SEL" */
11009 /* XN PI Debug Port Select */
11010 /* ==================================================================== */
11012 #define SH_XN_PI_DEBUG_SEL 0x00000001500310a0
11013 #define SH_XN_PI_DEBUG_SEL_MASK 0x7777777777777777
11014 #define SH_XN_PI_DEBUG_SEL_INIT 0x0000000000000000
11016 /* SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL */
11017 /* Description: Nibble 0 input select */
11018 #define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
11019 #define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
11021 /* SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */
11022 /* Description: Nibble 0 Nibble select */
11023 #define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
11024 #define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
11026 /* SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL */
11027 /* Description: Nibble 1 input select */
11028 #define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
11029 #define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
11031 /* SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */
11032 /* Description: Nibble 1 Nibble select */
11033 #define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
11034 #define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
11036 /* SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL */
11037 /* Description: Nibble 2 input select */
11038 #define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
11039 #define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
11041 /* SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */
11042 /* Description: Nibble 2 Nibble select */
11043 #define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
11044 #define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
11046 /* SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL */
11047 /* Description: Nibble 3 input select */
11048 #define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
11049 #define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
11051 /* SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */
11052 /* Description: Nibble 3 Nibble select */
11053 #define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
11054 #define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
11056 /* SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL */
11057 /* Description: Nibble 4 input select */
11058 #define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
11059 #define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
11061 /* SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */
11062 /* Description: Nibble 4 Nibble select */
11063 #define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
11064 #define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
11066 /* SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL */
11067 /* Description: Nibble 5 input select */
11068 #define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
11069 #define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
11071 /* SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */
11072 /* Description: Nibble 5 Nibble select */
11073 #define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
11074 #define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
11076 /* SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL */
11077 /* Description: Nibble 6 input select */
11078 #define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
11079 #define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
11081 /* SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */
11082 /* Description: Nibble 6 Nibble select */
11083 #define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
11084 #define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
11086 /* SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL */
11087 /* Description: Nibble 7 input select */
11088 #define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
11089 #define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
11091 /* SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */
11092 /* Description: Nibble 7 Nibble select */
11093 #define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
11094 #define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
11096 /* ==================================================================== */
11097 /* Register "SH_XN_MD_DEBUG_SEL" */
11098 /* XN MD Debug Port Select */
11099 /* ==================================================================== */
11101 #define SH_XN_MD_DEBUG_SEL 0x0000000150031080
11102 #define SH_XN_MD_DEBUG_SEL_MASK 0x7777777777777777
11103 #define SH_XN_MD_DEBUG_SEL_INIT 0x0000000000000000
11105 /* SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL */
11106 /* Description: Nibble 0 input select */
11107 #define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
11108 #define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
11110 /* SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */
11111 /* Description: Nibble 0 Nibble select */
11112 #define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
11113 #define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
11115 /* SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL */
11116 /* Description: Nibble 1 input select */
11117 #define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
11118 #define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
11120 /* SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */
11121 /* Description: Nibble 1 Nibble select */
11122 #define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
11123 #define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
11125 /* SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL */
11126 /* Description: Nibble 2 input select */
11127 #define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
11128 #define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
11130 /* SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */
11131 /* Description: Nibble 2 Nibble select */
11132 #define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
11133 #define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
11135 /* SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL */
11136 /* Description: Nibble 3 input select */
11137 #define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
11138 #define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
11140 /* SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */
11141 /* Description: Nibble 3 Nibble select */
11142 #define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
11143 #define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
11145 /* SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL */
11146 /* Description: Nibble 4 input select */
11147 #define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
11148 #define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
11150 /* SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */
11151 /* Description: Nibble 4 Nibble select */
11152 #define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
11153 #define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
11155 /* SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL */
11156 /* Description: Nibble 5 input select */
11157 #define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
11158 #define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
11160 /* SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */
11161 /* Description: Nibble 5 Nibble select */
11162 #define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
11163 #define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
11165 /* SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL */
11166 /* Description: Nibble 6 input select */
11167 #define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
11168 #define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
11170 /* SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */
11171 /* Description: Nibble 6 Nibble select */
11172 #define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
11173 #define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
11175 /* SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL */
11176 /* Description: Nibble 7 input select */
11177 #define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
11178 #define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
11180 /* SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */
11181 /* Description: Nibble 7 Nibble select */
11182 #define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
11183 #define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
11185 /* ==================================================================== */
11186 /* Register "SH_XN_NI0_DEBUG_SEL" */
11187 /* XN NI0 Debug Port Select */
11188 /* ==================================================================== */
11190 #define SH_XN_NI0_DEBUG_SEL 0x00000001500310c0
11191 #define SH_XN_NI0_DEBUG_SEL_MASK 0x7777777777777777
11192 #define SH_XN_NI0_DEBUG_SEL_INIT 0x0000000000000000
11194 /* SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL */
11195 /* Description: Nibble 0 input select */
11196 #define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
11197 #define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
11199 /* SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */
11200 /* Description: Nibble 0 Nibble select */
11201 #define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
11202 #define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
11204 /* SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL */
11205 /* Description: Nibble 1 input select */
11206 #define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
11207 #define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
11209 /* SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */
11210 /* Description: Nibble 1 Nibble select */
11211 #define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
11212 #define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
11214 /* SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL */
11215 /* Description: Nibble 2 input select */
11216 #define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
11217 #define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
11219 /* SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */
11220 /* Description: Nibble 2 Nibble select */
11221 #define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
11222 #define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
11224 /* SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL */
11225 /* Description: Nibble 3 input select */
11226 #define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
11227 #define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
11229 /* SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */
11230 /* Description: Nibble 3 Nibble select */
11231 #define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
11232 #define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
11234 /* SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL */
11235 /* Description: Nibble 4 input select */
11236 #define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
11237 #define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
11239 /* SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */
11240 /* Description: Nibble 4 Nibble select */
11241 #define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
11242 #define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
11244 /* SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL */
11245 /* Description: Nibble 5 input select */
11246 #define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
11247 #define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
11249 /* SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */
11250 /* Description: Nibble 5 Nibble select */
11251 #define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
11252 #define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
11254 /* SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL */
11255 /* Description: Nibble 6 input select */
11256 #define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
11257 #define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
11259 /* SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */
11260 /* Description: Nibble 6 Nibble select */
11261 #define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
11262 #define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
11264 /* SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL */
11265 /* Description: Nibble 7 input select */
11266 #define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
11267 #define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
11269 /* SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */
11270 /* Description: Nibble 7 Nibble select */
11271 #define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
11272 #define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
11274 /* ==================================================================== */
11275 /* Register "SH_XN_NI1_DEBUG_SEL" */
11276 /* XN NI1 Debug Port Select */
11277 /* ==================================================================== */
11279 #define SH_XN_NI1_DEBUG_SEL 0x00000001500310e0
11280 #define SH_XN_NI1_DEBUG_SEL_MASK 0x7777777777777777
11281 #define SH_XN_NI1_DEBUG_SEL_INIT 0x0000000000000000
11283 /* SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL */
11284 /* Description: Nibble 0 input select */
11285 #define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
11286 #define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
11288 /* SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */
11289 /* Description: Nibble 0 Nibble select */
11290 #define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
11291 #define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
11293 /* SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL */
11294 /* Description: Nibble 1 input select */
11295 #define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
11296 #define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
11298 /* SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */
11299 /* Description: Nibble 1 Nibble select */
11300 #define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
11301 #define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
11303 /* SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL */
11304 /* Description: Nibble 2 input select */
11305 #define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
11306 #define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
11308 /* SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */
11309 /* Description: Nibble 2 Nibble select */
11310 #define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
11311 #define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
11313 /* SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL */
11314 /* Description: Nibble 3 input select */
11315 #define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
11316 #define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
11318 /* SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */
11319 /* Description: Nibble 3 Nibble select */
11320 #define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
11321 #define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
11323 /* SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL */
11324 /* Description: Nibble 4 input select */
11325 #define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
11326 #define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
11328 /* SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */
11329 /* Description: Nibble 4 Nibble select */
11330 #define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
11331 #define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
11333 /* SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL */
11334 /* Description: Nibble 5 input select */
11335 #define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
11336 #define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
11338 /* SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */
11339 /* Description: Nibble 5 Nibble select */
11340 #define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
11341 #define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
11343 /* SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL */
11344 /* Description: Nibble 6 input select */
11345 #define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
11346 #define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
11348 /* SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */
11349 /* Description: Nibble 6 Nibble select */
11350 #define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
11351 #define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
11353 /* SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL */
11354 /* Description: Nibble 7 input select */
11355 #define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
11356 #define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
11358 /* SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */
11359 /* Description: Nibble 7 Nibble select */
11360 #define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
11361 #define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
11363 /* ==================================================================== */
11364 /* Register "SH_XN_IILB_LB_CMP_EXP_DATA0" */
11365 /* IILB compare LB input expected data0 */
11366 /* ==================================================================== */
11368 #define SH_XN_IILB_LB_CMP_EXP_DATA0 0x0000000150031100
11369 #define SH_XN_IILB_LB_CMP_EXP_DATA0_MASK 0xffffffffffffffff
11370 #define SH_XN_IILB_LB_CMP_EXP_DATA0_INIT 0x0000000000000000
11372 /* SH_XN_IILB_LB_CMP_EXP_DATA0_DATA */
11373 /* Description: Expected data 0 */
11374 #define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_SHFT 0
11375 #define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
11377 /* ==================================================================== */
11378 /* Register "SH_XN_IILB_LB_CMP_EXP_DATA1" */
11379 /* IILB compare LB input expected data1 */
11380 /* ==================================================================== */
11382 #define SH_XN_IILB_LB_CMP_EXP_DATA1 0x0000000150031110
11383 #define SH_XN_IILB_LB_CMP_EXP_DATA1_MASK 0xffffffffffffffff
11384 #define SH_XN_IILB_LB_CMP_EXP_DATA1_INIT 0x0000000000000000
11386 /* SH_XN_IILB_LB_CMP_EXP_DATA1_DATA */
11387 /* Description: Expected data 1 */
11388 #define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_SHFT 0
11389 #define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
11391 /* ==================================================================== */
11392 /* Register "SH_XN_IILB_LB_CMP_ENABLE0" */
11393 /* IILB compare LB input enable0 */
11394 /* ==================================================================== */
11396 #define SH_XN_IILB_LB_CMP_ENABLE0 0x0000000150031120
11397 #define SH_XN_IILB_LB_CMP_ENABLE0_MASK 0xffffffffffffffff
11398 #define SH_XN_IILB_LB_CMP_ENABLE0_INIT 0x0000000000000000
11400 /* SH_XN_IILB_LB_CMP_ENABLE0_ENABLE */
11401 /* Description: Enable0 */
11402 #define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_SHFT 0
11403 #define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
11405 /* ==================================================================== */
11406 /* Register "SH_XN_IILB_LB_CMP_ENABLE1" */
11407 /* IILB compare LB input enable1 */
11408 /* ==================================================================== */
11410 #define SH_XN_IILB_LB_CMP_ENABLE1 0x0000000150031130
11411 #define SH_XN_IILB_LB_CMP_ENABLE1_MASK 0xffffffffffffffff
11412 #define SH_XN_IILB_LB_CMP_ENABLE1_INIT 0x0000000000000000
11414 /* SH_XN_IILB_LB_CMP_ENABLE1_ENABLE */
11415 /* Description: Enable1 */
11416 #define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_SHFT 0
11417 #define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
11419 /* ==================================================================== */
11420 /* Register "SH_XN_IILB_II_CMP_EXP_DATA0" */
11421 /* IILB compare II input expected data0 */
11422 /* ==================================================================== */
11424 #define SH_XN_IILB_II_CMP_EXP_DATA0 0x0000000150031140
11425 #define SH_XN_IILB_II_CMP_EXP_DATA0_MASK 0xffffffffffffffff
11426 #define SH_XN_IILB_II_CMP_EXP_DATA0_INIT 0x0000000000000000
11428 /* SH_XN_IILB_II_CMP_EXP_DATA0_DATA */
11429 /* Description: Expected data 0 */
11430 #define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_SHFT 0
11431 #define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
11433 /* ==================================================================== */
11434 /* Register "SH_XN_IILB_II_CMP_EXP_DATA1" */
11435 /* IILB compare II input expected data1 */
11436 /* ==================================================================== */
11438 #define SH_XN_IILB_II_CMP_EXP_DATA1 0x0000000150031150
11439 #define SH_XN_IILB_II_CMP_EXP_DATA1_MASK 0xffffffffffffffff
11440 #define SH_XN_IILB_II_CMP_EXP_DATA1_INIT 0x0000000000000000
11442 /* SH_XN_IILB_II_CMP_EXP_DATA1_DATA */
11443 /* Description: Expected data 1 */
11444 #define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_SHFT 0
11445 #define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
11447 /* ==================================================================== */
11448 /* Register "SH_XN_IILB_II_CMP_ENABLE0" */
11449 /* IILB compare II input enable0 */
11450 /* ==================================================================== */
11452 #define SH_XN_IILB_II_CMP_ENABLE0 0x0000000150031160
11453 #define SH_XN_IILB_II_CMP_ENABLE0_MASK 0xffffffffffffffff
11454 #define SH_XN_IILB_II_CMP_ENABLE0_INIT 0x0000000000000000
11456 /* SH_XN_IILB_II_CMP_ENABLE0_ENABLE */
11457 /* Description: Enable0 */
11458 #define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_SHFT 0
11459 #define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
11461 /* ==================================================================== */
11462 /* Register "SH_XN_IILB_II_CMP_ENABLE1" */
11463 /* IILB compare II input enable1 */
11464 /* ==================================================================== */
11466 #define SH_XN_IILB_II_CMP_ENABLE1 0x0000000150031170
11467 #define SH_XN_IILB_II_CMP_ENABLE1_MASK 0xffffffffffffffff
11468 #define SH_XN_IILB_II_CMP_ENABLE1_INIT 0x0000000000000000
11470 /* SH_XN_IILB_II_CMP_ENABLE1_ENABLE */
11471 /* Description: Enable1 */
11472 #define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_SHFT 0
11473 #define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
11475 /* ==================================================================== */
11476 /* Register "SH_XN_IILB_MD_CMP_EXP_DATA0" */
11477 /* IILB compare MD input expected data0 */
11478 /* ==================================================================== */
11480 #define SH_XN_IILB_MD_CMP_EXP_DATA0 0x0000000150031180
11481 #define SH_XN_IILB_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff
11482 #define SH_XN_IILB_MD_CMP_EXP_DATA0_INIT 0x0000000000000000
11484 /* SH_XN_IILB_MD_CMP_EXP_DATA0_DATA */
11485 /* Description: Expected data 0 */
11486 #define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_SHFT 0
11487 #define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
11489 /* ==================================================================== */
11490 /* Register "SH_XN_IILB_MD_CMP_EXP_DATA1" */
11491 /* IILB compare MD input expected data1 */
11492 /* ==================================================================== */
11494 #define SH_XN_IILB_MD_CMP_EXP_DATA1 0x0000000150031190
11495 #define SH_XN_IILB_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff
11496 #define SH_XN_IILB_MD_CMP_EXP_DATA1_INIT 0x0000000000000000
11498 /* SH_XN_IILB_MD_CMP_EXP_DATA1_DATA */
11499 /* Description: Expected data 1 */
11500 #define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_SHFT 0
11501 #define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
11503 /* ==================================================================== */
11504 /* Register "SH_XN_IILB_MD_CMP_ENABLE0" */
11505 /* IILB compare MD input enable0 */
11506 /* ==================================================================== */
11508 #define SH_XN_IILB_MD_CMP_ENABLE0 0x00000001500311a0
11509 #define SH_XN_IILB_MD_CMP_ENABLE0_MASK 0xffffffffffffffff
11510 #define SH_XN_IILB_MD_CMP_ENABLE0_INIT 0x0000000000000000
11512 /* SH_XN_IILB_MD_CMP_ENABLE0_ENABLE */
11513 /* Description: Enable0 */
11514 #define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_SHFT 0
11515 #define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
11517 /* ==================================================================== */
11518 /* Register "SH_XN_IILB_MD_CMP_ENABLE1" */
11519 /* IILB compare MD input enable1 */
11520 /* ==================================================================== */
11522 #define SH_XN_IILB_MD_CMP_ENABLE1 0x00000001500311b0
11523 #define SH_XN_IILB_MD_CMP_ENABLE1_MASK 0xffffffffffffffff
11524 #define SH_XN_IILB_MD_CMP_ENABLE1_INIT 0x0000000000000000
11526 /* SH_XN_IILB_MD_CMP_ENABLE1_ENABLE */
11527 /* Description: Enable1 */
11528 #define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_SHFT 0
11529 #define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
11531 /* ==================================================================== */
11532 /* Register "SH_XN_IILB_PI_CMP_EXP_DATA0" */
11533 /* IILB compare PI input expected data0 */
11534 /* ==================================================================== */
11536 #define SH_XN_IILB_PI_CMP_EXP_DATA0 0x00000001500311c0
11537 #define SH_XN_IILB_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff
11538 #define SH_XN_IILB_PI_CMP_EXP_DATA0_INIT 0x0000000000000000
11540 /* SH_XN_IILB_PI_CMP_EXP_DATA0_DATA */
11541 /* Description: Expected data 0 */
11542 #define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_SHFT 0
11543 #define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
11545 /* ==================================================================== */
11546 /* Register "SH_XN_IILB_PI_CMP_EXP_DATA1" */
11547 /* IILB compare PI input expected data1 */
11548 /* ==================================================================== */
11550 #define SH_XN_IILB_PI_CMP_EXP_DATA1 0x00000001500311d0
11551 #define SH_XN_IILB_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff
11552 #define SH_XN_IILB_PI_CMP_EXP_DATA1_INIT 0x0000000000000000
11554 /* SH_XN_IILB_PI_CMP_EXP_DATA1_DATA */
11555 /* Description: Expected data 1 */
11556 #define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_SHFT 0
11557 #define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
11559 /* ==================================================================== */
11560 /* Register "SH_XN_IILB_PI_CMP_ENABLE0" */
11561 /* IILB compare PI input enable0 */
11562 /* ==================================================================== */
11564 #define SH_XN_IILB_PI_CMP_ENABLE0 0x00000001500311e0
11565 #define SH_XN_IILB_PI_CMP_ENABLE0_MASK 0xffffffffffffffff
11566 #define SH_XN_IILB_PI_CMP_ENABLE0_INIT 0x0000000000000000
11568 /* SH_XN_IILB_PI_CMP_ENABLE0_ENABLE */
11569 /* Description: Enable0 */
11570 #define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_SHFT 0
11571 #define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
11573 /* ==================================================================== */
11574 /* Register "SH_XN_IILB_PI_CMP_ENABLE1" */
11575 /* IILB compare PI input enable1 */
11576 /* ==================================================================== */
11578 #define SH_XN_IILB_PI_CMP_ENABLE1 0x00000001500311f0
11579 #define SH_XN_IILB_PI_CMP_ENABLE1_MASK 0xffffffffffffffff
11580 #define SH_XN_IILB_PI_CMP_ENABLE1_INIT 0x0000000000000000
11582 /* SH_XN_IILB_PI_CMP_ENABLE1_ENABLE */
11583 /* Description: Enable1 */
11584 #define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_SHFT 0
11585 #define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
11587 /* ==================================================================== */
11588 /* Register "SH_XN_IILB_NI0_CMP_EXP_DATA0" */
11589 /* IILB compare NI0 input expected data0 */
11590 /* ==================================================================== */
11592 #define SH_XN_IILB_NI0_CMP_EXP_DATA0 0x0000000150031200
11593 #define SH_XN_IILB_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff
11594 #define SH_XN_IILB_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000
11596 /* SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA */
11597 /* Description: Expected data 0 */
11598 #define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_SHFT 0
11599 #define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
11601 /* ==================================================================== */
11602 /* Register "SH_XN_IILB_NI0_CMP_EXP_DATA1" */
11603 /* IILB compare NI0 input expected data1 */
11604 /* ==================================================================== */
11606 #define SH_XN_IILB_NI0_CMP_EXP_DATA1 0x0000000150031210
11607 #define SH_XN_IILB_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff
11608 #define SH_XN_IILB_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000
11610 /* SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA */
11611 /* Description: Expected data 1 */
11612 #define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_SHFT 0
11613 #define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
11615 /* ==================================================================== */
11616 /* Register "SH_XN_IILB_NI0_CMP_ENABLE0" */
11617 /* IILB compare NI0 input enable0 */
11618 /* ==================================================================== */
11620 #define SH_XN_IILB_NI0_CMP_ENABLE0 0x0000000150031220
11621 #define SH_XN_IILB_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff
11622 #define SH_XN_IILB_NI0_CMP_ENABLE0_INIT 0x0000000000000000
11624 /* SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE */
11625 /* Description: Enable0 */
11626 #define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_SHFT 0
11627 #define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
11629 /* ==================================================================== */
11630 /* Register "SH_XN_IILB_NI0_CMP_ENABLE1" */
11631 /* IILB compare NI0 input enable1 */
11632 /* ==================================================================== */
11634 #define SH_XN_IILB_NI0_CMP_ENABLE1 0x0000000150031230
11635 #define SH_XN_IILB_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff
11636 #define SH_XN_IILB_NI0_CMP_ENABLE1_INIT 0x0000000000000000
11638 /* SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE */
11639 /* Description: Enable1 */
11640 #define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_SHFT 0
11641 #define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
11643 /* ==================================================================== */
11644 /* Register "SH_XN_IILB_NI1_CMP_EXP_DATA0" */
11645 /* IILB compare NI1 input expected data0 */
11646 /* ==================================================================== */
11648 #define SH_XN_IILB_NI1_CMP_EXP_DATA0 0x0000000150031240
11649 #define SH_XN_IILB_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff
11650 #define SH_XN_IILB_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000
11652 /* SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA */
11653 /* Description: Expected data 0 */
11654 #define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_SHFT 0
11655 #define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
11657 /* ==================================================================== */
11658 /* Register "SH_XN_IILB_NI1_CMP_EXP_DATA1" */
11659 /* IILB compare NI1 input expected data1 */
11660 /* ==================================================================== */
11662 #define SH_XN_IILB_NI1_CMP_EXP_DATA1 0x0000000150031250
11663 #define SH_XN_IILB_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff
11664 #define SH_XN_IILB_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000
11666 /* SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA */
11667 /* Description: Expected data 1 */
11668 #define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_SHFT 0
11669 #define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
11671 /* ==================================================================== */
11672 /* Register "SH_XN_IILB_NI1_CMP_ENABLE0" */
11673 /* IILB compare NI1 input enable0 */
11674 /* ==================================================================== */
11676 #define SH_XN_IILB_NI1_CMP_ENABLE0 0x0000000150031260
11677 #define SH_XN_IILB_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff
11678 #define SH_XN_IILB_NI1_CMP_ENABLE0_INIT 0x0000000000000000
11680 /* SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE */
11681 /* Description: Enable0 */
11682 #define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_SHFT 0
11683 #define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
11685 /* ==================================================================== */
11686 /* Register "SH_XN_IILB_NI1_CMP_ENABLE1" */
11687 /* IILB compare NI1 input enable1 */
11688 /* ==================================================================== */
11690 #define SH_XN_IILB_NI1_CMP_ENABLE1 0x0000000150031270
11691 #define SH_XN_IILB_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff
11692 #define SH_XN_IILB_NI1_CMP_ENABLE1_INIT 0x0000000000000000
11694 /* SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE */
11695 /* Description: Enable1 */
11696 #define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_SHFT 0
11697 #define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
11699 /* ==================================================================== */
11700 /* Register "SH_XN_MD_IILB_CMP_EXP_DATA0" */
11701 /* MD compare IILB input expected data0 */
11702 /* ==================================================================== */
11704 #define SH_XN_MD_IILB_CMP_EXP_DATA0 0x0000000150031500
11705 #define SH_XN_MD_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff
11706 #define SH_XN_MD_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000
11708 /* SH_XN_MD_IILB_CMP_EXP_DATA0_DATA */
11709 /* Description: Expected data 0 */
11710 #define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_SHFT 0
11711 #define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
11713 /* ==================================================================== */
11714 /* Register "SH_XN_MD_IILB_CMP_EXP_DATA1" */
11715 /* MD compare IILB input expected data1 */
11716 /* ==================================================================== */
11718 #define SH_XN_MD_IILB_CMP_EXP_DATA1 0x0000000150031510
11719 #define SH_XN_MD_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff
11720 #define SH_XN_MD_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000
11722 /* SH_XN_MD_IILB_CMP_EXP_DATA1_DATA */
11723 /* Description: Expected data 1 */
11724 #define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_SHFT 0
11725 #define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
11727 /* ==================================================================== */
11728 /* Register "SH_XN_MD_IILB_CMP_ENABLE0" */
11729 /* MD compare IILB input enable0 */
11730 /* ==================================================================== */
11732 #define SH_XN_MD_IILB_CMP_ENABLE0 0x0000000150031520
11733 #define SH_XN_MD_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff
11734 #define SH_XN_MD_IILB_CMP_ENABLE0_INIT 0x0000000000000000
11736 /* SH_XN_MD_IILB_CMP_ENABLE0_ENABLE */
11737 /* Description: Enable0 */
11738 #define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_SHFT 0
11739 #define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
11741 /* ==================================================================== */
11742 /* Register "SH_XN_MD_IILB_CMP_ENABLE1" */
11743 /* MD compare IILB input enable1 */
11744 /* ==================================================================== */
11746 #define SH_XN_MD_IILB_CMP_ENABLE1 0x0000000150031530
11747 #define SH_XN_MD_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff
11748 #define SH_XN_MD_IILB_CMP_ENABLE1_INIT 0x0000000000000000
11750 /* SH_XN_MD_IILB_CMP_ENABLE1_ENABLE */
11751 /* Description: Enable1 */
11752 #define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_SHFT 0
11753 #define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
11755 /* ==================================================================== */
11756 /* Register "SH_XN_MD_NI0_CMP_EXP_DATA0" */
11757 /* MD compare NI0 input expected data0 */
11758 /* ==================================================================== */
11760 #define SH_XN_MD_NI0_CMP_EXP_DATA0 0x0000000150031540
11761 #define SH_XN_MD_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff
11762 #define SH_XN_MD_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000
11764 /* SH_XN_MD_NI0_CMP_EXP_DATA0_DATA */
11765 /* Description: Expected data 0 */
11766 #define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_SHFT 0
11767 #define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
11769 /* ==================================================================== */
11770 /* Register "SH_XN_MD_NI0_CMP_EXP_DATA1" */
11771 /* MD compare NI0 input expected data1 */
11772 /* ==================================================================== */
11774 #define SH_XN_MD_NI0_CMP_EXP_DATA1 0x0000000150031550
11775 #define SH_XN_MD_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff
11776 #define SH_XN_MD_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000
11778 /* SH_XN_MD_NI0_CMP_EXP_DATA1_DATA */
11779 /* Description: Expected data 1 */
11780 #define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_SHFT 0
11781 #define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
11783 /* ==================================================================== */
11784 /* Register "SH_XN_MD_NI0_CMP_ENABLE0" */
11785 /* MD compare NI0 input enable0 */
11786 /* ==================================================================== */
11788 #define SH_XN_MD_NI0_CMP_ENABLE0 0x0000000150031560
11789 #define SH_XN_MD_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff
11790 #define SH_XN_MD_NI0_CMP_ENABLE0_INIT 0x0000000000000000
11792 /* SH_XN_MD_NI0_CMP_ENABLE0_ENABLE */
11793 /* Description: Enable0 */
11794 #define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_SHFT 0
11795 #define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
11797 /* ==================================================================== */
11798 /* Register "SH_XN_MD_NI0_CMP_ENABLE1" */
11799 /* MD compare NI0 input enable1 */
11800 /* ==================================================================== */
11802 #define SH_XN_MD_NI0_CMP_ENABLE1 0x0000000150031570
11803 #define SH_XN_MD_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff
11804 #define SH_XN_MD_NI0_CMP_ENABLE1_INIT 0x0000000000000000
11806 /* SH_XN_MD_NI0_CMP_ENABLE1_ENABLE */
11807 /* Description: Enable1 */
11808 #define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_SHFT 0
11809 #define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
11811 /* ==================================================================== */
11812 /* Register "SH_XN_MD_NI1_CMP_EXP_DATA0" */
11813 /* MD compare NI1 input expected data0 */
11814 /* ==================================================================== */
11816 #define SH_XN_MD_NI1_CMP_EXP_DATA0 0x0000000150031580
11817 #define SH_XN_MD_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff
11818 #define SH_XN_MD_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000
11820 /* SH_XN_MD_NI1_CMP_EXP_DATA0_DATA */
11821 /* Description: Expected data 0 */
11822 #define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_SHFT 0
11823 #define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
11825 /* ==================================================================== */
11826 /* Register "SH_XN_MD_NI1_CMP_EXP_DATA1" */
11827 /* MD compare NI1 input expected data1 */
11828 /* ==================================================================== */
11830 #define SH_XN_MD_NI1_CMP_EXP_DATA1 0x0000000150031590
11831 #define SH_XN_MD_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff
11832 #define SH_XN_MD_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000
11834 /* SH_XN_MD_NI1_CMP_EXP_DATA1_DATA */
11835 /* Description: Expected data 1 */
11836 #define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_SHFT 0
11837 #define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
11839 /* ==================================================================== */
11840 /* Register "SH_XN_MD_NI1_CMP_ENABLE0" */
11841 /* MD compare NI1 input enable0 */
11842 /* ==================================================================== */
11844 #define SH_XN_MD_NI1_CMP_ENABLE0 0x00000001500315a0
11845 #define SH_XN_MD_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff
11846 #define SH_XN_MD_NI1_CMP_ENABLE0_INIT 0x0000000000000000
11848 /* SH_XN_MD_NI1_CMP_ENABLE0_ENABLE */
11849 /* Description: Enable0 */
11850 #define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_SHFT 0
11851 #define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
11853 /* ==================================================================== */
11854 /* Register "SH_XN_MD_NI1_CMP_ENABLE1" */
11855 /* MD compare NI1 input enable1 */
11856 /* ==================================================================== */
11858 #define SH_XN_MD_NI1_CMP_ENABLE1 0x00000001500315b0
11859 #define SH_XN_MD_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff
11860 #define SH_XN_MD_NI1_CMP_ENABLE1_INIT 0x0000000000000000
11862 /* SH_XN_MD_NI1_CMP_ENABLE1_ENABLE */
11863 /* Description: Enable1 */
11864 #define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_SHFT 0
11865 #define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
11867 /* ==================================================================== */
11868 /* Register "SH_XN_MD_SIC_CMP_EXP_HDR0" */
11869 /* MD compare SIC input expected header0 */
11870 /* ==================================================================== */
11872 #define SH_XN_MD_SIC_CMP_EXP_HDR0 0x00000001500315c0
11873 #define SH_XN_MD_SIC_CMP_EXP_HDR0_MASK 0xffffffffffffffff
11874 #define SH_XN_MD_SIC_CMP_EXP_HDR0_INIT 0x0000000000000000
11876 /* SH_XN_MD_SIC_CMP_EXP_HDR0_DATA */
11877 /* Description: Expected data 0 */
11878 #define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_SHFT 0
11879 #define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_MASK 0xffffffffffffffff
11881 /* ==================================================================== */
11882 /* Register "SH_XN_MD_SIC_CMP_EXP_HDR1" */
11883 /* MD compare SIC input expected header1 */
11884 /* ==================================================================== */
11886 #define SH_XN_MD_SIC_CMP_EXP_HDR1 0x00000001500315d0
11887 #define SH_XN_MD_SIC_CMP_EXP_HDR1_MASK 0x000003ffffffffff
11888 #define SH_XN_MD_SIC_CMP_EXP_HDR1_INIT 0x0000000000000000
11890 /* SH_XN_MD_SIC_CMP_EXP_HDR1_DATA */
11891 /* Description: Expected data 1 */
11892 #define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_SHFT 0
11893 #define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_MASK 0x000003ffffffffff
11895 /* ==================================================================== */
11896 /* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0" */
11897 /* MD compare SIC header enable0 */
11898 /* ==================================================================== */
11900 #define SH_XN_MD_SIC_CMP_HDR_ENABLE0 0x00000001500315e0
11901 #define SH_XN_MD_SIC_CMP_HDR_ENABLE0_MASK 0xffffffffffffffff
11902 #define SH_XN_MD_SIC_CMP_HDR_ENABLE0_INIT 0x0000000000000000
11904 /* SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE */
11905 /* Description: Enable0 */
11906 #define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0
11907 #define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff
11909 /* ==================================================================== */
11910 /* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1" */
11911 /* MD compare SIC header enable1 */
11912 /* ==================================================================== */
11914 #define SH_XN_MD_SIC_CMP_HDR_ENABLE1 0x00000001500315f0
11915 #define SH_XN_MD_SIC_CMP_HDR_ENABLE1_MASK 0x000003ffffffffff
11916 #define SH_XN_MD_SIC_CMP_HDR_ENABLE1_INIT 0x0000000000000000
11918 /* SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE */
11919 /* Description: Enable1 */
11920 #define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0
11921 #define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff
11923 /* ==================================================================== */
11924 /* Register "SH_XN_MD_SIC_CMP_DATA0" */
11925 /* MD compare SIC data0 */
11926 /* ==================================================================== */
11928 #define SH_XN_MD_SIC_CMP_DATA0 0x0000000150031600
11929 #define SH_XN_MD_SIC_CMP_DATA0_MASK 0xffffffffffffffff
11930 #define SH_XN_MD_SIC_CMP_DATA0_INIT 0x0000000000000000
11932 /* SH_XN_MD_SIC_CMP_DATA0_DATA0 */
11933 /* Description: Data0 */
11934 #define SH_XN_MD_SIC_CMP_DATA0_DATA0_SHFT 0
11935 #define SH_XN_MD_SIC_CMP_DATA0_DATA0_MASK 0xffffffffffffffff
11937 /* ==================================================================== */
11938 /* Register "SH_XN_MD_SIC_CMP_DATA1" */
11939 /* MD compare SIC data1 */
11940 /* ==================================================================== */
11942 #define SH_XN_MD_SIC_CMP_DATA1 0x0000000150031610
11943 #define SH_XN_MD_SIC_CMP_DATA1_MASK 0xffffffffffffffff
11944 #define SH_XN_MD_SIC_CMP_DATA1_INIT 0x0000000000000000
11946 /* SH_XN_MD_SIC_CMP_DATA1_DATA1 */
11947 /* Description: Data1 */
11948 #define SH_XN_MD_SIC_CMP_DATA1_DATA1_SHFT 0
11949 #define SH_XN_MD_SIC_CMP_DATA1_DATA1_MASK 0xffffffffffffffff
11951 /* ==================================================================== */
11952 /* Register "SH_XN_MD_SIC_CMP_DATA2" */
11953 /* MD compare SIC data2 */
11954 /* ==================================================================== */
11956 #define SH_XN_MD_SIC_CMP_DATA2 0x0000000150031620
11957 #define SH_XN_MD_SIC_CMP_DATA2_MASK 0xffffffffffffffff
11958 #define SH_XN_MD_SIC_CMP_DATA2_INIT 0x0000000000000000
11960 /* SH_XN_MD_SIC_CMP_DATA2_DATA2 */
11961 /* Description: Data2 */
11962 #define SH_XN_MD_SIC_CMP_DATA2_DATA2_SHFT 0
11963 #define SH_XN_MD_SIC_CMP_DATA2_DATA2_MASK 0xffffffffffffffff
11965 /* ==================================================================== */
11966 /* Register "SH_XN_MD_SIC_CMP_DATA3" */
11967 /* MD compare SIC data3 */
11968 /* ==================================================================== */
11970 #define SH_XN_MD_SIC_CMP_DATA3 0x0000000150031630
11971 #define SH_XN_MD_SIC_CMP_DATA3_MASK 0xffffffffffffffff
11972 #define SH_XN_MD_SIC_CMP_DATA3_INIT 0x0000000000000000
11974 /* SH_XN_MD_SIC_CMP_DATA3_DATA3 */
11975 /* Description: Data3 */
11976 #define SH_XN_MD_SIC_CMP_DATA3_DATA3_SHFT 0
11977 #define SH_XN_MD_SIC_CMP_DATA3_DATA3_MASK 0xffffffffffffffff
11979 /* ==================================================================== */
11980 /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0" */
11981 /* MD enable compare SIC data0 */
11982 /* ==================================================================== */
11984 #define SH_XN_MD_SIC_CMP_DATA_ENABLE0 0x0000000150031640
11985 #define SH_XN_MD_SIC_CMP_DATA_ENABLE0_MASK 0xffffffffffffffff
11986 #define SH_XN_MD_SIC_CMP_DATA_ENABLE0_INIT 0x0000000000000000
11988 /* SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0 */
11989 /* Description: Data0 */
11990 #define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0
11991 #define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff
11993 /* ==================================================================== */
11994 /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1" */
11995 /* MD enable compare SIC data1 */
11996 /* ==================================================================== */
11998 #define SH_XN_MD_SIC_CMP_DATA_ENABLE1 0x0000000150031650
11999 #define SH_XN_MD_SIC_CMP_DATA_ENABLE1_MASK 0xffffffffffffffff
12000 #define SH_XN_MD_SIC_CMP_DATA_ENABLE1_INIT 0x0000000000000000
12002 /* SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1 */
12003 /* Description: Data1 */
12004 #define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0
12005 #define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff
12007 /* ==================================================================== */
12008 /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2" */
12009 /* MD enable compare SIC data2 */
12010 /* ==================================================================== */
12012 #define SH_XN_MD_SIC_CMP_DATA_ENABLE2 0x0000000150031660
12013 #define SH_XN_MD_SIC_CMP_DATA_ENABLE2_MASK 0xffffffffffffffff
12014 #define SH_XN_MD_SIC_CMP_DATA_ENABLE2_INIT 0x0000000000000000
12016 /* SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2 */
12017 /* Description: Data2 */
12018 #define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0
12019 #define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff
12021 /* ==================================================================== */
12022 /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3" */
12023 /* MD enable compare SIC data3 */
12024 /* ==================================================================== */
12026 #define SH_XN_MD_SIC_CMP_DATA_ENABLE3 0x0000000150031670
12027 #define SH_XN_MD_SIC_CMP_DATA_ENABLE3_MASK 0xffffffffffffffff
12028 #define SH_XN_MD_SIC_CMP_DATA_ENABLE3_INIT 0x0000000000000000
12030 /* SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3 */
12031 /* Description: Data3 */
12032 #define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0
12033 #define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff
12035 /* ==================================================================== */
12036 /* Register "SH_XN_PI_IILB_CMP_EXP_DATA0" */
12037 /* PI compare IILB input expected data0 */
12038 /* ==================================================================== */
12040 #define SH_XN_PI_IILB_CMP_EXP_DATA0 0x0000000150031300
12041 #define SH_XN_PI_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12042 #define SH_XN_PI_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000
12044 /* SH_XN_PI_IILB_CMP_EXP_DATA0_DATA */
12045 /* Description: Expected data 0 */
12046 #define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_SHFT 0
12047 #define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12049 /* ==================================================================== */
12050 /* Register "SH_XN_PI_IILB_CMP_EXP_DATA1" */
12051 /* PI compare IILB input expected data1 */
12052 /* ==================================================================== */
12054 #define SH_XN_PI_IILB_CMP_EXP_DATA1 0x0000000150031310
12055 #define SH_XN_PI_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12056 #define SH_XN_PI_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000
12058 /* SH_XN_PI_IILB_CMP_EXP_DATA1_DATA */
12059 /* Description: Expected data 1 */
12060 #define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_SHFT 0
12061 #define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12063 /* ==================================================================== */
12064 /* Register "SH_XN_PI_IILB_CMP_ENABLE0" */
12065 /* PI compare IILB input enable0 */
12066 /* ==================================================================== */
12068 #define SH_XN_PI_IILB_CMP_ENABLE0 0x0000000150031320
12069 #define SH_XN_PI_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff
12070 #define SH_XN_PI_IILB_CMP_ENABLE0_INIT 0x0000000000000000
12072 /* SH_XN_PI_IILB_CMP_ENABLE0_ENABLE */
12073 /* Description: Enable0 */
12074 #define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_SHFT 0
12075 #define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12077 /* ==================================================================== */
12078 /* Register "SH_XN_PI_IILB_CMP_ENABLE1" */
12079 /* PI compare IILB input enable1 */
12080 /* ==================================================================== */
12082 #define SH_XN_PI_IILB_CMP_ENABLE1 0x0000000150031330
12083 #define SH_XN_PI_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff
12084 #define SH_XN_PI_IILB_CMP_ENABLE1_INIT 0x0000000000000000
12086 /* SH_XN_PI_IILB_CMP_ENABLE1_ENABLE */
12087 /* Description: Enable1 */
12088 #define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_SHFT 0
12089 #define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12091 /* ==================================================================== */
12092 /* Register "SH_XN_PI_NI0_CMP_EXP_DATA0" */
12093 /* PI compare NI0 input expected data0 */
12094 /* ==================================================================== */
12096 #define SH_XN_PI_NI0_CMP_EXP_DATA0 0x0000000150031340
12097 #define SH_XN_PI_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12098 #define SH_XN_PI_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000
12100 /* SH_XN_PI_NI0_CMP_EXP_DATA0_DATA */
12101 /* Description: Expected data 0 */
12102 #define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_SHFT 0
12103 #define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12105 /* ==================================================================== */
12106 /* Register "SH_XN_PI_NI0_CMP_EXP_DATA1" */
12107 /* PI compare NI0 input expected data1 */
12108 /* ==================================================================== */
12110 #define SH_XN_PI_NI0_CMP_EXP_DATA1 0x0000000150031350
12111 #define SH_XN_PI_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12112 #define SH_XN_PI_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000
12114 /* SH_XN_PI_NI0_CMP_EXP_DATA1_DATA */
12115 /* Description: Expected data 1 */
12116 #define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_SHFT 0
12117 #define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12119 /* ==================================================================== */
12120 /* Register "SH_XN_PI_NI0_CMP_ENABLE0" */
12121 /* PI compare NI0 input enable0 */
12122 /* ==================================================================== */
12124 #define SH_XN_PI_NI0_CMP_ENABLE0 0x0000000150031360
12125 #define SH_XN_PI_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff
12126 #define SH_XN_PI_NI0_CMP_ENABLE0_INIT 0x0000000000000000
12128 /* SH_XN_PI_NI0_CMP_ENABLE0_ENABLE */
12129 /* Description: Enable0 */
12130 #define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_SHFT 0
12131 #define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12133 /* ==================================================================== */
12134 /* Register "SH_XN_PI_NI0_CMP_ENABLE1" */
12135 /* PI compare NI0 input enable1 */
12136 /* ==================================================================== */
12138 #define SH_XN_PI_NI0_CMP_ENABLE1 0x0000000150031370
12139 #define SH_XN_PI_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff
12140 #define SH_XN_PI_NI0_CMP_ENABLE1_INIT 0x0000000000000000
12142 /* SH_XN_PI_NI0_CMP_ENABLE1_ENABLE */
12143 /* Description: Enable1 */
12144 #define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_SHFT 0
12145 #define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12147 /* ==================================================================== */
12148 /* Register "SH_XN_PI_NI1_CMP_EXP_DATA0" */
12149 /* PI compare NI1 input expected data0 */
12150 /* ==================================================================== */
12152 #define SH_XN_PI_NI1_CMP_EXP_DATA0 0x0000000150031380
12153 #define SH_XN_PI_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12154 #define SH_XN_PI_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000
12156 /* SH_XN_PI_NI1_CMP_EXP_DATA0_DATA */
12157 /* Description: Expected data 0 */
12158 #define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_SHFT 0
12159 #define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12161 /* ==================================================================== */
12162 /* Register "SH_XN_PI_NI1_CMP_EXP_DATA1" */
12163 /* PI compare NI1 input expected data1 */
12164 /* ==================================================================== */
12166 #define SH_XN_PI_NI1_CMP_EXP_DATA1 0x0000000150031390
12167 #define SH_XN_PI_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12168 #define SH_XN_PI_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000
12170 /* SH_XN_PI_NI1_CMP_EXP_DATA1_DATA */
12171 /* Description: Expected data 1 */
12172 #define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_SHFT 0
12173 #define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12175 /* ==================================================================== */
12176 /* Register "SH_XN_PI_NI1_CMP_ENABLE0" */
12177 /* PI compare NI1 input enable0 */
12178 /* ==================================================================== */
12180 #define SH_XN_PI_NI1_CMP_ENABLE0 0x00000001500313a0
12181 #define SH_XN_PI_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff
12182 #define SH_XN_PI_NI1_CMP_ENABLE0_INIT 0x0000000000000000
12184 /* SH_XN_PI_NI1_CMP_ENABLE0_ENABLE */
12185 /* Description: Enable0 */
12186 #define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_SHFT 0
12187 #define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12189 /* ==================================================================== */
12190 /* Register "SH_XN_PI_NI1_CMP_ENABLE1" */
12191 /* PI compare NI1 input enable1 */
12192 /* ==================================================================== */
12194 #define SH_XN_PI_NI1_CMP_ENABLE1 0x00000001500313b0
12195 #define SH_XN_PI_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff
12196 #define SH_XN_PI_NI1_CMP_ENABLE1_INIT 0x0000000000000000
12198 /* SH_XN_PI_NI1_CMP_ENABLE1_ENABLE */
12199 /* Description: Enable1 */
12200 #define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_SHFT 0
12201 #define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12203 /* ==================================================================== */
12204 /* Register "SH_XN_PI_SIC_CMP_EXP_HDR0" */
12205 /* PI compare SIC input expected header0 */
12206 /* ==================================================================== */
12208 #define SH_XN_PI_SIC_CMP_EXP_HDR0 0x00000001500313c0
12209 #define SH_XN_PI_SIC_CMP_EXP_HDR0_MASK 0xffffffffffffffff
12210 #define SH_XN_PI_SIC_CMP_EXP_HDR0_INIT 0x0000000000000000
12212 /* SH_XN_PI_SIC_CMP_EXP_HDR0_DATA */
12213 /* Description: Expected data 0 */
12214 #define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_SHFT 0
12215 #define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_MASK 0xffffffffffffffff
12217 /* ==================================================================== */
12218 /* Register "SH_XN_PI_SIC_CMP_EXP_HDR1" */
12219 /* PI compare SIC input expected header1 */
12220 /* ==================================================================== */
12222 #define SH_XN_PI_SIC_CMP_EXP_HDR1 0x00000001500313d0
12223 #define SH_XN_PI_SIC_CMP_EXP_HDR1_MASK 0x000003ffffffffff
12224 #define SH_XN_PI_SIC_CMP_EXP_HDR1_INIT 0x0000000000000000
12226 /* SH_XN_PI_SIC_CMP_EXP_HDR1_DATA */
12227 /* Description: Expected data 1 */
12228 #define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_SHFT 0
12229 #define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_MASK 0x000003ffffffffff
12231 /* ==================================================================== */
12232 /* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0" */
12233 /* PI compare SIC header enable0 */
12234 /* ==================================================================== */
12236 #define SH_XN_PI_SIC_CMP_HDR_ENABLE0 0x00000001500313e0
12237 #define SH_XN_PI_SIC_CMP_HDR_ENABLE0_MASK 0xffffffffffffffff
12238 #define SH_XN_PI_SIC_CMP_HDR_ENABLE0_INIT 0x0000000000000000
12240 /* SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE */
12241 /* Description: Enable0 */
12242 #define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0
12243 #define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12245 /* ==================================================================== */
12246 /* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1" */
12247 /* PI compare SIC header enable1 */
12248 /* ==================================================================== */
12250 #define SH_XN_PI_SIC_CMP_HDR_ENABLE1 0x00000001500313f0
12251 #define SH_XN_PI_SIC_CMP_HDR_ENABLE1_MASK 0x000003ffffffffff
12252 #define SH_XN_PI_SIC_CMP_HDR_ENABLE1_INIT 0x0000000000000000
12254 /* SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE */
12255 /* Description: Enable1 */
12256 #define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0
12257 #define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff
12259 /* ==================================================================== */
12260 /* Register "SH_XN_PI_SIC_CMP_DATA0" */
12261 /* PI compare SIC data0 */
12262 /* ==================================================================== */
12264 #define SH_XN_PI_SIC_CMP_DATA0 0x0000000150031400
12265 #define SH_XN_PI_SIC_CMP_DATA0_MASK 0xffffffffffffffff
12266 #define SH_XN_PI_SIC_CMP_DATA0_INIT 0x0000000000000000
12268 /* SH_XN_PI_SIC_CMP_DATA0_DATA0 */
12269 /* Description: Data0 */
12270 #define SH_XN_PI_SIC_CMP_DATA0_DATA0_SHFT 0
12271 #define SH_XN_PI_SIC_CMP_DATA0_DATA0_MASK 0xffffffffffffffff
12273 /* ==================================================================== */
12274 /* Register "SH_XN_PI_SIC_CMP_DATA1" */
12275 /* PI compare SIC data1 */
12276 /* ==================================================================== */
12278 #define SH_XN_PI_SIC_CMP_DATA1 0x0000000150031410
12279 #define SH_XN_PI_SIC_CMP_DATA1_MASK 0xffffffffffffffff
12280 #define SH_XN_PI_SIC_CMP_DATA1_INIT 0x0000000000000000
12282 /* SH_XN_PI_SIC_CMP_DATA1_DATA1 */
12283 /* Description: Data1 */
12284 #define SH_XN_PI_SIC_CMP_DATA1_DATA1_SHFT 0
12285 #define SH_XN_PI_SIC_CMP_DATA1_DATA1_MASK 0xffffffffffffffff
12287 /* ==================================================================== */
12288 /* Register "SH_XN_PI_SIC_CMP_DATA2" */
12289 /* PI compare SIC data2 */
12290 /* ==================================================================== */
12292 #define SH_XN_PI_SIC_CMP_DATA2 0x0000000150031420
12293 #define SH_XN_PI_SIC_CMP_DATA2_MASK 0xffffffffffffffff
12294 #define SH_XN_PI_SIC_CMP_DATA2_INIT 0x0000000000000000
12296 /* SH_XN_PI_SIC_CMP_DATA2_DATA2 */
12297 /* Description: Data2 */
12298 #define SH_XN_PI_SIC_CMP_DATA2_DATA2_SHFT 0
12299 #define SH_XN_PI_SIC_CMP_DATA2_DATA2_MASK 0xffffffffffffffff
12301 /* ==================================================================== */
12302 /* Register "SH_XN_PI_SIC_CMP_DATA3" */
12303 /* PI compare SIC data3 */
12304 /* ==================================================================== */
12306 #define SH_XN_PI_SIC_CMP_DATA3 0x0000000150031430
12307 #define SH_XN_PI_SIC_CMP_DATA3_MASK 0xffffffffffffffff
12308 #define SH_XN_PI_SIC_CMP_DATA3_INIT 0x0000000000000000
12310 /* SH_XN_PI_SIC_CMP_DATA3_DATA3 */
12311 /* Description: Data3 */
12312 #define SH_XN_PI_SIC_CMP_DATA3_DATA3_SHFT 0
12313 #define SH_XN_PI_SIC_CMP_DATA3_DATA3_MASK 0xffffffffffffffff
12315 /* ==================================================================== */
12316 /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0" */
12317 /* PI enable compare SIC data0 */
12318 /* ==================================================================== */
12320 #define SH_XN_PI_SIC_CMP_DATA_ENABLE0 0x0000000150031440
12321 #define SH_XN_PI_SIC_CMP_DATA_ENABLE0_MASK 0xffffffffffffffff
12322 #define SH_XN_PI_SIC_CMP_DATA_ENABLE0_INIT 0x0000000000000000
12324 /* SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0 */
12325 /* Description: Data0 */
12326 #define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0
12327 #define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff
12329 /* ==================================================================== */
12330 /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1" */
12331 /* PI enable compare SIC data1 */
12332 /* ==================================================================== */
12334 #define SH_XN_PI_SIC_CMP_DATA_ENABLE1 0x0000000150031450
12335 #define SH_XN_PI_SIC_CMP_DATA_ENABLE1_MASK 0xffffffffffffffff
12336 #define SH_XN_PI_SIC_CMP_DATA_ENABLE1_INIT 0x0000000000000000
12338 /* SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1 */
12339 /* Description: Data1 */
12340 #define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0
12341 #define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff
12343 /* ==================================================================== */
12344 /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2" */
12345 /* PI enable compare SIC data2 */
12346 /* ==================================================================== */
12348 #define SH_XN_PI_SIC_CMP_DATA_ENABLE2 0x0000000150031460
12349 #define SH_XN_PI_SIC_CMP_DATA_ENABLE2_MASK 0xffffffffffffffff
12350 #define SH_XN_PI_SIC_CMP_DATA_ENABLE2_INIT 0x0000000000000000
12352 /* SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2 */
12353 /* Description: Data2 */
12354 #define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0
12355 #define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff
12357 /* ==================================================================== */
12358 /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3" */
12359 /* PI enable compare SIC data3 */
12360 /* ==================================================================== */
12362 #define SH_XN_PI_SIC_CMP_DATA_ENABLE3 0x0000000150031470
12363 #define SH_XN_PI_SIC_CMP_DATA_ENABLE3_MASK 0xffffffffffffffff
12364 #define SH_XN_PI_SIC_CMP_DATA_ENABLE3_INIT 0x0000000000000000
12366 /* SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3 */
12367 /* Description: Data3 */
12368 #define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0
12369 #define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff
12371 /* ==================================================================== */
12372 /* Register "SH_XN_NI0_IILB_CMP_EXP_DATA0" */
12373 /* NI0 compare IILB input expected data0 */
12374 /* ==================================================================== */
12376 #define SH_XN_NI0_IILB_CMP_EXP_DATA0 0x0000000150031700
12377 #define SH_XN_NI0_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12378 #define SH_XN_NI0_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000
12380 /* SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA */
12381 /* Description: Expected data 0 */
12382 #define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_SHFT 0
12383 #define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12385 /* ==================================================================== */
12386 /* Register "SH_XN_NI0_IILB_CMP_EXP_DATA1" */
12387 /* NI0 compare IILB input expected data1 */
12388 /* ==================================================================== */
12390 #define SH_XN_NI0_IILB_CMP_EXP_DATA1 0x0000000150031710
12391 #define SH_XN_NI0_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12392 #define SH_XN_NI0_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000
12394 /* SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA */
12395 /* Description: Expected data 1 */
12396 #define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_SHFT 0
12397 #define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12399 /* ==================================================================== */
12400 /* Register "SH_XN_NI0_IILB_CMP_ENABLE0" */
12401 /* NI0 compare IILB input enable0 */
12402 /* ==================================================================== */
12404 #define SH_XN_NI0_IILB_CMP_ENABLE0 0x0000000150031720
12405 #define SH_XN_NI0_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff
12406 #define SH_XN_NI0_IILB_CMP_ENABLE0_INIT 0x0000000000000000
12408 /* SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE */
12409 /* Description: Enable0 */
12410 #define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_SHFT 0
12411 #define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12413 /* ==================================================================== */
12414 /* Register "SH_XN_NI0_IILB_CMP_ENABLE1" */
12415 /* NI0 compare IILB input enable1 */
12416 /* ==================================================================== */
12418 #define SH_XN_NI0_IILB_CMP_ENABLE1 0x0000000150031730
12419 #define SH_XN_NI0_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff
12420 #define SH_XN_NI0_IILB_CMP_ENABLE1_INIT 0x0000000000000000
12422 /* SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE */
12423 /* Description: Enable1 */
12424 #define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_SHFT 0
12425 #define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12427 /* ==================================================================== */
12428 /* Register "SH_XN_NI0_PI_CMP_EXP_DATA0" */
12429 /* NI0 compare PI input expected data0 */
12430 /* ==================================================================== */
12432 #define SH_XN_NI0_PI_CMP_EXP_DATA0 0x0000000150031740
12433 #define SH_XN_NI0_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12434 #define SH_XN_NI0_PI_CMP_EXP_DATA0_INIT 0x0000000000000000
12436 /* SH_XN_NI0_PI_CMP_EXP_DATA0_DATA */
12437 /* Description: Expected data 0 */
12438 #define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_SHFT 0
12439 #define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12441 /* ==================================================================== */
12442 /* Register "SH_XN_NI0_PI_CMP_EXP_DATA1" */
12443 /* NI0 compare PI input expected data1 */
12444 /* ==================================================================== */
12446 #define SH_XN_NI0_PI_CMP_EXP_DATA1 0x0000000150031750
12447 #define SH_XN_NI0_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12448 #define SH_XN_NI0_PI_CMP_EXP_DATA1_INIT 0x0000000000000000
12450 /* SH_XN_NI0_PI_CMP_EXP_DATA1_DATA */
12451 /* Description: Expected data 1 */
12452 #define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_SHFT 0
12453 #define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12455 /* ==================================================================== */
12456 /* Register "SH_XN_NI0_PI_CMP_ENABLE0" */
12457 /* NI0 compare PI input enable0 */
12458 /* ==================================================================== */
12460 #define SH_XN_NI0_PI_CMP_ENABLE0 0x0000000150031760
12461 #define SH_XN_NI0_PI_CMP_ENABLE0_MASK 0xffffffffffffffff
12462 #define SH_XN_NI0_PI_CMP_ENABLE0_INIT 0x0000000000000000
12464 /* SH_XN_NI0_PI_CMP_ENABLE0_ENABLE */
12465 /* Description: Enable0 */
12466 #define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_SHFT 0
12467 #define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12469 /* ==================================================================== */
12470 /* Register "SH_XN_NI0_PI_CMP_ENABLE1" */
12471 /* NI0 compare PI input enable1 */
12472 /* ==================================================================== */
12474 #define SH_XN_NI0_PI_CMP_ENABLE1 0x0000000150031770
12475 #define SH_XN_NI0_PI_CMP_ENABLE1_MASK 0xffffffffffffffff
12476 #define SH_XN_NI0_PI_CMP_ENABLE1_INIT 0x0000000000000000
12478 /* SH_XN_NI0_PI_CMP_ENABLE1_ENABLE */
12479 /* Description: Enable1 */
12480 #define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_SHFT 0
12481 #define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12483 /* ==================================================================== */
12484 /* Register "SH_XN_NI0_MD_CMP_EXP_DATA0" */
12485 /* NI0 compare MD input expected data0 */
12486 /* ==================================================================== */
12488 #define SH_XN_NI0_MD_CMP_EXP_DATA0 0x0000000150031780
12489 #define SH_XN_NI0_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12490 #define SH_XN_NI0_MD_CMP_EXP_DATA0_INIT 0x0000000000000000
12492 /* SH_XN_NI0_MD_CMP_EXP_DATA0_DATA */
12493 /* Description: Expected data 0 */
12494 #define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_SHFT 0
12495 #define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12497 /* ==================================================================== */
12498 /* Register "SH_XN_NI0_MD_CMP_EXP_DATA1" */
12499 /* NI0 compare MD input expected data1 */
12500 /* ==================================================================== */
12502 #define SH_XN_NI0_MD_CMP_EXP_DATA1 0x0000000150031790
12503 #define SH_XN_NI0_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12504 #define SH_XN_NI0_MD_CMP_EXP_DATA1_INIT 0x0000000000000000
12506 /* SH_XN_NI0_MD_CMP_EXP_DATA1_DATA */
12507 /* Description: Expected data 1 */
12508 #define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_SHFT 0
12509 #define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12511 /* ==================================================================== */
12512 /* Register "SH_XN_NI0_MD_CMP_ENABLE0" */
12513 /* NI0 compare MD input enable0 */
12514 /* ==================================================================== */
12516 #define SH_XN_NI0_MD_CMP_ENABLE0 0x00000001500317a0
12517 #define SH_XN_NI0_MD_CMP_ENABLE0_MASK 0xffffffffffffffff
12518 #define SH_XN_NI0_MD_CMP_ENABLE0_INIT 0x0000000000000000
12520 /* SH_XN_NI0_MD_CMP_ENABLE0_ENABLE */
12521 /* Description: Enable0 */
12522 #define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_SHFT 0
12523 #define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12525 /* ==================================================================== */
12526 /* Register "SH_XN_NI0_MD_CMP_ENABLE1" */
12527 /* NI0 compare MD input enable1 */
12528 /* ==================================================================== */
12530 #define SH_XN_NI0_MD_CMP_ENABLE1 0x00000001500317b0
12531 #define SH_XN_NI0_MD_CMP_ENABLE1_MASK 0xffffffffffffffff
12532 #define SH_XN_NI0_MD_CMP_ENABLE1_INIT 0x0000000000000000
12534 /* SH_XN_NI0_MD_CMP_ENABLE1_ENABLE */
12535 /* Description: Enable1 */
12536 #define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_SHFT 0
12537 #define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12539 /* ==================================================================== */
12540 /* Register "SH_XN_NI0_NI_CMP_EXP_DATA0" */
12541 /* NI0 compare NI input expected data0 */
12542 /* ==================================================================== */
12544 #define SH_XN_NI0_NI_CMP_EXP_DATA0 0x00000001500317c0
12545 #define SH_XN_NI0_NI_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12546 #define SH_XN_NI0_NI_CMP_EXP_DATA0_INIT 0x0000000000000000
12548 /* SH_XN_NI0_NI_CMP_EXP_DATA0_DATA */
12549 /* Description: Expected data 0 */
12550 #define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_SHFT 0
12551 #define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12553 /* ==================================================================== */
12554 /* Register "SH_XN_NI0_NI_CMP_EXP_DATA1" */
12555 /* NI0 compare NI input expected data1 */
12556 /* ==================================================================== */
12558 #define SH_XN_NI0_NI_CMP_EXP_DATA1 0x00000001500317d0
12559 #define SH_XN_NI0_NI_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12560 #define SH_XN_NI0_NI_CMP_EXP_DATA1_INIT 0x0000000000000000
12562 /* SH_XN_NI0_NI_CMP_EXP_DATA1_DATA */
12563 /* Description: Expected data 1 */
12564 #define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_SHFT 0
12565 #define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12567 /* ==================================================================== */
12568 /* Register "SH_XN_NI0_NI_CMP_ENABLE0" */
12569 /* NI0 compare NI input enable0 */
12570 /* ==================================================================== */
12572 #define SH_XN_NI0_NI_CMP_ENABLE0 0x00000001500317e0
12573 #define SH_XN_NI0_NI_CMP_ENABLE0_MASK 0xffffffffffffffff
12574 #define SH_XN_NI0_NI_CMP_ENABLE0_INIT 0x0000000000000000
12576 /* SH_XN_NI0_NI_CMP_ENABLE0_ENABLE */
12577 /* Description: Enable0 */
12578 #define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_SHFT 0
12579 #define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12581 /* ==================================================================== */
12582 /* Register "SH_XN_NI0_NI_CMP_ENABLE1" */
12583 /* NI0 compare NI input enable1 */
12584 /* ==================================================================== */
12586 #define SH_XN_NI0_NI_CMP_ENABLE1 0x00000001500317f0
12587 #define SH_XN_NI0_NI_CMP_ENABLE1_MASK 0xffffffffffffffff
12588 #define SH_XN_NI0_NI_CMP_ENABLE1_INIT 0x0000000000000000
12590 /* SH_XN_NI0_NI_CMP_ENABLE1_ENABLE */
12591 /* Description: Enable1 */
12592 #define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_SHFT 0
12593 #define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12595 /* ==================================================================== */
12596 /* Register "SH_XN_NI0_LLP_CMP_EXP_DATA0" */
12597 /* NI0 compare LLP input expected data0 */
12598 /* ==================================================================== */
12600 #define SH_XN_NI0_LLP_CMP_EXP_DATA0 0x0000000150031800
12601 #define SH_XN_NI0_LLP_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12602 #define SH_XN_NI0_LLP_CMP_EXP_DATA0_INIT 0x0000000000000000
12604 /* SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA */
12605 /* Description: Expected data 0 */
12606 #define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_SHFT 0
12607 #define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12609 /* ==================================================================== */
12610 /* Register "SH_XN_NI0_LLP_CMP_EXP_DATA1" */
12611 /* NI0 compare LLP input expected data1 */
12612 /* ==================================================================== */
12614 #define SH_XN_NI0_LLP_CMP_EXP_DATA1 0x0000000150031810
12615 #define SH_XN_NI0_LLP_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12616 #define SH_XN_NI0_LLP_CMP_EXP_DATA1_INIT 0x0000000000000000
12618 /* SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA */
12619 /* Description: Expected data 1 */
12620 #define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_SHFT 0
12621 #define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12623 /* ==================================================================== */
12624 /* Register "SH_XN_NI0_LLP_CMP_ENABLE0" */
12625 /* NI0 compare LLP input enable0 */
12626 /* ==================================================================== */
12628 #define SH_XN_NI0_LLP_CMP_ENABLE0 0x0000000150031820
12629 #define SH_XN_NI0_LLP_CMP_ENABLE0_MASK 0xffffffffffffffff
12630 #define SH_XN_NI0_LLP_CMP_ENABLE0_INIT 0x0000000000000000
12632 /* SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE */
12633 /* Description: Enable0 */
12634 #define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_SHFT 0
12635 #define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12637 /* ==================================================================== */
12638 /* Register "SH_XN_NI0_LLP_CMP_ENABLE1" */
12639 /* NI0 compare LLP input enable1 */
12640 /* ==================================================================== */
12642 #define SH_XN_NI0_LLP_CMP_ENABLE1 0x0000000150031830
12643 #define SH_XN_NI0_LLP_CMP_ENABLE1_MASK 0xffffffffffffffff
12644 #define SH_XN_NI0_LLP_CMP_ENABLE1_INIT 0x0000000000000000
12646 /* SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE */
12647 /* Description: Enable1 */
12648 #define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_SHFT 0
12649 #define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12651 /* ==================================================================== */
12652 /* Register "SH_XN_NI1_IILB_CMP_EXP_DATA0" */
12653 /* NI1 compare IILB input expected data0 */
12654 /* ==================================================================== */
12656 #define SH_XN_NI1_IILB_CMP_EXP_DATA0 0x0000000150031900
12657 #define SH_XN_NI1_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12658 #define SH_XN_NI1_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000
12660 /* SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA */
12661 /* Description: Expected data 0 */
12662 #define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_SHFT 0
12663 #define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12665 /* ==================================================================== */
12666 /* Register "SH_XN_NI1_IILB_CMP_EXP_DATA1" */
12667 /* NI1 compare IILB input expected data1 */
12668 /* ==================================================================== */
12670 #define SH_XN_NI1_IILB_CMP_EXP_DATA1 0x0000000150031910
12671 #define SH_XN_NI1_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12672 #define SH_XN_NI1_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000
12674 /* SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA */
12675 /* Description: Expected data 1 */
12676 #define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_SHFT 0
12677 #define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12679 /* ==================================================================== */
12680 /* Register "SH_XN_NI1_IILB_CMP_ENABLE0" */
12681 /* NI1 compare IILB input enable0 */
12682 /* ==================================================================== */
12684 #define SH_XN_NI1_IILB_CMP_ENABLE0 0x0000000150031920
12685 #define SH_XN_NI1_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff
12686 #define SH_XN_NI1_IILB_CMP_ENABLE0_INIT 0x0000000000000000
12688 /* SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE */
12689 /* Description: Enable0 */
12690 #define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_SHFT 0
12691 #define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12693 /* ==================================================================== */
12694 /* Register "SH_XN_NI1_IILB_CMP_ENABLE1" */
12695 /* NI1 compare IILB input enable1 */
12696 /* ==================================================================== */
12698 #define SH_XN_NI1_IILB_CMP_ENABLE1 0x0000000150031930
12699 #define SH_XN_NI1_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff
12700 #define SH_XN_NI1_IILB_CMP_ENABLE1_INIT 0x0000000000000000
12702 /* SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE */
12703 /* Description: Enable1 */
12704 #define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_SHFT 0
12705 #define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12707 /* ==================================================================== */
12708 /* Register "SH_XN_NI1_PI_CMP_EXP_DATA0" */
12709 /* NI1 compare PI input expected data0 */
12710 /* ==================================================================== */
12712 #define SH_XN_NI1_PI_CMP_EXP_DATA0 0x0000000150031940
12713 #define SH_XN_NI1_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12714 #define SH_XN_NI1_PI_CMP_EXP_DATA0_INIT 0x0000000000000000
12716 /* SH_XN_NI1_PI_CMP_EXP_DATA0_DATA */
12717 /* Description: Expected data 0 */
12718 #define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_SHFT 0
12719 #define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12721 /* ==================================================================== */
12722 /* Register "SH_XN_NI1_PI_CMP_EXP_DATA1" */
12723 /* NI1 compare PI input expected data1 */
12724 /* ==================================================================== */
12726 #define SH_XN_NI1_PI_CMP_EXP_DATA1 0x0000000150031950
12727 #define SH_XN_NI1_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12728 #define SH_XN_NI1_PI_CMP_EXP_DATA1_INIT 0x0000000000000000
12730 /* SH_XN_NI1_PI_CMP_EXP_DATA1_DATA */
12731 /* Description: Expected data 1 */
12732 #define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_SHFT 0
12733 #define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12735 /* ==================================================================== */
12736 /* Register "SH_XN_NI1_PI_CMP_ENABLE0" */
12737 /* NI1 compare PI input enable0 */
12738 /* ==================================================================== */
12740 #define SH_XN_NI1_PI_CMP_ENABLE0 0x0000000150031960
12741 #define SH_XN_NI1_PI_CMP_ENABLE0_MASK 0xffffffffffffffff
12742 #define SH_XN_NI1_PI_CMP_ENABLE0_INIT 0x0000000000000000
12744 /* SH_XN_NI1_PI_CMP_ENABLE0_ENABLE */
12745 /* Description: Enable0 */
12746 #define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_SHFT 0
12747 #define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12749 /* ==================================================================== */
12750 /* Register "SH_XN_NI1_PI_CMP_ENABLE1" */
12751 /* NI1 compare PI input enable1 */
12752 /* ==================================================================== */
12754 #define SH_XN_NI1_PI_CMP_ENABLE1 0x0000000150031970
12755 #define SH_XN_NI1_PI_CMP_ENABLE1_MASK 0xffffffffffffffff
12756 #define SH_XN_NI1_PI_CMP_ENABLE1_INIT 0x0000000000000000
12758 /* SH_XN_NI1_PI_CMP_ENABLE1_ENABLE */
12759 /* Description: Enable1 */
12760 #define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_SHFT 0
12761 #define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12763 /* ==================================================================== */
12764 /* Register "SH_XN_NI1_MD_CMP_EXP_DATA0" */
12765 /* NI1 compare MD input expected data0 */
12766 /* ==================================================================== */
12768 #define SH_XN_NI1_MD_CMP_EXP_DATA0 0x0000000150031980
12769 #define SH_XN_NI1_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12770 #define SH_XN_NI1_MD_CMP_EXP_DATA0_INIT 0x0000000000000000
12772 /* SH_XN_NI1_MD_CMP_EXP_DATA0_DATA */
12773 /* Description: Expected data 0 */
12774 #define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_SHFT 0
12775 #define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12777 /* ==================================================================== */
12778 /* Register "SH_XN_NI1_MD_CMP_EXP_DATA1" */
12779 /* NI1 compare MD input expected data1 */
12780 /* ==================================================================== */
12782 #define SH_XN_NI1_MD_CMP_EXP_DATA1 0x0000000150031990
12783 #define SH_XN_NI1_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12784 #define SH_XN_NI1_MD_CMP_EXP_DATA1_INIT 0x0000000000000000
12786 /* SH_XN_NI1_MD_CMP_EXP_DATA1_DATA */
12787 /* Description: Expected data 1 */
12788 #define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_SHFT 0
12789 #define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12791 /* ==================================================================== */
12792 /* Register "SH_XN_NI1_MD_CMP_ENABLE0" */
12793 /* NI1 compare MD input enable0 */
12794 /* ==================================================================== */
12796 #define SH_XN_NI1_MD_CMP_ENABLE0 0x00000001500319a0
12797 #define SH_XN_NI1_MD_CMP_ENABLE0_MASK 0xffffffffffffffff
12798 #define SH_XN_NI1_MD_CMP_ENABLE0_INIT 0x0000000000000000
12800 /* SH_XN_NI1_MD_CMP_ENABLE0_ENABLE */
12801 /* Description: Enable0 */
12802 #define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_SHFT 0
12803 #define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12805 /* ==================================================================== */
12806 /* Register "SH_XN_NI1_MD_CMP_ENABLE1" */
12807 /* NI1 compare MD input enable1 */
12808 /* ==================================================================== */
12810 #define SH_XN_NI1_MD_CMP_ENABLE1 0x00000001500319b0
12811 #define SH_XN_NI1_MD_CMP_ENABLE1_MASK 0xffffffffffffffff
12812 #define SH_XN_NI1_MD_CMP_ENABLE1_INIT 0x0000000000000000
12814 /* SH_XN_NI1_MD_CMP_ENABLE1_ENABLE */
12815 /* Description: Enable1 */
12816 #define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_SHFT 0
12817 #define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12819 /* ==================================================================== */
12820 /* Register "SH_XN_NI1_NI_CMP_EXP_DATA0" */
12821 /* NI1 compare NI input expected data0 */
12822 /* ==================================================================== */
12824 #define SH_XN_NI1_NI_CMP_EXP_DATA0 0x00000001500319c0
12825 #define SH_XN_NI1_NI_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12826 #define SH_XN_NI1_NI_CMP_EXP_DATA0_INIT 0x0000000000000000
12828 /* SH_XN_NI1_NI_CMP_EXP_DATA0_DATA */
12829 /* Description: Expected data 0 */
12830 #define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_SHFT 0
12831 #define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12833 /* ==================================================================== */
12834 /* Register "SH_XN_NI1_NI_CMP_EXP_DATA1" */
12835 /* NI1 compare NI input expected data1 */
12836 /* ==================================================================== */
12838 #define SH_XN_NI1_NI_CMP_EXP_DATA1 0x00000001500319d0
12839 #define SH_XN_NI1_NI_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12840 #define SH_XN_NI1_NI_CMP_EXP_DATA1_INIT 0x0000000000000000
12842 /* SH_XN_NI1_NI_CMP_EXP_DATA1_DATA */
12843 /* Description: Expected data 1 */
12844 #define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_SHFT 0
12845 #define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12847 /* ==================================================================== */
12848 /* Register "SH_XN_NI1_NI_CMP_ENABLE0" */
12849 /* NI1 compare NI input enable0 */
12850 /* ==================================================================== */
12852 #define SH_XN_NI1_NI_CMP_ENABLE0 0x00000001500319e0
12853 #define SH_XN_NI1_NI_CMP_ENABLE0_MASK 0xffffffffffffffff
12854 #define SH_XN_NI1_NI_CMP_ENABLE0_INIT 0x0000000000000000
12856 /* SH_XN_NI1_NI_CMP_ENABLE0_ENABLE */
12857 /* Description: Enable0 */
12858 #define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_SHFT 0
12859 #define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12861 /* ==================================================================== */
12862 /* Register "SH_XN_NI1_NI_CMP_ENABLE1" */
12863 /* NI1 compare NI input enable1 */
12864 /* ==================================================================== */
12866 #define SH_XN_NI1_NI_CMP_ENABLE1 0x00000001500319f0
12867 #define SH_XN_NI1_NI_CMP_ENABLE1_MASK 0xffffffffffffffff
12868 #define SH_XN_NI1_NI_CMP_ENABLE1_INIT 0x0000000000000000
12870 /* SH_XN_NI1_NI_CMP_ENABLE1_ENABLE */
12871 /* Description: Enable1 */
12872 #define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_SHFT 0
12873 #define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12875 /* ==================================================================== */
12876 /* Register "SH_XN_NI1_LLP_CMP_EXP_DATA0" */
12877 /* NI1 compare LLP input expected data0 */
12878 /* ==================================================================== */
12880 #define SH_XN_NI1_LLP_CMP_EXP_DATA0 0x0000000150031a00
12881 #define SH_XN_NI1_LLP_CMP_EXP_DATA0_MASK 0xffffffffffffffff
12882 #define SH_XN_NI1_LLP_CMP_EXP_DATA0_INIT 0x0000000000000000
12884 /* SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA */
12885 /* Description: Expected data 0 */
12886 #define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_SHFT 0
12887 #define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff
12889 /* ==================================================================== */
12890 /* Register "SH_XN_NI1_LLP_CMP_EXP_DATA1" */
12891 /* NI1 compare LLP input expected data1 */
12892 /* ==================================================================== */
12894 #define SH_XN_NI1_LLP_CMP_EXP_DATA1 0x0000000150031a10
12895 #define SH_XN_NI1_LLP_CMP_EXP_DATA1_MASK 0xffffffffffffffff
12896 #define SH_XN_NI1_LLP_CMP_EXP_DATA1_INIT 0x0000000000000000
12898 /* SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA */
12899 /* Description: Expected data 1 */
12900 #define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_SHFT 0
12901 #define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff
12903 /* ==================================================================== */
12904 /* Register "SH_XN_NI1_LLP_CMP_ENABLE0" */
12905 /* NI1 compare LLP input enable0 */
12906 /* ==================================================================== */
12908 #define SH_XN_NI1_LLP_CMP_ENABLE0 0x0000000150031a20
12909 #define SH_XN_NI1_LLP_CMP_ENABLE0_MASK 0xffffffffffffffff
12910 #define SH_XN_NI1_LLP_CMP_ENABLE0_INIT 0x0000000000000000
12912 /* SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE */
12913 /* Description: Enable0 */
12914 #define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_SHFT 0
12915 #define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff
12917 /* ==================================================================== */
12918 /* Register "SH_XN_NI1_LLP_CMP_ENABLE1" */
12919 /* NI1 compare LLP input enable1 */
12920 /* ==================================================================== */
12922 #define SH_XN_NI1_LLP_CMP_ENABLE1 0x0000000150031a30
12923 #define SH_XN_NI1_LLP_CMP_ENABLE1_MASK 0xffffffffffffffff
12924 #define SH_XN_NI1_LLP_CMP_ENABLE1_INIT 0x0000000000000000
12926 /* SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE */
12927 /* Description: Enable1 */
12928 #define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_SHFT 0
12929 #define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff
12931 /* ==================================================================== */
12932 /* Register "SH_XNPI_ECC_INJ_REG" */
12933 /* ==================================================================== */
12935 #define SH_XNPI_ECC_INJ_REG 0x0000000150032000
12936 #define SH_XNPI_ECC_INJ_REG_MASK 0xf0fff0fff0fff0ff
12937 #define SH_XNPI_ECC_INJ_REG_INIT 0x0000000000000000
12939 /* SH_XNPI_ECC_INJ_REG_BYTE0 */
12940 /* Description: Replacement Checkbyte */
12941 #define SH_XNPI_ECC_INJ_REG_BYTE0_SHFT 0
12942 #define SH_XNPI_ECC_INJ_REG_BYTE0_MASK 0x00000000000000ff
12944 /* SH_XNPI_ECC_INJ_REG_DATA_1SHOT0 */
12945 /* Description: 1 shot mask data */
12946 #define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_SHFT 12
12947 #define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_MASK 0x0000000000001000
12949 /* SH_XNPI_ECC_INJ_REG_DATA_CONT0 */
12950 /* Description: toggle mask data */
12951 #define SH_XNPI_ECC_INJ_REG_DATA_CONT0_SHFT 13
12952 #define SH_XNPI_ECC_INJ_REG_DATA_CONT0_MASK 0x0000000000002000
12954 /* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0 */
12955 /* Description: Replace Checkbyte One Shot */
12956 #define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT 14
12957 #define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_MASK 0x0000000000004000
12959 /* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0 */
12960 /* Description: Replace Checkbyte Continuous */
12961 #define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_SHFT 15
12962 #define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_MASK 0x0000000000008000
12964 /* SH_XNPI_ECC_INJ_REG_BYTE1 */
12965 /* Description: Replacement Checkbyte */
12966 #define SH_XNPI_ECC_INJ_REG_BYTE1_SHFT 16
12967 #define SH_XNPI_ECC_INJ_REG_BYTE1_MASK 0x0000000000ff0000
12969 /* SH_XNPI_ECC_INJ_REG_DATA_1SHOT1 */
12970 /* Description: 1 shot mask data */
12971 #define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_SHFT 28
12972 #define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_MASK 0x0000000010000000
12974 /* SH_XNPI_ECC_INJ_REG_DATA_CONT1 */
12975 /* Description: toggle mask data */
12976 #define SH_XNPI_ECC_INJ_REG_DATA_CONT1_SHFT 29
12977 #define SH_XNPI_ECC_INJ_REG_DATA_CONT1_MASK 0x0000000020000000
12979 /* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1 */
12980 /* Description: Replace Checkbyte One Shot */
12981 #define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT 30
12982 #define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_MASK 0x0000000040000000
12984 /* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1 */
12985 /* Description: Replace Checkbyte Continous */
12986 #define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_SHFT 31
12987 #define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_MASK 0x0000000080000000
12989 /* SH_XNPI_ECC_INJ_REG_BYTE2 */
12990 /* Description: Replacement Checkbyte */
12991 #define SH_XNPI_ECC_INJ_REG_BYTE2_SHFT 32
12992 #define SH_XNPI_ECC_INJ_REG_BYTE2_MASK 0x000000ff00000000
12994 /* SH_XNPI_ECC_INJ_REG_DATA_1SHOT2 */
12995 /* Description: 1 shot mask data */
12996 #define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_SHFT 44
12997 #define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_MASK 0x0000100000000000
12999 /* SH_XNPI_ECC_INJ_REG_DATA_CONT2 */
13000 /* Description: toggle mask data */
13001 #define SH_XNPI_ECC_INJ_REG_DATA_CONT2_SHFT 45
13002 #define SH_XNPI_ECC_INJ_REG_DATA_CONT2_MASK 0x0000200000000000
13004 /* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2 */
13005 /* Description: Replace Checkbyte OneShot */
13006 #define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT 46
13007 #define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_MASK 0x0000400000000000
13009 /* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2 */
13010 /* Description: Replace Checkbyte Continous */
13011 #define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_SHFT 47
13012 #define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_MASK 0x0000800000000000
13014 /* SH_XNPI_ECC_INJ_REG_BYTE3 */
13015 /* Description: Replacement Checkbyte */
13016 #define SH_XNPI_ECC_INJ_REG_BYTE3_SHFT 48
13017 #define SH_XNPI_ECC_INJ_REG_BYTE3_MASK 0x00ff000000000000
13019 /* SH_XNPI_ECC_INJ_REG_DATA_1SHOT3 */
13020 /* Description: 1 shot mask data */
13021 #define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_SHFT 60
13022 #define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_MASK 0x1000000000000000
13024 /* SH_XNPI_ECC_INJ_REG_DATA_CONT3 */
13025 /* Description: toggle mask data */
13026 #define SH_XNPI_ECC_INJ_REG_DATA_CONT3_SHFT 61
13027 #define SH_XNPI_ECC_INJ_REG_DATA_CONT3_MASK 0x2000000000000000
13029 /* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3 */
13030 /* Description: Replace Checkbyte One-Shot */
13031 #define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT 62
13032 #define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_MASK 0x4000000000000000
13034 /* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3 */
13035 /* Description: Replace Checkbyte Continous */
13036 #define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_SHFT 63
13037 #define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_MASK 0x8000000000000000
13039 /* ==================================================================== */
13040 /* Register "SH_XNPI_ECC0_INJ_MASK_REG" */
13041 /* ==================================================================== */
13043 #define SH_XNPI_ECC0_INJ_MASK_REG 0x0000000150032008
13044 #define SH_XNPI_ECC0_INJ_MASK_REG_MASK 0xffffffffffffffff
13045 #define SH_XNPI_ECC0_INJ_MASK_REG_INIT 0x0000000000000000
13047 /* SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0 */
13048 /* Description: Replacement Data */
13049 #define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0
13050 #define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff
13052 /* ==================================================================== */
13053 /* Register "SH_XNPI_ECC1_INJ_MASK_REG" */
13054 /* ==================================================================== */
13056 #define SH_XNPI_ECC1_INJ_MASK_REG 0x0000000150032010
13057 #define SH_XNPI_ECC1_INJ_MASK_REG_MASK 0xffffffffffffffff
13058 #define SH_XNPI_ECC1_INJ_MASK_REG_INIT 0x0000000000000000
13060 /* SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1 */
13061 /* Description: Replacement Data */
13062 #define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0
13063 #define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff
13065 /* ==================================================================== */
13066 /* Register "SH_XNPI_ECC2_INJ_MASK_REG" */
13067 /* ==================================================================== */
13069 #define SH_XNPI_ECC2_INJ_MASK_REG 0x0000000150032018
13070 #define SH_XNPI_ECC2_INJ_MASK_REG_MASK 0xffffffffffffffff
13071 #define SH_XNPI_ECC2_INJ_MASK_REG_INIT 0x0000000000000000
13073 /* SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2 */
13074 /* Description: Replacement Data */
13075 #define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0
13076 #define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff
13078 /* ==================================================================== */
13079 /* Register "SH_XNPI_ECC3_INJ_MASK_REG" */
13080 /* ==================================================================== */
13082 #define SH_XNPI_ECC3_INJ_MASK_REG 0x0000000150032020
13083 #define SH_XNPI_ECC3_INJ_MASK_REG_MASK 0xffffffffffffffff
13084 #define SH_XNPI_ECC3_INJ_MASK_REG_INIT 0x0000000000000000
13086 /* SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3 */
13087 /* Description: Replacement Data */
13088 #define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0
13089 #define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff
13091 /* ==================================================================== */
13092 /* Register "SH_XNMD_ECC_INJ_REG" */
13093 /* ==================================================================== */
13095 #define SH_XNMD_ECC_INJ_REG 0x0000000150032030
13096 #define SH_XNMD_ECC_INJ_REG_MASK 0xf0fff0fff0fff0ff
13097 #define SH_XNMD_ECC_INJ_REG_INIT 0x0000000000000000
13099 /* SH_XNMD_ECC_INJ_REG_BYTE0 */
13100 /* Description: Replacement Checkbyte */
13101 #define SH_XNMD_ECC_INJ_REG_BYTE0_SHFT 0
13102 #define SH_XNMD_ECC_INJ_REG_BYTE0_MASK 0x00000000000000ff
13104 /* SH_XNMD_ECC_INJ_REG_DATA_1SHOT0 */
13105 /* Description: 1 shot mask data */
13106 #define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_SHFT 12
13107 #define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_MASK 0x0000000000001000
13109 /* SH_XNMD_ECC_INJ_REG_DATA_CONT0 */
13110 /* Description: toggle mask data */
13111 #define SH_XNMD_ECC_INJ_REG_DATA_CONT0_SHFT 13
13112 #define SH_XNMD_ECC_INJ_REG_DATA_CONT0_MASK 0x0000000000002000
13114 /* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0 */
13115 /* Description: Replace Checkbyte One Shot */
13116 #define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT 14
13117 #define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_MASK 0x0000000000004000
13119 /* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0 */
13120 /* Description: Replace Checkbyte Continuous */
13121 #define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_SHFT 15
13122 #define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_MASK 0x0000000000008000
13124 /* SH_XNMD_ECC_INJ_REG_BYTE1 */
13125 /* Description: Replacement Checkbyte */
13126 #define SH_XNMD_ECC_INJ_REG_BYTE1_SHFT 16
13127 #define SH_XNMD_ECC_INJ_REG_BYTE1_MASK 0x0000000000ff0000
13129 /* SH_XNMD_ECC_INJ_REG_DATA_1SHOT1 */
13130 /* Description: 1 shot mask data */
13131 #define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_SHFT 28
13132 #define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_MASK 0x0000000010000000
13134 /* SH_XNMD_ECC_INJ_REG_DATA_CONT1 */
13135 /* Description: toggle mask data */
13136 #define SH_XNMD_ECC_INJ_REG_DATA_CONT1_SHFT 29
13137 #define SH_XNMD_ECC_INJ_REG_DATA_CONT1_MASK 0x0000000020000000
13139 /* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1 */
13140 /* Description: Replace Checkbyte One Shot */
13141 #define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT 30
13142 #define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_MASK 0x0000000040000000
13144 /* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1 */
13145 /* Description: Replace Checkbyte Continous */
13146 #define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_SHFT 31
13147 #define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_MASK 0x0000000080000000
13149 /* SH_XNMD_ECC_INJ_REG_BYTE2 */
13150 /* Description: Replacement Checkbyte */
13151 #define SH_XNMD_ECC_INJ_REG_BYTE2_SHFT 32
13152 #define SH_XNMD_ECC_INJ_REG_BYTE2_MASK 0x000000ff00000000
13154 /* SH_XNMD_ECC_INJ_REG_DATA_1SHOT2 */
13155 /* Description: 1 shot mask data */
13156 #define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_SHFT 44
13157 #define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_MASK 0x0000100000000000
13159 /* SH_XNMD_ECC_INJ_REG_DATA_CONT2 */
13160 /* Description: toggle mask data */
13161 #define SH_XNMD_ECC_INJ_REG_DATA_CONT2_SHFT 45
13162 #define SH_XNMD_ECC_INJ_REG_DATA_CONT2_MASK 0x0000200000000000
13164 /* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2 */
13165 /* Description: Replace Checkbyte OneShot */
13166 #define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT 46
13167 #define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_MASK 0x0000400000000000
13169 /* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2 */
13170 /* Description: Replace Checkbyte Continous */
13171 #define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_SHFT 47
13172 #define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_MASK 0x0000800000000000
13174 /* SH_XNMD_ECC_INJ_REG_BYTE3 */
13175 /* Description: Replacement Checkbyte */
13176 #define SH_XNMD_ECC_INJ_REG_BYTE3_SHFT 48
13177 #define SH_XNMD_ECC_INJ_REG_BYTE3_MASK 0x00ff000000000000
13179 /* SH_XNMD_ECC_INJ_REG_DATA_1SHOT3 */
13180 /* Description: 1 shot mask data */
13181 #define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_SHFT 60
13182 #define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_MASK 0x1000000000000000
13184 /* SH_XNMD_ECC_INJ_REG_DATA_CONT3 */
13185 /* Description: toggle mask data */
13186 #define SH_XNMD_ECC_INJ_REG_DATA_CONT3_SHFT 61
13187 #define SH_XNMD_ECC_INJ_REG_DATA_CONT3_MASK 0x2000000000000000
13189 /* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3 */
13190 /* Description: Replace Checkbyte One-Shot */
13191 #define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT 62
13192 #define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_MASK 0x4000000000000000
13194 /* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3 */
13195 /* Description: Replace Checkbyte Continous */
13196 #define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_SHFT 63
13197 #define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_MASK 0x8000000000000000
13199 /* ==================================================================== */
13200 /* Register "SH_XNMD_ECC0_INJ_MASK_REG" */
13201 /* ==================================================================== */
13203 #define SH_XNMD_ECC0_INJ_MASK_REG 0x0000000150032038
13204 #define SH_XNMD_ECC0_INJ_MASK_REG_MASK 0xffffffffffffffff
13205 #define SH_XNMD_ECC0_INJ_MASK_REG_INIT 0x0000000000000000
13207 /* SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0 */
13208 /* Description: Replacement Data */
13209 #define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0
13210 #define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff
13212 /* ==================================================================== */
13213 /* Register "SH_XNMD_ECC1_INJ_MASK_REG" */
13214 /* ==================================================================== */
13216 #define SH_XNMD_ECC1_INJ_MASK_REG 0x0000000150032040
13217 #define SH_XNMD_ECC1_INJ_MASK_REG_MASK 0xffffffffffffffff
13218 #define SH_XNMD_ECC1_INJ_MASK_REG_INIT 0x0000000000000000
13220 /* SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1 */
13221 /* Description: Replacement Data */
13222 #define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0
13223 #define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff
13225 /* ==================================================================== */
13226 /* Register "SH_XNMD_ECC2_INJ_MASK_REG" */
13227 /* ==================================================================== */
13229 #define SH_XNMD_ECC2_INJ_MASK_REG 0x0000000150032048
13230 #define SH_XNMD_ECC2_INJ_MASK_REG_MASK 0xffffffffffffffff
13231 #define SH_XNMD_ECC2_INJ_MASK_REG_INIT 0x0000000000000000
13233 /* SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2 */
13234 /* Description: Replacement Data */
13235 #define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0
13236 #define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff
13238 /* ==================================================================== */
13239 /* Register "SH_XNMD_ECC3_INJ_MASK_REG" */
13240 /* ==================================================================== */
13242 #define SH_XNMD_ECC3_INJ_MASK_REG 0x0000000150032050
13243 #define SH_XNMD_ECC3_INJ_MASK_REG_MASK 0xffffffffffffffff
13244 #define SH_XNMD_ECC3_INJ_MASK_REG_INIT 0x0000000000000000
13246 /* SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3 */
13247 /* Description: Replacement Data */
13248 #define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0
13249 #define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff
13251 /* ==================================================================== */
13252 /* Register "SH_XNMD_ECC_ERR_REPORT" */
13253 /* ==================================================================== */
13255 #define SH_XNMD_ECC_ERR_REPORT 0x0000000150032058
13256 #define SH_XNMD_ECC_ERR_REPORT_MASK 0x0001000100010001
13257 #define SH_XNMD_ECC_ERR_REPORT_INIT 0x0000000000000000
13259 /* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0 */
13260 /* Description: Disable Error Correction */
13261 #define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_SHFT 0
13262 #define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_MASK 0x0000000000000001
13264 /* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1 */
13265 /* Description: Disable Error Correction */
13266 #define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_SHFT 16
13267 #define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_MASK 0x0000000000010000
13269 /* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2 */
13270 /* Description: Disable Error Correction */
13271 #define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_SHFT 32
13272 #define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_MASK 0x0000000100000000
13274 /* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3 */
13275 /* Description: Disable Error Correction */
13276 #define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_SHFT 48
13277 #define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_MASK 0x0001000000000000
13279 /* ==================================================================== */
13280 /* Register "SH_NI0_ERROR_SUMMARY_1" */
13281 /* ni0 Error Summary Bits */
13282 /* ==================================================================== */
13284 #define SH_NI0_ERROR_SUMMARY_1 0x0000000150040500
13285 #define SH_NI0_ERROR_SUMMARY_1_MASK 0xffffffffffffffff
13286 #define SH_NI0_ERROR_SUMMARY_1_INIT 0xffffffffffffffff
13288 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0 */
13289 /* Description: Fifo 02 debit0 overflow */
13290 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
13291 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
13293 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2 */
13294 /* Description: Fifo 02 debit2 overflow */
13295 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
13296 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
13298 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0 */
13299 /* Description: Fifo 13 debit0 overflow */
13300 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
13301 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
13303 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2 */
13304 /* Description: Fifo 13 debit2 overflow */
13305 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
13306 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
13308 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP */
13309 /* Description: Fifo 02 vc0 pop overflow */
13310 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
13311 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
13313 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP */
13314 /* Description: Fifo 02 vc2 pop overflow */
13315 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
13316 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
13318 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP */
13319 /* Description: Fifo 13 vc1 pop overflow */
13320 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
13321 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
13323 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP */
13324 /* Description: Fifo 13 vc3 pop overflow */
13325 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
13326 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
13328 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH */
13329 /* Description: Fifo 02 vc0 push overflow */
13330 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
13331 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
13333 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH */
13334 /* Description: Fifo 02 vc2 push overflow */
13335 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
13336 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
13338 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH */
13339 /* Description: Fifo 13 vc1 push overflow */
13340 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
13341 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
13343 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH */
13344 /* Description: Fifo 13 vc3 push overflow */
13345 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
13346 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
13348 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT */
13349 /* Description: Fifo 02 vc0 credit overflow */
13350 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
13351 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
13353 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT */
13354 /* Description: Fifo 02 vc2 credit overflow */
13355 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
13356 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
13358 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT */
13359 /* Description: Fifo 13 vc0 credit overflow */
13360 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
13361 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
13363 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT */
13364 /* Description: Fifo 13 vc2 credit overflow */
13365 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
13366 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
13368 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT */
13369 /* Description: VC0 credit overflow 0 */
13370 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16
13371 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
13373 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT */
13374 /* Description: VC0 credit overflow 1 */
13375 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17
13376 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
13378 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT */
13379 /* Description: VC0 credit overflow 2 */
13380 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18
13381 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
13383 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT */
13384 /* Description: VC2 credit overflow 0 */
13385 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19
13386 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
13388 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT */
13389 /* Description: VC2 credit overflow 1 */
13390 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20
13391 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
13393 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT */
13394 /* Description: VC2 credit overflow 2 */
13395 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21
13396 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
13398 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0 */
13399 /* Description: PI Fifo debit0 overflow */
13400 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
13401 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
13403 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2 */
13404 /* Description: PI Fifo debit2 overflow */
13405 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
13406 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
13408 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0 */
13409 /* Description: IILB Fifo debit0 overflow */
13410 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
13411 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
13413 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2 */
13414 /* Description: IILB Fifo debit2 overflow */
13415 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
13416 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
13418 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0 */
13419 /* Description: MD Fifo debit0 overflow */
13420 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
13421 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
13423 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2 */
13424 /* Description: MD Fifo debit2 overflow */
13425 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
13426 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
13428 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0 */
13429 /* Description: NI Fifo debit0 overflow */
13430 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
13431 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
13433 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1 */
13434 /* Description: NI Fifo debit1 overflow */
13435 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
13436 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
13438 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2 */
13439 /* Description: NI Fifo debit2 overflow */
13440 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
13441 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
13443 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3 */
13444 /* Description: NI Fifo debit3 overflow */
13445 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
13446 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
13448 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP */
13449 /* Description: PI Fifo vc0 pop overflow */
13450 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
13451 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
13453 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP */
13454 /* Description: PI Fifo vc2 pop overflow */
13455 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
13456 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
13458 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP */
13459 /* Description: IILB Fifo vc0 pop overflow */
13460 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
13461 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
13463 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP */
13464 /* Description: IILB Fifo vc2 pop overflow */
13465 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
13466 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
13468 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP */
13469 /* Description: MD Fifo vc0 pop overflow */
13470 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
13471 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
13473 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP */
13474 /* Description: MD Fifo vc2 pop overflow */
13475 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
13476 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
13478 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP */
13479 /* Description: NI Fifo vc0 pop overflow */
13480 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
13481 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
13483 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP */
13484 /* Description: NI Fifo vc2 pop overflow */
13485 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
13486 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
13488 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH */
13489 /* Description: PI Fifo vc0 push overflow */
13490 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
13491 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
13493 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH */
13494 /* Description: PI Fifo vc2 push overflow */
13495 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
13496 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
13498 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH */
13499 /* Description: IILB Fifo vc0 push overflow */
13500 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
13501 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
13503 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH */
13504 /* Description: IILB Fifo vc2 push overflow */
13505 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
13506 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
13508 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH */
13509 /* Description: MD Fifo vc0 push overflow */
13510 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
13511 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
13513 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH */
13514 /* Description: MD Fifo vc2 push overflow */
13515 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
13516 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
13518 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT */
13519 /* Description: PI Fifo vc0 credit overflow */
13520 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
13521 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
13523 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT */
13524 /* Description: PI Fifo vc2 credit overflow */
13525 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
13526 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
13528 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */
13529 /* Description: IILB Fifo vc0 credit overflow */
13530 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
13531 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
13533 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */
13534 /* Description: IILB Fifo vc2 credit overflow */
13535 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
13536 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
13538 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT */
13539 /* Description: MD Fifo vc0 credit overflow */
13540 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
13541 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
13543 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT */
13544 /* Description: MD Fifo vc2 credit overflow */
13545 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
13546 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
13548 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT */
13549 /* Description: NI Fifo vc0 credit overflow */
13550 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
13551 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
13553 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT */
13554 /* Description: NI Fifo vc1 credit overflow */
13555 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
13556 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
13558 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT */
13559 /* Description: NI Fifo vc2 credit overflow */
13560 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
13561 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
13563 /* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT */
13564 /* Description: NI Fifo vc3 credit overflow */
13565 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
13566 #define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
13568 /* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0 */
13569 /* Description: Fifo02 vc0 tail timeout */
13570 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
13571 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
13573 /* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2 */
13574 /* Description: Fifo02 vc2 tail timeout */
13575 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
13576 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
13578 /* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1 */
13579 /* Description: Fifo13 vc1 tail timeout */
13580 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
13581 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
13583 /* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3 */
13584 /* Description: Fifo13 vc3 tail timeout */
13585 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
13586 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
13588 /* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0 */
13589 /* Description: NI vc0 tail timeout */
13590 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
13591 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
13593 /* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1 */
13594 /* Description: NI vc1 tail timeout */
13595 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
13596 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
13598 /* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2 */
13599 /* Description: NI vc2 tail timeout */
13600 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
13601 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
13603 /* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3 */
13604 /* Description: NI vc3 tail timeout */
13605 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
13606 #define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
13608 /* ==================================================================== */
13609 /* Register "SH_NI0_ERROR_SUMMARY_1_ALIAS" */
13610 /* ni0 Error Summary Bits Alias */
13611 /* ==================================================================== */
13613 #define SH_NI0_ERROR_SUMMARY_1_ALIAS 0x0000000150040508
13615 /* ==================================================================== */
13616 /* Register "SH_NI0_ERROR_SUMMARY_2" */
13617 /* ni0 Error Summary Bits */
13618 /* ==================================================================== */
13620 #define SH_NI0_ERROR_SUMMARY_2 0x0000000150040510
13621 #define SH_NI0_ERROR_SUMMARY_2_MASK 0x7fffffff003fffff
13622 #define SH_NI0_ERROR_SUMMARY_2_INIT 0x7fffffff003fffff
13624 /* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI */
13625 /* Description: Illegal VC NI */
13626 #define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0
13627 #define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001
13629 /* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI */
13630 /* Description: Illegal VC PI */
13631 #define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1
13632 #define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002
13634 /* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD */
13635 /* Description: Illegal VC MD */
13636 #define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2
13637 #define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004
13639 /* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB */
13640 /* Description: Illegal VC IILB */
13641 #define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3
13642 #define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
13644 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP */
13645 /* Description: Fifo 02 vc0 pop underflow */
13646 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
13647 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
13649 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP */
13650 /* Description: Fifo 02 vc2 pop underflow */
13651 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
13652 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
13654 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP */
13655 /* Description: Fifo 13 vc1 pop underflow */
13656 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
13657 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
13659 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP */
13660 /* Description: Fifo 13 vc3 pop underflow */
13661 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
13662 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
13664 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH */
13665 /* Description: Fifo 02 vc0 push underflow */
13666 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
13667 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
13669 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH */
13670 /* Description: Fifo 02 vc2 push underflow */
13671 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
13672 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
13674 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH */
13675 /* Description: Fifo 13 vc1 push underflow */
13676 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
13677 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
13679 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH */
13680 /* Description: Fifo 13 vc3 push underflow */
13681 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
13682 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
13684 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT */
13685 /* Description: Fifo 02 vc0 credit underflow */
13686 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
13687 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
13689 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT */
13690 /* Description: Fifo 02 vc2 credit underflow */
13691 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
13692 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
13694 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT */
13695 /* Description: Fifo 13 vc0 credit underflow */
13696 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
13697 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
13699 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT */
13700 /* Description: Fifo 13 vc2 credit underflow */
13701 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
13702 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
13704 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT */
13705 /* Description: VC0 credit underflow 0 */
13706 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
13707 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
13709 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT */
13710 /* Description: VC0 credit underflow 1 */
13711 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
13712 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
13714 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT */
13715 /* Description: VC0 credit underflow 2 */
13716 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
13717 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
13719 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT */
13720 /* Description: VC2 credit underflow 0 */
13721 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
13722 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
13724 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT */
13725 /* Description: VC2 credit underflow 1 */
13726 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
13727 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
13729 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT */
13730 /* Description: VC2 credit underflow 2 */
13731 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
13732 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
13734 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP */
13735 /* Description: PI Fifo vc0 pop underflow */
13736 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
13737 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
13739 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP */
13740 /* Description: PI Fifo vc2 pop underflow */
13741 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
13742 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
13744 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP */
13745 /* Description: IILB Fifo vc0 pop underflow */
13746 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
13747 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
13749 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP */
13750 /* Description: IILB Fifo vc2 pop underflow */
13751 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
13752 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
13754 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP */
13755 /* Description: MD Fifo vc0 pop underflow */
13756 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
13757 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
13759 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP */
13760 /* Description: MD Fifo vc2 pop underflow */
13761 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
13762 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
13764 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP */
13765 /* Description: NI Fifo vc0 pop underflow */
13766 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
13767 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
13769 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP */
13770 /* Description: NI Fifo vc2 pop underflow */
13771 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
13772 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
13774 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH */
13775 /* Description: PI Fifo vc0 push underflow */
13776 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
13777 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
13779 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH */
13780 /* Description: PI Fifo vc2 push underflow */
13781 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
13782 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
13784 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */
13785 /* Description: IILB Fifo vc0 push underflow */
13786 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
13787 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
13789 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */
13790 /* Description: IILB Fifo vc2 push underflow */
13791 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
13792 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
13794 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH */
13795 /* Description: MD Fifo vc0 push underflow */
13796 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
13797 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
13799 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH */
13800 /* Description: MD Fifo vc2 push underflow */
13801 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
13802 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
13804 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */
13805 /* Description: PI Fifo vc0 credit underflow */
13806 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
13807 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
13809 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */
13810 /* Description: PI Fifo vc2 credit underflow */
13811 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
13812 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
13814 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */
13815 /* Description: IILB Fifo vc0 credit underflow */
13816 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
13817 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
13819 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */
13820 /* Description: IILB Fifo vc2 credit underflow */
13821 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
13822 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
13824 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */
13825 /* Description: MD Fifo vc0 credit underflow */
13826 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
13827 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
13829 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */
13830 /* Description: MD Fifo vc2 credit underflow */
13831 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
13832 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
13834 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */
13835 /* Description: NI Fifo vc0 credit underflow */
13836 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
13837 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
13839 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */
13840 /* Description: NI Fifo vc1 credit underflow */
13841 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
13842 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
13844 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */
13845 /* Description: NI Fifo vc2 credit underflow */
13846 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
13847 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
13849 /* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */
13850 /* Description: NI Fifo vc3 credit underflow */
13851 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
13852 #define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
13854 /* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0 */
13855 /* Description: llp deadlock vc0 */
13856 #define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56
13857 #define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
13859 /* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1 */
13860 /* Description: llp deadlock vc1 */
13861 #define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57
13862 #define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
13864 /* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2 */
13865 /* Description: llp deadlock vc2 */
13866 #define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58
13867 #define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
13869 /* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3 */
13870 /* Description: llp deadlock vc3 */
13871 #define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59
13872 #define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
13874 /* SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH */
13875 /* Description: chiplet nomatch */
13876 #define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60
13877 #define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
13879 /* SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR */
13880 /* Description: LUT Read Error */
13881 #define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61
13882 #define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000
13884 /* SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR */
13885 /* Description: Retry Timeout Error */
13886 #define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62
13887 #define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
13889 /* ==================================================================== */
13890 /* Register "SH_NI0_ERROR_SUMMARY_2_ALIAS" */
13891 /* ni0 Error Summary Bits Alias */
13892 /* ==================================================================== */
13894 #define SH_NI0_ERROR_SUMMARY_2_ALIAS 0x0000000150040518
13896 /* ==================================================================== */
13897 /* Register "SH_NI0_ERROR_OVERFLOW_1" */
13898 /* ni0 Error Overflow Bits */
13899 /* ==================================================================== */
13901 #define SH_NI0_ERROR_OVERFLOW_1 0x0000000150040520
13902 #define SH_NI0_ERROR_OVERFLOW_1_MASK 0xffffffffffffffff
13903 #define SH_NI0_ERROR_OVERFLOW_1_INIT 0xffffffffffffffff
13905 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0 */
13906 /* Description: Fifo 02 debit0 overflow */
13907 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
13908 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
13910 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2 */
13911 /* Description: Fifo 02 debit2 overflow */
13912 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
13913 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
13915 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0 */
13916 /* Description: Fifo 13 debit0 overflow */
13917 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
13918 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
13920 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2 */
13921 /* Description: Fifo 13 debit2 overflow */
13922 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
13923 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
13925 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP */
13926 /* Description: Fifo 02 vc0 pop overflow */
13927 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
13928 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
13930 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP */
13931 /* Description: Fifo 02 vc2 pop overflow */
13932 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
13933 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
13935 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP */
13936 /* Description: Fifo 13 vc1 pop overflow */
13937 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
13938 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
13940 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP */
13941 /* Description: Fifo 13 vc3 pop overflow */
13942 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
13943 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
13945 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH */
13946 /* Description: Fifo 02 vc0 push overflow */
13947 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
13948 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
13950 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH */
13951 /* Description: Fifo 02 vc2 push overflow */
13952 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
13953 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
13955 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH */
13956 /* Description: Fifo 13 vc1 push overflow */
13957 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
13958 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
13960 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH */
13961 /* Description: Fifo 13 vc3 push overflow */
13962 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
13963 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
13965 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT */
13966 /* Description: Fifo 02 vc0 credit overflow */
13967 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
13968 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
13970 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT */
13971 /* Description: Fifo 02 vc2 credit overflow */
13972 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
13973 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
13975 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT */
13976 /* Description: Fifo 13 vc0 credit overflow */
13977 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
13978 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
13980 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT */
13981 /* Description: Fifo 13 vc2 credit overflow */
13982 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
13983 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
13985 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT */
13986 /* Description: VC0 credit overflow 0 */
13987 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16
13988 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
13990 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT */
13991 /* Description: VC0 credit overflow 1 */
13992 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17
13993 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
13995 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT */
13996 /* Description: VC0 credit overflow 2 */
13997 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18
13998 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
14000 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT */
14001 /* Description: VC2 credit overflow 0 */
14002 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19
14003 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
14005 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT */
14006 /* Description: VC2 credit overflow 1 */
14007 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20
14008 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
14010 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT */
14011 /* Description: VC2 credit overflow 2 */
14012 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21
14013 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
14015 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0 */
14016 /* Description: PI Fifo debit0 overflow */
14017 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
14018 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
14020 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2 */
14021 /* Description: PI Fifo debit2 overflow */
14022 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
14023 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
14025 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0 */
14026 /* Description: IILB Fifo debit0 overflow */
14027 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
14028 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
14030 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2 */
14031 /* Description: IILB Fifo debit2 overflow */
14032 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
14033 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
14035 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0 */
14036 /* Description: MD Fifo debit0 overflow */
14037 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
14038 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
14040 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2 */
14041 /* Description: MD Fifo debit2 overflow */
14042 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
14043 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
14045 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0 */
14046 /* Description: NI Fifo debit0 overflow */
14047 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
14048 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
14050 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1 */
14051 /* Description: NI Fifo debit1 overflow */
14052 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
14053 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
14055 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2 */
14056 /* Description: NI Fifo debit2 overflow */
14057 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
14058 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
14060 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3 */
14061 /* Description: NI Fifo debit3 overflow */
14062 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
14063 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
14065 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP */
14066 /* Description: PI Fifo vc0 pop overflow */
14067 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
14068 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
14070 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP */
14071 /* Description: PI Fifo vc2 pop overflow */
14072 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
14073 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
14075 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP */
14076 /* Description: IILB Fifo vc0 pop overflow */
14077 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
14078 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
14080 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP */
14081 /* Description: IILB Fifo vc2 pop overflow */
14082 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
14083 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
14085 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP */
14086 /* Description: MD Fifo vc0 pop overflow */
14087 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
14088 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
14090 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP */
14091 /* Description: MD Fifo vc2 pop overflow */
14092 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
14093 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
14095 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP */
14096 /* Description: NI Fifo vc0 pop overflow */
14097 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
14098 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
14100 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP */
14101 /* Description: NI Fifo vc2 pop overflow */
14102 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
14103 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
14105 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH */
14106 /* Description: PI Fifo vc0 push overflow */
14107 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
14108 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
14110 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH */
14111 /* Description: PI Fifo vc2 push overflow */
14112 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
14113 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
14115 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH */
14116 /* Description: IILB Fifo vc0 push overflow */
14117 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
14118 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
14120 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH */
14121 /* Description: IILB Fifo vc2 push overflow */
14122 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
14123 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
14125 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH */
14126 /* Description: MD Fifo vc0 push overflow */
14127 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
14128 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
14130 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH */
14131 /* Description: MD Fifo vc2 push overflow */
14132 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
14133 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
14135 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT */
14136 /* Description: PI Fifo vc0 credit overflow */
14137 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
14138 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
14140 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT */
14141 /* Description: PI Fifo vc2 credit overflow */
14142 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
14143 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
14145 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */
14146 /* Description: IILB Fifo vc0 credit overflow */
14147 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
14148 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
14150 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */
14151 /* Description: IILB Fifo vc2 credit overflow */
14152 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
14153 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
14155 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT */
14156 /* Description: MD Fifo vc0 credit overflow */
14157 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
14158 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
14160 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT */
14161 /* Description: MD Fifo vc2 credit overflow */
14162 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
14163 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
14165 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT */
14166 /* Description: NI Fifo vc0 credit overflow */
14167 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
14168 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
14170 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT */
14171 /* Description: NI Fifo vc1 credit overflow */
14172 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
14173 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
14175 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT */
14176 /* Description: NI Fifo vc2 credit overflow */
14177 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
14178 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
14180 /* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT */
14181 /* Description: NI Fifo vc3 credit overflow */
14182 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
14183 #define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
14185 /* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0 */
14186 /* Description: Fifo02 vc0 tail timeout */
14187 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
14188 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
14190 /* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2 */
14191 /* Description: Fifo02 vc2 tail timeout */
14192 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
14193 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
14195 /* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1 */
14196 /* Description: Fifo13 vc1 tail timeout */
14197 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
14198 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
14200 /* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3 */
14201 /* Description: Fifo13 vc3 tail timeout */
14202 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
14203 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
14205 /* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0 */
14206 /* Description: NI vc0 tail timeout */
14207 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
14208 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
14210 /* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1 */
14211 /* Description: NI vc1 tail timeout */
14212 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
14213 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
14215 /* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2 */
14216 /* Description: NI vc2 tail timeout */
14217 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
14218 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
14220 /* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3 */
14221 /* Description: NI vc3 tail timeout */
14222 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
14223 #define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
14225 /* ==================================================================== */
14226 /* Register "SH_NI0_ERROR_OVERFLOW_1_ALIAS" */
14227 /* ni0 Error Overflow Bits Alias */
14228 /* ==================================================================== */
14230 #define SH_NI0_ERROR_OVERFLOW_1_ALIAS 0x0000000150040528
14232 /* ==================================================================== */
14233 /* Register "SH_NI0_ERROR_OVERFLOW_2" */
14234 /* ni0 Error Overflow Bits */
14235 /* ==================================================================== */
14237 #define SH_NI0_ERROR_OVERFLOW_2 0x0000000150040530
14238 #define SH_NI0_ERROR_OVERFLOW_2_MASK 0x7fffffff003fffff
14239 #define SH_NI0_ERROR_OVERFLOW_2_INIT 0x7fffffff003fffff
14241 /* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI */
14242 /* Description: Illegal VC NI */
14243 #define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0
14244 #define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001
14246 /* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI */
14247 /* Description: Illegal VC PI */
14248 #define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1
14249 #define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002
14251 /* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD */
14252 /* Description: Illegal VC MD */
14253 #define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2
14254 #define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004
14256 /* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB */
14257 /* Description: Illegal VC IILB */
14258 #define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3
14259 #define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
14261 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP */
14262 /* Description: Fifo 02 vc0 pop underflow */
14263 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
14264 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
14266 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP */
14267 /* Description: Fifo 02 vc2 pop underflow */
14268 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
14269 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
14271 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP */
14272 /* Description: Fifo 13 vc1 pop underflow */
14273 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
14274 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
14276 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP */
14277 /* Description: Fifo 13 vc3 pop underflow */
14278 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
14279 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
14281 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH */
14282 /* Description: Fifo 02 vc0 push underflow */
14283 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
14284 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
14286 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH */
14287 /* Description: Fifo 02 vc2 push underflow */
14288 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
14289 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
14291 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH */
14292 /* Description: Fifo 13 vc1 push underflow */
14293 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
14294 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
14296 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH */
14297 /* Description: Fifo 13 vc3 push underflow */
14298 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
14299 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
14301 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT */
14302 /* Description: Fifo 02 vc0 credit underflow */
14303 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
14304 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
14306 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT */
14307 /* Description: Fifo 02 vc2 credit underflow */
14308 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
14309 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
14311 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT */
14312 /* Description: Fifo 13 vc0 credit underflow */
14313 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
14314 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
14316 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT */
14317 /* Description: Fifo 13 vc2 credit underflow */
14318 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
14319 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
14321 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT */
14322 /* Description: VC0 credit underflow 0 */
14323 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
14324 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
14326 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT */
14327 /* Description: VC0 credit underflow 1 */
14328 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
14329 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
14331 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT */
14332 /* Description: VC0 credit underflow 2 */
14333 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
14334 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
14336 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT */
14337 /* Description: VC2 credit underflow 0 */
14338 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
14339 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
14341 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT */
14342 /* Description: VC2 credit underflow 1 */
14343 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
14344 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
14346 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT */
14347 /* Description: VC2 credit underflow 2 */
14348 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
14349 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
14351 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP */
14352 /* Description: PI Fifo vc0 pop underflow */
14353 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
14354 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
14356 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP */
14357 /* Description: PI Fifo vc2 pop underflow */
14358 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
14359 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
14361 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP */
14362 /* Description: IILB Fifo vc0 pop underflow */
14363 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
14364 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
14366 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP */
14367 /* Description: IILB Fifo vc2 pop underflow */
14368 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
14369 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
14371 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP */
14372 /* Description: MD Fifo vc0 pop underflow */
14373 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
14374 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
14376 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP */
14377 /* Description: MD Fifo vc2 pop underflow */
14378 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
14379 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
14381 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP */
14382 /* Description: NI Fifo vc0 pop underflow */
14383 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
14384 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
14386 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP */
14387 /* Description: NI Fifo vc2 pop underflow */
14388 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
14389 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
14391 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH */
14392 /* Description: PI Fifo vc0 push underflow */
14393 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
14394 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
14396 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH */
14397 /* Description: PI Fifo vc2 push underflow */
14398 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
14399 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
14401 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */
14402 /* Description: IILB Fifo vc0 push underflow */
14403 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
14404 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
14406 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */
14407 /* Description: IILB Fifo vc2 push underflow */
14408 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
14409 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
14411 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH */
14412 /* Description: MD Fifo vc0 push underflow */
14413 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
14414 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
14416 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH */
14417 /* Description: MD Fifo vc2 push underflow */
14418 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
14419 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
14421 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */
14422 /* Description: PI Fifo vc0 credit underflow */
14423 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
14424 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
14426 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */
14427 /* Description: PI Fifo vc2 credit underflow */
14428 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
14429 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
14431 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */
14432 /* Description: IILB Fifo vc0 credit underflow */
14433 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
14434 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
14436 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */
14437 /* Description: IILB Fifo vc2 credit underflow */
14438 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
14439 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
14441 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */
14442 /* Description: MD Fifo vc0 credit underflow */
14443 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
14444 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
14446 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */
14447 /* Description: MD Fifo vc2 credit underflow */
14448 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
14449 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
14451 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */
14452 /* Description: NI Fifo vc0 credit underflow */
14453 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
14454 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
14456 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */
14457 /* Description: NI Fifo vc1 credit underflow */
14458 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
14459 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
14461 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */
14462 /* Description: NI Fifo vc2 credit underflow */
14463 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
14464 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
14466 /* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */
14467 /* Description: NI Fifo vc3 credit underflow */
14468 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
14469 #define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
14471 /* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0 */
14472 /* Description: llp deadlock vc0 */
14473 #define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56
14474 #define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
14476 /* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1 */
14477 /* Description: llp deadlock vc1 */
14478 #define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57
14479 #define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
14481 /* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2 */
14482 /* Description: llp deadlock vc2 */
14483 #define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58
14484 #define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
14486 /* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3 */
14487 /* Description: llp deadlock vc3 */
14488 #define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59
14489 #define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
14491 /* SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH */
14492 /* Description: chiplet nomatch */
14493 #define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60
14494 #define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
14496 /* SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR */
14497 /* Description: LUT Read Error */
14498 #define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61
14499 #define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000
14501 /* SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR */
14502 /* Description: Retry Timeout Error */
14503 #define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62
14504 #define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
14506 /* ==================================================================== */
14507 /* Register "SH_NI0_ERROR_OVERFLOW_2_ALIAS" */
14508 /* ni0 Error Overflow Bits Alias */
14509 /* ==================================================================== */
14511 #define SH_NI0_ERROR_OVERFLOW_2_ALIAS 0x0000000150040538
14513 /* ==================================================================== */
14514 /* Register "SH_NI0_ERROR_MASK_1" */
14515 /* ni0 Error Mask Bits */
14516 /* ==================================================================== */
14518 #define SH_NI0_ERROR_MASK_1 0x0000000150040540
14519 #define SH_NI0_ERROR_MASK_1_MASK 0xffffffffffffffff
14520 #define SH_NI0_ERROR_MASK_1_INIT 0xffffffffffffffff
14522 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0 */
14523 /* Description: Fifo 02 debit0 overflow */
14524 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
14525 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
14527 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2 */
14528 /* Description: Fifo 02 debit2 overflow */
14529 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
14530 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
14532 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0 */
14533 /* Description: Fifo 13 debit0 overflow */
14534 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
14535 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
14537 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2 */
14538 /* Description: Fifo 13 debit2 overflow */
14539 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
14540 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
14542 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP */
14543 /* Description: Fifo 02 vc0 pop overflow */
14544 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
14545 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
14547 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP */
14548 /* Description: Fifo 02 vc2 pop overflow */
14549 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
14550 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
14552 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP */
14553 /* Description: Fifo 13 vc1 pop overflow */
14554 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
14555 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
14557 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP */
14558 /* Description: Fifo 13 vc3 pop overflow */
14559 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
14560 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
14562 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH */
14563 /* Description: Fifo 02 vc0 push overflow */
14564 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
14565 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
14567 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH */
14568 /* Description: Fifo 02 vc2 push overflow */
14569 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
14570 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
14572 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH */
14573 /* Description: Fifo 13 vc1 push overflow */
14574 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
14575 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
14577 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH */
14578 /* Description: Fifo 13 vc3 push overflow */
14579 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
14580 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
14582 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT */
14583 /* Description: Fifo 02 vc0 credit overflow */
14584 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
14585 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
14587 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT */
14588 /* Description: Fifo 02 vc2 credit overflow */
14589 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
14590 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
14592 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT */
14593 /* Description: Fifo 13 vc0 credit overflow */
14594 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
14595 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
14597 /* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT */
14598 /* Description: Fifo 13 vc2 credit overflow */
14599 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
14600 #define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
14602 /* SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT */
14603 /* Description: VC0 credit overflow 0 */
14604 #define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16
14605 #define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
14607 /* SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT */
14608 /* Description: VC0 credit overflow 1 */
14609 #define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17
14610 #define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
14612 /* SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT */
14613 /* Description: VC0 credit overflow 2 */
14614 #define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18
14615 #define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
14617 /* SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT */
14618 /* Description: VC2 credit overflow 0 */
14619 #define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19
14620 #define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
14622 /* SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT */
14623 /* Description: VC2 credit overflow 1 */
14624 #define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20
14625 #define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
14627 /* SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT */
14628 /* Description: VC2 credit overflow 2 */
14629 #define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21
14630 #define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
14632 /* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0 */
14633 /* Description: PI Fifo debit0 overflow */
14634 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
14635 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
14637 /* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2 */
14638 /* Description: PI Fifo debit2 overflow */
14639 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
14640 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
14642 /* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0 */
14643 /* Description: IILB Fifo debit0 overflow */
14644 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
14645 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
14647 /* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2 */
14648 /* Description: IILB Fifo debit2 overflow */
14649 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
14650 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
14652 /* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0 */
14653 /* Description: MD Fifo debit0 overflow */
14654 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
14655 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
14657 /* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2 */
14658 /* Description: MD Fifo debit2 overflow */
14659 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
14660 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
14662 /* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0 */
14663 /* Description: NI Fifo debit0 overflow */
14664 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
14665 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
14667 /* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1 */
14668 /* Description: NI Fifo debit1 overflow */
14669 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
14670 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
14672 /* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2 */
14673 /* Description: NI Fifo debit2 overflow */
14674 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
14675 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
14677 /* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3 */
14678 /* Description: NI Fifo debit3 overflow */
14679 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
14680 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
14682 /* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP */
14683 /* Description: PI Fifo vc0 pop overflow */
14684 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
14685 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
14687 /* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP */
14688 /* Description: PI Fifo vc2 pop overflow */
14689 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
14690 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
14692 /* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP */
14693 /* Description: IILB Fifo vc0 pop overflow */
14694 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
14695 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
14697 /* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP */
14698 /* Description: IILB Fifo vc2 pop overflow */
14699 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
14700 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
14702 /* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP */
14703 /* Description: MD Fifo vc0 pop overflow */
14704 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
14705 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
14707 /* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP */
14708 /* Description: MD Fifo vc2 pop overflow */
14709 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
14710 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
14712 /* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP */
14713 /* Description: NI Fifo vc0 pop overflow */
14714 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
14715 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
14717 /* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP */
14718 /* Description: NI Fifo vc2 pop overflow */
14719 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
14720 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
14722 /* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH */
14723 /* Description: PI Fifo vc0 push overflow */
14724 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
14725 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
14727 /* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH */
14728 /* Description: PI Fifo vc2 push overflow */
14729 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
14730 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
14732 /* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH */
14733 /* Description: IILB Fifo vc0 push overflow */
14734 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
14735 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
14737 /* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH */
14738 /* Description: IILB Fifo vc2 push overflow */
14739 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
14740 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
14742 /* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH */
14743 /* Description: MD Fifo vc0 push overflow */
14744 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
14745 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
14747 /* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH */
14748 /* Description: MD Fifo vc2 push overflow */
14749 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
14750 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
14752 /* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT */
14753 /* Description: PI Fifo vc0 credit overflow */
14754 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
14755 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
14757 /* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT */
14758 /* Description: PI Fifo vc2 credit overflow */
14759 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
14760 #define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
14762 /* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */
14763 /* Description: IILB Fifo vc0 credit overflow */
14764 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
14765 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
14767 /* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */
14768 /* Description: IILB Fifo vc2 credit overflow */
14769 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
14770 #define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
14772 /* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT */
14773 /* Description: MD Fifo vc0 credit overflow */
14774 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
14775 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
14777 /* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT */
14778 /* Description: MD Fifo vc2 credit overflow */
14779 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
14780 #define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
14782 /* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT */
14783 /* Description: NI Fifo vc0 credit overflow */
14784 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
14785 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
14787 /* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT */
14788 /* Description: NI Fifo vc1 credit overflow */
14789 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
14790 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
14792 /* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT */
14793 /* Description: NI Fifo vc2 credit overflow */
14794 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
14795 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
14797 /* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT */
14798 /* Description: NI Fifo vc3 credit overflow */
14799 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
14800 #define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
14802 /* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0 */
14803 /* Description: Fifo02 vc0 tail timeout */
14804 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
14805 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
14807 /* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2 */
14808 /* Description: Fifo02 vc2 tail timeout */
14809 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
14810 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
14812 /* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1 */
14813 /* Description: Fifo13 vc1 tail timeout */
14814 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
14815 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
14817 /* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3 */
14818 /* Description: Fifo13 vc3 tail timeout */
14819 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
14820 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
14822 /* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0 */
14823 /* Description: NI vc0 tail timeout */
14824 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
14825 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
14827 /* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1 */
14828 /* Description: NI vc1 tail timeout */
14829 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
14830 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
14832 /* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2 */
14833 /* Description: NI vc2 tail timeout */
14834 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
14835 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
14837 /* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3 */
14838 /* Description: NI vc3 tail timeout */
14839 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
14840 #define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
14842 /* ==================================================================== */
14843 /* Register "SH_NI0_ERROR_MASK_2" */
14844 /* ni0 Error Mask Bits */
14845 /* ==================================================================== */
14847 #define SH_NI0_ERROR_MASK_2 0x0000000150040550
14848 #define SH_NI0_ERROR_MASK_2_MASK 0x7fffffff003fffff
14849 #define SH_NI0_ERROR_MASK_2_INIT 0x7fffffff003fffff
14851 /* SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI */
14852 /* Description: Illegal VC NI */
14853 #define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_SHFT 0
14854 #define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_MASK 0x0000000000000001
14856 /* SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI */
14857 /* Description: Illegal VC PI */
14858 #define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_SHFT 1
14859 #define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_MASK 0x0000000000000002
14861 /* SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD */
14862 /* Description: Illegal VC MD */
14863 #define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_SHFT 2
14864 #define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_MASK 0x0000000000000004
14866 /* SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB */
14867 /* Description: Illegal VC IILB */
14868 #define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT 3
14869 #define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
14871 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP */
14872 /* Description: Fifo 02 vc0 pop underflow */
14873 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
14874 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
14876 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP */
14877 /* Description: Fifo 02 vc2 pop underflow */
14878 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
14879 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
14881 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP */
14882 /* Description: Fifo 13 vc1 pop underflow */
14883 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
14884 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
14886 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP */
14887 /* Description: Fifo 13 vc3 pop underflow */
14888 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
14889 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
14891 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH */
14892 /* Description: Fifo 02 vc0 push underflow */
14893 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
14894 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
14896 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH */
14897 /* Description: Fifo 02 vc2 push underflow */
14898 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
14899 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
14901 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH */
14902 /* Description: Fifo 13 vc1 push underflow */
14903 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
14904 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
14906 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH */
14907 /* Description: Fifo 13 vc3 push underflow */
14908 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
14909 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
14911 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT */
14912 /* Description: Fifo 02 vc0 credit underflow */
14913 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
14914 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
14916 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT */
14917 /* Description: Fifo 02 vc2 credit underflow */
14918 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
14919 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
14921 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT */
14922 /* Description: Fifo 13 vc0 credit underflow */
14923 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
14924 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
14926 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT */
14927 /* Description: Fifo 13 vc2 credit underflow */
14928 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
14929 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
14931 /* SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT */
14932 /* Description: VC0 credit underflow 0 */
14933 #define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
14934 #define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
14936 /* SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT */
14937 /* Description: VC0 credit underflow 1 */
14938 #define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
14939 #define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
14941 /* SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT */
14942 /* Description: VC0 credit underflow 2 */
14943 #define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
14944 #define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
14946 /* SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT */
14947 /* Description: VC2 credit underflow 0 */
14948 #define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
14949 #define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
14951 /* SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT */
14952 /* Description: VC2 credit underflow 1 */
14953 #define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
14954 #define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
14956 /* SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT */
14957 /* Description: VC2 credit underflow 2 */
14958 #define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
14959 #define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
14961 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP */
14962 /* Description: PI Fifo vc0 pop underflow */
14963 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
14964 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
14966 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP */
14967 /* Description: PI Fifo vc2 pop underflow */
14968 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
14969 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
14971 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP */
14972 /* Description: IILB Fifo vc0 pop underflow */
14973 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
14974 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
14976 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP */
14977 /* Description: IILB Fifo vc2 pop underflow */
14978 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
14979 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
14981 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP */
14982 /* Description: MD Fifo vc0 pop underflow */
14983 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
14984 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
14986 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP */
14987 /* Description: MD Fifo vc2 pop underflow */
14988 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
14989 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
14991 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP */
14992 /* Description: NI Fifo vc0 pop underflow */
14993 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
14994 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
14996 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP */
14997 /* Description: NI Fifo vc2 pop underflow */
14998 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
14999 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
15001 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH */
15002 /* Description: PI Fifo vc0 push underflow */
15003 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
15004 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
15006 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH */
15007 /* Description: PI Fifo vc2 push underflow */
15008 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
15009 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
15011 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */
15012 /* Description: IILB Fifo vc0 push underflow */
15013 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
15014 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
15016 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */
15017 /* Description: IILB Fifo vc2 push underflow */
15018 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
15019 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
15021 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH */
15022 /* Description: MD Fifo vc0 push underflow */
15023 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
15024 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
15026 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH */
15027 /* Description: MD Fifo vc2 push underflow */
15028 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
15029 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
15031 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */
15032 /* Description: PI Fifo vc0 credit underflow */
15033 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
15034 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
15036 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */
15037 /* Description: PI Fifo vc2 credit underflow */
15038 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
15039 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
15041 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */
15042 /* Description: IILB Fifo vc0 credit underflow */
15043 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
15044 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
15046 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */
15047 /* Description: IILB Fifo vc2 credit underflow */
15048 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
15049 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
15051 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */
15052 /* Description: MD Fifo vc0 credit underflow */
15053 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
15054 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
15056 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */
15057 /* Description: MD Fifo vc2 credit underflow */
15058 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
15059 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
15061 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */
15062 /* Description: NI Fifo vc0 credit underflow */
15063 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
15064 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
15066 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */
15067 /* Description: NI Fifo vc1 credit underflow */
15068 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
15069 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
15071 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */
15072 /* Description: NI Fifo vc2 credit underflow */
15073 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
15074 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
15076 /* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */
15077 /* Description: NI Fifo vc3 credit underflow */
15078 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
15079 #define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
15081 /* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0 */
15082 /* Description: llp deadlock vc0 */
15083 #define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56
15084 #define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
15086 /* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1 */
15087 /* Description: llp deadlock vc1 */
15088 #define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57
15089 #define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
15091 /* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2 */
15092 /* Description: llp deadlock vc2 */
15093 #define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58
15094 #define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
15096 /* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3 */
15097 /* Description: llp deadlock vc3 */
15098 #define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59
15099 #define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
15101 /* SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH */
15102 /* Description: chiplet nomatch */
15103 #define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60
15104 #define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
15106 /* SH_NI0_ERROR_MASK_2_LUT_READ_ERROR */
15107 /* Description: LUT Read Error */
15108 #define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_SHFT 61
15109 #define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_MASK 0x2000000000000000
15111 /* SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR */
15112 /* Description: Retry Timeout Error */
15113 #define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62
15114 #define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
15116 /* ==================================================================== */
15117 /* Register "SH_NI0_FIRST_ERROR_1" */
15118 /* ni0 First Error Bits */
15119 /* ==================================================================== */
15121 #define SH_NI0_FIRST_ERROR_1 0x0000000150040560
15122 #define SH_NI0_FIRST_ERROR_1_MASK 0xffffffffffffffff
15123 #define SH_NI0_FIRST_ERROR_1_INIT 0xffffffffffffffff
15125 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0 */
15126 /* Description: Fifo 02 debit0 overflow */
15127 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
15128 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
15130 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2 */
15131 /* Description: Fifo 02 debit2 overflow */
15132 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
15133 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
15135 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0 */
15136 /* Description: Fifo 13 debit0 overflow */
15137 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
15138 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
15140 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2 */
15141 /* Description: Fifo 13 debit2 overflow */
15142 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
15143 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
15145 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP */
15146 /* Description: Fifo 02 vc0 pop overflow */
15147 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
15148 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
15150 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP */
15151 /* Description: Fifo 02 vc2 pop overflow */
15152 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
15153 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
15155 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP */
15156 /* Description: Fifo 13 vc1 pop overflow */
15157 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
15158 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
15160 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP */
15161 /* Description: Fifo 13 vc3 pop overflow */
15162 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
15163 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
15165 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH */
15166 /* Description: Fifo 02 vc0 push overflow */
15167 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
15168 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
15170 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH */
15171 /* Description: Fifo 02 vc2 push overflow */
15172 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
15173 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
15175 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH */
15176 /* Description: Fifo 13 vc1 push overflow */
15177 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
15178 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
15180 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH */
15181 /* Description: Fifo 13 vc3 push overflow */
15182 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
15183 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
15185 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT */
15186 /* Description: Fifo 02 vc0 credit overflow */
15187 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
15188 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
15190 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT */
15191 /* Description: Fifo 02 vc2 credit overflow */
15192 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
15193 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
15195 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT */
15196 /* Description: Fifo 13 vc0 credit overflow */
15197 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
15198 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
15200 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT */
15201 /* Description: Fifo 13 vc2 credit overflow */
15202 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
15203 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
15205 /* SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT */
15206 /* Description: VC0 credit overflow 0 */
15207 #define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16
15208 #define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
15210 /* SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT */
15211 /* Description: VC0 credit overflow 1 */
15212 #define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17
15213 #define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
15215 /* SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT */
15216 /* Description: VC0 credit overflow 2 */
15217 #define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18
15218 #define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
15220 /* SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT */
15221 /* Description: VC2 credit overflow 0 */
15222 #define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19
15223 #define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
15225 /* SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT */
15226 /* Description: VC2 credit overflow 1 */
15227 #define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20
15228 #define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
15230 /* SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT */
15231 /* Description: VC2 credit overflow 2 */
15232 #define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21
15233 #define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
15235 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0 */
15236 /* Description: PI Fifo debit0 overflow */
15237 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
15238 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
15240 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2 */
15241 /* Description: PI Fifo debit2 overflow */
15242 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
15243 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
15245 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0 */
15246 /* Description: IILB Fifo debit0 overflow */
15247 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
15248 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
15250 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2 */
15251 /* Description: IILB Fifo debit2 overflow */
15252 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
15253 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
15255 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0 */
15256 /* Description: MD Fifo debit0 overflow */
15257 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
15258 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
15260 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2 */
15261 /* Description: MD Fifo debit2 overflow */
15262 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
15263 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
15265 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0 */
15266 /* Description: NI Fifo debit0 overflow */
15267 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
15268 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
15270 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1 */
15271 /* Description: NI Fifo debit1 overflow */
15272 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
15273 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
15275 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2 */
15276 /* Description: NI Fifo debit2 overflow */
15277 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
15278 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
15280 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3 */
15281 /* Description: NI Fifo debit3 overflow */
15282 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
15283 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
15285 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP */
15286 /* Description: PI Fifo vc0 pop overflow */
15287 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
15288 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
15290 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP */
15291 /* Description: PI Fifo vc2 pop overflow */
15292 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
15293 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
15295 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP */
15296 /* Description: IILB Fifo vc0 pop overflow */
15297 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
15298 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
15300 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP */
15301 /* Description: IILB Fifo vc2 pop overflow */
15302 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
15303 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
15305 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP */
15306 /* Description: MD Fifo vc0 pop overflow */
15307 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
15308 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
15310 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP */
15311 /* Description: MD Fifo vc2 pop overflow */
15312 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
15313 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
15315 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP */
15316 /* Description: NI Fifo vc0 pop overflow */
15317 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
15318 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
15320 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP */
15321 /* Description: NI Fifo vc2 pop overflow */
15322 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
15323 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
15325 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH */
15326 /* Description: PI Fifo vc0 push overflow */
15327 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
15328 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
15330 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH */
15331 /* Description: PI Fifo vc2 push overflow */
15332 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
15333 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
15335 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH */
15336 /* Description: IILB Fifo vc0 push overflow */
15337 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
15338 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
15340 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH */
15341 /* Description: IILB Fifo vc2 push overflow */
15342 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
15343 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
15345 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH */
15346 /* Description: MD Fifo vc0 push overflow */
15347 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
15348 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
15350 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH */
15351 /* Description: MD Fifo vc2 push overflow */
15352 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
15353 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
15355 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT */
15356 /* Description: PI Fifo vc0 credit overflow */
15357 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
15358 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
15360 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT */
15361 /* Description: PI Fifo vc2 credit overflow */
15362 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
15363 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
15365 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */
15366 /* Description: IILB Fifo vc0 credit overflow */
15367 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
15368 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
15370 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */
15371 /* Description: IILB Fifo vc2 credit overflow */
15372 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
15373 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
15375 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT */
15376 /* Description: MD Fifo vc0 credit overflow */
15377 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
15378 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
15380 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT */
15381 /* Description: MD Fifo vc2 credit overflow */
15382 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
15383 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
15385 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT */
15386 /* Description: NI Fifo vc0 credit overflow */
15387 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
15388 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
15390 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT */
15391 /* Description: NI Fifo vc1 credit overflow */
15392 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
15393 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
15395 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT */
15396 /* Description: NI Fifo vc2 credit overflow */
15397 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
15398 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
15400 /* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT */
15401 /* Description: NI Fifo vc3 credit overflow */
15402 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
15403 #define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
15405 /* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0 */
15406 /* Description: Fifo02 vc0 tail timeout */
15407 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
15408 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
15410 /* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2 */
15411 /* Description: Fifo02 vc2 tail timeout */
15412 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
15413 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
15415 /* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1 */
15416 /* Description: Fifo13 vc1 tail timeout */
15417 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
15418 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
15420 /* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3 */
15421 /* Description: Fifo13 vc3 tail timeout */
15422 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
15423 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
15425 /* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0 */
15426 /* Description: NI vc0 tail timeout */
15427 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
15428 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
15430 /* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1 */
15431 /* Description: NI vc1 tail timeout */
15432 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
15433 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
15435 /* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2 */
15436 /* Description: NI vc2 tail timeout */
15437 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
15438 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
15440 /* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3 */
15441 /* Description: NI vc3 tail timeout */
15442 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
15443 #define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
15445 /* ==================================================================== */
15446 /* Register "SH_NI0_FIRST_ERROR_2" */
15447 /* ni0 First Error Bits */
15448 /* ==================================================================== */
15450 #define SH_NI0_FIRST_ERROR_2 0x0000000150040570
15451 #define SH_NI0_FIRST_ERROR_2_MASK 0x7fffffff003fffff
15452 #define SH_NI0_FIRST_ERROR_2_INIT 0x7fffffff003fffff
15454 /* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI */
15455 /* Description: Illegal VC NI */
15456 #define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT 0
15457 #define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_MASK 0x0000000000000001
15459 /* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI */
15460 /* Description: Illegal VC PI */
15461 #define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT 1
15462 #define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_MASK 0x0000000000000002
15464 /* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD */
15465 /* Description: Illegal VC MD */
15466 #define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT 2
15467 #define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_MASK 0x0000000000000004
15469 /* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB */
15470 /* Description: Illegal VC IILB */
15471 #define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3
15472 #define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
15474 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP */
15475 /* Description: Fifo 02 vc0 pop underflow */
15476 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
15477 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
15479 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP */
15480 /* Description: Fifo 02 vc2 pop underflow */
15481 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
15482 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
15484 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP */
15485 /* Description: Fifo 13 vc1 pop underflow */
15486 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
15487 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
15489 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP */
15490 /* Description: Fifo 13 vc3 pop underflow */
15491 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
15492 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
15494 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH */
15495 /* Description: Fifo 02 vc0 push underflow */
15496 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
15497 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
15499 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH */
15500 /* Description: Fifo 02 vc2 push underflow */
15501 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
15502 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
15504 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH */
15505 /* Description: Fifo 13 vc1 push underflow */
15506 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
15507 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
15509 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH */
15510 /* Description: Fifo 13 vc3 push underflow */
15511 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
15512 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
15514 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT */
15515 /* Description: Fifo 02 vc0 credit underflow */
15516 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
15517 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
15519 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT */
15520 /* Description: Fifo 02 vc2 credit underflow */
15521 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
15522 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
15524 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT */
15525 /* Description: Fifo 13 vc0 credit underflow */
15526 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
15527 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
15529 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT */
15530 /* Description: Fifo 13 vc2 credit underflow */
15531 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
15532 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
15534 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT */
15535 /* Description: VC0 credit underflow 0 */
15536 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
15537 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
15539 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT */
15540 /* Description: VC0 credit underflow 1 */
15541 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
15542 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
15544 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT */
15545 /* Description: VC0 credit underflow 2 */
15546 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
15547 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
15549 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT */
15550 /* Description: VC2 credit underflow 0 */
15551 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
15552 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
15554 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT */
15555 /* Description: VC2 credit underflow 1 */
15556 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
15557 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
15559 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT */
15560 /* Description: VC2 credit underflow 2 */
15561 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
15562 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
15564 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP */
15565 /* Description: PI Fifo vc0 pop underflow */
15566 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
15567 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
15569 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP */
15570 /* Description: PI Fifo vc2 pop underflow */
15571 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
15572 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
15574 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP */
15575 /* Description: IILB Fifo vc0 pop underflow */
15576 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
15577 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
15579 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP */
15580 /* Description: IILB Fifo vc2 pop underflow */
15581 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
15582 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
15584 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP */
15585 /* Description: MD Fifo vc0 pop underflow */
15586 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
15587 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
15589 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP */
15590 /* Description: MD Fifo vc2 pop underflow */
15591 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
15592 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
15594 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP */
15595 /* Description: NI Fifo vc0 pop underflow */
15596 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
15597 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
15599 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP */
15600 /* Description: NI Fifo vc2 pop underflow */
15601 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
15602 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
15604 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH */
15605 /* Description: PI Fifo vc0 push underflow */
15606 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
15607 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
15609 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH */
15610 /* Description: PI Fifo vc2 push underflow */
15611 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
15612 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
15614 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */
15615 /* Description: IILB Fifo vc0 push underflow */
15616 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
15617 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
15619 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */
15620 /* Description: IILB Fifo vc2 push underflow */
15621 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
15622 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
15624 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH */
15625 /* Description: MD Fifo vc0 push underflow */
15626 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
15627 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
15629 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH */
15630 /* Description: MD Fifo vc2 push underflow */
15631 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
15632 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
15634 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */
15635 /* Description: PI Fifo vc0 credit underflow */
15636 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
15637 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
15639 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */
15640 /* Description: PI Fifo vc2 credit underflow */
15641 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
15642 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
15644 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */
15645 /* Description: IILB Fifo vc0 credit underflow */
15646 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
15647 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
15649 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */
15650 /* Description: IILB Fifo vc2 credit underflow */
15651 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
15652 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
15654 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */
15655 /* Description: MD Fifo vc0 credit underflow */
15656 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
15657 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
15659 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */
15660 /* Description: MD Fifo vc2 credit underflow */
15661 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
15662 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
15664 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */
15665 /* Description: NI Fifo vc0 credit underflow */
15666 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
15667 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
15669 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */
15670 /* Description: NI Fifo vc1 credit underflow */
15671 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
15672 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
15674 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */
15675 /* Description: NI Fifo vc2 credit underflow */
15676 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
15677 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
15679 /* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */
15680 /* Description: NI Fifo vc3 credit underflow */
15681 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
15682 #define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
15684 /* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0 */
15685 /* Description: llp deadlock vc0 */
15686 #define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56
15687 #define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
15689 /* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1 */
15690 /* Description: llp deadlock vc1 */
15691 #define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57
15692 #define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
15694 /* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2 */
15695 /* Description: llp deadlock vc2 */
15696 #define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58
15697 #define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
15699 /* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3 */
15700 /* Description: llp deadlock vc3 */
15701 #define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59
15702 #define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
15704 /* SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH */
15705 /* Description: chiplet nomatch */
15706 #define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60
15707 #define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
15709 /* SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR */
15710 /* Description: LUT Read Error */
15711 #define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61
15712 #define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000
15714 /* SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR */
15715 /* Description: Retry Timeout Error */
15716 #define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62
15717 #define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
15719 /* ==================================================================== */
15720 /* Register "SH_NI0_ERROR_DETAIL_1" */
15721 /* ni0 Chiplet no match header bits 63:0 */
15722 /* ==================================================================== */
15724 #define SH_NI0_ERROR_DETAIL_1 0x0000000150040580
15725 #define SH_NI0_ERROR_DETAIL_1_MASK 0xffffffffffffffff
15726 #define SH_NI0_ERROR_DETAIL_1_INIT 0x0000000000000000
15728 /* SH_NI0_ERROR_DETAIL_1_HEADER */
15729 /* Description: Header bits 63:0 */
15730 #define SH_NI0_ERROR_DETAIL_1_HEADER_SHFT 0
15731 #define SH_NI0_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff
15733 /* ==================================================================== */
15734 /* Register "SH_NI0_ERROR_DETAIL_2" */
15735 /* ni0 Chiplet no match header bits 127:64 */
15736 /* ==================================================================== */
15738 #define SH_NI0_ERROR_DETAIL_2 0x0000000150040590
15739 #define SH_NI0_ERROR_DETAIL_2_MASK 0xffffffffffffffff
15740 #define SH_NI0_ERROR_DETAIL_2_INIT 0x0000000000000000
15742 /* SH_NI0_ERROR_DETAIL_2_HEADER */
15743 /* Description: Header bits 127:64 */
15744 #define SH_NI0_ERROR_DETAIL_2_HEADER_SHFT 0
15745 #define SH_NI0_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff
15747 /* ==================================================================== */
15748 /* Register "SH_NI1_ERROR_SUMMARY_1" */
15749 /* ni1 Error Summary Bits */
15750 /* ==================================================================== */
15752 #define SH_NI1_ERROR_SUMMARY_1 0x0000000150040600
15753 #define SH_NI1_ERROR_SUMMARY_1_MASK 0xffffffffffffffff
15754 #define SH_NI1_ERROR_SUMMARY_1_INIT 0xffffffffffffffff
15756 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0 */
15757 /* Description: Fifo 02 debit0 overflow */
15758 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
15759 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
15761 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2 */
15762 /* Description: Fifo 02 debit2 overflow */
15763 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
15764 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
15766 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0 */
15767 /* Description: Fifo 13 debit0 overflow */
15768 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
15769 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
15771 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2 */
15772 /* Description: Fifo 13 debit2 overflow */
15773 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
15774 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
15776 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP */
15777 /* Description: Fifo 02 vc0 pop overflow */
15778 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
15779 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
15781 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP */
15782 /* Description: Fifo 02 vc2 pop overflow */
15783 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
15784 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
15786 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP */
15787 /* Description: Fifo 13 vc1 pop overflow */
15788 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
15789 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
15791 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP */
15792 /* Description: Fifo 13 vc3 pop overflow */
15793 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
15794 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
15796 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH */
15797 /* Description: Fifo 02 vc0 push overflow */
15798 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
15799 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
15801 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH */
15802 /* Description: Fifo 02 vc2 push overflow */
15803 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
15804 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
15806 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH */
15807 /* Description: Fifo 13 vc1 push overflow */
15808 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
15809 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
15811 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH */
15812 /* Description: Fifo 13 vc3 push overflow */
15813 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
15814 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
15816 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT */
15817 /* Description: Fifo 02 vc0 credit overflow */
15818 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
15819 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
15821 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT */
15822 /* Description: Fifo 02 vc2 credit overflow */
15823 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
15824 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
15826 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT */
15827 /* Description: Fifo 13 vc0 credit overflow */
15828 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
15829 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
15831 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT */
15832 /* Description: Fifo 13 vc2 credit overflow */
15833 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
15834 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
15836 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT */
15837 /* Description: VC0 credit overflow 0 */
15838 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16
15839 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
15841 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT */
15842 /* Description: VC0 credit overflow 1 */
15843 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17
15844 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
15846 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT */
15847 /* Description: VC0 credit overflow 2 */
15848 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18
15849 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
15851 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT */
15852 /* Description: VC2 credit overflow 0 */
15853 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19
15854 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
15856 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT */
15857 /* Description: VC2 credit overflow 1 */
15858 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20
15859 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
15861 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT */
15862 /* Description: VC2 credit overflow 2 */
15863 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21
15864 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
15866 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0 */
15867 /* Description: PI Fifo debit0 overflow */
15868 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
15869 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
15871 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2 */
15872 /* Description: PI Fifo debit2 overflow */
15873 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
15874 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
15876 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0 */
15877 /* Description: IILB Fifo debit0 overflow */
15878 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
15879 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
15881 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2 */
15882 /* Description: IILB Fifo debit2 overflow */
15883 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
15884 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
15886 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0 */
15887 /* Description: MD Fifo debit0 overflow */
15888 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
15889 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
15891 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2 */
15892 /* Description: MD Fifo debit2 overflow */
15893 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
15894 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
15896 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0 */
15897 /* Description: NI Fifo debit0 overflow */
15898 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
15899 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
15901 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1 */
15902 /* Description: NI Fifo debit1 overflow */
15903 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
15904 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
15906 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2 */
15907 /* Description: NI Fifo debit2 overflow */
15908 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
15909 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
15911 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3 */
15912 /* Description: NI Fifo debit3 overflow */
15913 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
15914 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
15916 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP */
15917 /* Description: PI Fifo vc0 pop overflow */
15918 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
15919 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
15921 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP */
15922 /* Description: PI Fifo vc2 pop overflow */
15923 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
15924 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
15926 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP */
15927 /* Description: IILB Fifo vc0 pop overflow */
15928 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
15929 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
15931 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP */
15932 /* Description: IILB Fifo vc2 pop overflow */
15933 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
15934 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
15936 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP */
15937 /* Description: MD Fifo vc0 pop overflow */
15938 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
15939 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
15941 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP */
15942 /* Description: MD Fifo vc2 pop overflow */
15943 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
15944 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
15946 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP */
15947 /* Description: NI Fifo vc0 pop overflow */
15948 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
15949 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
15951 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP */
15952 /* Description: NI Fifo vc2 pop overflow */
15953 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
15954 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
15956 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH */
15957 /* Description: PI Fifo vc0 push overflow */
15958 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
15959 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
15961 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH */
15962 /* Description: PI Fifo vc2 push overflow */
15963 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
15964 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
15966 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH */
15967 /* Description: IILB Fifo vc0 push overflow */
15968 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
15969 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
15971 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH */
15972 /* Description: IILB Fifo vc2 push overflow */
15973 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
15974 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
15976 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH */
15977 /* Description: MD Fifo vc0 push overflow */
15978 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
15979 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
15981 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH */
15982 /* Description: MD Fifo vc2 push overflow */
15983 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
15984 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
15986 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT */
15987 /* Description: PI Fifo vc0 credit overflow */
15988 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
15989 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
15991 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT */
15992 /* Description: PI Fifo vc2 credit overflow */
15993 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
15994 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
15996 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */
15997 /* Description: IILB Fifo vc0 credit overflow */
15998 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
15999 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
16001 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */
16002 /* Description: IILB Fifo vc2 credit overflow */
16003 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
16004 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
16006 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT */
16007 /* Description: MD Fifo vc0 credit overflow */
16008 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
16009 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
16011 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT */
16012 /* Description: MD Fifo vc2 credit overflow */
16013 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
16014 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
16016 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT */
16017 /* Description: NI Fifo vc0 credit overflow */
16018 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
16019 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
16021 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT */
16022 /* Description: NI Fifo vc1 credit overflow */
16023 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
16024 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
16026 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT */
16027 /* Description: NI Fifo vc2 credit overflow */
16028 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
16029 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
16031 /* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT */
16032 /* Description: NI Fifo vc3 credit overflow */
16033 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
16034 #define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
16036 /* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0 */
16037 /* Description: Fifo02 vc0 tail timeout */
16038 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
16039 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
16041 /* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2 */
16042 /* Description: Fifo02 vc2 tail timeout */
16043 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
16044 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
16046 /* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1 */
16047 /* Description: Fifo13 vc1 tail timeout */
16048 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
16049 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
16051 /* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3 */
16052 /* Description: Fifo13 vc3 tail timeout */
16053 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
16054 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
16056 /* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0 */
16057 /* Description: NI vc0 tail timeout */
16058 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
16059 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
16061 /* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1 */
16062 /* Description: NI vc1 tail timeout */
16063 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
16064 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
16066 /* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2 */
16067 /* Description: NI vc2 tail timeout */
16068 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
16069 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
16071 /* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3 */
16072 /* Description: NI vc3 tail timeout */
16073 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
16074 #define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
16076 /* ==================================================================== */
16077 /* Register "SH_NI1_ERROR_SUMMARY_1_ALIAS" */
16078 /* ni1 Error Summary Bits Alias */
16079 /* ==================================================================== */
16081 #define SH_NI1_ERROR_SUMMARY_1_ALIAS 0x0000000150040608
16083 /* ==================================================================== */
16084 /* Register "SH_NI1_ERROR_SUMMARY_2" */
16085 /* ni1 Error Summary Bits */
16086 /* ==================================================================== */
16088 #define SH_NI1_ERROR_SUMMARY_2 0x0000000150040610
16089 #define SH_NI1_ERROR_SUMMARY_2_MASK 0x7fffffff003fffff
16090 #define SH_NI1_ERROR_SUMMARY_2_INIT 0x7fffffff003fffff
16092 /* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI */
16093 /* Description: Illegal VC NI */
16094 #define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0
16095 #define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001
16097 /* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI */
16098 /* Description: Illegal VC PI */
16099 #define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1
16100 #define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002
16102 /* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD */
16103 /* Description: Illegal VC MD */
16104 #define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2
16105 #define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004
16107 /* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB */
16108 /* Description: Illegal VC IILB */
16109 #define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3
16110 #define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
16112 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP */
16113 /* Description: Fifo 02 vc0 pop underflow */
16114 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
16115 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
16117 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP */
16118 /* Description: Fifo 02 vc2 pop underflow */
16119 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
16120 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
16122 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP */
16123 /* Description: Fifo 13 vc1 pop underflow */
16124 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
16125 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
16127 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP */
16128 /* Description: Fifo 13 vc3 pop underflow */
16129 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
16130 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
16132 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH */
16133 /* Description: Fifo 02 vc0 push underflow */
16134 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
16135 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
16137 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH */
16138 /* Description: Fifo 02 vc2 push underflow */
16139 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
16140 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
16142 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH */
16143 /* Description: Fifo 13 vc1 push underflow */
16144 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
16145 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
16147 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH */
16148 /* Description: Fifo 13 vc3 push underflow */
16149 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
16150 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
16152 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT */
16153 /* Description: Fifo 02 vc0 credit underflow */
16154 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
16155 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
16157 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT */
16158 /* Description: Fifo 02 vc2 credit underflow */
16159 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
16160 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
16162 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT */
16163 /* Description: Fifo 13 vc0 credit underflow */
16164 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
16165 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
16167 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT */
16168 /* Description: Fifo 13 vc2 credit underflow */
16169 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
16170 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
16172 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT */
16173 /* Description: VC0 credit underflow 0 */
16174 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
16175 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
16177 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT */
16178 /* Description: VC0 credit underflow 1 */
16179 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
16180 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
16182 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT */
16183 /* Description: VC0 credit underflow 2 */
16184 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
16185 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
16187 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT */
16188 /* Description: VC2 credit underflow 0 */
16189 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
16190 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
16192 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT */
16193 /* Description: VC2 credit underflow 1 */
16194 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
16195 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
16197 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT */
16198 /* Description: VC2 credit underflow 2 */
16199 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
16200 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
16202 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP */
16203 /* Description: PI Fifo vc0 pop underflow */
16204 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
16205 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
16207 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP */
16208 /* Description: PI Fifo vc2 pop underflow */
16209 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
16210 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
16212 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP */
16213 /* Description: IILB Fifo vc0 pop underflow */
16214 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
16215 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
16217 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP */
16218 /* Description: IILB Fifo vc2 pop underflow */
16219 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
16220 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
16222 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP */
16223 /* Description: MD Fifo vc0 pop underflow */
16224 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
16225 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
16227 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP */
16228 /* Description: MD Fifo vc2 pop underflow */
16229 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
16230 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
16232 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP */
16233 /* Description: NI Fifo vc0 pop underflow */
16234 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
16235 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
16237 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP */
16238 /* Description: NI Fifo vc2 pop underflow */
16239 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
16240 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
16242 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH */
16243 /* Description: PI Fifo vc0 push underflow */
16244 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
16245 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
16247 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH */
16248 /* Description: PI Fifo vc2 push underflow */
16249 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
16250 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
16252 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */
16253 /* Description: IILB Fifo vc0 push underflow */
16254 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
16255 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
16257 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */
16258 /* Description: IILB Fifo vc2 push underflow */
16259 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
16260 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
16262 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH */
16263 /* Description: MD Fifo vc0 push underflow */
16264 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
16265 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
16267 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH */
16268 /* Description: MD Fifo vc2 push underflow */
16269 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
16270 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
16272 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */
16273 /* Description: PI Fifo vc0 credit underflow */
16274 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
16275 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
16277 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */
16278 /* Description: PI Fifo vc2 credit underflow */
16279 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
16280 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
16282 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */
16283 /* Description: IILB Fifo vc0 credit underflow */
16284 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
16285 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
16287 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */
16288 /* Description: IILB Fifo vc2 credit underflow */
16289 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
16290 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
16292 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */
16293 /* Description: MD Fifo vc0 credit underflow */
16294 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
16295 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
16297 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */
16298 /* Description: MD Fifo vc2 credit underflow */
16299 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
16300 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
16302 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */
16303 /* Description: NI Fifo vc0 credit underflow */
16304 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
16305 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
16307 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */
16308 /* Description: NI Fifo vc1 credit underflow */
16309 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
16310 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
16312 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */
16313 /* Description: NI Fifo vc2 credit underflow */
16314 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
16315 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
16317 /* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */
16318 /* Description: NI Fifo vc3 credit underflow */
16319 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
16320 #define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
16322 /* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0 */
16323 /* Description: llp deadlock vc0 */
16324 #define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56
16325 #define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
16327 /* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1 */
16328 /* Description: llp deadlock vc1 */
16329 #define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57
16330 #define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
16332 /* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2 */
16333 /* Description: llp deadlock vc2 */
16334 #define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58
16335 #define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
16337 /* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3 */
16338 /* Description: llp deadlock vc3 */
16339 #define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59
16340 #define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
16342 /* SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH */
16343 /* Description: chiplet nomatch */
16344 #define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60
16345 #define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
16347 /* SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR */
16348 /* Description: LUT Read Error */
16349 #define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61
16350 #define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000
16352 /* SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR */
16353 /* Description: Retry Timeout Error */
16354 #define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62
16355 #define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
16357 /* ==================================================================== */
16358 /* Register "SH_NI1_ERROR_SUMMARY_2_ALIAS" */
16359 /* ni1 Error Summary Bits Alias */
16360 /* ==================================================================== */
16362 #define SH_NI1_ERROR_SUMMARY_2_ALIAS 0x0000000150040618
16364 /* ==================================================================== */
16365 /* Register "SH_NI1_ERROR_OVERFLOW_1" */
16366 /* ni1 Error Overflow Bits */
16367 /* ==================================================================== */
16369 #define SH_NI1_ERROR_OVERFLOW_1 0x0000000150040620
16370 #define SH_NI1_ERROR_OVERFLOW_1_MASK 0xffffffffffffffff
16371 #define SH_NI1_ERROR_OVERFLOW_1_INIT 0xffffffffffffffff
16373 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0 */
16374 /* Description: Fifo 02 debit0 overflow */
16375 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
16376 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
16378 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2 */
16379 /* Description: Fifo 02 debit2 overflow */
16380 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
16381 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
16383 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0 */
16384 /* Description: Fifo 13 debit0 overflow */
16385 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
16386 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
16388 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2 */
16389 /* Description: Fifo 13 debit2 overflow */
16390 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
16391 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
16393 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP */
16394 /* Description: Fifo 02 vc0 pop overflow */
16395 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
16396 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
16398 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP */
16399 /* Description: Fifo 02 vc2 pop overflow */
16400 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
16401 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
16403 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP */
16404 /* Description: Fifo 13 vc1 pop overflow */
16405 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
16406 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
16408 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP */
16409 /* Description: Fifo 13 vc3 pop overflow */
16410 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
16411 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
16413 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH */
16414 /* Description: Fifo 02 vc0 push overflow */
16415 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
16416 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
16418 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH */
16419 /* Description: Fifo 02 vc2 push overflow */
16420 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
16421 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
16423 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH */
16424 /* Description: Fifo 13 vc1 push overflow */
16425 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
16426 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
16428 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH */
16429 /* Description: Fifo 13 vc3 push overflow */
16430 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
16431 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
16433 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT */
16434 /* Description: Fifo 02 vc0 credit overflow */
16435 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
16436 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
16438 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT */
16439 /* Description: Fifo 02 vc2 credit overflow */
16440 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
16441 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
16443 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT */
16444 /* Description: Fifo 13 vc0 credit overflow */
16445 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
16446 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
16448 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT */
16449 /* Description: Fifo 13 vc2 credit overflow */
16450 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
16451 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
16453 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT */
16454 /* Description: VC0 credit overflow 0 */
16455 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16
16456 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
16458 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT */
16459 /* Description: VC0 credit overflow 1 */
16460 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17
16461 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
16463 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT */
16464 /* Description: VC0 credit overflow 2 */
16465 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18
16466 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
16468 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT */
16469 /* Description: VC2 credit overflow 0 */
16470 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19
16471 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
16473 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT */
16474 /* Description: VC2 credit overflow 1 */
16475 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20
16476 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
16478 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT */
16479 /* Description: VC2 credit overflow 2 */
16480 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21
16481 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
16483 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0 */
16484 /* Description: PI Fifo debit0 overflow */
16485 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
16486 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
16488 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2 */
16489 /* Description: PI Fifo debit2 overflow */
16490 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
16491 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
16493 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0 */
16494 /* Description: IILB Fifo debit0 overflow */
16495 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
16496 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
16498 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2 */
16499 /* Description: IILB Fifo debit2 overflow */
16500 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
16501 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
16503 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0 */
16504 /* Description: MD Fifo debit0 overflow */
16505 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
16506 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
16508 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2 */
16509 /* Description: MD Fifo debit2 overflow */
16510 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
16511 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
16513 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0 */
16514 /* Description: NI Fifo debit0 overflow */
16515 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
16516 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
16518 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1 */
16519 /* Description: NI Fifo debit1 overflow */
16520 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
16521 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
16523 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2 */
16524 /* Description: NI Fifo debit2 overflow */
16525 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
16526 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
16528 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3 */
16529 /* Description: NI Fifo debit3 overflow */
16530 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
16531 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
16533 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP */
16534 /* Description: PI Fifo vc0 pop overflow */
16535 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
16536 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
16538 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP */
16539 /* Description: PI Fifo vc2 pop overflow */
16540 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
16541 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
16543 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP */
16544 /* Description: IILB Fifo vc0 pop overflow */
16545 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
16546 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
16548 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP */
16549 /* Description: IILB Fifo vc2 pop overflow */
16550 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
16551 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
16553 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP */
16554 /* Description: MD Fifo vc0 pop overflow */
16555 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
16556 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
16558 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP */
16559 /* Description: MD Fifo vc2 pop overflow */
16560 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
16561 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
16563 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP */
16564 /* Description: NI Fifo vc0 pop overflow */
16565 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
16566 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
16568 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP */
16569 /* Description: NI Fifo vc2 pop overflow */
16570 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
16571 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
16573 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH */
16574 /* Description: PI Fifo vc0 push overflow */
16575 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
16576 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
16578 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH */
16579 /* Description: PI Fifo vc2 push overflow */
16580 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
16581 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
16583 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH */
16584 /* Description: IILB Fifo vc0 push overflow */
16585 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
16586 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
16588 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH */
16589 /* Description: IILB Fifo vc2 push overflow */
16590 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
16591 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
16593 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH */
16594 /* Description: MD Fifo vc0 push overflow */
16595 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
16596 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
16598 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH */
16599 /* Description: MD Fifo vc2 push overflow */
16600 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
16601 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
16603 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT */
16604 /* Description: PI Fifo vc0 credit overflow */
16605 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
16606 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
16608 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT */
16609 /* Description: PI Fifo vc2 credit overflow */
16610 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
16611 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
16613 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */
16614 /* Description: IILB Fifo vc0 credit overflow */
16615 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
16616 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
16618 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */
16619 /* Description: IILB Fifo vc2 credit overflow */
16620 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
16621 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
16623 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT */
16624 /* Description: MD Fifo vc0 credit overflow */
16625 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
16626 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
16628 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT */
16629 /* Description: MD Fifo vc2 credit overflow */
16630 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
16631 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
16633 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT */
16634 /* Description: NI Fifo vc0 credit overflow */
16635 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
16636 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
16638 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT */
16639 /* Description: NI Fifo vc1 credit overflow */
16640 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
16641 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
16643 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT */
16644 /* Description: NI Fifo vc2 credit overflow */
16645 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
16646 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
16648 /* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT */
16649 /* Description: NI Fifo vc3 credit overflow */
16650 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
16651 #define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
16653 /* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0 */
16654 /* Description: Fifo02 vc0 tail timeout */
16655 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
16656 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
16658 /* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2 */
16659 /* Description: Fifo02 vc2 tail timeout */
16660 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
16661 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
16663 /* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1 */
16664 /* Description: Fifo13 vc1 tail timeout */
16665 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
16666 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
16668 /* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3 */
16669 /* Description: Fifo13 vc3 tail timeout */
16670 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
16671 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
16673 /* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0 */
16674 /* Description: NI vc0 tail timeout */
16675 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
16676 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
16678 /* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1 */
16679 /* Description: NI vc1 tail timeout */
16680 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
16681 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
16683 /* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2 */
16684 /* Description: NI vc2 tail timeout */
16685 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
16686 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
16688 /* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3 */
16689 /* Description: NI vc3 tail timeout */
16690 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
16691 #define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
16693 /* ==================================================================== */
16694 /* Register "SH_NI1_ERROR_OVERFLOW_1_ALIAS" */
16695 /* ni1 Error Overflow Bits Alias */
16696 /* ==================================================================== */
16698 #define SH_NI1_ERROR_OVERFLOW_1_ALIAS 0x0000000150040628
16700 /* ==================================================================== */
16701 /* Register "SH_NI1_ERROR_OVERFLOW_2" */
16702 /* ni1 Error Overflow Bits */
16703 /* ==================================================================== */
16705 #define SH_NI1_ERROR_OVERFLOW_2 0x0000000150040630
16706 #define SH_NI1_ERROR_OVERFLOW_2_MASK 0x7fffffff003fffff
16707 #define SH_NI1_ERROR_OVERFLOW_2_INIT 0x7fffffff003fffff
16709 /* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI */
16710 /* Description: Illegal VC NI */
16711 #define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0
16712 #define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001
16714 /* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI */
16715 /* Description: Illegal VC PI */
16716 #define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1
16717 #define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002
16719 /* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD */
16720 /* Description: Illegal VC MD */
16721 #define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2
16722 #define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004
16724 /* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB */
16725 /* Description: Illegal VC IILB */
16726 #define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3
16727 #define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
16729 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP */
16730 /* Description: Fifo 02 vc0 pop underflow */
16731 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
16732 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
16734 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP */
16735 /* Description: Fifo 02 vc2 pop underflow */
16736 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
16737 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
16739 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP */
16740 /* Description: Fifo 13 vc1 pop underflow */
16741 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
16742 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
16744 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP */
16745 /* Description: Fifo 13 vc3 pop underflow */
16746 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
16747 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
16749 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH */
16750 /* Description: Fifo 02 vc0 push underflow */
16751 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
16752 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
16754 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH */
16755 /* Description: Fifo 02 vc2 push underflow */
16756 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
16757 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
16759 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH */
16760 /* Description: Fifo 13 vc1 push underflow */
16761 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
16762 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
16764 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH */
16765 /* Description: Fifo 13 vc3 push underflow */
16766 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
16767 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
16769 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT */
16770 /* Description: Fifo 02 vc0 credit underflow */
16771 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
16772 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
16774 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT */
16775 /* Description: Fifo 02 vc2 credit underflow */
16776 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
16777 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
16779 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT */
16780 /* Description: Fifo 13 vc0 credit underflow */
16781 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
16782 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
16784 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT */
16785 /* Description: Fifo 13 vc2 credit underflow */
16786 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
16787 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
16789 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT */
16790 /* Description: VC0 credit underflow 0 */
16791 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
16792 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
16794 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT */
16795 /* Description: VC0 credit underflow 1 */
16796 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
16797 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
16799 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT */
16800 /* Description: VC0 credit underflow 2 */
16801 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
16802 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
16804 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT */
16805 /* Description: VC2 credit underflow 0 */
16806 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
16807 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
16809 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT */
16810 /* Description: VC2 credit underflow 1 */
16811 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
16812 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
16814 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT */
16815 /* Description: VC2 credit underflow 2 */
16816 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
16817 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
16819 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP */
16820 /* Description: PI Fifo vc0 pop underflow */
16821 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
16822 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
16824 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP */
16825 /* Description: PI Fifo vc2 pop underflow */
16826 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
16827 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
16829 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP */
16830 /* Description: IILB Fifo vc0 pop underflow */
16831 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
16832 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
16834 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP */
16835 /* Description: IILB Fifo vc2 pop underflow */
16836 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
16837 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
16839 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP */
16840 /* Description: MD Fifo vc0 pop underflow */
16841 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
16842 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
16844 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP */
16845 /* Description: MD Fifo vc2 pop underflow */
16846 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
16847 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
16849 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP */
16850 /* Description: NI Fifo vc0 pop underflow */
16851 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
16852 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
16854 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP */
16855 /* Description: NI Fifo vc2 pop underflow */
16856 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
16857 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
16859 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH */
16860 /* Description: PI Fifo vc0 push underflow */
16861 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
16862 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
16864 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH */
16865 /* Description: PI Fifo vc2 push underflow */
16866 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
16867 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
16869 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */
16870 /* Description: IILB Fifo vc0 push underflow */
16871 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
16872 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
16874 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */
16875 /* Description: IILB Fifo vc2 push underflow */
16876 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
16877 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
16879 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH */
16880 /* Description: MD Fifo vc0 push underflow */
16881 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
16882 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
16884 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH */
16885 /* Description: MD Fifo vc2 push underflow */
16886 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
16887 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
16889 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */
16890 /* Description: PI Fifo vc0 credit underflow */
16891 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
16892 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
16894 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */
16895 /* Description: PI Fifo vc2 credit underflow */
16896 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
16897 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
16899 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */
16900 /* Description: IILB Fifo vc0 credit underflow */
16901 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
16902 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
16904 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */
16905 /* Description: IILB Fifo vc2 credit underflow */
16906 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
16907 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
16909 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */
16910 /* Description: MD Fifo vc0 credit underflow */
16911 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
16912 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
16914 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */
16915 /* Description: MD Fifo vc2 credit underflow */
16916 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
16917 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
16919 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */
16920 /* Description: NI Fifo vc0 credit underflow */
16921 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
16922 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
16924 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */
16925 /* Description: NI Fifo vc1 credit underflow */
16926 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
16927 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
16929 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */
16930 /* Description: NI Fifo vc2 credit underflow */
16931 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
16932 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
16934 /* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */
16935 /* Description: NI Fifo vc3 credit underflow */
16936 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
16937 #define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
16939 /* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0 */
16940 /* Description: llp deadlock vc0 */
16941 #define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56
16942 #define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
16944 /* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1 */
16945 /* Description: llp deadlock vc1 */
16946 #define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57
16947 #define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
16949 /* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2 */
16950 /* Description: llp deadlock vc2 */
16951 #define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58
16952 #define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
16954 /* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3 */
16955 /* Description: llp deadlock vc3 */
16956 #define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59
16957 #define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
16959 /* SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH */
16960 /* Description: chiplet nomatch */
16961 #define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60
16962 #define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
16964 /* SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR */
16965 /* Description: LUT Read Error */
16966 #define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61
16967 #define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000
16969 /* SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR */
16970 /* Description: Retry Timeout Error */
16971 #define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62
16972 #define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
16974 /* ==================================================================== */
16975 /* Register "SH_NI1_ERROR_OVERFLOW_2_ALIAS" */
16976 /* ni1 Error Overflow Bits Alias */
16977 /* ==================================================================== */
16979 #define SH_NI1_ERROR_OVERFLOW_2_ALIAS 0x0000000150040638
16981 /* ==================================================================== */
16982 /* Register "SH_NI1_ERROR_MASK_1" */
16983 /* ni1 Error Mask Bits */
16984 /* ==================================================================== */
16986 #define SH_NI1_ERROR_MASK_1 0x0000000150040640
16987 #define SH_NI1_ERROR_MASK_1_MASK 0xffffffffffffffff
16988 #define SH_NI1_ERROR_MASK_1_INIT 0xffffffffffffffff
16990 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0 */
16991 /* Description: Fifo 02 debit0 overflow */
16992 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
16993 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
16995 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2 */
16996 /* Description: Fifo 02 debit2 overflow */
16997 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
16998 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
17000 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0 */
17001 /* Description: Fifo 13 debit0 overflow */
17002 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
17003 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
17005 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2 */
17006 /* Description: Fifo 13 debit2 overflow */
17007 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
17008 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
17010 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP */
17011 /* Description: Fifo 02 vc0 pop overflow */
17012 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
17013 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
17015 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP */
17016 /* Description: Fifo 02 vc2 pop overflow */
17017 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
17018 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
17020 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP */
17021 /* Description: Fifo 13 vc1 pop overflow */
17022 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
17023 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
17025 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP */
17026 /* Description: Fifo 13 vc3 pop overflow */
17027 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
17028 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
17030 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH */
17031 /* Description: Fifo 02 vc0 push overflow */
17032 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
17033 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
17035 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH */
17036 /* Description: Fifo 02 vc2 push overflow */
17037 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
17038 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
17040 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH */
17041 /* Description: Fifo 13 vc1 push overflow */
17042 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
17043 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
17045 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH */
17046 /* Description: Fifo 13 vc3 push overflow */
17047 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
17048 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
17050 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT */
17051 /* Description: Fifo 02 vc0 credit overflow */
17052 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
17053 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
17055 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT */
17056 /* Description: Fifo 02 vc2 credit overflow */
17057 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
17058 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
17060 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT */
17061 /* Description: Fifo 13 vc0 credit overflow */
17062 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
17063 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
17065 /* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT */
17066 /* Description: Fifo 13 vc2 credit overflow */
17067 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
17068 #define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
17070 /* SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT */
17071 /* Description: VC0 credit overflow 0 */
17072 #define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16
17073 #define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
17075 /* SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT */
17076 /* Description: VC0 credit overflow 1 */
17077 #define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17
17078 #define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
17080 /* SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT */
17081 /* Description: VC0 credit overflow 2 */
17082 #define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18
17083 #define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
17085 /* SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT */
17086 /* Description: VC2 credit overflow 0 */
17087 #define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19
17088 #define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
17090 /* SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT */
17091 /* Description: VC2 credit overflow 1 */
17092 #define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20
17093 #define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
17095 /* SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT */
17096 /* Description: VC2 credit overflow 2 */
17097 #define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21
17098 #define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
17100 /* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0 */
17101 /* Description: PI Fifo debit0 overflow */
17102 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
17103 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
17105 /* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2 */
17106 /* Description: PI Fifo debit2 overflow */
17107 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
17108 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
17110 /* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0 */
17111 /* Description: IILB Fifo debit0 overflow */
17112 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
17113 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
17115 /* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2 */
17116 /* Description: IILB Fifo debit2 overflow */
17117 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
17118 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
17120 /* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0 */
17121 /* Description: MD Fifo debit0 overflow */
17122 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
17123 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
17125 /* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2 */
17126 /* Description: MD Fifo debit2 overflow */
17127 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
17128 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
17130 /* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0 */
17131 /* Description: NI Fifo debit0 overflow */
17132 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
17133 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
17135 /* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1 */
17136 /* Description: NI Fifo debit1 overflow */
17137 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
17138 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
17140 /* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2 */
17141 /* Description: NI Fifo debit2 overflow */
17142 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
17143 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
17145 /* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3 */
17146 /* Description: NI Fifo debit3 overflow */
17147 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
17148 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
17150 /* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP */
17151 /* Description: PI Fifo vc0 pop overflow */
17152 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
17153 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
17155 /* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP */
17156 /* Description: PI Fifo vc2 pop overflow */
17157 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
17158 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
17160 /* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP */
17161 /* Description: IILB Fifo vc0 pop overflow */
17162 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
17163 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
17165 /* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP */
17166 /* Description: IILB Fifo vc2 pop overflow */
17167 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
17168 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
17170 /* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP */
17171 /* Description: MD Fifo vc0 pop overflow */
17172 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
17173 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
17175 /* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP */
17176 /* Description: MD Fifo vc2 pop overflow */
17177 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
17178 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
17180 /* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP */
17181 /* Description: NI Fifo vc0 pop overflow */
17182 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
17183 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
17185 /* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP */
17186 /* Description: NI Fifo vc2 pop overflow */
17187 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
17188 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
17190 /* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH */
17191 /* Description: PI Fifo vc0 push overflow */
17192 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
17193 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
17195 /* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH */
17196 /* Description: PI Fifo vc2 push overflow */
17197 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
17198 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
17200 /* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH */
17201 /* Description: IILB Fifo vc0 push overflow */
17202 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
17203 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
17205 /* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH */
17206 /* Description: IILB Fifo vc2 push overflow */
17207 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
17208 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
17210 /* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH */
17211 /* Description: MD Fifo vc0 push overflow */
17212 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
17213 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
17215 /* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH */
17216 /* Description: MD Fifo vc2 push overflow */
17217 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
17218 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
17220 /* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT */
17221 /* Description: PI Fifo vc0 credit overflow */
17222 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
17223 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
17225 /* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT */
17226 /* Description: PI Fifo vc2 credit overflow */
17227 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
17228 #define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
17230 /* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */
17231 /* Description: IILB Fifo vc0 credit overflow */
17232 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
17233 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
17235 /* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */
17236 /* Description: IILB Fifo vc2 credit overflow */
17237 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
17238 #define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
17240 /* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT */
17241 /* Description: MD Fifo vc0 credit overflow */
17242 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
17243 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
17245 /* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT */
17246 /* Description: MD Fifo vc2 credit overflow */
17247 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
17248 #define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
17250 /* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT */
17251 /* Description: NI Fifo vc0 credit overflow */
17252 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
17253 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
17255 /* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT */
17256 /* Description: NI Fifo vc1 credit overflow */
17257 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
17258 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
17260 /* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT */
17261 /* Description: NI Fifo vc2 credit overflow */
17262 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
17263 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
17265 /* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT */
17266 /* Description: NI Fifo vc3 credit overflow */
17267 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
17268 #define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
17270 /* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0 */
17271 /* Description: Fifo02 vc0 tail timeout */
17272 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
17273 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
17275 /* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2 */
17276 /* Description: Fifo02 vc2 tail timeout */
17277 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
17278 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
17280 /* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1 */
17281 /* Description: Fifo13 vc1 tail timeout */
17282 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
17283 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
17285 /* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3 */
17286 /* Description: Fifo13 vc3 tail timeout */
17287 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
17288 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
17290 /* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0 */
17291 /* Description: NI vc0 tail timeout */
17292 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
17293 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
17295 /* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1 */
17296 /* Description: NI vc1 tail timeout */
17297 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
17298 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
17300 /* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2 */
17301 /* Description: NI vc2 tail timeout */
17302 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
17303 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
17305 /* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3 */
17306 /* Description: NI vc3 tail timeout */
17307 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
17308 #define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
17310 /* ==================================================================== */
17311 /* Register "SH_NI1_ERROR_MASK_2" */
17312 /* ni1 Error Mask Bits */
17313 /* ==================================================================== */
17315 #define SH_NI1_ERROR_MASK_2 0x0000000150040650
17316 #define SH_NI1_ERROR_MASK_2_MASK 0x7fffffff003fffff
17317 #define SH_NI1_ERROR_MASK_2_INIT 0x7fffffff003fffff
17319 /* SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI */
17320 /* Description: Illegal VC NI */
17321 #define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_SHFT 0
17322 #define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_MASK 0x0000000000000001
17324 /* SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI */
17325 /* Description: Illegal VC PI */
17326 #define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_SHFT 1
17327 #define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_MASK 0x0000000000000002
17329 /* SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD */
17330 /* Description: Illegal VC MD */
17331 #define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_SHFT 2
17332 #define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_MASK 0x0000000000000004
17334 /* SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB */
17335 /* Description: Illegal VC IILB */
17336 #define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT 3
17337 #define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
17339 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP */
17340 /* Description: Fifo 02 vc0 pop underflow */
17341 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
17342 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
17344 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP */
17345 /* Description: Fifo 02 vc2 pop underflow */
17346 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
17347 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
17349 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP */
17350 /* Description: Fifo 13 vc1 pop underflow */
17351 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
17352 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
17354 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP */
17355 /* Description: Fifo 13 vc3 pop underflow */
17356 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
17357 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
17359 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH */
17360 /* Description: Fifo 02 vc0 push underflow */
17361 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
17362 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
17364 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH */
17365 /* Description: Fifo 02 vc2 push underflow */
17366 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
17367 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
17369 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH */
17370 /* Description: Fifo 13 vc1 push underflow */
17371 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
17372 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
17374 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH */
17375 /* Description: Fifo 13 vc3 push underflow */
17376 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
17377 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
17379 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT */
17380 /* Description: Fifo 02 vc0 credit underflow */
17381 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
17382 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
17384 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT */
17385 /* Description: Fifo 02 vc2 credit underflow */
17386 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
17387 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
17389 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT */
17390 /* Description: Fifo 13 vc0 credit underflow */
17391 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
17392 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
17394 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT */
17395 /* Description: Fifo 13 vc2 credit underflow */
17396 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
17397 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
17399 /* SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT */
17400 /* Description: VC0 credit underflow 0 */
17401 #define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
17402 #define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
17404 /* SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT */
17405 /* Description: VC0 credit underflow 1 */
17406 #define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
17407 #define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
17409 /* SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT */
17410 /* Description: VC0 credit underflow 2 */
17411 #define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
17412 #define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
17414 /* SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT */
17415 /* Description: VC2 credit underflow 0 */
17416 #define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
17417 #define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
17419 /* SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT */
17420 /* Description: VC2 credit underflow 1 */
17421 #define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
17422 #define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
17424 /* SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT */
17425 /* Description: VC2 credit underflow 2 */
17426 #define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
17427 #define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
17429 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP */
17430 /* Description: PI Fifo vc0 pop underflow */
17431 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
17432 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
17434 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP */
17435 /* Description: PI Fifo vc2 pop underflow */
17436 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
17437 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
17439 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP */
17440 /* Description: IILB Fifo vc0 pop underflow */
17441 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
17442 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
17444 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP */
17445 /* Description: IILB Fifo vc2 pop underflow */
17446 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
17447 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
17449 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP */
17450 /* Description: MD Fifo vc0 pop underflow */
17451 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
17452 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
17454 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP */
17455 /* Description: MD Fifo vc2 pop underflow */
17456 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
17457 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
17459 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP */
17460 /* Description: NI Fifo vc0 pop underflow */
17461 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
17462 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
17464 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP */
17465 /* Description: NI Fifo vc2 pop underflow */
17466 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
17467 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
17469 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH */
17470 /* Description: PI Fifo vc0 push underflow */
17471 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
17472 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
17474 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH */
17475 /* Description: PI Fifo vc2 push underflow */
17476 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
17477 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
17479 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */
17480 /* Description: IILB Fifo vc0 push underflow */
17481 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
17482 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
17484 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */
17485 /* Description: IILB Fifo vc2 push underflow */
17486 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
17487 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
17489 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH */
17490 /* Description: MD Fifo vc0 push underflow */
17491 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
17492 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
17494 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH */
17495 /* Description: MD Fifo vc2 push underflow */
17496 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
17497 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
17499 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */
17500 /* Description: PI Fifo vc0 credit underflow */
17501 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
17502 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
17504 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */
17505 /* Description: PI Fifo vc2 credit underflow */
17506 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
17507 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
17509 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */
17510 /* Description: IILB Fifo vc0 credit underflow */
17511 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
17512 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
17514 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */
17515 /* Description: IILB Fifo vc2 credit underflow */
17516 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
17517 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
17519 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */
17520 /* Description: MD Fifo vc0 credit underflow */
17521 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
17522 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
17524 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */
17525 /* Description: MD Fifo vc2 credit underflow */
17526 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
17527 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
17529 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */
17530 /* Description: NI Fifo vc0 credit underflow */
17531 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
17532 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
17534 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */
17535 /* Description: NI Fifo vc1 credit underflow */
17536 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
17537 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
17539 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */
17540 /* Description: NI Fifo vc2 credit underflow */
17541 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
17542 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
17544 /* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */
17545 /* Description: NI Fifo vc3 credit underflow */
17546 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
17547 #define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
17549 /* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0 */
17550 /* Description: llp deadlock vc0 */
17551 #define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56
17552 #define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
17554 /* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1 */
17555 /* Description: llp deadlock vc1 */
17556 #define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57
17557 #define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
17559 /* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2 */
17560 /* Description: llp deadlock vc2 */
17561 #define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58
17562 #define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
17564 /* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3 */
17565 /* Description: llp deadlock vc3 */
17566 #define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59
17567 #define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
17569 /* SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH */
17570 /* Description: chiplet nomatch */
17571 #define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60
17572 #define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
17574 /* SH_NI1_ERROR_MASK_2_LUT_READ_ERROR */
17575 /* Description: LUT Read Error */
17576 #define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_SHFT 61
17577 #define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_MASK 0x2000000000000000
17579 /* SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR */
17580 /* Description: Retry Timeout Error */
17581 #define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62
17582 #define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
17584 /* ==================================================================== */
17585 /* Register "SH_NI1_FIRST_ERROR_1" */
17586 /* ni1 First Error Bits */
17587 /* ==================================================================== */
17589 #define SH_NI1_FIRST_ERROR_1 0x0000000150040660
17590 #define SH_NI1_FIRST_ERROR_1_MASK 0xffffffffffffffff
17591 #define SH_NI1_FIRST_ERROR_1_INIT 0xffffffffffffffff
17593 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0 */
17594 /* Description: Fifo 02 debit0 overflow */
17595 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
17596 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
17598 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2 */
17599 /* Description: Fifo 02 debit2 overflow */
17600 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
17601 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
17603 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0 */
17604 /* Description: Fifo 13 debit0 overflow */
17605 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
17606 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
17608 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2 */
17609 /* Description: Fifo 13 debit2 overflow */
17610 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
17611 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
17613 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP */
17614 /* Description: Fifo 02 vc0 pop overflow */
17615 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
17616 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
17618 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP */
17619 /* Description: Fifo 02 vc2 pop overflow */
17620 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
17621 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
17623 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP */
17624 /* Description: Fifo 13 vc1 pop overflow */
17625 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
17626 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
17628 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP */
17629 /* Description: Fifo 13 vc3 pop overflow */
17630 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
17631 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
17633 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH */
17634 /* Description: Fifo 02 vc0 push overflow */
17635 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
17636 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
17638 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH */
17639 /* Description: Fifo 02 vc2 push overflow */
17640 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
17641 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
17643 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH */
17644 /* Description: Fifo 13 vc1 push overflow */
17645 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
17646 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
17648 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH */
17649 /* Description: Fifo 13 vc3 push overflow */
17650 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
17651 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
17653 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT */
17654 /* Description: Fifo 02 vc0 credit overflow */
17655 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
17656 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
17658 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT */
17659 /* Description: Fifo 02 vc2 credit overflow */
17660 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
17661 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
17663 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT */
17664 /* Description: Fifo 13 vc0 credit overflow */
17665 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
17666 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
17668 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT */
17669 /* Description: Fifo 13 vc2 credit overflow */
17670 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
17671 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
17673 /* SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT */
17674 /* Description: VC0 credit overflow 0 */
17675 #define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16
17676 #define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
17678 /* SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT */
17679 /* Description: VC0 credit overflow 1 */
17680 #define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17
17681 #define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
17683 /* SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT */
17684 /* Description: VC0 credit overflow 2 */
17685 #define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18
17686 #define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
17688 /* SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT */
17689 /* Description: VC2 credit overflow 0 */
17690 #define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19
17691 #define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
17693 /* SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT */
17694 /* Description: VC2 credit overflow 1 */
17695 #define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20
17696 #define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
17698 /* SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT */
17699 /* Description: VC2 credit overflow 2 */
17700 #define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21
17701 #define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
17703 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0 */
17704 /* Description: PI Fifo debit0 overflow */
17705 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
17706 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
17708 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2 */
17709 /* Description: PI Fifo debit2 overflow */
17710 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
17711 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
17713 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0 */
17714 /* Description: IILB Fifo debit0 overflow */
17715 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
17716 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
17718 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2 */
17719 /* Description: IILB Fifo debit2 overflow */
17720 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
17721 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
17723 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0 */
17724 /* Description: MD Fifo debit0 overflow */
17725 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
17726 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
17728 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2 */
17729 /* Description: MD Fifo debit2 overflow */
17730 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
17731 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
17733 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0 */
17734 /* Description: NI Fifo debit0 overflow */
17735 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
17736 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
17738 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1 */
17739 /* Description: NI Fifo debit1 overflow */
17740 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
17741 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
17743 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2 */
17744 /* Description: NI Fifo debit2 overflow */
17745 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
17746 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
17748 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3 */
17749 /* Description: NI Fifo debit3 overflow */
17750 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
17751 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
17753 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP */
17754 /* Description: PI Fifo vc0 pop overflow */
17755 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
17756 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
17758 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP */
17759 /* Description: PI Fifo vc2 pop overflow */
17760 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
17761 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
17763 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP */
17764 /* Description: IILB Fifo vc0 pop overflow */
17765 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
17766 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
17768 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP */
17769 /* Description: IILB Fifo vc2 pop overflow */
17770 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
17771 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
17773 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP */
17774 /* Description: MD Fifo vc0 pop overflow */
17775 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
17776 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
17778 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP */
17779 /* Description: MD Fifo vc2 pop overflow */
17780 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
17781 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
17783 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP */
17784 /* Description: NI Fifo vc0 pop overflow */
17785 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
17786 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
17788 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP */
17789 /* Description: NI Fifo vc2 pop overflow */
17790 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
17791 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
17793 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH */
17794 /* Description: PI Fifo vc0 push overflow */
17795 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
17796 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
17798 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH */
17799 /* Description: PI Fifo vc2 push overflow */
17800 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
17801 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
17803 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH */
17804 /* Description: IILB Fifo vc0 push overflow */
17805 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
17806 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
17808 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH */
17809 /* Description: IILB Fifo vc2 push overflow */
17810 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
17811 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
17813 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH */
17814 /* Description: MD Fifo vc0 push overflow */
17815 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
17816 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
17818 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH */
17819 /* Description: MD Fifo vc2 push overflow */
17820 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
17821 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
17823 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT */
17824 /* Description: PI Fifo vc0 credit overflow */
17825 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
17826 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
17828 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT */
17829 /* Description: PI Fifo vc2 credit overflow */
17830 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
17831 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
17833 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */
17834 /* Description: IILB Fifo vc0 credit overflow */
17835 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
17836 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
17838 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */
17839 /* Description: IILB Fifo vc2 credit overflow */
17840 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
17841 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
17843 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT */
17844 /* Description: MD Fifo vc0 credit overflow */
17845 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
17846 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
17848 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT */
17849 /* Description: MD Fifo vc2 credit overflow */
17850 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
17851 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
17853 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT */
17854 /* Description: NI Fifo vc0 credit overflow */
17855 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
17856 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
17858 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT */
17859 /* Description: NI Fifo vc1 credit overflow */
17860 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
17861 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
17863 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT */
17864 /* Description: NI Fifo vc2 credit overflow */
17865 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
17866 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
17868 /* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT */
17869 /* Description: NI Fifo vc3 credit overflow */
17870 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
17871 #define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
17873 /* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0 */
17874 /* Description: Fifo02 vc0 tail timeout */
17875 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
17876 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
17878 /* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2 */
17879 /* Description: Fifo02 vc2 tail timeout */
17880 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
17881 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
17883 /* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1 */
17884 /* Description: Fifo13 vc1 tail timeout */
17885 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
17886 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
17888 /* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3 */
17889 /* Description: Fifo13 vc3 tail timeout */
17890 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
17891 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
17893 /* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0 */
17894 /* Description: NI vc0 tail timeout */
17895 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
17896 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
17898 /* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1 */
17899 /* Description: NI vc1 tail timeout */
17900 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
17901 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
17903 /* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2 */
17904 /* Description: NI vc2 tail timeout */
17905 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
17906 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
17908 /* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3 */
17909 /* Description: NI vc3 tail timeout */
17910 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
17911 #define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
17913 /* ==================================================================== */
17914 /* Register "SH_NI1_FIRST_ERROR_2" */
17915 /* ni1 First Error Bits */
17916 /* ==================================================================== */
17918 #define SH_NI1_FIRST_ERROR_2 0x0000000150040670
17919 #define SH_NI1_FIRST_ERROR_2_MASK 0x7fffffff003fffff
17920 #define SH_NI1_FIRST_ERROR_2_INIT 0x7fffffff003fffff
17922 /* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI */
17923 /* Description: Illegal VC NI */
17924 #define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT 0
17925 #define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_MASK 0x0000000000000001
17927 /* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI */
17928 /* Description: Illegal VC PI */
17929 #define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT 1
17930 #define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_MASK 0x0000000000000002
17932 /* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD */
17933 /* Description: Illegal VC MD */
17934 #define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT 2
17935 #define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_MASK 0x0000000000000004
17937 /* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB */
17938 /* Description: Illegal VC IILB */
17939 #define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3
17940 #define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
17942 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP */
17943 /* Description: Fifo 02 vc0 pop underflow */
17944 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
17945 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
17947 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP */
17948 /* Description: Fifo 02 vc2 pop underflow */
17949 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
17950 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
17952 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP */
17953 /* Description: Fifo 13 vc1 pop underflow */
17954 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
17955 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
17957 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP */
17958 /* Description: Fifo 13 vc3 pop underflow */
17959 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
17960 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
17962 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH */
17963 /* Description: Fifo 02 vc0 push underflow */
17964 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
17965 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
17967 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH */
17968 /* Description: Fifo 02 vc2 push underflow */
17969 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
17970 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
17972 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH */
17973 /* Description: Fifo 13 vc1 push underflow */
17974 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
17975 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
17977 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH */
17978 /* Description: Fifo 13 vc3 push underflow */
17979 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
17980 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
17982 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT */
17983 /* Description: Fifo 02 vc0 credit underflow */
17984 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
17985 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
17987 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT */
17988 /* Description: Fifo 02 vc2 credit underflow */
17989 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
17990 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
17992 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT */
17993 /* Description: Fifo 13 vc0 credit underflow */
17994 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
17995 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
17997 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT */
17998 /* Description: Fifo 13 vc2 credit underflow */
17999 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
18000 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
18002 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT */
18003 /* Description: VC0 credit underflow 0 */
18004 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
18005 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
18007 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT */
18008 /* Description: VC0 credit underflow 1 */
18009 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
18010 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
18012 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT */
18013 /* Description: VC0 credit underflow 2 */
18014 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
18015 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
18017 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT */
18018 /* Description: VC2 credit underflow 0 */
18019 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
18020 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
18022 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT */
18023 /* Description: VC2 credit underflow 1 */
18024 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
18025 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
18027 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT */
18028 /* Description: VC2 credit underflow 2 */
18029 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
18030 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
18032 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP */
18033 /* Description: PI Fifo vc0 pop underflow */
18034 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
18035 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
18037 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP */
18038 /* Description: PI Fifo vc2 pop underflow */
18039 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
18040 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
18042 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP */
18043 /* Description: IILB Fifo vc0 pop underflow */
18044 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
18045 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
18047 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP */
18048 /* Description: IILB Fifo vc2 pop underflow */
18049 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
18050 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
18052 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP */
18053 /* Description: MD Fifo vc0 pop underflow */
18054 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
18055 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
18057 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP */
18058 /* Description: MD Fifo vc2 pop underflow */
18059 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
18060 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
18062 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP */
18063 /* Description: NI Fifo vc0 pop underflow */
18064 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
18065 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
18067 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP */
18068 /* Description: NI Fifo vc2 pop underflow */
18069 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
18070 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
18072 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH */
18073 /* Description: PI Fifo vc0 push underflow */
18074 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
18075 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
18077 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH */
18078 /* Description: PI Fifo vc2 push underflow */
18079 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
18080 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
18082 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */
18083 /* Description: IILB Fifo vc0 push underflow */
18084 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
18085 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
18087 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */
18088 /* Description: IILB Fifo vc2 push underflow */
18089 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
18090 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
18092 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH */
18093 /* Description: MD Fifo vc0 push underflow */
18094 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
18095 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
18097 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH */
18098 /* Description: MD Fifo vc2 push underflow */
18099 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
18100 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
18102 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */
18103 /* Description: PI Fifo vc0 credit underflow */
18104 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
18105 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
18107 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */
18108 /* Description: PI Fifo vc2 credit underflow */
18109 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
18110 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
18112 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */
18113 /* Description: IILB Fifo vc0 credit underflow */
18114 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
18115 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
18117 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */
18118 /* Description: IILB Fifo vc2 credit underflow */
18119 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
18120 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
18122 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */
18123 /* Description: MD Fifo vc0 credit underflow */
18124 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
18125 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
18127 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */
18128 /* Description: MD Fifo vc2 credit underflow */
18129 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
18130 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
18132 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */
18133 /* Description: NI Fifo vc0 credit underflow */
18134 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
18135 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
18137 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */
18138 /* Description: NI Fifo vc1 credit underflow */
18139 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
18140 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
18142 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */
18143 /* Description: NI Fifo vc2 credit underflow */
18144 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
18145 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
18147 /* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */
18148 /* Description: NI Fifo vc3 credit underflow */
18149 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
18150 #define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
18152 /* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0 */
18153 /* Description: llp deadlock vc0 */
18154 #define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56
18155 #define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
18157 /* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1 */
18158 /* Description: llp deadlock vc1 */
18159 #define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57
18160 #define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
18162 /* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2 */
18163 /* Description: llp deadlock vc2 */
18164 #define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58
18165 #define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
18167 /* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3 */
18168 /* Description: llp deadlock vc3 */
18169 #define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59
18170 #define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
18172 /* SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH */
18173 /* Description: chiplet nomatch */
18174 #define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60
18175 #define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
18177 /* SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR */
18178 /* Description: LUT Read Error */
18179 #define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61
18180 #define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000
18182 /* SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR */
18183 /* Description: Retry Timeout Error */
18184 #define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62
18185 #define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
18187 /* ==================================================================== */
18188 /* Register "SH_NI1_ERROR_DETAIL_1" */
18189 /* ni1 Chiplet no match header bits 63:0 */
18190 /* ==================================================================== */
18192 #define SH_NI1_ERROR_DETAIL_1 0x0000000150040680
18193 #define SH_NI1_ERROR_DETAIL_1_MASK 0xffffffffffffffff
18194 #define SH_NI1_ERROR_DETAIL_1_INIT 0x0000000000000000
18196 /* SH_NI1_ERROR_DETAIL_1_HEADER */
18197 /* Description: Header bits 63:0 */
18198 #define SH_NI1_ERROR_DETAIL_1_HEADER_SHFT 0
18199 #define SH_NI1_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff
18201 /* ==================================================================== */
18202 /* Register "SH_NI1_ERROR_DETAIL_2" */
18203 /* ni1 Chiplet no match header bits 127:64 */
18204 /* ==================================================================== */
18206 #define SH_NI1_ERROR_DETAIL_2 0x0000000150040690
18207 #define SH_NI1_ERROR_DETAIL_2_MASK 0xffffffffffffffff
18208 #define SH_NI1_ERROR_DETAIL_2_INIT 0x0000000000000000
18210 /* SH_NI1_ERROR_DETAIL_2_HEADER */
18211 /* Description: Header bits 127:64 */
18212 #define SH_NI1_ERROR_DETAIL_2_HEADER_SHFT 0
18213 #define SH_NI1_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff
18215 /* ==================================================================== */
18216 /* Register "SH_XN_CORRECTED_DETAIL_1" */
18217 /* Corrected error details */
18218 /* ==================================================================== */
18220 #define SH_XN_CORRECTED_DETAIL_1 0x0000000150040070
18221 #define SH_XN_CORRECTED_DETAIL_1_MASK 0x0fff0fff0fff0fff
18222 #define SH_XN_CORRECTED_DETAIL_1_INIT 0x0000000000000000
18224 /* SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME */
18225 /* Description: ECC0 Syndrome */
18226 #define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0
18227 #define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff
18229 /* SH_XN_CORRECTED_DETAIL_1_ECC0_WC */
18230 /* Description: ECC0 Word Count */
18231 #define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_SHFT 8
18232 #define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_MASK 0x0000000000000300
18234 /* SH_XN_CORRECTED_DETAIL_1_ECC0_VC */
18235 /* Description: ECC0 Virtual Channel */
18236 #define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_SHFT 10
18237 #define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_MASK 0x0000000000000c00
18239 /* SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME */
18240 /* Description: ECC1 Syndrome */
18241 #define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16
18242 #define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000
18244 /* SH_XN_CORRECTED_DETAIL_1_ECC1_WC */
18245 /* Description: ECC1 Word Count */
18246 #define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_SHFT 24
18247 #define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_MASK 0x0000000003000000
18249 /* SH_XN_CORRECTED_DETAIL_1_ECC1_VC */
18250 /* Description: ECC1 Virtual Channel */
18251 #define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_SHFT 26
18252 #define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_MASK 0x000000000c000000
18254 /* SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME */
18255 /* Description: ECC2 Syndrome */
18256 #define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32
18257 #define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000
18259 /* SH_XN_CORRECTED_DETAIL_1_ECC2_WC */
18260 /* Description: ECC2 Word Count */
18261 #define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_SHFT 40
18262 #define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_MASK 0x0000030000000000
18264 /* SH_XN_CORRECTED_DETAIL_1_ECC2_VC */
18265 /* Description: ECC2 Virtual Channel */
18266 #define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_SHFT 42
18267 #define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_MASK 0x00000c0000000000
18269 /* SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME */
18270 /* Description: ECC3 Syndrome */
18271 #define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48
18272 #define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000
18274 /* SH_XN_CORRECTED_DETAIL_1_ECC3_WC */
18275 /* Description: ECC3 Word Count */
18276 #define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_SHFT 56
18277 #define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_MASK 0x0300000000000000
18279 /* SH_XN_CORRECTED_DETAIL_1_ECC3_VC */
18280 /* Description: ECC3 Virtual Channel */
18281 #define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_SHFT 58
18282 #define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_MASK 0x0c00000000000000
18284 /* ==================================================================== */
18285 /* Register "SH_XN_CORRECTED_DETAIL_2" */
18286 /* Corrected error data */
18287 /* ==================================================================== */
18289 #define SH_XN_CORRECTED_DETAIL_2 0x0000000150040080
18290 #define SH_XN_CORRECTED_DETAIL_2_MASK 0xffffffffffffffff
18291 #define SH_XN_CORRECTED_DETAIL_2_INIT 0x0000000000000000
18293 /* SH_XN_CORRECTED_DETAIL_2_DATA */
18294 /* Description: ECC data */
18295 #define SH_XN_CORRECTED_DETAIL_2_DATA_SHFT 0
18296 #define SH_XN_CORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff
18298 /* ==================================================================== */
18299 /* Register "SH_XN_CORRECTED_DETAIL_3" */
18300 /* Corrected error header0 */
18301 /* ==================================================================== */
18303 #define SH_XN_CORRECTED_DETAIL_3 0x0000000150040090
18304 #define SH_XN_CORRECTED_DETAIL_3_MASK 0xffffffffffffffff
18305 #define SH_XN_CORRECTED_DETAIL_3_INIT 0x0000000000000000
18307 /* SH_XN_CORRECTED_DETAIL_3_HEADER0 */
18308 /* Description: ECC header0 (bits 63 - 0) */
18309 #define SH_XN_CORRECTED_DETAIL_3_HEADER0_SHFT 0
18310 #define SH_XN_CORRECTED_DETAIL_3_HEADER0_MASK 0xffffffffffffffff
18312 /* ==================================================================== */
18313 /* Register "SH_XN_CORRECTED_DETAIL_4" */
18314 /* Corrected error header1 */
18315 /* ==================================================================== */
18317 #define SH_XN_CORRECTED_DETAIL_4 0x00000001500400a0
18318 #define SH_XN_CORRECTED_DETAIL_4_MASK 0xc00003ffffffffff
18319 #define SH_XN_CORRECTED_DETAIL_4_INIT 0x0000000000000000
18321 /* SH_XN_CORRECTED_DETAIL_4_HEADER1 */
18322 /* Description: ECC header1 (bits 104 - 64) */
18323 #define SH_XN_CORRECTED_DETAIL_4_HEADER1_SHFT 0
18324 #define SH_XN_CORRECTED_DETAIL_4_HEADER1_MASK 0x000003ffffffffff
18326 /* SH_XN_CORRECTED_DETAIL_4_ERR_GROUP */
18327 /* Description: Error group */
18328 #define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_SHFT 62
18329 #define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_MASK 0xc000000000000000
18331 /* ==================================================================== */
18332 /* Register "SH_XN_UNCORRECTED_DETAIL_1" */
18333 /* Uncorrected error details */
18334 /* ==================================================================== */
18336 #define SH_XN_UNCORRECTED_DETAIL_1 0x00000001500400b0
18337 #define SH_XN_UNCORRECTED_DETAIL_1_MASK 0x0fff0fff0fff0fff
18338 #define SH_XN_UNCORRECTED_DETAIL_1_INIT 0x0000000000000000
18340 /* SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME */
18341 /* Description: ECC0 Syndrome */
18342 #define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0
18343 #define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff
18345 /* SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC */
18346 /* Description: ECC0 Word Count */
18347 #define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_SHFT 8
18348 #define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_MASK 0x0000000000000300
18350 /* SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC */
18351 /* Description: ECC0 Virtual Channel */
18352 #define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_SHFT 10
18353 #define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_MASK 0x0000000000000c00
18355 /* SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME */
18356 /* Description: ECC1 Syndrome */
18357 #define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16
18358 #define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000
18360 /* SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC */
18361 /* Description: ECC1 Word Count */
18362 #define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_SHFT 24
18363 #define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_MASK 0x0000000003000000
18365 /* SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC */
18366 /* Description: ECC1 Virtual Channel */
18367 #define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_SHFT 26
18368 #define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_MASK 0x000000000c000000
18370 /* SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME */
18371 /* Description: ECC2 Syndrome */
18372 #define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32
18373 #define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000
18375 /* SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC */
18376 /* Description: ECC2 Word Count */
18377 #define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_SHFT 40
18378 #define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_MASK 0x0000030000000000
18380 /* SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC */
18381 /* Description: ECC2 Virtual Channel */
18382 #define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_SHFT 42
18383 #define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_MASK 0x00000c0000000000
18385 /* SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME */
18386 /* Description: ECC3 Syndrome */
18387 #define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48
18388 #define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000
18390 /* SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC */
18391 /* Description: ECC3 Word Count */
18392 #define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_SHFT 56
18393 #define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_MASK 0x0300000000000000
18395 /* SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC */
18396 /* Description: ECC3 Virtual Channel */
18397 #define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_SHFT 58
18398 #define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_MASK 0x0c00000000000000
18400 /* ==================================================================== */
18401 /* Register "SH_XN_UNCORRECTED_DETAIL_2" */
18402 /* Uncorrected error data */
18403 /* ==================================================================== */
18405 #define SH_XN_UNCORRECTED_DETAIL_2 0x00000001500400c0
18406 #define SH_XN_UNCORRECTED_DETAIL_2_MASK 0xffffffffffffffff
18407 #define SH_XN_UNCORRECTED_DETAIL_2_INIT 0x0000000000000000
18409 /* SH_XN_UNCORRECTED_DETAIL_2_DATA */
18410 /* Description: ECC data */
18411 #define SH_XN_UNCORRECTED_DETAIL_2_DATA_SHFT 0
18412 #define SH_XN_UNCORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff
18414 /* ==================================================================== */
18415 /* Register "SH_XN_UNCORRECTED_DETAIL_3" */
18416 /* Uncorrected error header0 */
18417 /* ==================================================================== */
18419 #define SH_XN_UNCORRECTED_DETAIL_3 0x00000001500400d0
18420 #define SH_XN_UNCORRECTED_DETAIL_3_MASK 0xffffffffffffffff
18421 #define SH_XN_UNCORRECTED_DETAIL_3_INIT 0x0000000000000000
18423 /* SH_XN_UNCORRECTED_DETAIL_3_HEADER0 */
18424 /* Description: ECC header0 (bits 63 - 0) */
18425 #define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_SHFT 0
18426 #define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_MASK 0xffffffffffffffff
18428 /* ==================================================================== */
18429 /* Register "SH_XN_UNCORRECTED_DETAIL_4" */
18430 /* Uncorrected error header1 */
18431 /* ==================================================================== */
18433 #define SH_XN_UNCORRECTED_DETAIL_4 0x00000001500400e0
18434 #define SH_XN_UNCORRECTED_DETAIL_4_MASK 0xc00003ffffffffff
18435 #define SH_XN_UNCORRECTED_DETAIL_4_INIT 0x0000000000000000
18437 /* SH_XN_UNCORRECTED_DETAIL_4_HEADER1 */
18438 /* Description: ECC header1 (bits 104 - 64) */
18439 #define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_SHFT 0
18440 #define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_MASK 0x000003ffffffffff
18442 /* SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP */
18443 /* Description: Error group */
18444 #define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_SHFT 62
18445 #define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_MASK 0xc000000000000000
18447 /* ==================================================================== */
18448 /* Register "SH_XNMD_ERROR_DETAIL_1" */
18449 /* Look Up Table Address (md) */
18450 /* ==================================================================== */
18452 #define SH_XNMD_ERROR_DETAIL_1 0x00000001500400f0
18453 #define SH_XNMD_ERROR_DETAIL_1_MASK 0x00000000000007ff
18454 #define SH_XNMD_ERROR_DETAIL_1_INIT 0x0000000000000000
18456 /* SH_XNMD_ERROR_DETAIL_1_LUT_ADDR */
18457 /* Description: Look Up Table Read Address */
18458 #define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_SHFT 0
18459 #define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_MASK 0x00000000000007ff
18461 /* ==================================================================== */
18462 /* Register "SH_XNPI_ERROR_DETAIL_1" */
18463 /* Look Up Table Address (pi) */
18464 /* ==================================================================== */
18466 #define SH_XNPI_ERROR_DETAIL_1 0x0000000150040100
18467 #define SH_XNPI_ERROR_DETAIL_1_MASK 0x00000000000007ff
18468 #define SH_XNPI_ERROR_DETAIL_1_INIT 0x0000000000000000
18470 /* SH_XNPI_ERROR_DETAIL_1_LUT_ADDR */
18471 /* Description: Look Up Table Read Address */
18472 #define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_SHFT 0
18473 #define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_MASK 0x00000000000007ff
18475 /* ==================================================================== */
18476 /* Register "SH_XNIILB_ERROR_DETAIL_1" */
18477 /* Chiplet NoMatch header [63:0] */
18478 /* ==================================================================== */
18480 #define SH_XNIILB_ERROR_DETAIL_1 0x0000000150040110
18481 #define SH_XNIILB_ERROR_DETAIL_1_MASK 0xffffffffffffffff
18482 #define SH_XNIILB_ERROR_DETAIL_1_INIT 0x0000000000000000
18484 /* SH_XNIILB_ERROR_DETAIL_1_HEADER */
18485 /* Description: header bits [63:0] */
18486 #define SH_XNIILB_ERROR_DETAIL_1_HEADER_SHFT 0
18487 #define SH_XNIILB_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff
18489 /* ==================================================================== */
18490 /* Register "SH_XNIILB_ERROR_DETAIL_2" */
18491 /* Chiplet NoMatch header [127:64] */
18492 /* ==================================================================== */
18494 #define SH_XNIILB_ERROR_DETAIL_2 0x0000000150040120
18495 #define SH_XNIILB_ERROR_DETAIL_2_MASK 0xffffffffffffffff
18496 #define SH_XNIILB_ERROR_DETAIL_2_INIT 0x0000000000000000
18498 /* SH_XNIILB_ERROR_DETAIL_2_HEADER */
18499 /* Description: header bits [127:64] */
18500 #define SH_XNIILB_ERROR_DETAIL_2_HEADER_SHFT 0
18501 #define SH_XNIILB_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff
18503 /* ==================================================================== */
18504 /* Register "SH_XNIILB_ERROR_DETAIL_3" */
18505 /* Look Up Table Address (iilb) */
18506 /* ==================================================================== */
18508 #define SH_XNIILB_ERROR_DETAIL_3 0x0000000150040130
18509 #define SH_XNIILB_ERROR_DETAIL_3_MASK 0x00000000000007ff
18510 #define SH_XNIILB_ERROR_DETAIL_3_INIT 0x0000000000000000
18512 /* SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR */
18513 /* Description: Look Up Table Read Address */
18514 #define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_SHFT 0
18515 #define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff
18517 /* ==================================================================== */
18518 /* Register "SH_NI0_ERROR_DETAIL_3" */
18519 /* Look Up Table Address (ni0) */
18520 /* ==================================================================== */
18522 #define SH_NI0_ERROR_DETAIL_3 0x0000000150040140
18523 #define SH_NI0_ERROR_DETAIL_3_MASK 0x00000000000007ff
18524 #define SH_NI0_ERROR_DETAIL_3_INIT 0x0000000000000000
18526 /* SH_NI0_ERROR_DETAIL_3_LUT_ADDR */
18527 /* Description: Look Up Table Read Address */
18528 #define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_SHFT 0
18529 #define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff
18531 /* ==================================================================== */
18532 /* Register "SH_NI1_ERROR_DETAIL_3" */
18533 /* Look Up Table Address (ni1) */
18534 /* ==================================================================== */
18536 #define SH_NI1_ERROR_DETAIL_3 0x0000000150040150
18537 #define SH_NI1_ERROR_DETAIL_3_MASK 0x00000000000007ff
18538 #define SH_NI1_ERROR_DETAIL_3_INIT 0x0000000000000000
18540 /* SH_NI1_ERROR_DETAIL_3_LUT_ADDR */
18541 /* Description: Look Up Table Read Address */
18542 #define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_SHFT 0
18543 #define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff
18545 /* ==================================================================== */
18546 /* Register "SH_XN_ERROR_SUMMARY" */
18547 /* ==================================================================== */
18549 #define SH_XN_ERROR_SUMMARY 0x0000000150040000
18550 #define SH_XN_ERROR_SUMMARY_MASK 0x0000003fffffffff
18551 #define SH_XN_ERROR_SUMMARY_INIT 0x0000003fffffffff
18553 /* SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW */
18554 /* Description: NI0 pop overflow */
18555 #define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_SHFT 0
18556 #define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_MASK 0x0000000000000001
18558 /* SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW */
18559 /* Description: NI0 push overflow */
18560 #define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_SHFT 1
18561 #define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002
18563 /* SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW */
18564 /* Description: NI0 credit overflow */
18565 #define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_SHFT 2
18566 #define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
18568 /* SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW */
18569 /* Description: NI0 debit overflow */
18570 #define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_SHFT 3
18571 #define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
18573 /* SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW */
18574 /* Description: NI0 pop underflow */
18575 #define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_SHFT 4
18576 #define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_MASK 0x0000000000000010
18578 /* SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW */
18579 /* Description: NI0 push underflow */
18580 #define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_SHFT 5
18581 #define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
18583 /* SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW */
18584 /* Description: NI0 credit underflow */
18585 #define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_SHFT 6
18586 #define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
18588 /* SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR */
18589 /* Description: NI0 llp error */
18590 #define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_SHFT 7
18591 #define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_MASK 0x0000000000000080
18593 /* SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR */
18594 /* Description: NI0 Pipe in/out errors */
18595 #define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_SHFT 8
18596 #define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_MASK 0x0000000000000100
18598 /* SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW */
18599 /* Description: NI1 pop overflow */
18600 #define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_SHFT 9
18601 #define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_MASK 0x0000000000000200
18603 /* SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW */
18604 /* Description: NI1 push overflow */
18605 #define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_SHFT 10
18606 #define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400
18608 /* SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW */
18609 /* Description: NI1 credit overflow */
18610 #define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_SHFT 11
18611 #define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
18613 /* SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW */
18614 /* Description: NI1 debit overflow */
18615 #define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_SHFT 12
18616 #define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
18618 /* SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW */
18619 /* Description: NI1 pop underflow */
18620 #define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_SHFT 13
18621 #define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_MASK 0x0000000000002000
18623 /* SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW */
18624 /* Description: NI1 push underflow */
18625 #define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_SHFT 14
18626 #define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
18628 /* SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW */
18629 /* Description: NI1 credit underflow */
18630 #define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_SHFT 15
18631 #define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
18633 /* SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR */
18634 /* Description: NI1 llp error */
18635 #define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_SHFT 16
18636 #define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_MASK 0x0000000000010000
18638 /* SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR */
18639 /* Description: NI1 pipe in/out error */
18640 #define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_SHFT 17
18641 #define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_MASK 0x0000000000020000
18643 /* SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW */
18644 /* Description: XNMD credit overflow */
18645 #define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_SHFT 18
18646 #define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
18648 /* SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW */
18649 /* Description: XNMD debit overflow */
18650 #define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_SHFT 19
18651 #define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
18653 /* SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW */
18654 /* Description: XNMD data buffer overflow */
18655 #define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
18656 #define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
18658 /* SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW */
18659 /* Description: XNMD credit underflow */
18660 #define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_SHFT 21
18661 #define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
18663 /* SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR */
18664 /* Description: XNMD single bit error */
18665 #define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_SHFT 22
18666 #define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_MASK 0x0000000000400000
18668 /* SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR */
18669 /* Description: XNMD uncorrectable error */
18670 #define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_SHFT 23
18671 #define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_MASK 0x0000000000800000
18673 /* SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR */
18674 /* Description: XNMD look up table error */
18675 #define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_SHFT 24
18676 #define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_MASK 0x0000000001000000
18678 /* SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW */
18679 /* Description: XNMD credit overflow */
18680 #define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_SHFT 25
18681 #define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
18683 /* SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW */
18684 /* Description: XNPI debit overflow */
18685 #define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_SHFT 26
18686 #define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
18688 /* SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW */
18689 /* Description: XNPI data buffer overflow */
18690 #define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
18691 #define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
18693 /* SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW */
18694 /* Description: XNPI credit underflow */
18695 #define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_SHFT 28
18696 #define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
18698 /* SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR */
18699 /* Description: XNPI single bit error */
18700 #define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_SHFT 29
18701 #define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_MASK 0x0000000020000000
18703 /* SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR */
18704 /* Description: XNPI uncorrectable error */
18705 #define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_SHFT 30
18706 #define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_MASK 0x0000000040000000
18708 /* SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR */
18709 /* Description: XNPI look up table error */
18710 #define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_SHFT 31
18711 #define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_MASK 0x0000000080000000
18713 /* SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW */
18714 /* Description: IILB debit overflow */
18715 #define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_SHFT 32
18716 #define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
18718 /* SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW */
18719 /* Description: IILB credit overflow */
18720 #define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_SHFT 33
18721 #define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
18723 /* SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW */
18724 /* Description: IILB fifo overflow */
18725 #define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_SHFT 34
18726 #define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
18728 /* SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW */
18729 /* Description: IILB credit underflow */
18730 #define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_SHFT 35
18731 #define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
18733 /* SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW */
18734 /* Description: IILB fifo underflow */
18735 #define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_SHFT 36
18736 #define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
18738 /* SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT */
18739 /* Description: IILB chiplet nomatch or lut read error */
18740 #define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_SHFT 37
18741 #define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
18743 /* ==================================================================== */
18744 /* Register "SH_XN_ERRORS_ALIAS" */
18745 /* ==================================================================== */
18747 #define SH_XN_ERRORS_ALIAS 0x0000000150040008
18749 /* ==================================================================== */
18750 /* Register "SH_XN_ERROR_OVERFLOW" */
18751 /* ==================================================================== */
18753 #define SH_XN_ERROR_OVERFLOW 0x0000000150040020
18754 #define SH_XN_ERROR_OVERFLOW_MASK 0x0000003fffffffff
18755 #define SH_XN_ERROR_OVERFLOW_INIT 0x0000003fffffffff
18757 /* SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW */
18758 /* Description: NI0 pop overflow */
18759 #define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_SHFT 0
18760 #define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_MASK 0x0000000000000001
18762 /* SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW */
18763 /* Description: NI0 push overflow */
18764 #define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_SHFT 1
18765 #define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002
18767 /* SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW */
18768 /* Description: NI0 credit overflow */
18769 #define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_SHFT 2
18770 #define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
18772 /* SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW */
18773 /* Description: NI0 debit overflow */
18774 #define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_SHFT 3
18775 #define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
18777 /* SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW */
18778 /* Description: NI0 pop underflow */
18779 #define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_SHFT 4
18780 #define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_MASK 0x0000000000000010
18782 /* SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW */
18783 /* Description: NI0 push underflow */
18784 #define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_SHFT 5
18785 #define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
18787 /* SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW */
18788 /* Description: NI0 credit underflow */
18789 #define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_SHFT 6
18790 #define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
18792 /* SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR */
18793 /* Description: NI0 llp error */
18794 #define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_SHFT 7
18795 #define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_MASK 0x0000000000000080
18797 /* SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR */
18798 /* Description: NI0 Pipe in/out errors */
18799 #define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_SHFT 8
18800 #define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_MASK 0x0000000000000100
18802 /* SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW */
18803 /* Description: NI1 pop overflow */
18804 #define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_SHFT 9
18805 #define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_MASK 0x0000000000000200
18807 /* SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW */
18808 /* Description: NI1 push overflow */
18809 #define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_SHFT 10
18810 #define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400
18812 /* SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW */
18813 /* Description: NI1 credit overflow */
18814 #define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_SHFT 11
18815 #define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
18817 /* SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW */
18818 /* Description: NI1 debit overflow */
18819 #define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_SHFT 12
18820 #define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
18822 /* SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW */
18823 /* Description: NI1 pop underflow */
18824 #define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_SHFT 13
18825 #define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_MASK 0x0000000000002000
18827 /* SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW */
18828 /* Description: NI1 push underflow */
18829 #define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_SHFT 14
18830 #define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
18832 /* SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW */
18833 /* Description: NI1 credit underflow */
18834 #define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_SHFT 15
18835 #define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
18837 /* SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR */
18838 /* Description: NI1 llp error */
18839 #define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_SHFT 16
18840 #define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_MASK 0x0000000000010000
18842 /* SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR */
18843 /* Description: NI1 pipe in/out error */
18844 #define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_SHFT 17
18845 #define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_MASK 0x0000000000020000
18847 /* SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW */
18848 /* Description: XNMD credit overflow */
18849 #define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_SHFT 18
18850 #define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
18852 /* SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW */
18853 /* Description: XNMD debit overflow */
18854 #define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_SHFT 19
18855 #define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
18857 /* SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW */
18858 /* Description: XNMD data buffer overflow */
18859 #define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
18860 #define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
18862 /* SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW */
18863 /* Description: XNMD credit underflow */
18864 #define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_SHFT 21
18865 #define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
18867 /* SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR */
18868 /* Description: XNMD single bit error */
18869 #define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_SHFT 22
18870 #define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_MASK 0x0000000000400000
18872 /* SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR */
18873 /* Description: XNMD uncorrectable error */
18874 #define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_SHFT 23
18875 #define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_MASK 0x0000000000800000
18877 /* SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR */
18878 /* Description: XNMD look up table error */
18879 #define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_SHFT 24
18880 #define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_MASK 0x0000000001000000
18882 /* SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW */
18883 /* Description: XNMD credit overflow */
18884 #define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_SHFT 25
18885 #define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
18887 /* SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW */
18888 /* Description: XNPI debit overflow */
18889 #define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_SHFT 26
18890 #define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
18892 /* SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW */
18893 /* Description: XNPI data buffer overflow */
18894 #define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
18895 #define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
18897 /* SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW */
18898 /* Description: XNPI credit underflow */
18899 #define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_SHFT 28
18900 #define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
18902 /* SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR */
18903 /* Description: XNPI single bit error */
18904 #define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_SHFT 29
18905 #define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_MASK 0x0000000020000000
18907 /* SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR */
18908 /* Description: XNPI uncorrectable error */
18909 #define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_SHFT 30
18910 #define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_MASK 0x0000000040000000
18912 /* SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR */
18913 /* Description: XNPI look up table error */
18914 #define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_SHFT 31
18915 #define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_MASK 0x0000000080000000
18917 /* SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW */
18918 /* Description: IILB debit overflow */
18919 #define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_SHFT 32
18920 #define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
18922 /* SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW */
18923 /* Description: IILB credit overflow */
18924 #define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_SHFT 33
18925 #define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
18927 /* SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW */
18928 /* Description: IILB fifo overflow */
18929 #define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_SHFT 34
18930 #define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
18932 /* SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW */
18933 /* Description: IILB credit underflow */
18934 #define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_SHFT 35
18935 #define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
18937 /* SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW */
18938 /* Description: IILB fifo underflow */
18939 #define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_SHFT 36
18940 #define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
18942 /* SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT */
18943 /* Description: IILB chiplet nomatch or lut read error */
18944 #define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_SHFT 37
18945 #define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
18947 /* ==================================================================== */
18948 /* Register "SH_XN_ERROR_OVERFLOW_ALIAS" */
18949 /* ==================================================================== */
18951 #define SH_XN_ERROR_OVERFLOW_ALIAS 0x0000000150040028
18953 /* ==================================================================== */
18954 /* Register "SH_XN_ERROR_MASK" */
18955 /* ==================================================================== */
18957 #define SH_XN_ERROR_MASK 0x0000000150040040
18958 #define SH_XN_ERROR_MASK_MASK 0x0000003fffffffff
18959 #define SH_XN_ERROR_MASK_INIT 0x0000003fffffffff
18961 /* SH_XN_ERROR_MASK_NI0_POP_OVERFLOW */
18962 /* Description: NI0 pop overflow */
18963 #define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_SHFT 0
18964 #define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_MASK 0x0000000000000001
18966 /* SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW */
18967 /* Description: NI0 push overflow */
18968 #define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_SHFT 1
18969 #define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002
18971 /* SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW */
18972 /* Description: NI0 credit overflow */
18973 #define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_SHFT 2
18974 #define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
18976 /* SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW */
18977 /* Description: NI0 debit overflow */
18978 #define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_SHFT 3
18979 #define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
18981 /* SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW */
18982 /* Description: NI0 pop underflow */
18983 #define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_SHFT 4
18984 #define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_MASK 0x0000000000000010
18986 /* SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW */
18987 /* Description: NI0 push underflow */
18988 #define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_SHFT 5
18989 #define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
18991 /* SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW */
18992 /* Description: NI0 credit underflow */
18993 #define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_SHFT 6
18994 #define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
18996 /* SH_XN_ERROR_MASK_NI0_LLP_ERROR */
18997 /* Description: NI0 llp error */
18998 #define SH_XN_ERROR_MASK_NI0_LLP_ERROR_SHFT 7
18999 #define SH_XN_ERROR_MASK_NI0_LLP_ERROR_MASK 0x0000000000000080
19001 /* SH_XN_ERROR_MASK_NI0_PIPE_ERROR */
19002 /* Description: NI0 Pipe in/out errors */
19003 #define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_SHFT 8
19004 #define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_MASK 0x0000000000000100
19006 /* SH_XN_ERROR_MASK_NI1_POP_OVERFLOW */
19007 /* Description: NI1 pop overflow */
19008 #define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_SHFT 9
19009 #define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_MASK 0x0000000000000200
19011 /* SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW */
19012 /* Description: NI1 push overflow */
19013 #define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_SHFT 10
19014 #define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400
19016 /* SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW */
19017 /* Description: NI1 credit overflow */
19018 #define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_SHFT 11
19019 #define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
19021 /* SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW */
19022 /* Description: NI1 debit overflow */
19023 #define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_SHFT 12
19024 #define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
19026 /* SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW */
19027 /* Description: NI1 pop underflow */
19028 #define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_SHFT 13
19029 #define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_MASK 0x0000000000002000
19031 /* SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW */
19032 /* Description: NI1 push underflow */
19033 #define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_SHFT 14
19034 #define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
19036 /* SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW */
19037 /* Description: NI1 credit underflow */
19038 #define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_SHFT 15
19039 #define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
19041 /* SH_XN_ERROR_MASK_NI1_LLP_ERROR */
19042 /* Description: NI1 llp error */
19043 #define SH_XN_ERROR_MASK_NI1_LLP_ERROR_SHFT 16
19044 #define SH_XN_ERROR_MASK_NI1_LLP_ERROR_MASK 0x0000000000010000
19046 /* SH_XN_ERROR_MASK_NI1_PIPE_ERROR */
19047 /* Description: NI1 pipe in/out error */
19048 #define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_SHFT 17
19049 #define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_MASK 0x0000000000020000
19051 /* SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW */
19052 /* Description: XNMD credit overflow */
19053 #define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_SHFT 18
19054 #define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
19056 /* SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW */
19057 /* Description: XNMD debit overflow */
19058 #define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_SHFT 19
19059 #define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
19061 /* SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW */
19062 /* Description: XNMD data buffer overflow */
19063 #define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
19064 #define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
19066 /* SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW */
19067 /* Description: XNMD credit underflow */
19068 #define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_SHFT 21
19069 #define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
19071 /* SH_XN_ERROR_MASK_XNMD_SBE_ERROR */
19072 /* Description: XNMD single bit error */
19073 #define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_SHFT 22
19074 #define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_MASK 0x0000000000400000
19076 /* SH_XN_ERROR_MASK_XNMD_UCE_ERROR */
19077 /* Description: XNMD uncorrectable error */
19078 #define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_SHFT 23
19079 #define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_MASK 0x0000000000800000
19081 /* SH_XN_ERROR_MASK_XNMD_LUT_ERROR */
19082 /* Description: XNMD look up table error */
19083 #define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_SHFT 24
19084 #define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_MASK 0x0000000001000000
19086 /* SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW */
19087 /* Description: XNMD credit overflow */
19088 #define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_SHFT 25
19089 #define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
19091 /* SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW */
19092 /* Description: XNPI debit overflow */
19093 #define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_SHFT 26
19094 #define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
19096 /* SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW */
19097 /* Description: XNPI data buffer overflow */
19098 #define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
19099 #define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
19101 /* SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW */
19102 /* Description: XNPI credit underflow */
19103 #define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_SHFT 28
19104 #define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
19106 /* SH_XN_ERROR_MASK_XNPI_SBE_ERROR */
19107 /* Description: XNPI single bit error */
19108 #define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_SHFT 29
19109 #define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_MASK 0x0000000020000000
19111 /* SH_XN_ERROR_MASK_XNPI_UCE_ERROR */
19112 /* Description: XNPI uncorrectable error */
19113 #define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_SHFT 30
19114 #define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_MASK 0x0000000040000000
19116 /* SH_XN_ERROR_MASK_XNPI_LUT_ERROR */
19117 /* Description: XNPI look up table error */
19118 #define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_SHFT 31
19119 #define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_MASK 0x0000000080000000
19121 /* SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW */
19122 /* Description: IILB debit overflow */
19123 #define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_SHFT 32
19124 #define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
19126 /* SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW */
19127 /* Description: IILB credit overflow */
19128 #define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_SHFT 33
19129 #define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
19131 /* SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW */
19132 /* Description: IILB fifo overflow */
19133 #define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_SHFT 34
19134 #define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
19136 /* SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW */
19137 /* Description: IILB credit underflow */
19138 #define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_SHFT 35
19139 #define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
19141 /* SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW */
19142 /* Description: IILB fifo underflow */
19143 #define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_SHFT 36
19144 #define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
19146 /* SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT */
19147 /* Description: IILB chiplet nomatch or lut read error */
19148 #define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_SHFT 37
19149 #define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
19151 /* ==================================================================== */
19152 /* Register "SH_XN_FIRST_ERROR" */
19153 /* ==================================================================== */
19155 #define SH_XN_FIRST_ERROR 0x0000000150040060
19156 #define SH_XN_FIRST_ERROR_MASK 0x0000003fffffffff
19157 #define SH_XN_FIRST_ERROR_INIT 0x0000003fffffffff
19159 /* SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW */
19160 /* Description: NI0 pop overflow */
19161 #define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_SHFT 0
19162 #define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_MASK 0x0000000000000001
19164 /* SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW */
19165 /* Description: NI0 push overflow */
19166 #define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_SHFT 1
19167 #define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002
19169 /* SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW */
19170 /* Description: NI0 credit overflow */
19171 #define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_SHFT 2
19172 #define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
19174 /* SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW */
19175 /* Description: NI0 debit overflow */
19176 #define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_SHFT 3
19177 #define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
19179 /* SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW */
19180 /* Description: NI0 pop underflow */
19181 #define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_SHFT 4
19182 #define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_MASK 0x0000000000000010
19184 /* SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW */
19185 /* Description: NI0 push underflow */
19186 #define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_SHFT 5
19187 #define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
19189 /* SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW */
19190 /* Description: NI0 credit underflow */
19191 #define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_SHFT 6
19192 #define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
19194 /* SH_XN_FIRST_ERROR_NI0_LLP_ERROR */
19195 /* Description: NI0 llp error */
19196 #define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_SHFT 7
19197 #define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_MASK 0x0000000000000080
19199 /* SH_XN_FIRST_ERROR_NI0_PIPE_ERROR */
19200 /* Description: NI0 Pipe in/out errors */
19201 #define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_SHFT 8
19202 #define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_MASK 0x0000000000000100
19204 /* SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW */
19205 /* Description: NI1 pop overflow */
19206 #define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_SHFT 9
19207 #define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_MASK 0x0000000000000200
19209 /* SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW */
19210 /* Description: NI1 push overflow */
19211 #define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_SHFT 10
19212 #define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400
19214 /* SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW */
19215 /* Description: NI1 credit overflow */
19216 #define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_SHFT 11
19217 #define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
19219 /* SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW */
19220 /* Description: NI1 debit overflow */
19221 #define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_SHFT 12
19222 #define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
19224 /* SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW */
19225 /* Description: NI1 pop underflow */
19226 #define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_SHFT 13
19227 #define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_MASK 0x0000000000002000
19229 /* SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW */
19230 /* Description: NI1 push underflow */
19231 #define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_SHFT 14
19232 #define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
19234 /* SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW */
19235 /* Description: NI1 credit underflow */
19236 #define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_SHFT 15
19237 #define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
19239 /* SH_XN_FIRST_ERROR_NI1_LLP_ERROR */
19240 /* Description: NI1 llp error */
19241 #define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_SHFT 16
19242 #define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_MASK 0x0000000000010000
19244 /* SH_XN_FIRST_ERROR_NI1_PIPE_ERROR */
19245 /* Description: NI1 pipe in/out error */
19246 #define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_SHFT 17
19247 #define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_MASK 0x0000000000020000
19249 /* SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW */
19250 /* Description: XNMD credit overflow */
19251 #define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_SHFT 18
19252 #define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
19254 /* SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW */
19255 /* Description: XNMD debit overflow */
19256 #define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_SHFT 19
19257 #define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
19259 /* SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW */
19260 /* Description: XNMD data buffer overflow */
19261 #define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
19262 #define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
19264 /* SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW */
19265 /* Description: XNMD credit underflow */
19266 #define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_SHFT 21
19267 #define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
19269 /* SH_XN_FIRST_ERROR_XNMD_SBE_ERROR */
19270 /* Description: XNMD single bit error */
19271 #define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_SHFT 22
19272 #define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_MASK 0x0000000000400000
19274 /* SH_XN_FIRST_ERROR_XNMD_UCE_ERROR */
19275 /* Description: XNMD uncorrectable error */
19276 #define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_SHFT 23
19277 #define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_MASK 0x0000000000800000
19279 /* SH_XN_FIRST_ERROR_XNMD_LUT_ERROR */
19280 /* Description: XNMD look up table error */
19281 #define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_SHFT 24
19282 #define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_MASK 0x0000000001000000
19284 /* SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW */
19285 /* Description: XNMD credit overflow */
19286 #define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_SHFT 25
19287 #define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
19289 /* SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW */
19290 /* Description: XNPI debit overflow */
19291 #define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_SHFT 26
19292 #define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
19294 /* SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW */
19295 /* Description: XNPI data buffer overflow */
19296 #define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
19297 #define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
19299 /* SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW */
19300 /* Description: XNPI credit underflow */
19301 #define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_SHFT 28
19302 #define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
19304 /* SH_XN_FIRST_ERROR_XNPI_SBE_ERROR */
19305 /* Description: XNPI single bit error */
19306 #define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_SHFT 29
19307 #define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_MASK 0x0000000020000000
19309 /* SH_XN_FIRST_ERROR_XNPI_UCE_ERROR */
19310 /* Description: XNPI uncorrectable error */
19311 #define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_SHFT 30
19312 #define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_MASK 0x0000000040000000
19314 /* SH_XN_FIRST_ERROR_XNPI_LUT_ERROR */
19315 /* Description: XNPI look up table error */
19316 #define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_SHFT 31
19317 #define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_MASK 0x0000000080000000
19319 /* SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW */
19320 /* Description: IILB debit overflow */
19321 #define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_SHFT 32
19322 #define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
19324 /* SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW */
19325 /* Description: IILB credit overflow */
19326 #define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_SHFT 33
19327 #define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
19329 /* SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW */
19330 /* Description: IILB fifo overflow */
19331 #define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_SHFT 34
19332 #define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
19334 /* SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW */
19335 /* Description: IILB credit underflow */
19336 #define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_SHFT 35
19337 #define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
19339 /* SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW */
19340 /* Description: IILB fifo underflow */
19341 #define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_SHFT 36
19342 #define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
19344 /* SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT */
19345 /* Description: IILB chiplet nomatch or lut read error */
19346 #define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_SHFT 37
19347 #define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
19349 /* ==================================================================== */
19350 /* Register "SH_XNIILB_ERROR_SUMMARY" */
19351 /* ==================================================================== */
19353 #define SH_XNIILB_ERROR_SUMMARY 0x0000000150040200
19354 #define SH_XNIILB_ERROR_SUMMARY_MASK 0xffffffffffffffff
19355 #define SH_XNIILB_ERROR_SUMMARY_INIT 0xffffffffffffffff
19357 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0 */
19358 /* Description: II debit0 overflow */
19359 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_SHFT 0
19360 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
19362 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2 */
19363 /* Description: II debit2 overflow */
19364 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_SHFT 1
19365 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
19367 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0 */
19368 /* Description: LB debit0 overflow */
19369 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_SHFT 2
19370 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
19372 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2 */
19373 /* Description: LB debit2 overflow */
19374 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_SHFT 3
19375 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
19377 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0 */
19378 /* Description: II VC0 fifo overflow */
19379 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_SHFT 4
19380 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_MASK 0x0000000000000010
19382 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2 */
19383 /* Description: II VC2 fifo overflow */
19384 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_SHFT 5
19385 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_MASK 0x0000000000000020
19387 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0 */
19388 /* Description: II VC0 fifo underflow */
19389 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_SHFT 6
19390 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_MASK 0x0000000000000040
19392 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2 */
19393 /* Description: II VC2 fifo underflow */
19394 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_SHFT 7
19395 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_MASK 0x0000000000000080
19397 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0 */
19398 /* Description: LB VC0 fifo overflow */
19399 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_SHFT 8
19400 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_MASK 0x0000000000000100
19402 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2 */
19403 /* Description: LB VC2 fifo overflow */
19404 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_SHFT 9
19405 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_MASK 0x0000000000000200
19407 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0 */
19408 /* Description: LB VC0 fifo underflow */
19409 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_SHFT 10
19410 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
19412 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2 */
19413 /* Description: LB VC2 fifo underflow */
19414 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_SHFT 11
19415 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
19417 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN */
19418 /* Description: PI VC0 credit overflow Pipe In */
19419 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
19420 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
19422 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN */
19423 /* Description: IILB VC0 credit overflow Pipe In */
19424 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
19425 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
19427 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN */
19428 /* Description: MD VC0 credit overflow Pipe In */
19429 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
19430 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
19432 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN */
19433 /* Description: NI0 VC0 credit overflow Pipe In */
19434 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
19435 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
19437 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN */
19438 /* Description: NI1 VC0 credit overflow Pipe In */
19439 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
19440 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
19442 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN */
19443 /* Description: PI VC2 credit overflow Pipe In */
19444 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
19445 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
19447 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN */
19448 /* Description: IILB VC2 credit overflow Pipe In */
19449 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
19450 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
19452 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN */
19453 /* Description: MD VC2 credit overflow Pipe In */
19454 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
19455 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
19457 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN */
19458 /* Description: NI0 VC2 credit overflow Pipe In */
19459 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
19460 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
19462 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN */
19463 /* Description: NI1 VC2 credit overflow Pipe In */
19464 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
19465 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
19467 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN */
19468 /* Description: PI VC0 credit overflow Pipe In */
19469 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
19470 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
19472 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN */
19473 /* Description: IILB VC0 credit overflow Pipe In */
19474 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
19475 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
19477 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN */
19478 /* Description: MD VC0 credit overflow Pipe In */
19479 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
19480 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
19482 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN */
19483 /* Description: NI0 VC0 credit overflow Pipe In */
19484 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
19485 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
19487 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN */
19488 /* Description: NI1 VC0 credit overflow Pipe In */
19489 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
19490 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
19492 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN */
19493 /* Description: PI VC2 credit overflow Pipe In */
19494 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
19495 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
19497 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN */
19498 /* Description: IILB VC2 credit overflow Pipe In */
19499 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
19500 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
19502 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN */
19503 /* Description: MD VC2 credit overflow Pipe In */
19504 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
19505 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
19507 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN */
19508 /* Description: NI0 VC2 credit overflow Pipe In */
19509 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
19510 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
19512 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN */
19513 /* Description: NI1 VC2 credit overflow Pipe In */
19514 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
19515 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
19517 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0 */
19518 /* Description: PI Fifo Debit0 overflow */
19519 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_SHFT 32
19520 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
19522 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2 */
19523 /* Description: PI Fifo Debit2 overflow */
19524 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_SHFT 33
19525 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
19527 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */
19528 /* Description: IILB Fifo Debit0 overflow */
19529 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 34
19530 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
19532 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */
19533 /* Description: IILB Fifo Debit2 overflow */
19534 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 35
19535 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
19537 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0 */
19538 /* Description: MD Fifo Debit0 overflow */
19539 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_SHFT 36
19540 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
19542 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2 */
19543 /* Description: MD Fifo Debit2 overflow */
19544 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_SHFT 37
19545 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
19547 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */
19548 /* Description: NI0 Fifo Debit0 overflow */
19549 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 38
19550 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
19552 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */
19553 /* Description: NI0 Fifo Debit2 overflow */
19554 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 39
19555 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
19557 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */
19558 /* Description: NI1 Fifo Debit0 overflow */
19559 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 40
19560 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
19562 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */
19563 /* Description: NI1 Fifo Debit2 overflow */
19564 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 41
19565 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
19567 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT */
19568 /* Description: PI VC0 Credit overflow Pipe Out */
19569 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
19570 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
19572 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT */
19573 /* Description: PI VC0 Credit overflow Pipe Out */
19574 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
19575 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
19577 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT */
19578 /* Description: MD VC0 Credit overflow Pipe Out */
19579 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
19580 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
19582 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT */
19583 /* Description: MD VC0 Credit overflow Pipe Out */
19584 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
19585 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
19587 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT */
19588 /* Description: IILB VC0 Credit overflow Pipe Out */
19589 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
19590 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
19592 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT */
19593 /* Description: IILB VC0 Credit overflow Pipe Out */
19594 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
19595 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
19597 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT */
19598 /* Description: NI0 VC0 Credit overflow Pipe Out */
19599 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
19600 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
19602 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT */
19603 /* Description: NI0 VC0 Credit overflow Pipe Out */
19604 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
19605 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
19607 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT */
19608 /* Description: NI1 VC0 Credit overflow Pipe Out */
19609 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
19610 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
19612 /* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT */
19613 /* Description: NI1 VC0 Credit overflow Pipe Out */
19614 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
19615 #define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
19617 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT */
19618 /* Description: PI VC0 Credit overflow Pipe Out */
19619 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
19620 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
19622 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT */
19623 /* Description: PI VC0 Credit overflow Pipe Out */
19624 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
19625 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
19627 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT */
19628 /* Description: MD VC0 Credit overflow Pipe Out */
19629 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
19630 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
19632 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT */
19633 /* Description: MD VC0 Credit overflow Pipe Out */
19634 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
19635 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
19637 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT */
19638 /* Description: IILB VC0 Credit overflow Pipe Out */
19639 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
19640 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
19642 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT */
19643 /* Description: IILB VC0 Credit overflow Pipe Out */
19644 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
19645 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
19647 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT */
19648 /* Description: NI0 VC0 Credit overflow Pipe Out */
19649 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
19650 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
19652 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT */
19653 /* Description: NI0 VC0 Credit overflow Pipe Out */
19654 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
19655 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
19657 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT */
19658 /* Description: NI1 VC0 Credit overflow Pipe Out */
19659 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
19660 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
19662 /* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT */
19663 /* Description: NI1 VC0 Credit overflow Pipe Out */
19664 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
19665 #define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
19667 /* SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH */
19668 /* Description: chiplet nomatch */
19669 #define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_SHFT 62
19670 #define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_MASK 0x4000000000000000
19672 /* SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR */
19673 /* Description: LUT Read Error */
19674 #define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 63
19675 #define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x8000000000000000
19677 /* ==================================================================== */
19678 /* Register "SH_XNIILB_ERRORS_ALIAS" */
19679 /* ==================================================================== */
19681 #define SH_XNIILB_ERRORS_ALIAS 0x0000000150040208
19683 /* ==================================================================== */
19684 /* Register "SH_XNIILB_ERROR_OVERFLOW" */
19685 /* ==================================================================== */
19687 #define SH_XNIILB_ERROR_OVERFLOW 0x0000000150040220
19688 #define SH_XNIILB_ERROR_OVERFLOW_MASK 0xffffffffffffffff
19689 #define SH_XNIILB_ERROR_OVERFLOW_INIT 0xffffffffffffffff
19691 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0 */
19692 /* Description: II debit0 overflow */
19693 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_SHFT 0
19694 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
19696 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2 */
19697 /* Description: II debit2 overflow */
19698 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_SHFT 1
19699 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
19701 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0 */
19702 /* Description: LB debit0 overflow */
19703 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_SHFT 2
19704 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
19706 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2 */
19707 /* Description: LB debit2 overflow */
19708 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_SHFT 3
19709 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
19711 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0 */
19712 /* Description: II VC0 fifo overflow */
19713 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_SHFT 4
19714 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_MASK 0x0000000000000010
19716 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2 */
19717 /* Description: II VC2 fifo overflow */
19718 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_SHFT 5
19719 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_MASK 0x0000000000000020
19721 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0 */
19722 /* Description: II VC0 fifo underflow */
19723 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_SHFT 6
19724 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_MASK 0x0000000000000040
19726 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2 */
19727 /* Description: II VC2 fifo underflow */
19728 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_SHFT 7
19729 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_MASK 0x0000000000000080
19731 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0 */
19732 /* Description: LB VC0 fifo overflow */
19733 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_SHFT 8
19734 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_MASK 0x0000000000000100
19736 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2 */
19737 /* Description: LB VC2 fifo overflow */
19738 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_SHFT 9
19739 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_MASK 0x0000000000000200
19741 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0 */
19742 /* Description: LB VC0 fifo underflow */
19743 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_SHFT 10
19744 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
19746 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2 */
19747 /* Description: LB VC2 fifo underflow */
19748 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_SHFT 11
19749 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
19751 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN */
19752 /* Description: PI VC0 credit overflow Pipe In */
19753 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
19754 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
19756 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN */
19757 /* Description: IILB VC0 credit overflow Pipe In */
19758 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
19759 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
19761 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN */
19762 /* Description: MD VC0 credit overflow Pipe In */
19763 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
19764 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
19766 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN */
19767 /* Description: NI0 VC0 credit overflow Pipe In */
19768 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
19769 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
19771 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN */
19772 /* Description: NI1 VC0 credit overflow Pipe In */
19773 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
19774 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
19776 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN */
19777 /* Description: PI VC2 credit overflow Pipe In */
19778 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
19779 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
19781 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN */
19782 /* Description: IILB VC2 credit overflow Pipe In */
19783 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
19784 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
19786 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN */
19787 /* Description: MD VC2 credit overflow Pipe In */
19788 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
19789 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
19791 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN */
19792 /* Description: NI0 VC2 credit overflow Pipe In */
19793 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
19794 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
19796 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN */
19797 /* Description: NI1 VC2 credit overflow Pipe In */
19798 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
19799 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
19801 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN */
19802 /* Description: PI VC0 credit overflow Pipe In */
19803 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
19804 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
19806 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN */
19807 /* Description: IILB VC0 credit overflow Pipe In */
19808 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
19809 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
19811 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN */
19812 /* Description: MD VC0 credit overflow Pipe In */
19813 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
19814 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
19816 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN */
19817 /* Description: NI0 VC0 credit overflow Pipe In */
19818 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
19819 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
19821 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN */
19822 /* Description: NI1 VC0 credit overflow Pipe In */
19823 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
19824 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
19826 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN */
19827 /* Description: PI VC2 credit overflow Pipe In */
19828 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
19829 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
19831 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN */
19832 /* Description: IILB VC2 credit overflow Pipe In */
19833 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
19834 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
19836 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN */
19837 /* Description: MD VC2 credit overflow Pipe In */
19838 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
19839 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
19841 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN */
19842 /* Description: NI0 VC2 credit overflow Pipe In */
19843 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
19844 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
19846 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN */
19847 /* Description: NI1 VC2 credit overflow Pipe In */
19848 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
19849 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
19851 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0 */
19852 /* Description: PI Fifo Debit0 overflow */
19853 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_SHFT 32
19854 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
19856 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2 */
19857 /* Description: PI Fifo Debit2 overflow */
19858 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_SHFT 33
19859 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
19861 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */
19862 /* Description: IILB Fifo Debit0 overflow */
19863 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 34
19864 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
19866 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */
19867 /* Description: IILB Fifo Debit2 overflow */
19868 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 35
19869 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
19871 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0 */
19872 /* Description: MD Fifo Debit0 overflow */
19873 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_SHFT 36
19874 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
19876 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2 */
19877 /* Description: MD Fifo Debit2 overflow */
19878 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_SHFT 37
19879 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
19881 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */
19882 /* Description: NI0 Fifo Debit0 overflow */
19883 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 38
19884 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
19886 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */
19887 /* Description: NI0 Fifo Debit2 overflow */
19888 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 39
19889 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
19891 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */
19892 /* Description: NI1 Fifo Debit0 overflow */
19893 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 40
19894 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
19896 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */
19897 /* Description: NI1 Fifo Debit2 overflow */
19898 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 41
19899 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
19901 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT */
19902 /* Description: PI VC0 Credit overflow Pipe Out */
19903 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
19904 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
19906 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT */
19907 /* Description: PI VC0 Credit overflow Pipe Out */
19908 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
19909 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
19911 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT */
19912 /* Description: MD VC0 Credit overflow Pipe Out */
19913 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
19914 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
19916 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT */
19917 /* Description: MD VC0 Credit overflow Pipe Out */
19918 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
19919 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
19921 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT */
19922 /* Description: IILB VC0 Credit overflow Pipe Out */
19923 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
19924 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
19926 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT */
19927 /* Description: IILB VC0 Credit overflow Pipe Out */
19928 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
19929 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
19931 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT */
19932 /* Description: NI0 VC0 Credit overflow Pipe Out */
19933 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
19934 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
19936 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT */
19937 /* Description: NI0 VC0 Credit overflow Pipe Out */
19938 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
19939 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
19941 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT */
19942 /* Description: NI1 VC0 Credit overflow Pipe Out */
19943 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
19944 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
19946 /* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT */
19947 /* Description: NI1 VC0 Credit overflow Pipe Out */
19948 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
19949 #define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
19951 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT */
19952 /* Description: PI VC0 Credit overflow Pipe Out */
19953 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
19954 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
19956 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT */
19957 /* Description: PI VC0 Credit overflow Pipe Out */
19958 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
19959 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
19961 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT */
19962 /* Description: MD VC0 Credit overflow Pipe Out */
19963 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
19964 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
19966 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT */
19967 /* Description: MD VC0 Credit overflow Pipe Out */
19968 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
19969 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
19971 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT */
19972 /* Description: IILB VC0 Credit overflow Pipe Out */
19973 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
19974 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
19976 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT */
19977 /* Description: IILB VC0 Credit overflow Pipe Out */
19978 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
19979 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
19981 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT */
19982 /* Description: NI0 VC0 Credit overflow Pipe Out */
19983 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
19984 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
19986 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT */
19987 /* Description: NI0 VC0 Credit overflow Pipe Out */
19988 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
19989 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
19991 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT */
19992 /* Description: NI1 VC0 Credit overflow Pipe Out */
19993 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
19994 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
19996 /* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT */
19997 /* Description: NI1 VC0 Credit overflow Pipe Out */
19998 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
19999 #define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
20001 /* SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH */
20002 /* Description: chiplet nomatch */
20003 #define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_SHFT 62
20004 #define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_MASK 0x4000000000000000
20006 /* SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR */
20007 /* Description: LUT Read Error */
20008 #define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 63
20009 #define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x8000000000000000
20011 /* ==================================================================== */
20012 /* Register "SH_XNIILB_ERROR_OVERFLOW_ALIAS" */
20013 /* ==================================================================== */
20015 #define SH_XNIILB_ERROR_OVERFLOW_ALIAS 0x0000000150040228
20017 /* ==================================================================== */
20018 /* Register "SH_XNIILB_ERROR_MASK" */
20019 /* ==================================================================== */
20021 #define SH_XNIILB_ERROR_MASK 0x0000000150040240
20022 #define SH_XNIILB_ERROR_MASK_MASK 0xffffffffffffffff
20023 #define SH_XNIILB_ERROR_MASK_INIT 0xffffffffffffffff
20025 /* SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0 */
20026 /* Description: II debit0 overflow */
20027 #define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_SHFT 0
20028 #define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
20030 /* SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2 */
20031 /* Description: II debit2 overflow */
20032 #define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_SHFT 1
20033 #define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
20035 /* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0 */
20036 /* Description: LB debit0 overflow */
20037 #define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_SHFT 2
20038 #define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
20040 /* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2 */
20041 /* Description: LB debit2 overflow */
20042 #define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_SHFT 3
20043 #define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
20045 /* SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0 */
20046 /* Description: II VC0 fifo overflow */
20047 #define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_SHFT 4
20048 #define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_MASK 0x0000000000000010
20050 /* SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2 */
20051 /* Description: II VC2 fifo overflow */
20052 #define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_SHFT 5
20053 #define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_MASK 0x0000000000000020
20055 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0 */
20056 /* Description: II VC0 fifo underflow */
20057 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_SHFT 6
20058 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_MASK 0x0000000000000040
20060 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2 */
20061 /* Description: II VC2 fifo underflow */
20062 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_SHFT 7
20063 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_MASK 0x0000000000000080
20065 /* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0 */
20066 /* Description: LB VC0 fifo overflow */
20067 #define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_SHFT 8
20068 #define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_MASK 0x0000000000000100
20070 /* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2 */
20071 /* Description: LB VC2 fifo overflow */
20072 #define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_SHFT 9
20073 #define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_MASK 0x0000000000000200
20075 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0 */
20076 /* Description: LB VC0 fifo underflow */
20077 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_SHFT 10
20078 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
20080 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2 */
20081 /* Description: LB VC2 fifo underflow */
20082 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_SHFT 11
20083 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
20085 /* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN */
20086 /* Description: PI VC0 credit overflow Pipe In */
20087 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
20088 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
20090 /* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN */
20091 /* Description: IILB VC0 credit overflow Pipe In */
20092 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
20093 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
20095 /* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN */
20096 /* Description: MD VC0 credit overflow Pipe In */
20097 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
20098 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
20100 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN */
20101 /* Description: NI0 VC0 credit overflow Pipe In */
20102 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
20103 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
20105 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN */
20106 /* Description: NI1 VC0 credit overflow Pipe In */
20107 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
20108 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
20110 /* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN */
20111 /* Description: PI VC2 credit overflow Pipe In */
20112 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
20113 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
20115 /* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN */
20116 /* Description: IILB VC2 credit overflow Pipe In */
20117 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
20118 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
20120 /* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN */
20121 /* Description: MD VC2 credit overflow Pipe In */
20122 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
20123 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
20125 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN */
20126 /* Description: NI0 VC2 credit overflow Pipe In */
20127 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
20128 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
20130 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN */
20131 /* Description: NI1 VC2 credit overflow Pipe In */
20132 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
20133 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
20135 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN */
20136 /* Description: PI VC0 credit overflow Pipe In */
20137 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
20138 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
20140 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN */
20141 /* Description: IILB VC0 credit overflow Pipe In */
20142 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
20143 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
20145 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN */
20146 /* Description: MD VC0 credit overflow Pipe In */
20147 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
20148 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
20150 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN */
20151 /* Description: NI0 VC0 credit overflow Pipe In */
20152 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
20153 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
20155 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN */
20156 /* Description: NI1 VC0 credit overflow Pipe In */
20157 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
20158 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
20160 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN */
20161 /* Description: PI VC2 credit overflow Pipe In */
20162 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
20163 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
20165 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN */
20166 /* Description: IILB VC2 credit overflow Pipe In */
20167 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
20168 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
20170 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN */
20171 /* Description: MD VC2 credit overflow Pipe In */
20172 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
20173 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
20175 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN */
20176 /* Description: NI0 VC2 credit overflow Pipe In */
20177 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
20178 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
20180 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN */
20181 /* Description: NI1 VC2 credit overflow Pipe In */
20182 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
20183 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
20185 /* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0 */
20186 /* Description: PI Fifo Debit0 overflow */
20187 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_SHFT 32
20188 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
20190 /* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2 */
20191 /* Description: PI Fifo Debit2 overflow */
20192 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_SHFT 33
20193 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
20195 /* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */
20196 /* Description: IILB Fifo Debit0 overflow */
20197 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 34
20198 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
20200 /* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */
20201 /* Description: IILB Fifo Debit2 overflow */
20202 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 35
20203 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
20205 /* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0 */
20206 /* Description: MD Fifo Debit0 overflow */
20207 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_SHFT 36
20208 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
20210 /* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2 */
20211 /* Description: MD Fifo Debit2 overflow */
20212 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_SHFT 37
20213 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
20215 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */
20216 /* Description: NI0 Fifo Debit0 overflow */
20217 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 38
20218 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
20220 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */
20221 /* Description: NI0 Fifo Debit2 overflow */
20222 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 39
20223 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
20225 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */
20226 /* Description: NI1 Fifo Debit0 overflow */
20227 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 40
20228 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
20230 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */
20231 /* Description: NI1 Fifo Debit2 overflow */
20232 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 41
20233 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
20235 /* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT */
20236 /* Description: PI VC0 Credit overflow Pipe Out */
20237 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
20238 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
20240 /* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT */
20241 /* Description: PI VC0 Credit overflow Pipe Out */
20242 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
20243 #define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
20245 /* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT */
20246 /* Description: MD VC0 Credit overflow Pipe Out */
20247 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
20248 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
20250 /* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT */
20251 /* Description: MD VC0 Credit overflow Pipe Out */
20252 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
20253 #define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
20255 /* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT */
20256 /* Description: IILB VC0 Credit overflow Pipe Out */
20257 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
20258 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
20260 /* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT */
20261 /* Description: IILB VC0 Credit overflow Pipe Out */
20262 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
20263 #define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
20265 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT */
20266 /* Description: NI0 VC0 Credit overflow Pipe Out */
20267 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
20268 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
20270 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT */
20271 /* Description: NI0 VC0 Credit overflow Pipe Out */
20272 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
20273 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
20275 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT */
20276 /* Description: NI1 VC0 Credit overflow Pipe Out */
20277 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
20278 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
20280 /* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT */
20281 /* Description: NI1 VC0 Credit overflow Pipe Out */
20282 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
20283 #define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
20285 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT */
20286 /* Description: PI VC0 Credit overflow Pipe Out */
20287 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
20288 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
20290 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT */
20291 /* Description: PI VC0 Credit overflow Pipe Out */
20292 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
20293 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
20295 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT */
20296 /* Description: MD VC0 Credit overflow Pipe Out */
20297 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
20298 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
20300 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT */
20301 /* Description: MD VC0 Credit overflow Pipe Out */
20302 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
20303 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
20305 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT */
20306 /* Description: IILB VC0 Credit overflow Pipe Out */
20307 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
20308 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
20310 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT */
20311 /* Description: IILB VC0 Credit overflow Pipe Out */
20312 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
20313 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
20315 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT */
20316 /* Description: NI0 VC0 Credit overflow Pipe Out */
20317 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
20318 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
20320 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT */
20321 /* Description: NI0 VC0 Credit overflow Pipe Out */
20322 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
20323 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
20325 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT */
20326 /* Description: NI1 VC0 Credit overflow Pipe Out */
20327 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
20328 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
20330 /* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT */
20331 /* Description: NI1 VC0 Credit overflow Pipe Out */
20332 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
20333 #define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
20335 /* SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH */
20336 /* Description: chiplet nomatch */
20337 #define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_SHFT 62
20338 #define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_MASK 0x4000000000000000
20340 /* SH_XNIILB_ERROR_MASK_LUT_READ_ERROR */
20341 /* Description: LUT Read Error */
20342 #define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_SHFT 63
20343 #define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_MASK 0x8000000000000000
20345 /* ==================================================================== */
20346 /* Register "SH_XNIILB_FIRST_ERROR" */
20347 /* ==================================================================== */
20349 #define SH_XNIILB_FIRST_ERROR 0x0000000150040260
20350 #define SH_XNIILB_FIRST_ERROR_MASK 0xffffffffffffffff
20351 #define SH_XNIILB_FIRST_ERROR_INIT 0xffffffffffffffff
20353 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0 */
20354 /* Description: II debit0 overflow */
20355 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_SHFT 0
20356 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
20358 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2 */
20359 /* Description: II debit2 overflow */
20360 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_SHFT 1
20361 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
20363 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0 */
20364 /* Description: LB debit0 overflow */
20365 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_SHFT 2
20366 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
20368 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2 */
20369 /* Description: LB debit2 overflow */
20370 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_SHFT 3
20371 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
20373 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0 */
20374 /* Description: II VC0 fifo overflow */
20375 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_SHFT 4
20376 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_MASK 0x0000000000000010
20378 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2 */
20379 /* Description: II VC2 fifo overflow */
20380 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_SHFT 5
20381 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_MASK 0x0000000000000020
20383 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0 */
20384 /* Description: II VC0 fifo underflow */
20385 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_SHFT 6
20386 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_MASK 0x0000000000000040
20388 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2 */
20389 /* Description: II VC2 fifo underflow */
20390 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_SHFT 7
20391 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_MASK 0x0000000000000080
20393 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0 */
20394 /* Description: LB VC0 fifo overflow */
20395 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_SHFT 8
20396 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_MASK 0x0000000000000100
20398 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2 */
20399 /* Description: LB VC2 fifo overflow */
20400 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_SHFT 9
20401 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_MASK 0x0000000000000200
20403 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0 */
20404 /* Description: LB VC0 fifo underflow */
20405 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_SHFT 10
20406 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
20408 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2 */
20409 /* Description: LB VC2 fifo underflow */
20410 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_SHFT 11
20411 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
20413 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN */
20414 /* Description: PI VC0 credit overflow Pipe In */
20415 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
20416 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
20418 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN */
20419 /* Description: IILB VC0 credit overflow Pipe In */
20420 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
20421 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
20423 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN */
20424 /* Description: MD VC0 credit overflow Pipe In */
20425 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
20426 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
20428 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN */
20429 /* Description: NI0 VC0 credit overflow Pipe In */
20430 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
20431 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
20433 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN */
20434 /* Description: NI1 VC0 credit overflow Pipe In */
20435 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
20436 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
20438 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN */
20439 /* Description: PI VC2 credit overflow Pipe In */
20440 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
20441 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
20443 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN */
20444 /* Description: IILB VC2 credit overflow Pipe In */
20445 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
20446 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
20448 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN */
20449 /* Description: MD VC2 credit overflow Pipe In */
20450 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
20451 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
20453 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN */
20454 /* Description: NI0 VC2 credit overflow Pipe In */
20455 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
20456 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
20458 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN */
20459 /* Description: NI1 VC2 credit overflow Pipe In */
20460 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
20461 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
20463 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN */
20464 /* Description: PI VC0 credit overflow Pipe In */
20465 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
20466 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
20468 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN */
20469 /* Description: IILB VC0 credit overflow Pipe In */
20470 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
20471 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
20473 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN */
20474 /* Description: MD VC0 credit overflow Pipe In */
20475 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
20476 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
20478 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN */
20479 /* Description: NI0 VC0 credit overflow Pipe In */
20480 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
20481 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
20483 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN */
20484 /* Description: NI1 VC0 credit overflow Pipe In */
20485 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
20486 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
20488 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN */
20489 /* Description: PI VC2 credit overflow Pipe In */
20490 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
20491 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
20493 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN */
20494 /* Description: IILB VC2 credit overflow Pipe In */
20495 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
20496 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
20498 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN */
20499 /* Description: MD VC2 credit overflow Pipe In */
20500 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
20501 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
20503 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN */
20504 /* Description: NI0 VC2 credit overflow Pipe In */
20505 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
20506 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
20508 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN */
20509 /* Description: NI1 VC2 credit overflow Pipe In */
20510 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
20511 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
20513 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0 */
20514 /* Description: PI Fifo Debit0 overflow */
20515 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_SHFT 32
20516 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
20518 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2 */
20519 /* Description: PI Fifo Debit2 overflow */
20520 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_SHFT 33
20521 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
20523 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */
20524 /* Description: IILB Fifo Debit0 overflow */
20525 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 34
20526 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
20528 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */
20529 /* Description: IILB Fifo Debit2 overflow */
20530 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 35
20531 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
20533 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0 */
20534 /* Description: MD Fifo Debit0 overflow */
20535 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_SHFT 36
20536 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
20538 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2 */
20539 /* Description: MD Fifo Debit2 overflow */
20540 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_SHFT 37
20541 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
20543 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */
20544 /* Description: NI0 Fifo Debit0 overflow */
20545 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 38
20546 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
20548 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */
20549 /* Description: NI0 Fifo Debit2 overflow */
20550 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 39
20551 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
20553 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */
20554 /* Description: NI1 Fifo Debit0 overflow */
20555 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 40
20556 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
20558 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */
20559 /* Description: NI1 Fifo Debit2 overflow */
20560 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 41
20561 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
20563 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT */
20564 /* Description: PI VC0 Credit overflow Pipe Out */
20565 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
20566 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
20568 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT */
20569 /* Description: PI VC0 Credit overflow Pipe Out */
20570 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
20571 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
20573 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT */
20574 /* Description: MD VC0 Credit overflow Pipe Out */
20575 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
20576 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
20578 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT */
20579 /* Description: MD VC0 Credit overflow Pipe Out */
20580 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
20581 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
20583 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT */
20584 /* Description: IILB VC0 Credit overflow Pipe Out */
20585 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
20586 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
20588 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT */
20589 /* Description: IILB VC0 Credit overflow Pipe Out */
20590 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
20591 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
20593 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT */
20594 /* Description: NI0 VC0 Credit overflow Pipe Out */
20595 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
20596 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
20598 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT */
20599 /* Description: NI0 VC0 Credit overflow Pipe Out */
20600 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
20601 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
20603 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT */
20604 /* Description: NI1 VC0 Credit overflow Pipe Out */
20605 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
20606 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
20608 /* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT */
20609 /* Description: NI1 VC0 Credit overflow Pipe Out */
20610 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
20611 #define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
20613 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT */
20614 /* Description: PI VC0 Credit overflow Pipe Out */
20615 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
20616 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
20618 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT */
20619 /* Description: PI VC0 Credit overflow Pipe Out */
20620 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
20621 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
20623 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT */
20624 /* Description: MD VC0 Credit overflow Pipe Out */
20625 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
20626 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
20628 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT */
20629 /* Description: MD VC0 Credit overflow Pipe Out */
20630 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
20631 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
20633 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT */
20634 /* Description: IILB VC0 Credit overflow Pipe Out */
20635 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
20636 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
20638 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT */
20639 /* Description: IILB VC0 Credit overflow Pipe Out */
20640 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
20641 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
20643 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT */
20644 /* Description: NI0 VC0 Credit overflow Pipe Out */
20645 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
20646 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
20648 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT */
20649 /* Description: NI0 VC0 Credit overflow Pipe Out */
20650 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
20651 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
20653 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT */
20654 /* Description: NI1 VC0 Credit overflow Pipe Out */
20655 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
20656 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
20658 /* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT */
20659 /* Description: NI1 VC0 Credit overflow Pipe Out */
20660 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
20661 #define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
20663 /* SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH */
20664 /* Description: chiplet nomatch */
20665 #define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_SHFT 62
20666 #define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_MASK 0x4000000000000000
20668 /* SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR */
20669 /* Description: LUT Read Error */
20670 #define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_SHFT 63
20671 #define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_MASK 0x8000000000000000
20673 /* ==================================================================== */
20674 /* Register "SH_XNPI_ERROR_SUMMARY" */
20675 /* ==================================================================== */
20677 #define SH_XNPI_ERROR_SUMMARY 0x0000000150040300
20678 #define SH_XNPI_ERROR_SUMMARY_MASK 0x0003ffffffffffff
20679 #define SH_XNPI_ERROR_SUMMARY_INIT 0x0003ffffffffffff
20681 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0 */
20682 /* Description: NI0 VC0 fifo underflow */
20683 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0
20684 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
20686 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0 */
20687 /* Description: NI0 VC0 fifo overflow */
20688 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1
20689 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
20691 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2 */
20692 /* Description: NI0 VC2 fifo underflow */
20693 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2
20694 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
20696 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2 */
20697 /* Description: NI0 VC2 fifo overflow */
20698 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3
20699 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
20701 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0 */
20702 /* Description: NI1 VC0 fifo underflow */
20703 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4
20704 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
20706 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0 */
20707 /* Description: NI1 VC0 fifo overflow */
20708 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5
20709 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
20711 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2 */
20712 /* Description: NI1 VC2 fifo underflow */
20713 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6
20714 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
20716 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2 */
20717 /* Description: NI1 VC2 fifo overflow */
20718 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7
20719 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
20721 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0 */
20722 /* Description: IILB VC0 fifo underflow */
20723 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8
20724 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
20726 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0 */
20727 /* Description: IILB VC0 fifo overflow */
20728 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9
20729 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
20731 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2 */
20732 /* Description: IILB VC2 fifo underflow */
20733 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10
20734 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
20736 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2 */
20737 /* Description: IILB VC2 fifo overflow */
20738 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11
20739 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
20741 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT */
20742 /* Description: VC0 Credit underflow */
20743 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12
20744 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
20746 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT */
20747 /* Description: VC0 Credit overflow */
20748 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13
20749 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
20751 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT */
20752 /* Description: VC2 Credit underflow */
20753 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14
20754 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
20756 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT */
20757 /* Description: VC2 Credit overflow */
20758 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15
20759 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
20761 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0 */
20762 /* Description: VC0 Data Buffer overflow */
20763 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16
20764 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
20766 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2 */
20767 /* Description: VC2 Data Buffer overflow */
20768 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17
20769 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
20771 /* SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR */
20772 /* Description: LUT Read Error */
20773 #define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18
20774 #define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000
20776 /* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0 */
20777 /* Description: Single Bit Error in Bits 63:0 */
20778 #define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19
20779 #define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
20781 /* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1 */
20782 /* Description: Single Bit Error in Bits 127:64 */
20783 #define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20
20784 #define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
20786 /* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2 */
20787 /* Description: Single Bit Error in Bits 191:128 */
20788 #define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21
20789 #define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
20791 /* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3 */
20792 /* Description: Single Bit Error in Bits 255:192 */
20793 #define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22
20794 #define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
20796 /* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0 */
20797 /* Description: Uncorrectable Error in Bits 63:0 */
20798 #define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_SHFT 23
20799 #define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_MASK 0x0000000000800000
20801 /* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1 */
20802 /* Description: Uncorrectable Error in Bits 127:64 */
20803 #define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_SHFT 24
20804 #define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_MASK 0x0000000001000000
20806 /* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2 */
20807 /* Description: Uncorrectable Error in Bits 191:128 */
20808 #define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_SHFT 25
20809 #define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_MASK 0x0000000002000000
20811 /* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3 */
20812 /* Description: Uncorrectable Error in Bits 255:192 */
20813 #define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_SHFT 26
20814 #define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_MASK 0x0000000004000000
20816 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0 */
20817 /* Description: SIC Counter 0 Underflow */
20818 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27
20819 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
20821 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0 */
20822 /* Description: SIC Counter 0 Overflow */
20823 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28
20824 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
20826 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2 */
20827 /* Description: SIC Counter 2 Underflow */
20828 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29
20829 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
20831 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2 */
20832 /* Description: SIC Counter 2 Overflow */
20833 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30
20834 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
20836 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */
20837 /* Description: NI0 Debit 0 Overflow */
20838 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31
20839 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
20841 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */
20842 /* Description: NI0 Debit 2 Overflow */
20843 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32
20844 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
20846 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */
20847 /* Description: NI1 Debit 0 Overflow */
20848 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33
20849 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
20851 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */
20852 /* Description: NI1 Debit 2 Overflow */
20853 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34
20854 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
20856 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */
20857 /* Description: IILB Debit 0 Overflow */
20858 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35
20859 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
20861 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */
20862 /* Description: IILB Debit 2 Overflow */
20863 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36
20864 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
20866 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT */
20867 /* Description: NI0 VC0 Credit Underflow */
20868 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
20869 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
20871 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT */
20872 /* Description: NI0 VC0 Credit Overflow */
20873 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
20874 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
20876 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT */
20877 /* Description: NI0 VC2 Credit Underflow */
20878 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
20879 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
20881 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT */
20882 /* Description: NI0 VC2 Credit Overflow */
20883 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
20884 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
20886 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT */
20887 /* Description: NI1 VC0 Credit Underflow */
20888 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
20889 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
20891 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT */
20892 /* Description: NI1 VC0 Credit Overflow */
20893 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
20894 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
20896 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT */
20897 /* Description: NI1 VC2 Credit Underflow */
20898 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
20899 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
20901 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT */
20902 /* Description: NI1 VC2 Credit Overflow */
20903 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
20904 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
20906 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT */
20907 /* Description: IILB VC0 Credit Underflow */
20908 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
20909 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
20911 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT */
20912 /* Description: IILB VC0 Credit Overflow */
20913 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
20914 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
20916 /* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT */
20917 /* Description: IILB VC2 Credit Underflow */
20918 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
20919 #define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
20921 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT */
20922 /* Description: IILB VC2 Credit Overflow */
20923 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
20924 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
20926 /* SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO */
20927 /* Description: Header Cancel Fifo Overflow */
20928 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
20929 #define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
20931 /* ==================================================================== */
20932 /* Register "SH_XNPI_ERRORS_ALIAS" */
20933 /* ==================================================================== */
20935 #define SH_XNPI_ERRORS_ALIAS 0x0000000150040308
20937 /* ==================================================================== */
20938 /* Register "SH_XNPI_ERROR_OVERFLOW" */
20939 /* ==================================================================== */
20941 #define SH_XNPI_ERROR_OVERFLOW 0x0000000150040320
20942 #define SH_XNPI_ERROR_OVERFLOW_MASK 0x0003ffffffffffff
20943 #define SH_XNPI_ERROR_OVERFLOW_INIT 0x0003ffffffffffff
20945 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0 */
20946 /* Description: NI0 VC0 fifo underflow */
20947 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0
20948 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
20950 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0 */
20951 /* Description: NI0 VC0 fifo overflow */
20952 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1
20953 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
20955 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2 */
20956 /* Description: NI0 VC2 fifo underflow */
20957 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2
20958 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
20960 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2 */
20961 /* Description: NI0 VC2 fifo overflow */
20962 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3
20963 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
20965 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0 */
20966 /* Description: NI1 VC0 fifo underflow */
20967 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4
20968 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
20970 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0 */
20971 /* Description: NI1 VC0 fifo overflow */
20972 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5
20973 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
20975 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2 */
20976 /* Description: NI1 VC2 fifo underflow */
20977 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6
20978 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
20980 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2 */
20981 /* Description: NI1 VC2 fifo overflow */
20982 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7
20983 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
20985 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0 */
20986 /* Description: IILB VC0 fifo underflow */
20987 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8
20988 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
20990 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0 */
20991 /* Description: IILB VC0 fifo overflow */
20992 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9
20993 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
20995 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2 */
20996 /* Description: IILB VC2 fifo underflow */
20997 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10
20998 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
21000 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2 */
21001 /* Description: IILB VC2 fifo overflow */
21002 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11
21003 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
21005 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT */
21006 /* Description: VC0 Credit underflow */
21007 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12
21008 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
21010 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT */
21011 /* Description: VC0 Credit overflow */
21012 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13
21013 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
21015 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT */
21016 /* Description: VC2 Credit underflow */
21017 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14
21018 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
21020 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT */
21021 /* Description: VC2 Credit overflow */
21022 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15
21023 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
21025 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0 */
21026 /* Description: VC0 Data Buffer overflow */
21027 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16
21028 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
21030 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2 */
21031 /* Description: VC2 Data Buffer overflow */
21032 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17
21033 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
21035 /* SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR */
21036 /* Description: LUT Read Error */
21037 #define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18
21038 #define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000
21040 /* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0 */
21041 /* Description: Single Bit Error in Bits 63:0 */
21042 #define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19
21043 #define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
21045 /* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1 */
21046 /* Description: Single Bit Error in Bits 127:64 */
21047 #define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20
21048 #define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
21050 /* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2 */
21051 /* Description: Single Bit Error in Bits 191:128 */
21052 #define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21
21053 #define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
21055 /* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3 */
21056 /* Description: Single Bit Error in Bits 255:192 */
21057 #define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22
21058 #define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
21060 /* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0 */
21061 /* Description: Uncorrectable Error in Bits 63:0 */
21062 #define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23
21063 #define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000
21065 /* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1 */
21066 /* Description: Uncorrectable Error in Bits 127:64 */
21067 #define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24
21068 #define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000
21070 /* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2 */
21071 /* Description: Uncorrectable Error in Bits 191:128 */
21072 #define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25
21073 #define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000
21075 /* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3 */
21076 /* Description: Uncorrectable Error in Bits 255:192 */
21077 #define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26
21078 #define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000
21080 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0 */
21081 /* Description: SIC Counter 0 Underflow */
21082 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27
21083 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
21085 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0 */
21086 /* Description: SIC Counter 0 Overflow */
21087 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28
21088 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
21090 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2 */
21091 /* Description: SIC Counter 2 Underflow */
21092 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29
21093 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
21095 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2 */
21096 /* Description: SIC Counter 2 Overflow */
21097 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30
21098 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
21100 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */
21101 /* Description: NI0 Debit 0 Overflow */
21102 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31
21103 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
21105 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */
21106 /* Description: NI0 Debit 2 Overflow */
21107 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32
21108 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
21110 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */
21111 /* Description: NI1 Debit 0 Overflow */
21112 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33
21113 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
21115 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */
21116 /* Description: NI1 Debit 2 Overflow */
21117 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34
21118 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
21120 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */
21121 /* Description: IILB Debit 0 Overflow */
21122 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35
21123 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
21125 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */
21126 /* Description: IILB Debit 2 Overflow */
21127 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36
21128 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
21130 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT */
21131 /* Description: NI0 VC0 Credit Underflow */
21132 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
21133 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
21135 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT */
21136 /* Description: NI0 VC0 Credit Overflow */
21137 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
21138 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
21140 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT */
21141 /* Description: NI0 VC2 Credit Underflow */
21142 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
21143 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
21145 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT */
21146 /* Description: NI0 VC2 Credit Overflow */
21147 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
21148 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
21150 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT */
21151 /* Description: NI1 VC0 Credit Underflow */
21152 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
21153 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
21155 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT */
21156 /* Description: NI1 VC0 Credit Overflow */
21157 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
21158 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
21160 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT */
21161 /* Description: NI1 VC2 Credit Underflow */
21162 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
21163 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
21165 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT */
21166 /* Description: NI1 VC2 Credit Overflow */
21167 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
21168 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
21170 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT */
21171 /* Description: IILB VC0 Credit Underflow */
21172 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
21173 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
21175 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT */
21176 /* Description: IILB VC0 Credit Overflow */
21177 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
21178 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
21180 /* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT */
21181 /* Description: IILB VC2 Credit Underflow */
21182 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
21183 #define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
21185 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT */
21186 /* Description: IILB VC2 Credit Overflow */
21187 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
21188 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
21190 /* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO */
21191 /* Description: Header Cancel Fifo Overflow */
21192 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
21193 #define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
21195 /* ==================================================================== */
21196 /* Register "SH_XNPI_ERROR_OVERFLOW_ALIAS" */
21197 /* ==================================================================== */
21199 #define SH_XNPI_ERROR_OVERFLOW_ALIAS 0x0000000150040328
21201 /* ==================================================================== */
21202 /* Register "SH_XNPI_ERROR_MASK" */
21203 /* ==================================================================== */
21205 #define SH_XNPI_ERROR_MASK 0x0000000150040340
21206 #define SH_XNPI_ERROR_MASK_MASK 0x0003ffffffffffff
21207 #define SH_XNPI_ERROR_MASK_INIT 0x0003ffffffffffff
21209 /* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0 */
21210 /* Description: NI0 VC0 fifo underflow */
21211 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0
21212 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
21214 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0 */
21215 /* Description: NI0 VC0 fifo overflow */
21216 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1
21217 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
21219 /* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2 */
21220 /* Description: NI0 VC2 fifo underflow */
21221 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2
21222 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
21224 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2 */
21225 /* Description: NI0 VC2 fifo overflow */
21226 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3
21227 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
21229 /* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0 */
21230 /* Description: NI1 VC0 fifo underflow */
21231 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4
21232 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
21234 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0 */
21235 /* Description: NI1 VC0 fifo overflow */
21236 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5
21237 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
21239 /* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2 */
21240 /* Description: NI1 VC2 fifo underflow */
21241 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6
21242 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
21244 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2 */
21245 /* Description: NI1 VC2 fifo overflow */
21246 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7
21247 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
21249 /* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0 */
21250 /* Description: IILB VC0 fifo underflow */
21251 #define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8
21252 #define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
21254 /* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0 */
21255 /* Description: IILB VC0 fifo overflow */
21256 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9
21257 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
21259 /* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2 */
21260 /* Description: IILB VC2 fifo underflow */
21261 #define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10
21262 #define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
21264 /* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2 */
21265 /* Description: IILB VC2 fifo overflow */
21266 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11
21267 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
21269 /* SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT */
21270 /* Description: VC0 Credit underflow */
21271 #define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12
21272 #define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
21274 /* SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT */
21275 /* Description: VC0 Credit overflow */
21276 #define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13
21277 #define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
21279 /* SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT */
21280 /* Description: VC2 Credit underflow */
21281 #define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14
21282 #define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
21284 /* SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT */
21285 /* Description: VC2 Credit overflow */
21286 #define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15
21287 #define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
21289 /* SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0 */
21290 /* Description: VC0 Data Buffer overflow */
21291 #define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16
21292 #define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
21294 /* SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2 */
21295 /* Description: VC2 Data Buffer overflow */
21296 #define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17
21297 #define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
21299 /* SH_XNPI_ERROR_MASK_LUT_READ_ERROR */
21300 /* Description: LUT Read Error */
21301 #define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_SHFT 18
21302 #define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_MASK 0x0000000000040000
21304 /* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0 */
21305 /* Description: Single Bit Error in Bits 63:0 */
21306 #define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19
21307 #define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
21309 /* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1 */
21310 /* Description: Single Bit Error in Bits 127:64 */
21311 #define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20
21312 #define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
21314 /* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2 */
21315 /* Description: Single Bit Error in Bits 191:128 */
21316 #define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21
21317 #define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
21319 /* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3 */
21320 /* Description: Single Bit Error in Bits 255:192 */
21321 #define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22
21322 #define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
21324 /* SH_XNPI_ERROR_MASK_UNCOR_ERROR0 */
21325 /* Description: Uncorrectable Error in Bits 63:0 */
21326 #define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_SHFT 23
21327 #define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_MASK 0x0000000000800000
21329 /* SH_XNPI_ERROR_MASK_UNCOR_ERROR1 */
21330 /* Description: Uncorrectable Error in Bits 127:64 */
21331 #define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_SHFT 24
21332 #define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_MASK 0x0000000001000000
21334 /* SH_XNPI_ERROR_MASK_UNCOR_ERROR2 */
21335 /* Description: Uncorrectable Error in Bits 191:128 */
21336 #define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_SHFT 25
21337 #define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_MASK 0x0000000002000000
21339 /* SH_XNPI_ERROR_MASK_UNCOR_ERROR3 */
21340 /* Description: Uncorrectable Error in Bits 255:192 */
21341 #define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_SHFT 26
21342 #define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_MASK 0x0000000004000000
21344 /* SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0 */
21345 /* Description: SIC Counter 0 Underflow */
21346 #define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27
21347 #define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
21349 /* SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0 */
21350 /* Description: SIC Counter 0 Overflow */
21351 #define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28
21352 #define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
21354 /* SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2 */
21355 /* Description: SIC Counter 2 Underflow */
21356 #define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29
21357 #define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
21359 /* SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2 */
21360 /* Description: SIC Counter 2 Overflow */
21361 #define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30
21362 #define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
21364 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */
21365 /* Description: NI0 Debit 0 Overflow */
21366 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31
21367 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
21369 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */
21370 /* Description: NI0 Debit 2 Overflow */
21371 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32
21372 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
21374 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */
21375 /* Description: NI1 Debit 0 Overflow */
21376 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33
21377 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
21379 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */
21380 /* Description: NI1 Debit 2 Overflow */
21381 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34
21382 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
21384 /* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */
21385 /* Description: IILB Debit 0 Overflow */
21386 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35
21387 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
21389 /* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */
21390 /* Description: IILB Debit 2 Overflow */
21391 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36
21392 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
21394 /* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT */
21395 /* Description: NI0 VC0 Credit Underflow */
21396 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
21397 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
21399 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT */
21400 /* Description: NI0 VC0 Credit Overflow */
21401 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
21402 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
21404 /* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT */
21405 /* Description: NI0 VC2 Credit Underflow */
21406 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
21407 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
21409 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT */
21410 /* Description: NI0 VC2 Credit Overflow */
21411 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
21412 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
21414 /* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT */
21415 /* Description: NI1 VC0 Credit Underflow */
21416 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
21417 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
21419 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT */
21420 /* Description: NI1 VC0 Credit Overflow */
21421 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
21422 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
21424 /* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT */
21425 /* Description: NI1 VC2 Credit Underflow */
21426 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
21427 #define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
21429 /* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT */
21430 /* Description: NI1 VC2 Credit Overflow */
21431 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
21432 #define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
21434 /* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT */
21435 /* Description: IILB VC0 Credit Underflow */
21436 #define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
21437 #define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
21439 /* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT */
21440 /* Description: IILB VC0 Credit Overflow */
21441 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
21442 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
21444 /* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT */
21445 /* Description: IILB VC2 Credit Underflow */
21446 #define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
21447 #define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
21449 /* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT */
21450 /* Description: IILB VC2 Credit Overflow */
21451 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
21452 #define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
21454 /* SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO */
21455 /* Description: Header Cancel Fifo Overflow */
21456 #define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
21457 #define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
21459 /* ==================================================================== */
21460 /* Register "SH_XNPI_FIRST_ERROR" */
21461 /* ==================================================================== */
21463 #define SH_XNPI_FIRST_ERROR 0x0000000150040360
21464 #define SH_XNPI_FIRST_ERROR_MASK 0x0003ffffffffffff
21465 #define SH_XNPI_FIRST_ERROR_INIT 0x0003ffffffffffff
21467 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0 */
21468 /* Description: NI0 VC0 fifo underflow */
21469 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0
21470 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
21472 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0 */
21473 /* Description: NI0 VC0 fifo overflow */
21474 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1
21475 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
21477 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2 */
21478 /* Description: NI0 VC2 fifo underflow */
21479 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2
21480 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
21482 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2 */
21483 /* Description: NI0 VC2 fifo overflow */
21484 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3
21485 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
21487 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0 */
21488 /* Description: NI1 VC0 fifo underflow */
21489 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4
21490 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
21492 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0 */
21493 /* Description: NI1 VC0 fifo overflow */
21494 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5
21495 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
21497 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2 */
21498 /* Description: NI1 VC2 fifo underflow */
21499 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6
21500 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
21502 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2 */
21503 /* Description: NI1 VC2 fifo overflow */
21504 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7
21505 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
21507 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0 */
21508 /* Description: IILB VC0 fifo underflow */
21509 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8
21510 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
21512 /* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0 */
21513 /* Description: IILB VC0 fifo overflow */
21514 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9
21515 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
21517 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2 */
21518 /* Description: IILB VC2 fifo underflow */
21519 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10
21520 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
21522 /* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2 */
21523 /* Description: IILB VC2 fifo overflow */
21524 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11
21525 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
21527 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT */
21528 /* Description: VC0 Credit underflow */
21529 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12
21530 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
21532 /* SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT */
21533 /* Description: VC0 Credit overflow */
21534 #define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13
21535 #define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
21537 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT */
21538 /* Description: VC2 Credit underflow */
21539 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14
21540 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
21542 /* SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT */
21543 /* Description: VC2 Credit overflow */
21544 #define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15
21545 #define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
21547 /* SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0 */
21548 /* Description: VC0 Data Buffer overflow */
21549 #define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16
21550 #define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
21552 /* SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2 */
21553 /* Description: VC2 Data Buffer overflow */
21554 #define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17
21555 #define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
21557 /* SH_XNPI_FIRST_ERROR_LUT_READ_ERROR */
21558 /* Description: LUT Read Error */
21559 #define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_SHFT 18
21560 #define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_MASK 0x0000000000040000
21562 /* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0 */
21563 /* Description: Single Bit Error in Bits 63:0 */
21564 #define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19
21565 #define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
21567 /* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1 */
21568 /* Description: Single Bit Error in Bits 127:64 */
21569 #define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20
21570 #define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
21572 /* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2 */
21573 /* Description: Single Bit Error in Bits 191:128 */
21574 #define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21
21575 #define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
21577 /* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3 */
21578 /* Description: Single Bit Error in Bits 255:192 */
21579 #define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22
21580 #define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
21582 /* SH_XNPI_FIRST_ERROR_UNCOR_ERROR0 */
21583 /* Description: Uncorrectable Error in Bits 63:0 */
21584 #define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_SHFT 23
21585 #define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_MASK 0x0000000000800000
21587 /* SH_XNPI_FIRST_ERROR_UNCOR_ERROR1 */
21588 /* Description: Uncorrectable Error in Bits 127:64 */
21589 #define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_SHFT 24
21590 #define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_MASK 0x0000000001000000
21592 /* SH_XNPI_FIRST_ERROR_UNCOR_ERROR2 */
21593 /* Description: Uncorrectable Error in Bits 191:128 */
21594 #define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_SHFT 25
21595 #define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_MASK 0x0000000002000000
21597 /* SH_XNPI_FIRST_ERROR_UNCOR_ERROR3 */
21598 /* Description: Uncorrectable Error in Bits 255:192 */
21599 #define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_SHFT 26
21600 #define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_MASK 0x0000000004000000
21602 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0 */
21603 /* Description: SIC Counter 0 Underflow */
21604 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27
21605 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
21607 /* SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0 */
21608 /* Description: SIC Counter 0 Overflow */
21609 #define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28
21610 #define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
21612 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2 */
21613 /* Description: SIC Counter 2 Underflow */
21614 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29
21615 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
21617 /* SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2 */
21618 /* Description: SIC Counter 2 Overflow */
21619 #define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30
21620 #define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
21622 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */
21623 /* Description: NI0 Debit 0 Overflow */
21624 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31
21625 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
21627 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */
21628 /* Description: NI0 Debit 2 Overflow */
21629 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32
21630 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
21632 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */
21633 /* Description: NI1 Debit 0 Overflow */
21634 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33
21635 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
21637 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */
21638 /* Description: NI1 Debit 2 Overflow */
21639 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34
21640 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
21642 /* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */
21643 /* Description: IILB Debit 0 Overflow */
21644 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35
21645 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
21647 /* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */
21648 /* Description: IILB Debit 2 Overflow */
21649 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36
21650 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
21652 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT */
21653 /* Description: NI0 VC0 Credit Underflow */
21654 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
21655 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
21657 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT */
21658 /* Description: NI0 VC0 Credit Overflow */
21659 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
21660 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
21662 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT */
21663 /* Description: NI0 VC2 Credit Underflow */
21664 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
21665 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
21667 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT */
21668 /* Description: NI0 VC2 Credit Overflow */
21669 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
21670 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
21672 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT */
21673 /* Description: NI1 VC0 Credit Underflow */
21674 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
21675 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
21677 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT */
21678 /* Description: NI1 VC0 Credit Overflow */
21679 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
21680 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
21682 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT */
21683 /* Description: NI1 VC2 Credit Underflow */
21684 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
21685 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
21687 /* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT */
21688 /* Description: NI1 VC2 Credit Overflow */
21689 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
21690 #define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
21692 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT */
21693 /* Description: IILB VC0 Credit Underflow */
21694 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
21695 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
21697 /* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT */
21698 /* Description: IILB VC0 Credit Overflow */
21699 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
21700 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
21702 /* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT */
21703 /* Description: IILB VC2 Credit Underflow */
21704 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
21705 #define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
21707 /* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT */
21708 /* Description: IILB VC2 Credit Overflow */
21709 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
21710 #define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
21712 /* SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO */
21713 /* Description: Header Cancel Fifo Overflow */
21714 #define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
21715 #define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
21717 /* ==================================================================== */
21718 /* Register "SH_XNMD_ERROR_SUMMARY" */
21719 /* ==================================================================== */
21721 #define SH_XNMD_ERROR_SUMMARY 0x0000000150040400
21722 #define SH_XNMD_ERROR_SUMMARY_MASK 0x0003ffffffffffff
21723 #define SH_XNMD_ERROR_SUMMARY_INIT 0x0003ffffffffffff
21725 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0 */
21726 /* Description: NI0 VC0 fifo underflow */
21727 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0
21728 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
21730 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0 */
21731 /* Description: NI0 VC0 fifo overflow */
21732 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1
21733 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
21735 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2 */
21736 /* Description: NI0 VC2 fifo underflow */
21737 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2
21738 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
21740 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2 */
21741 /* Description: NI0 VC2 fifo overflow */
21742 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3
21743 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
21745 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0 */
21746 /* Description: NI1 VC0 fifo underflow */
21747 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4
21748 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
21750 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0 */
21751 /* Description: NI1 VC0 fifo overflow */
21752 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5
21753 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
21755 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2 */
21756 /* Description: NI1 VC2 fifo underflow */
21757 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6
21758 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
21760 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2 */
21761 /* Description: NI1 VC2 fifo overflow */
21762 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7
21763 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
21765 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0 */
21766 /* Description: IILB VC0 fifo underflow */
21767 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8
21768 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
21770 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0 */
21771 /* Description: IILB VC0 fifo overflow */
21772 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9
21773 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
21775 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2 */
21776 /* Description: IILB VC2 fifo underflow */
21777 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10
21778 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
21780 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2 */
21781 /* Description: IILB VC2 fifo overflow */
21782 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11
21783 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
21785 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT */
21786 /* Description: VC0 Credit underflow */
21787 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12
21788 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
21790 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT */
21791 /* Description: VC0 Credit overflow */
21792 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13
21793 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
21795 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT */
21796 /* Description: VC2 Credit underflow */
21797 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14
21798 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
21800 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT */
21801 /* Description: VC2 Credit overflow */
21802 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15
21803 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
21805 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0 */
21806 /* Description: VC0 Data Buffer overflow */
21807 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16
21808 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
21810 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2 */
21811 /* Description: VC2 Data Buffer overflow */
21812 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17
21813 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
21815 /* SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR */
21816 /* Description: LUT Read Error */
21817 #define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18
21818 #define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000
21820 /* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0 */
21821 /* Description: Single Bit Error in Bits 63:0 */
21822 #define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19
21823 #define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
21825 /* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1 */
21826 /* Description: Single Bit Error in Bits 127:64 */
21827 #define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20
21828 #define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
21830 /* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2 */
21831 /* Description: Single Bit Error in Bits 191:128 */
21832 #define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21
21833 #define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
21835 /* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3 */
21836 /* Description: Single Bit Error in Bits 255:192 */
21837 #define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22
21838 #define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
21840 /* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0 */
21841 /* Description: Uncorrectable Error in Bits 63:0 */
21842 #define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_SHFT 23
21843 #define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_MASK 0x0000000000800000
21845 /* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1 */
21846 /* Description: Uncorrectable Error in Bits 127:64 */
21847 #define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_SHFT 24
21848 #define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_MASK 0x0000000001000000
21850 /* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2 */
21851 /* Description: Uncorrectable Error in Bits 191:128 */
21852 #define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_SHFT 25
21853 #define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_MASK 0x0000000002000000
21855 /* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3 */
21856 /* Description: Uncorrectable Error in Bits 255:192 */
21857 #define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_SHFT 26
21858 #define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_MASK 0x0000000004000000
21860 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0 */
21861 /* Description: SIC Counter 0 Underflow */
21862 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27
21863 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
21865 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0 */
21866 /* Description: SIC Counter 0 Overflow */
21867 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28
21868 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
21870 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2 */
21871 /* Description: SIC Counter 2 Underflow */
21872 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29
21873 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
21875 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2 */
21876 /* Description: SIC Counter 2 Overflow */
21877 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30
21878 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
21880 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */
21881 /* Description: NI0 Debit 0 Overflow */
21882 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31
21883 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
21885 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */
21886 /* Description: NI0 Debit 2 Overflow */
21887 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32
21888 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
21890 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */
21891 /* Description: NI1 Debit 0 Overflow */
21892 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33
21893 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
21895 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */
21896 /* Description: NI1 Debit 2 Overflow */
21897 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34
21898 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
21900 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */
21901 /* Description: IILB Debit 0 Overflow */
21902 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35
21903 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
21905 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */
21906 /* Description: IILB Debit 2 Overflow */
21907 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36
21908 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
21910 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT */
21911 /* Description: NI0 VC0 Credit Underflow */
21912 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
21913 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
21915 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT */
21916 /* Description: NI0 VC0 Credit Overflow */
21917 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
21918 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
21920 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT */
21921 /* Description: NI0 VC2 Credit Underflow */
21922 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
21923 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
21925 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT */
21926 /* Description: NI0 VC2 Credit Overflow */
21927 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
21928 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
21930 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT */
21931 /* Description: NI1 VC0 Credit Underflow */
21932 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
21933 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
21935 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT */
21936 /* Description: NI1 VC0 Credit Overflow */
21937 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
21938 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
21940 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT */
21941 /* Description: NI1 VC2 Credit Underflow */
21942 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
21943 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
21945 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT */
21946 /* Description: NI1 VC2 Credit Overflow */
21947 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
21948 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
21950 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT */
21951 /* Description: IILB VC0 Credit Underflow */
21952 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
21953 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
21955 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT */
21956 /* Description: IILB VC0 Credit Overflow */
21957 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
21958 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
21960 /* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT */
21961 /* Description: IILB VC2 Credit Underflow */
21962 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
21963 #define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
21965 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT */
21966 /* Description: IILB VC2 Credit Overflow */
21967 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
21968 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
21970 /* SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO */
21971 /* Description: Header Cancel Fifo Overflow */
21972 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
21973 #define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
21975 /* ==================================================================== */
21976 /* Register "SH_XNMD_ERRORS_ALIAS" */
21977 /* ==================================================================== */
21979 #define SH_XNMD_ERRORS_ALIAS 0x0000000150040408
21981 /* ==================================================================== */
21982 /* Register "SH_XNMD_ERROR_OVERFLOW" */
21983 /* ==================================================================== */
21985 #define SH_XNMD_ERROR_OVERFLOW 0x0000000150040420
21986 #define SH_XNMD_ERROR_OVERFLOW_MASK 0x0003ffffffffffff
21987 #define SH_XNMD_ERROR_OVERFLOW_INIT 0x0003ffffffffffff
21989 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0 */
21990 /* Description: NI0 VC0 fifo underflow */
21991 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0
21992 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
21994 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0 */
21995 /* Description: NI0 VC0 fifo overflow */
21996 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1
21997 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
21999 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2 */
22000 /* Description: NI0 VC2 fifo underflow */
22001 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2
22002 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
22004 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2 */
22005 /* Description: NI0 VC2 fifo overflow */
22006 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3
22007 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
22009 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0 */
22010 /* Description: NI1 VC0 fifo underflow */
22011 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4
22012 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
22014 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0 */
22015 /* Description: NI1 VC0 fifo overflow */
22016 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5
22017 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
22019 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2 */
22020 /* Description: NI1 VC2 fifo underflow */
22021 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6
22022 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
22024 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2 */
22025 /* Description: NI1 VC2 fifo overflow */
22026 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7
22027 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
22029 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0 */
22030 /* Description: IILB VC0 fifo underflow */
22031 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8
22032 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
22034 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0 */
22035 /* Description: IILB VC0 fifo overflow */
22036 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9
22037 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
22039 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2 */
22040 /* Description: IILB VC2 fifo underflow */
22041 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10
22042 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
22044 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2 */
22045 /* Description: IILB VC2 fifo overflow */
22046 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11
22047 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
22049 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT */
22050 /* Description: VC0 Credit underflow */
22051 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12
22052 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
22054 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT */
22055 /* Description: VC0 Credit overflow */
22056 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13
22057 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
22059 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT */
22060 /* Description: VC2 Credit underflow */
22061 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14
22062 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
22064 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT */
22065 /* Description: VC2 Credit overflow */
22066 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15
22067 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
22069 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0 */
22070 /* Description: VC0 Data Buffer overflow */
22071 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16
22072 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
22074 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2 */
22075 /* Description: VC2 Data Buffer overflow */
22076 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17
22077 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
22079 /* SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR */
22080 /* Description: LUT Read Error */
22081 #define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18
22082 #define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000
22084 /* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0 */
22085 /* Description: Single Bit Error in Bits 63:0 */
22086 #define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19
22087 #define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
22089 /* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1 */
22090 /* Description: Single Bit Error in Bits 127:64 */
22091 #define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20
22092 #define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
22094 /* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2 */
22095 /* Description: Single Bit Error in Bits 191:128 */
22096 #define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21
22097 #define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
22099 /* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3 */
22100 /* Description: Single Bit Error in Bits 255:192 */
22101 #define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22
22102 #define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
22104 /* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0 */
22105 /* Description: Uncorrectable Error in Bits 63:0 */
22106 #define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23
22107 #define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000
22109 /* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1 */
22110 /* Description: Uncorrectable Error in Bits 127:64 */
22111 #define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24
22112 #define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000
22114 /* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2 */
22115 /* Description: Uncorrectable Error in Bits 191:128 */
22116 #define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25
22117 #define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000
22119 /* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3 */
22120 /* Description: Uncorrectable Error in Bits 255:192 */
22121 #define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26
22122 #define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000
22124 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0 */
22125 /* Description: SIC Counter 0 Underflow */
22126 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27
22127 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
22129 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0 */
22130 /* Description: SIC Counter 0 Overflow */
22131 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28
22132 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
22134 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2 */
22135 /* Description: SIC Counter 2 Underflow */
22136 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29
22137 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
22139 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2 */
22140 /* Description: SIC Counter 2 Overflow */
22141 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30
22142 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
22144 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */
22145 /* Description: NI0 Debit 0 Overflow */
22146 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31
22147 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
22149 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */
22150 /* Description: NI0 Debit 2 Overflow */
22151 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32
22152 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
22154 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */
22155 /* Description: NI1 Debit 0 Overflow */
22156 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33
22157 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
22159 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */
22160 /* Description: NI1 Debit 2 Overflow */
22161 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34
22162 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
22164 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */
22165 /* Description: IILB Debit 0 Overflow */
22166 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35
22167 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
22169 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */
22170 /* Description: IILB Debit 2 Overflow */
22171 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36
22172 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
22174 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT */
22175 /* Description: NI0 VC0 Credit Underflow */
22176 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
22177 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
22179 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT */
22180 /* Description: NI0 VC0 Credit Overflow */
22181 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
22182 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
22184 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT */
22185 /* Description: NI0 VC2 Credit Underflow */
22186 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
22187 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
22189 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT */
22190 /* Description: NI0 VC2 Credit Overflow */
22191 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
22192 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
22194 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT */
22195 /* Description: NI1 VC0 Credit Underflow */
22196 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
22197 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
22199 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT */
22200 /* Description: NI1 VC0 Credit Overflow */
22201 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
22202 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
22204 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT */
22205 /* Description: NI1 VC2 Credit Underflow */
22206 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
22207 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
22209 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT */
22210 /* Description: NI1 VC2 Credit Overflow */
22211 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
22212 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
22214 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT */
22215 /* Description: IILB VC0 Credit Underflow */
22216 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
22217 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
22219 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT */
22220 /* Description: IILB VC0 Credit Overflow */
22221 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
22222 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
22224 /* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT */
22225 /* Description: IILB VC2 Credit Underflow */
22226 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
22227 #define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
22229 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT */
22230 /* Description: IILB VC2 Credit Overflow */
22231 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
22232 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
22234 /* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO */
22235 /* Description: Header Cancel Fifo Overflow */
22236 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
22237 #define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
22239 /* ==================================================================== */
22240 /* Register "SH_XNMD_ERROR_OVERFLOW_ALIAS" */
22241 /* ==================================================================== */
22243 #define SH_XNMD_ERROR_OVERFLOW_ALIAS 0x0000000150040428
22245 /* ==================================================================== */
22246 /* Register "SH_XNMD_ERROR_MASK" */
22247 /* ==================================================================== */
22249 #define SH_XNMD_ERROR_MASK 0x0000000150040440
22250 #define SH_XNMD_ERROR_MASK_MASK 0x0003ffffffffffff
22251 #define SH_XNMD_ERROR_MASK_INIT 0x0003ffffffffffff
22253 /* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0 */
22254 /* Description: NI0 VC0 fifo underflow */
22255 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0
22256 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
22258 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0 */
22259 /* Description: NI0 VC0 fifo overflow */
22260 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1
22261 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
22263 /* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2 */
22264 /* Description: NI0 VC2 fifo underflow */
22265 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2
22266 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
22268 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2 */
22269 /* Description: NI0 VC2 fifo overflow */
22270 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3
22271 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
22273 /* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0 */
22274 /* Description: NI1 VC0 fifo underflow */
22275 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4
22276 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
22278 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0 */
22279 /* Description: NI1 VC0 fifo overflow */
22280 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5
22281 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
22283 /* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2 */
22284 /* Description: NI1 VC2 fifo underflow */
22285 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6
22286 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
22288 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2 */
22289 /* Description: NI1 VC2 fifo overflow */
22290 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7
22291 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
22293 /* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0 */
22294 /* Description: IILB VC0 fifo underflow */
22295 #define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8
22296 #define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
22298 /* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0 */
22299 /* Description: IILB VC0 fifo overflow */
22300 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9
22301 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
22303 /* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2 */
22304 /* Description: IILB VC2 fifo underflow */
22305 #define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10
22306 #define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
22308 /* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2 */
22309 /* Description: IILB VC2 fifo overflow */
22310 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11
22311 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
22313 /* SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT */
22314 /* Description: VC0 Credit underflow */
22315 #define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12
22316 #define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
22318 /* SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT */
22319 /* Description: VC0 Credit overflow */
22320 #define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13
22321 #define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
22323 /* SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT */
22324 /* Description: VC2 Credit underflow */
22325 #define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14
22326 #define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
22328 /* SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT */
22329 /* Description: VC2 Credit overflow */
22330 #define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15
22331 #define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
22333 /* SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0 */
22334 /* Description: VC0 Data Buffer overflow */
22335 #define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16
22336 #define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
22338 /* SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2 */
22339 /* Description: VC2 Data Buffer overflow */
22340 #define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17
22341 #define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
22343 /* SH_XNMD_ERROR_MASK_LUT_READ_ERROR */
22344 /* Description: LUT Read Error */
22345 #define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_SHFT 18
22346 #define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_MASK 0x0000000000040000
22348 /* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0 */
22349 /* Description: Single Bit Error in Bits 63:0 */
22350 #define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19
22351 #define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
22353 /* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1 */
22354 /* Description: Single Bit Error in Bits 127:64 */
22355 #define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20
22356 #define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
22358 /* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2 */
22359 /* Description: Single Bit Error in Bits 191:128 */
22360 #define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21
22361 #define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
22363 /* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3 */
22364 /* Description: Single Bit Error in Bits 255:192 */
22365 #define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22
22366 #define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
22368 /* SH_XNMD_ERROR_MASK_UNCOR_ERROR0 */
22369 /* Description: Uncorrectable Error in Bits 63:0 */
22370 #define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_SHFT 23
22371 #define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_MASK 0x0000000000800000
22373 /* SH_XNMD_ERROR_MASK_UNCOR_ERROR1 */
22374 /* Description: Uncorrectable Error in Bits 127:64 */
22375 #define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_SHFT 24
22376 #define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_MASK 0x0000000001000000
22378 /* SH_XNMD_ERROR_MASK_UNCOR_ERROR2 */
22379 /* Description: Uncorrectable Error in Bits 191:128 */
22380 #define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_SHFT 25
22381 #define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_MASK 0x0000000002000000
22383 /* SH_XNMD_ERROR_MASK_UNCOR_ERROR3 */
22384 /* Description: Uncorrectable Error in Bits 255:192 */
22385 #define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_SHFT 26
22386 #define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_MASK 0x0000000004000000
22388 /* SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0 */
22389 /* Description: SIC Counter 0 Underflow */
22390 #define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27
22391 #define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
22393 /* SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0 */
22394 /* Description: SIC Counter 0 Overflow */
22395 #define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28
22396 #define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
22398 /* SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2 */
22399 /* Description: SIC Counter 2 Underflow */
22400 #define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29
22401 #define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
22403 /* SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2 */
22404 /* Description: SIC Counter 2 Overflow */
22405 #define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30
22406 #define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
22408 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */
22409 /* Description: NI0 Debit 0 Overflow */
22410 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31
22411 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
22413 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */
22414 /* Description: NI0 Debit 2 Overflow */
22415 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32
22416 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
22418 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */
22419 /* Description: NI1 Debit 0 Overflow */
22420 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33
22421 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
22423 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */
22424 /* Description: NI1 Debit 2 Overflow */
22425 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34
22426 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
22428 /* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */
22429 /* Description: IILB Debit 0 Overflow */
22430 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35
22431 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
22433 /* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */
22434 /* Description: IILB Debit 2 Overflow */
22435 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36
22436 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
22438 /* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT */
22439 /* Description: NI0 VC0 Credit Underflow */
22440 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
22441 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
22443 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT */
22444 /* Description: NI0 VC0 Credit Overflow */
22445 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
22446 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
22448 /* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT */
22449 /* Description: NI0 VC2 Credit Underflow */
22450 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
22451 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
22453 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT */
22454 /* Description: NI0 VC2 Credit Overflow */
22455 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
22456 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
22458 /* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT */
22459 /* Description: NI1 VC0 Credit Underflow */
22460 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
22461 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
22463 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT */
22464 /* Description: NI1 VC0 Credit Overflow */
22465 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
22466 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
22468 /* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT */
22469 /* Description: NI1 VC2 Credit Underflow */
22470 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
22471 #define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
22473 /* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT */
22474 /* Description: NI1 VC2 Credit Overflow */
22475 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
22476 #define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
22478 /* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT */
22479 /* Description: IILB VC0 Credit Underflow */
22480 #define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
22481 #define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
22483 /* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT */
22484 /* Description: IILB VC0 Credit Overflow */
22485 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
22486 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
22488 /* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT */
22489 /* Description: IILB VC2 Credit Underflow */
22490 #define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
22491 #define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
22493 /* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT */
22494 /* Description: IILB VC2 Credit Overflow */
22495 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
22496 #define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
22498 /* SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO */
22499 /* Description: Header Cancel Fifo Overflow */
22500 #define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
22501 #define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
22503 /* ==================================================================== */
22504 /* Register "SH_XNMD_FIRST_ERROR" */
22505 /* ==================================================================== */
22507 #define SH_XNMD_FIRST_ERROR 0x0000000150040460
22508 #define SH_XNMD_FIRST_ERROR_MASK 0x0003ffffffffffff
22509 #define SH_XNMD_FIRST_ERROR_INIT 0x0003ffffffffffff
22511 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0 */
22512 /* Description: NI0 VC0 fifo underflow */
22513 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0
22514 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
22516 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0 */
22517 /* Description: NI0 VC0 fifo overflow */
22518 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1
22519 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
22521 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2 */
22522 /* Description: NI0 VC2 fifo underflow */
22523 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2
22524 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
22526 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2 */
22527 /* Description: NI0 VC2 fifo overflow */
22528 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3
22529 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
22531 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0 */
22532 /* Description: NI1 VC0 fifo underflow */
22533 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4
22534 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
22536 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0 */
22537 /* Description: NI1 VC0 fifo overflow */
22538 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5
22539 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
22541 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2 */
22542 /* Description: NI1 VC2 fifo underflow */
22543 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6
22544 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
22546 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2 */
22547 /* Description: NI1 VC2 fifo overflow */
22548 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7
22549 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
22551 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0 */
22552 /* Description: IILB VC0 fifo underflow */
22553 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8
22554 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
22556 /* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0 */
22557 /* Description: IILB VC0 fifo overflow */
22558 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9
22559 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
22561 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2 */
22562 /* Description: IILB VC2 fifo underflow */
22563 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10
22564 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
22566 /* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2 */
22567 /* Description: IILB VC2 fifo overflow */
22568 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11
22569 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
22571 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT */
22572 /* Description: VC0 Credit underflow */
22573 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12
22574 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
22576 /* SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT */
22577 /* Description: VC0 Credit overflow */
22578 #define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13
22579 #define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
22581 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT */
22582 /* Description: VC2 Credit underflow */
22583 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14
22584 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
22586 /* SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT */
22587 /* Description: VC2 Credit overflow */
22588 #define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15
22589 #define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
22591 /* SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0 */
22592 /* Description: VC0 Data Buffer overflow */
22593 #define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16
22594 #define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
22596 /* SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2 */
22597 /* Description: VC2 Data Buffer overflow */
22598 #define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17
22599 #define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
22601 /* SH_XNMD_FIRST_ERROR_LUT_READ_ERROR */
22602 /* Description: LUT Read Error */
22603 #define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_SHFT 18
22604 #define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_MASK 0x0000000000040000
22606 /* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0 */
22607 /* Description: Single Bit Error in Bits 63:0 */
22608 #define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19
22609 #define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
22611 /* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1 */
22612 /* Description: Single Bit Error in Bits 127:64 */
22613 #define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20
22614 #define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
22616 /* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2 */
22617 /* Description: Single Bit Error in Bits 191:128 */
22618 #define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21
22619 #define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
22621 /* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3 */
22622 /* Description: Single Bit Error in Bits 255:192 */
22623 #define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22
22624 #define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
22626 /* SH_XNMD_FIRST_ERROR_UNCOR_ERROR0 */
22627 /* Description: Uncorrectable Error in Bits 63:0 */
22628 #define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_SHFT 23
22629 #define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_MASK 0x0000000000800000
22631 /* SH_XNMD_FIRST_ERROR_UNCOR_ERROR1 */
22632 /* Description: Uncorrectable Error in Bits 127:64 */
22633 #define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_SHFT 24
22634 #define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_MASK 0x0000000001000000
22636 /* SH_XNMD_FIRST_ERROR_UNCOR_ERROR2 */
22637 /* Description: Uncorrectable Error in Bits 191:128 */
22638 #define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_SHFT 25
22639 #define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_MASK 0x0000000002000000
22641 /* SH_XNMD_FIRST_ERROR_UNCOR_ERROR3 */
22642 /* Description: Uncorrectable Error in Bits 255:192 */
22643 #define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_SHFT 26
22644 #define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_MASK 0x0000000004000000
22646 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0 */
22647 /* Description: SIC Counter 0 Underflow */
22648 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27
22649 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
22651 /* SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0 */
22652 /* Description: SIC Counter 0 Overflow */
22653 #define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28
22654 #define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
22656 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2 */
22657 /* Description: SIC Counter 2 Underflow */
22658 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29
22659 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
22661 /* SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2 */
22662 /* Description: SIC Counter 2 Overflow */
22663 #define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30
22664 #define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
22666 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */
22667 /* Description: NI0 Debit 0 Overflow */
22668 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31
22669 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
22671 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */
22672 /* Description: NI0 Debit 2 Overflow */
22673 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32
22674 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
22676 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */
22677 /* Description: NI1 Debit 0 Overflow */
22678 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33
22679 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
22681 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */
22682 /* Description: NI1 Debit 2 Overflow */
22683 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34
22684 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
22686 /* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */
22687 /* Description: IILB Debit 0 Overflow */
22688 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35
22689 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
22691 /* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */
22692 /* Description: IILB Debit 2 Overflow */
22693 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36
22694 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
22696 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT */
22697 /* Description: NI0 VC0 Credit Underflow */
22698 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
22699 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
22701 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT */
22702 /* Description: NI0 VC0 Credit Overflow */
22703 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
22704 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
22706 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT */
22707 /* Description: NI0 VC2 Credit Underflow */
22708 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
22709 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
22711 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT */
22712 /* Description: NI0 VC2 Credit Overflow */
22713 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
22714 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
22716 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT */
22717 /* Description: NI1 VC0 Credit Underflow */
22718 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
22719 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
22721 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT */
22722 /* Description: NI1 VC0 Credit Overflow */
22723 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
22724 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
22726 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT */
22727 /* Description: NI1 VC2 Credit Underflow */
22728 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
22729 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
22731 /* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT */
22732 /* Description: NI1 VC2 Credit Overflow */
22733 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
22734 #define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
22736 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT */
22737 /* Description: IILB VC0 Credit Underflow */
22738 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
22739 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
22741 /* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT */
22742 /* Description: IILB VC0 Credit Overflow */
22743 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
22744 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
22746 /* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT */
22747 /* Description: IILB VC2 Credit Underflow */
22748 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
22749 #define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
22751 /* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT */
22752 /* Description: IILB VC2 Credit Overflow */
22753 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
22754 #define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
22756 /* SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO */
22757 /* Description: Header Cancel Fifo Overflow */
22758 #define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
22759 #define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
22761 /* ==================================================================== */
22762 /* Register "SH_AUTO_REPLY_ENABLE0" */
22763 /* Automatic Maintenance Reply Enable 0 */
22764 /* ==================================================================== */
22766 #define SH_AUTO_REPLY_ENABLE0 0x0000000110061000
22767 #define SH_AUTO_REPLY_ENABLE0_MASK 0xffffffffffffffff
22768 #define SH_AUTO_REPLY_ENABLE0_INIT 0x0000000000000000
22770 /* SH_AUTO_REPLY_ENABLE0_ENABLE0 */
22771 /* Description: Enable 0 */
22772 #define SH_AUTO_REPLY_ENABLE0_ENABLE0_SHFT 0
22773 #define SH_AUTO_REPLY_ENABLE0_ENABLE0_MASK 0xffffffffffffffff
22775 /* ==================================================================== */
22776 /* Register "SH_AUTO_REPLY_ENABLE1" */
22777 /* Automatic Maintenance Reply Enable 1 */
22778 /* ==================================================================== */
22780 #define SH_AUTO_REPLY_ENABLE1 0x0000000110061080
22781 #define SH_AUTO_REPLY_ENABLE1_MASK 0xffffffffffffffff
22782 #define SH_AUTO_REPLY_ENABLE1_INIT 0x0000000000000000
22784 /* SH_AUTO_REPLY_ENABLE1_ENABLE1 */
22785 /* Description: Enable 1 */
22786 #define SH_AUTO_REPLY_ENABLE1_ENABLE1_SHFT 0
22787 #define SH_AUTO_REPLY_ENABLE1_ENABLE1_MASK 0xffffffffffffffff
22789 /* ==================================================================== */
22790 /* Register "SH_AUTO_REPLY_HEADER0" */
22791 /* Automatic Maintenance Reply Header 0 */
22792 /* ==================================================================== */
22794 #define SH_AUTO_REPLY_HEADER0 0x0000000110061100
22795 #define SH_AUTO_REPLY_HEADER0_MASK 0xffffffffffffffff
22796 #define SH_AUTO_REPLY_HEADER0_INIT 0x0000000000000000
22798 /* SH_AUTO_REPLY_HEADER0_HEADER0 */
22799 /* Description: Header 0 */
22800 #define SH_AUTO_REPLY_HEADER0_HEADER0_SHFT 0
22801 #define SH_AUTO_REPLY_HEADER0_HEADER0_MASK 0xffffffffffffffff
22803 /* ==================================================================== */
22804 /* Register "SH_AUTO_REPLY_HEADER1" */
22805 /* Automatic Maintenance Reply Header 1 */
22806 /* ==================================================================== */
22808 #define SH_AUTO_REPLY_HEADER1 0x0000000110061180
22809 #define SH_AUTO_REPLY_HEADER1_MASK 0xffffffffffffffff
22810 #define SH_AUTO_REPLY_HEADER1_INIT 0x0000000000000000
22812 /* SH_AUTO_REPLY_HEADER1_HEADER1 */
22813 /* Description: Header 1 */
22814 #define SH_AUTO_REPLY_HEADER1_HEADER1_SHFT 0
22815 #define SH_AUTO_REPLY_HEADER1_HEADER1_MASK 0xffffffffffffffff
22817 /* ==================================================================== */
22818 /* Register "SH_ENABLE_RP_AUTO_REPLY" */
22819 /* Enable Automatic Maintenance Reply From Reply Queue */
22820 /* ==================================================================== */
22822 #define SH_ENABLE_RP_AUTO_REPLY 0x0000000110061200
22823 #define SH_ENABLE_RP_AUTO_REPLY_MASK 0x0000000000000001
22824 #define SH_ENABLE_RP_AUTO_REPLY_INIT 0x0000000000000000
22826 /* SH_ENABLE_RP_AUTO_REPLY_ENABLE */
22827 /* Description: Enable Reply Auto Reply */
22828 #define SH_ENABLE_RP_AUTO_REPLY_ENABLE_SHFT 0
22829 #define SH_ENABLE_RP_AUTO_REPLY_ENABLE_MASK 0x0000000000000001
22831 /* ==================================================================== */
22832 /* Register "SH_ENABLE_RQ_AUTO_REPLY" */
22833 /* Enable Automatic Maintenance Reply From Request Queue */
22834 /* ==================================================================== */
22836 #define SH_ENABLE_RQ_AUTO_REPLY 0x0000000110061280
22837 #define SH_ENABLE_RQ_AUTO_REPLY_MASK 0x0000000000000001
22838 #define SH_ENABLE_RQ_AUTO_REPLY_INIT 0x0000000000000000
22840 /* SH_ENABLE_RQ_AUTO_REPLY_ENABLE */
22841 /* Description: Enable Request Auto Reply */
22842 #define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_SHFT 0
22843 #define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_MASK 0x0000000000000001
22845 /* ==================================================================== */
22846 /* Register "SH_REDIRECT_INVAL" */
22847 /* Redirect invalidate to LB instead of PI */
22848 /* ==================================================================== */
22850 #define SH_REDIRECT_INVAL 0x0000000110061300
22851 #define SH_REDIRECT_INVAL_MASK 0x0000000000000001
22852 #define SH_REDIRECT_INVAL_INIT 0x0000000000000000
22854 /* SH_REDIRECT_INVAL_REDIRECT */
22855 /* Description: Redirect invalidates to LB instead of PI */
22856 #define SH_REDIRECT_INVAL_REDIRECT_SHFT 0
22857 #define SH_REDIRECT_INVAL_REDIRECT_MASK 0x0000000000000001
22859 /* ==================================================================== */
22860 /* Register "SH_DIAG_MSG_CNTRL" */
22861 /* Diagnostic Message Control Register */
22862 /* ==================================================================== */
22864 #define SH_DIAG_MSG_CNTRL 0x0000000110062000
22865 #define SH_DIAG_MSG_CNTRL_MASK 0xc000000000003fff
22866 #define SH_DIAG_MSG_CNTRL_INIT 0x0000000000000000
22868 /* SH_DIAG_MSG_CNTRL_MSG_LENGTH */
22869 /* Description: Message data payload length, 0 - 63 */
22870 #define SH_DIAG_MSG_CNTRL_MSG_LENGTH_SHFT 0
22871 #define SH_DIAG_MSG_CNTRL_MSG_LENGTH_MASK 0x000000000000003f
22873 /* SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT */
22874 /* Description: Point message that the error bit would be activated */
22875 #define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_SHFT 6
22876 #define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_MASK 0x0000000000000fc0
22878 /* SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE */
22879 /* Description: Enable ERROR_INJECT_POINT field */
22880 #define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_SHFT 12
22881 #define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_MASK 0x0000000000001000
22883 /* SH_DIAG_MSG_CNTRL_PORT */
22884 /* Description: 0 = request port, 1 = reply port */
22885 #define SH_DIAG_MSG_CNTRL_PORT_SHFT 13
22886 #define SH_DIAG_MSG_CNTRL_PORT_MASK 0x0000000000002000
22888 /* SH_DIAG_MSG_CNTRL_START */
22889 /* Description: Start */
22890 #define SH_DIAG_MSG_CNTRL_START_SHFT 62
22891 #define SH_DIAG_MSG_CNTRL_START_MASK 0x4000000000000000
22893 /* SH_DIAG_MSG_CNTRL_BUSY */
22894 /* Description: Busy */
22895 #define SH_DIAG_MSG_CNTRL_BUSY_SHFT 63
22896 #define SH_DIAG_MSG_CNTRL_BUSY_MASK 0x8000000000000000
22898 /* ==================================================================== */
22899 /* Register "SH_DIAG_MSG_DATA0L" */
22900 /* Diagnostic Data, lower 64 bits */
22901 /* ==================================================================== */
22903 #define SH_DIAG_MSG_DATA0L 0x0000000110062080
22904 #define SH_DIAG_MSG_DATA0L_MASK 0xffffffffffffffff
22905 #define SH_DIAG_MSG_DATA0L_INIT 0x0000000000000000
22907 /* SH_DIAG_MSG_DATA0L_DATA_LOWER */
22908 /* Description: Lower 64 bits of Diagnositic Message Data */
22909 #define SH_DIAG_MSG_DATA0L_DATA_LOWER_SHFT 0
22910 #define SH_DIAG_MSG_DATA0L_DATA_LOWER_MASK 0xffffffffffffffff
22912 /* ==================================================================== */
22913 /* Register "SH_DIAG_MSG_DATA0U" */
22914 /* Diagnostice Data, upper 64 bits */
22915 /* ==================================================================== */
22917 #define SH_DIAG_MSG_DATA0U 0x0000000110062100
22918 #define SH_DIAG_MSG_DATA0U_MASK 0xffffffffffffffff
22919 #define SH_DIAG_MSG_DATA0U_INIT 0x0000000000000000
22921 /* SH_DIAG_MSG_DATA0U_DATA_UPPER */
22922 /* Description: Upper 64 bits of Diagnositic Message Data */
22923 #define SH_DIAG_MSG_DATA0U_DATA_UPPER_SHFT 0
22924 #define SH_DIAG_MSG_DATA0U_DATA_UPPER_MASK 0xffffffffffffffff
22926 /* ==================================================================== */
22927 /* Register "SH_DIAG_MSG_DATA1L" */
22928 /* Diagnostic Data, lower 64 bits */
22929 /* ==================================================================== */
22931 #define SH_DIAG_MSG_DATA1L 0x0000000110062180
22932 #define SH_DIAG_MSG_DATA1L_MASK 0xffffffffffffffff
22933 #define SH_DIAG_MSG_DATA1L_INIT 0x0000000000000000
22935 /* SH_DIAG_MSG_DATA1L_DATA_LOWER */
22936 /* Description: Lower 64 bits of Diagnositic Message Data */
22937 #define SH_DIAG_MSG_DATA1L_DATA_LOWER_SHFT 0
22938 #define SH_DIAG_MSG_DATA1L_DATA_LOWER_MASK 0xffffffffffffffff
22940 /* ==================================================================== */
22941 /* Register "SH_DIAG_MSG_DATA1U" */
22942 /* Diagnostice Data, upper 64 bits */
22943 /* ==================================================================== */
22945 #define SH_DIAG_MSG_DATA1U 0x0000000110062200
22946 #define SH_DIAG_MSG_DATA1U_MASK 0xffffffffffffffff
22947 #define SH_DIAG_MSG_DATA1U_INIT 0x0000000000000000
22949 /* SH_DIAG_MSG_DATA1U_DATA_UPPER */
22950 /* Description: Upper 64 bits of Diagnositic Message Data */
22951 #define SH_DIAG_MSG_DATA1U_DATA_UPPER_SHFT 0
22952 #define SH_DIAG_MSG_DATA1U_DATA_UPPER_MASK 0xffffffffffffffff
22954 /* ==================================================================== */
22955 /* Register "SH_DIAG_MSG_DATA2L" */
22956 /* Diagnostic Data, lower 64 bits */
22957 /* ==================================================================== */
22959 #define SH_DIAG_MSG_DATA2L 0x0000000110062280
22960 #define SH_DIAG_MSG_DATA2L_MASK 0xffffffffffffffff
22961 #define SH_DIAG_MSG_DATA2L_INIT 0x0000000000000000
22963 /* SH_DIAG_MSG_DATA2L_DATA_LOWER */
22964 /* Description: Lower 64 bits of Diagnositic Message Data */
22965 #define SH_DIAG_MSG_DATA2L_DATA_LOWER_SHFT 0
22966 #define SH_DIAG_MSG_DATA2L_DATA_LOWER_MASK 0xffffffffffffffff
22968 /* ==================================================================== */
22969 /* Register "SH_DIAG_MSG_DATA2U" */
22970 /* Diagnostice Data, upper 64 bits */
22971 /* ==================================================================== */
22973 #define SH_DIAG_MSG_DATA2U 0x0000000110062300
22974 #define SH_DIAG_MSG_DATA2U_MASK 0xffffffffffffffff
22975 #define SH_DIAG_MSG_DATA2U_INIT 0x0000000000000000
22977 /* SH_DIAG_MSG_DATA2U_DATA_UPPER */
22978 /* Description: Upper 64 bits of Diagnositic Message Data */
22979 #define SH_DIAG_MSG_DATA2U_DATA_UPPER_SHFT 0
22980 #define SH_DIAG_MSG_DATA2U_DATA_UPPER_MASK 0xffffffffffffffff
22982 /* ==================================================================== */
22983 /* Register "SH_DIAG_MSG_DATA3L" */
22984 /* Diagnostic Data, lower 64 bits */
22985 /* ==================================================================== */
22987 #define SH_DIAG_MSG_DATA3L 0x0000000110062380
22988 #define SH_DIAG_MSG_DATA3L_MASK 0xffffffffffffffff
22989 #define SH_DIAG_MSG_DATA3L_INIT 0x0000000000000000
22991 /* SH_DIAG_MSG_DATA3L_DATA_LOWER */
22992 /* Description: Lower 64 bits of Diagnositic Message Data */
22993 #define SH_DIAG_MSG_DATA3L_DATA_LOWER_SHFT 0
22994 #define SH_DIAG_MSG_DATA3L_DATA_LOWER_MASK 0xffffffffffffffff
22996 /* ==================================================================== */
22997 /* Register "SH_DIAG_MSG_DATA3U" */
22998 /* Diagnostice Data, upper 64 bits */
22999 /* ==================================================================== */
23001 #define SH_DIAG_MSG_DATA3U 0x0000000110062400
23002 #define SH_DIAG_MSG_DATA3U_MASK 0xffffffffffffffff
23003 #define SH_DIAG_MSG_DATA3U_INIT 0x0000000000000000
23005 /* SH_DIAG_MSG_DATA3U_DATA_UPPER */
23006 /* Description: Upper 64 bits of Diagnositic Message Data */
23007 #define SH_DIAG_MSG_DATA3U_DATA_UPPER_SHFT 0
23008 #define SH_DIAG_MSG_DATA3U_DATA_UPPER_MASK 0xffffffffffffffff
23010 /* ==================================================================== */
23011 /* Register "SH_DIAG_MSG_DATA4L" */
23012 /* Diagnostic Data, lower 64 bits */
23013 /* ==================================================================== */
23015 #define SH_DIAG_MSG_DATA4L 0x0000000110062480
23016 #define SH_DIAG_MSG_DATA4L_MASK 0xffffffffffffffff
23017 #define SH_DIAG_MSG_DATA4L_INIT 0x0000000000000000
23019 /* SH_DIAG_MSG_DATA4L_DATA_LOWER */
23020 /* Description: Lower 64 bits of Diagnositic Message Data */
23021 #define SH_DIAG_MSG_DATA4L_DATA_LOWER_SHFT 0
23022 #define SH_DIAG_MSG_DATA4L_DATA_LOWER_MASK 0xffffffffffffffff
23024 /* ==================================================================== */
23025 /* Register "SH_DIAG_MSG_DATA4U" */
23026 /* Diagnostice Data, upper 64 bits */
23027 /* ==================================================================== */
23029 #define SH_DIAG_MSG_DATA4U 0x0000000110062500
23030 #define SH_DIAG_MSG_DATA4U_MASK 0xffffffffffffffff
23031 #define SH_DIAG_MSG_DATA4U_INIT 0x0000000000000000
23033 /* SH_DIAG_MSG_DATA4U_DATA_UPPER */
23034 /* Description: Upper 64 bits of Diagnositic Message Data */
23035 #define SH_DIAG_MSG_DATA4U_DATA_UPPER_SHFT 0
23036 #define SH_DIAG_MSG_DATA4U_DATA_UPPER_MASK 0xffffffffffffffff
23038 /* ==================================================================== */
23039 /* Register "SH_DIAG_MSG_DATA5L" */
23040 /* Diagnostic Data, lower 64 bits */
23041 /* ==================================================================== */
23043 #define SH_DIAG_MSG_DATA5L 0x0000000110062580
23044 #define SH_DIAG_MSG_DATA5L_MASK 0xffffffffffffffff
23045 #define SH_DIAG_MSG_DATA5L_INIT 0x0000000000000000
23047 /* SH_DIAG_MSG_DATA5L_DATA_LOWER */
23048 /* Description: Lower 64 bits of Diagnositic Message Data */
23049 #define SH_DIAG_MSG_DATA5L_DATA_LOWER_SHFT 0
23050 #define SH_DIAG_MSG_DATA5L_DATA_LOWER_MASK 0xffffffffffffffff
23052 /* ==================================================================== */
23053 /* Register "SH_DIAG_MSG_DATA5U" */
23054 /* Diagnostice Data, upper 64 bits */
23055 /* ==================================================================== */
23057 #define SH_DIAG_MSG_DATA5U 0x0000000110062600
23058 #define SH_DIAG_MSG_DATA5U_MASK 0xffffffffffffffff
23059 #define SH_DIAG_MSG_DATA5U_INIT 0x0000000000000000
23061 /* SH_DIAG_MSG_DATA5U_DATA_UPPER */
23062 /* Description: Upper 64 bits of Diagnositic Message Data */
23063 #define SH_DIAG_MSG_DATA5U_DATA_UPPER_SHFT 0
23064 #define SH_DIAG_MSG_DATA5U_DATA_UPPER_MASK 0xffffffffffffffff
23066 /* ==================================================================== */
23067 /* Register "SH_DIAG_MSG_DATA6L" */
23068 /* Diagnostic Data, lower 64 bits */
23069 /* ==================================================================== */
23071 #define SH_DIAG_MSG_DATA6L 0x0000000110062680
23072 #define SH_DIAG_MSG_DATA6L_MASK 0xffffffffffffffff
23073 #define SH_DIAG_MSG_DATA6L_INIT 0x0000000000000000
23075 /* SH_DIAG_MSG_DATA6L_DATA_LOWER */
23076 /* Description: Lower 64 bits of Diagnositic Message Data */
23077 #define SH_DIAG_MSG_DATA6L_DATA_LOWER_SHFT 0
23078 #define SH_DIAG_MSG_DATA6L_DATA_LOWER_MASK 0xffffffffffffffff
23080 /* ==================================================================== */
23081 /* Register "SH_DIAG_MSG_DATA6U" */
23082 /* Diagnostice Data, upper 64 bits */
23083 /* ==================================================================== */
23085 #define SH_DIAG_MSG_DATA6U 0x0000000110062700
23086 #define SH_DIAG_MSG_DATA6U_MASK 0xffffffffffffffff
23087 #define SH_DIAG_MSG_DATA6U_INIT 0x0000000000000000
23089 /* SH_DIAG_MSG_DATA6U_DATA_UPPER */
23090 /* Description: Upper 64 bits of Diagnositic Message Data */
23091 #define SH_DIAG_MSG_DATA6U_DATA_UPPER_SHFT 0
23092 #define SH_DIAG_MSG_DATA6U_DATA_UPPER_MASK 0xffffffffffffffff
23094 /* ==================================================================== */
23095 /* Register "SH_DIAG_MSG_DATA7L" */
23096 /* Diagnostic Data, lower 64 bits */
23097 /* ==================================================================== */
23099 #define SH_DIAG_MSG_DATA7L 0x0000000110062780
23100 #define SH_DIAG_MSG_DATA7L_MASK 0xffffffffffffffff
23101 #define SH_DIAG_MSG_DATA7L_INIT 0x0000000000000000
23103 /* SH_DIAG_MSG_DATA7L_DATA_LOWER */
23104 /* Description: Lower 64 bits of Diagnositic Message Data */
23105 #define SH_DIAG_MSG_DATA7L_DATA_LOWER_SHFT 0
23106 #define SH_DIAG_MSG_DATA7L_DATA_LOWER_MASK 0xffffffffffffffff
23108 /* ==================================================================== */
23109 /* Register "SH_DIAG_MSG_DATA7U" */
23110 /* Diagnostice Data, upper 64 bits */
23111 /* ==================================================================== */
23113 #define SH_DIAG_MSG_DATA7U 0x0000000110062800
23114 #define SH_DIAG_MSG_DATA7U_MASK 0xffffffffffffffff
23115 #define SH_DIAG_MSG_DATA7U_INIT 0x0000000000000000
23117 /* SH_DIAG_MSG_DATA7U_DATA_UPPER */
23118 /* Description: Upper 64 bits of Diagnositic Message Data */
23119 #define SH_DIAG_MSG_DATA7U_DATA_UPPER_SHFT 0
23120 #define SH_DIAG_MSG_DATA7U_DATA_UPPER_MASK 0xffffffffffffffff
23122 /* ==================================================================== */
23123 /* Register "SH_DIAG_MSG_DATA8L" */
23124 /* Diagnostic Data, lower 64 bits */
23125 /* ==================================================================== */
23127 #define SH_DIAG_MSG_DATA8L 0x0000000110062880
23128 #define SH_DIAG_MSG_DATA8L_MASK 0xffffffffffffffff
23129 #define SH_DIAG_MSG_DATA8L_INIT 0x0000000000000000
23131 /* SH_DIAG_MSG_DATA8L_DATA_LOWER */
23132 /* Description: Lower 64 bits of Diagnositic Message Data */
23133 #define SH_DIAG_MSG_DATA8L_DATA_LOWER_SHFT 0
23134 #define SH_DIAG_MSG_DATA8L_DATA_LOWER_MASK 0xffffffffffffffff
23136 /* ==================================================================== */
23137 /* Register "SH_DIAG_MSG_DATA8U" */
23138 /* Diagnostice Data, upper 64 bits */
23139 /* ==================================================================== */
23141 #define SH_DIAG_MSG_DATA8U 0x0000000110062900
23142 #define SH_DIAG_MSG_DATA8U_MASK 0xffffffffffffffff
23143 #define SH_DIAG_MSG_DATA8U_INIT 0x0000000000000000
23145 /* SH_DIAG_MSG_DATA8U_DATA_UPPER */
23146 /* Description: Upper 64 bits of Diagnositic Message Data */
23147 #define SH_DIAG_MSG_DATA8U_DATA_UPPER_SHFT 0
23148 #define SH_DIAG_MSG_DATA8U_DATA_UPPER_MASK 0xffffffffffffffff
23150 /* ==================================================================== */
23151 /* Register "SH_DIAG_MSG_HDR0" */
23152 /* Diagnostice Data, lower 64 bits of header */
23153 /* ==================================================================== */
23155 #define SH_DIAG_MSG_HDR0 0x0000000110062980
23156 #define SH_DIAG_MSG_HDR0_MASK 0xffffffffffffffff
23157 #define SH_DIAG_MSG_HDR0_INIT 0x0000000000000000
23159 /* SH_DIAG_MSG_HDR0_HEADER0 */
23160 /* Description: Lower 64 bits of Diagnositic Message Header */
23161 #define SH_DIAG_MSG_HDR0_HEADER0_SHFT 0
23162 #define SH_DIAG_MSG_HDR0_HEADER0_MASK 0xffffffffffffffff
23164 /* ==================================================================== */
23165 /* Register "SH_DIAG_MSG_HDR1" */
23166 /* Diagnostice Data, upper 64 bits of header */
23167 /* ==================================================================== */
23169 #define SH_DIAG_MSG_HDR1 0x0000000110062a00
23170 #define SH_DIAG_MSG_HDR1_MASK 0xffffffffffffffff
23171 #define SH_DIAG_MSG_HDR1_INIT 0x0000000000000000
23173 /* SH_DIAG_MSG_HDR1_HEADER1 */
23174 /* Description: Upper 64 bits of Diagnositic Message Header */
23175 #define SH_DIAG_MSG_HDR1_HEADER1_SHFT 0
23176 #define SH_DIAG_MSG_HDR1_HEADER1_MASK 0xffffffffffffffff
23178 /* ==================================================================== */
23179 /* Register "SH_DEBUG_SELECT" */
23180 /* SHub Debug Port Select */
23181 /* ==================================================================== */
23183 #define SH_DEBUG_SELECT 0x0000000110063000
23184 #define SH_DEBUG_SELECT_MASK 0x8fffffffffffffff
23185 #define SH_DEBUG_SELECT_INIT 0x0000e38e38e38e38
23187 /* SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL */
23188 /* Description: Nibble0_nibble_select */
23189 #define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 0
23190 #define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000007
23192 /* SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL */
23193 /* Description: Nibble0_chiplet_select */
23194 #define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 3
23195 #define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000038
23197 /* SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL */
23198 /* Description: Nibble1_nibble_select */
23199 #define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 6
23200 #define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x00000000000001c0
23202 /* SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL */
23203 /* Description: Nibble1_chiplet_select */
23204 #define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 9
23205 #define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000e00
23207 /* SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL */
23208 /* Description: Nibble2_nibble_select */
23209 #define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 12
23210 #define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000007000
23212 /* SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL */
23213 /* Description: Nibble2_chiplet_select */
23214 #define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 15
23215 #define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000038000
23217 /* SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL */
23218 /* Description: Nibble3_nibble_select */
23219 #define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 18
23220 #define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x00000000001c0000
23222 /* SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL */
23223 /* Description: Nibble3_chiplet_select */
23224 #define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 21
23225 #define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000000e00000
23227 /* SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL */
23228 /* Description: Nibble4_nibble_select */
23229 #define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 24
23230 #define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000000007000000
23232 /* SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL */
23233 /* Description: Nibble4_chiplet_select */
23234 #define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 27
23235 #define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000038000000
23237 /* SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL */
23238 /* Description: Nibble5_nibble_select */
23239 #define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 30
23240 #define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x00000001c0000000
23242 /* SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL */
23243 /* Description: Nibble5_chiplet_select */
23244 #define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 33
23245 #define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000000e00000000
23247 /* SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL */
23248 /* Description: Nibble6_nibble_select */
23249 #define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 36
23250 #define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0000007000000000
23252 /* SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL */
23253 /* Description: Nibble6_chiplet_select */
23254 #define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 39
23255 #define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0000038000000000
23257 /* SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL */
23258 /* Description: Nibble7_nibble_select */
23259 #define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 42
23260 #define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x00001c0000000000
23262 /* SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL */
23263 /* Description: Nibble7_chiplet_select */
23264 #define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 45
23265 #define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0000e00000000000
23267 /* SH_DEBUG_SELECT_DEBUG_II_SEL */
23268 /* Description: Select bits to II port */
23269 #define SH_DEBUG_SELECT_DEBUG_II_SEL_SHFT 48
23270 #define SH_DEBUG_SELECT_DEBUG_II_SEL_MASK 0x0007000000000000
23272 /* SH_DEBUG_SELECT_SEL_II */
23273 /* Description: Select II to debug port */
23274 #define SH_DEBUG_SELECT_SEL_II_SHFT 51
23275 #define SH_DEBUG_SELECT_SEL_II_MASK 0x0ff8000000000000
23277 /* SH_DEBUG_SELECT_TRIGGER_ENABLE */
23278 /* Description: Enable trigger on bit 32 of Analyzer data */
23279 #define SH_DEBUG_SELECT_TRIGGER_ENABLE_SHFT 63
23280 #define SH_DEBUG_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
23282 /* ==================================================================== */
23283 /* Register "SH_TRIGGER_COMPARE_MASK" */
23284 /* SHub Trigger Compare Mask */
23285 /* ==================================================================== */
23287 #define SH_TRIGGER_COMPARE_MASK 0x0000000110063080
23288 #define SH_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff
23289 #define SH_TRIGGER_COMPARE_MASK_INIT 0x0000000000000000
23291 /* SH_TRIGGER_COMPARE_MASK_MASK */
23292 /* Description: SHub Trigger Compare Mask */
23293 #define SH_TRIGGER_COMPARE_MASK_MASK_SHFT 0
23294 #define SH_TRIGGER_COMPARE_MASK_MASK_MASK 0x00000000ffffffff
23296 /* ==================================================================== */
23297 /* Register "SH_TRIGGER_COMPARE_PATTERN" */
23298 /* SHub Trigger Compare Pattern */
23299 /* ==================================================================== */
23301 #define SH_TRIGGER_COMPARE_PATTERN 0x0000000110063100
23302 #define SH_TRIGGER_COMPARE_PATTERN_MASK 0x00000000ffffffff
23303 #define SH_TRIGGER_COMPARE_PATTERN_INIT 0x0000000000000000
23305 /* SH_TRIGGER_COMPARE_PATTERN_DATA */
23306 /* Description: SHub Trigger Compare Pattern */
23307 #define SH_TRIGGER_COMPARE_PATTERN_DATA_SHFT 0
23308 #define SH_TRIGGER_COMPARE_PATTERN_DATA_MASK 0x00000000ffffffff
23310 /* ==================================================================== */
23311 /* Register "SH_TRIGGER_SEL" */
23312 /* Trigger select for SHUB debug port */
23313 /* ==================================================================== */
23315 #define SH_TRIGGER_SEL 0x0000000110063180
23316 #define SH_TRIGGER_SEL_MASK 0x7777777777777777
23317 #define SH_TRIGGER_SEL_INIT 0x0000000000000000
23319 /* SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL */
23320 /* Description: Nibble 0 input select */
23321 #define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_SHFT 0
23322 #define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
23324 /* SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL */
23325 /* Description: Nibble 0 Nibble select */
23326 #define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
23327 #define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
23329 /* SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL */
23330 /* Description: Nibble 1 input select */
23331 #define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_SHFT 8
23332 #define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
23334 /* SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL */
23335 /* Description: Nibble 1 Nibble select */
23336 #define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
23337 #define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
23339 /* SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL */
23340 /* Description: Nibble 2 input select */
23341 #define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_SHFT 16
23342 #define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
23344 /* SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL */
23345 /* Description: Nibble 2 Nibble select */
23346 #define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
23347 #define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
23349 /* SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL */
23350 /* Description: Nibble 3 input select */
23351 #define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_SHFT 24
23352 #define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
23354 /* SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL */
23355 /* Description: Nibble 3 Nibble select */
23356 #define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
23357 #define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
23359 /* SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL */
23360 /* Description: Nibble 4 input select */
23361 #define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_SHFT 32
23362 #define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
23364 /* SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL */
23365 /* Description: Nibble 4 Nibble select */
23366 #define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
23367 #define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
23369 /* SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL */
23370 /* Description: Nibble 5 input select */
23371 #define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_SHFT 40
23372 #define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
23374 /* SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL */
23375 /* Description: Nibble 5 Nibble select */
23376 #define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
23377 #define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
23379 /* SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL */
23380 /* Description: Nibble 6 input select */
23381 #define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_SHFT 48
23382 #define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
23384 /* SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL */
23385 /* Description: Nibble 6 Nibble select */
23386 #define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
23387 #define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
23389 /* SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL */
23390 /* Description: Nibble 7 input select */
23391 #define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_SHFT 56
23392 #define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
23394 /* SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL */
23395 /* Description: Nibble 7 Nibble select */
23396 #define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
23397 #define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
23399 /* ==================================================================== */
23400 /* Register "SH_STOP_CLK_CONTROL" */
23401 /* Stop Clock Control */
23402 /* ==================================================================== */
23404 #define SH_STOP_CLK_CONTROL 0x0000000110064000
23405 #define SH_STOP_CLK_CONTROL_MASK 0x00000000000000ff
23406 #define SH_STOP_CLK_CONTROL_INIT 0x00000000000000e0
23408 /* SH_STOP_CLK_CONTROL_STIMULUS */
23409 /* Description: Counter stimulus */
23410 #define SH_STOP_CLK_CONTROL_STIMULUS_SHFT 0
23411 #define SH_STOP_CLK_CONTROL_STIMULUS_MASK 0x000000000000001f
23413 /* SH_STOP_CLK_CONTROL_EVENT */
23414 /* Description: Counter event select (0-greater than, 1-equal) */
23415 #define SH_STOP_CLK_CONTROL_EVENT_SHFT 5
23416 #define SH_STOP_CLK_CONTROL_EVENT_MASK 0x0000000000000020
23418 /* SH_STOP_CLK_CONTROL_POLARITY */
23419 /* Description: Counter polarity select (0-negative edge, 1-positiv */
23421 #define SH_STOP_CLK_CONTROL_POLARITY_SHFT 6
23422 #define SH_STOP_CLK_CONTROL_POLARITY_MASK 0x0000000000000040
23424 /* SH_STOP_CLK_CONTROL_MODE */
23425 /* Description: Counter mode select (0-internal, 1-external) */
23426 #define SH_STOP_CLK_CONTROL_MODE_SHFT 7
23427 #define SH_STOP_CLK_CONTROL_MODE_MASK 0x0000000000000080
23429 /* ==================================================================== */
23430 /* Register "SH_STOP_CLK_DELAY_PHASE" */
23431 /* Stop Clock Delay Phase */
23432 /* ==================================================================== */
23434 #define SH_STOP_CLK_DELAY_PHASE 0x0000000110064080
23435 #define SH_STOP_CLK_DELAY_PHASE_MASK 0x00000000000000ff
23436 #define SH_STOP_CLK_DELAY_PHASE_INIT 0x0000000000000000
23438 /* SH_STOP_CLK_DELAY_PHASE_DELAY */
23439 /* Description: Delay phase */
23440 #define SH_STOP_CLK_DELAY_PHASE_DELAY_SHFT 0
23441 #define SH_STOP_CLK_DELAY_PHASE_DELAY_MASK 0x00000000000000ff
23443 /* ==================================================================== */
23444 /* Register "SH_TSF_ARM_MASK" */
23445 /* Trigger sequencing facility arm mask */
23446 /* ==================================================================== */
23448 #define SH_TSF_ARM_MASK 0x0000000110065000
23449 #define SH_TSF_ARM_MASK_MASK 0xffffffffffffffff
23450 #define SH_TSF_ARM_MASK_INIT 0x0000000000000000
23452 /* SH_TSF_ARM_MASK_MASK */
23453 /* Description: Trigger sequencing facility arm mask */
23454 #define SH_TSF_ARM_MASK_MASK_SHFT 0
23455 #define SH_TSF_ARM_MASK_MASK_MASK 0xffffffffffffffff
23457 /* ==================================================================== */
23458 /* Register "SH_TSF_COUNTER_PRESETS" */
23459 /* Trigger sequencing facility counter presets */
23460 /* ==================================================================== */
23462 #define SH_TSF_COUNTER_PRESETS 0x0000000110065080
23463 #define SH_TSF_COUNTER_PRESETS_MASK 0xffffffffffffffff
23464 #define SH_TSF_COUNTER_PRESETS_INIT 0x0000000000000000
23466 /* SH_TSF_COUNTER_PRESETS_COUNT_32 */
23467 /* Description: Trigger sequencing facility counter 32 */
23468 #define SH_TSF_COUNTER_PRESETS_COUNT_32_SHFT 0
23469 #define SH_TSF_COUNTER_PRESETS_COUNT_32_MASK 0x00000000ffffffff
23471 /* SH_TSF_COUNTER_PRESETS_COUNT_16 */
23472 /* Description: Trigger sequencing facility counter 16 */
23473 #define SH_TSF_COUNTER_PRESETS_COUNT_16_SHFT 32
23474 #define SH_TSF_COUNTER_PRESETS_COUNT_16_MASK 0x0000ffff00000000
23476 /* SH_TSF_COUNTER_PRESETS_COUNT_8B */
23477 /* Description: Trigger sequencing facility counter 8b */
23478 #define SH_TSF_COUNTER_PRESETS_COUNT_8B_SHFT 48
23479 #define SH_TSF_COUNTER_PRESETS_COUNT_8B_MASK 0x00ff000000000000
23481 /* SH_TSF_COUNTER_PRESETS_COUNT_8A */
23482 /* Description: Trigger sequencing facility counter 8a */
23483 #define SH_TSF_COUNTER_PRESETS_COUNT_8A_SHFT 56
23484 #define SH_TSF_COUNTER_PRESETS_COUNT_8A_MASK 0xff00000000000000
23486 /* ==================================================================== */
23487 /* Register "SH_TSF_DECREMENT_CTL" */
23488 /* Trigger sequencing facility counter decrement control */
23489 /* ==================================================================== */
23491 #define SH_TSF_DECREMENT_CTL 0x0000000110065100
23492 #define SH_TSF_DECREMENT_CTL_MASK 0x000000000000ffff
23493 #define SH_TSF_DECREMENT_CTL_INIT 0x0000000000000000
23495 /* SH_TSF_DECREMENT_CTL_CTL */
23496 /* Description: Trigger sequencing facility counter decrement contr */
23497 #define SH_TSF_DECREMENT_CTL_CTL_SHFT 0
23498 #define SH_TSF_DECREMENT_CTL_CTL_MASK 0x000000000000ffff
23500 /* ==================================================================== */
23501 /* Register "SH_TSF_DIAG_MSG_CTL" */
23502 /* Trigger sequencing facility diagnostic message control */
23503 /* ==================================================================== */
23505 #define SH_TSF_DIAG_MSG_CTL 0x0000000110065180
23506 #define SH_TSF_DIAG_MSG_CTL_MASK 0x00000000000000ff
23507 #define SH_TSF_DIAG_MSG_CTL_INIT 0x0000000000000000
23509 /* SH_TSF_DIAG_MSG_CTL_ENABLE */
23510 /* Description: Trigger sequencing facility diagnostic message cont */
23511 #define SH_TSF_DIAG_MSG_CTL_ENABLE_SHFT 0
23512 #define SH_TSF_DIAG_MSG_CTL_ENABLE_MASK 0x00000000000000ff
23514 /* ==================================================================== */
23515 /* Register "SH_TSF_DISARM_MASK" */
23516 /* Trigger sequencing facility disarm mask */
23517 /* ==================================================================== */
23519 #define SH_TSF_DISARM_MASK 0x0000000110065200
23520 #define SH_TSF_DISARM_MASK_MASK 0xffffffffffffffff
23521 #define SH_TSF_DISARM_MASK_INIT 0x0000000000000000
23523 /* SH_TSF_DISARM_MASK_MASK */
23524 /* Description: Trigger sequencing facility disarm mask */
23525 #define SH_TSF_DISARM_MASK_MASK_SHFT 0
23526 #define SH_TSF_DISARM_MASK_MASK_MASK 0xffffffffffffffff
23528 /* ==================================================================== */
23529 /* Register "SH_TSF_ENABLE_CTL" */
23530 /* Trigger sequencing facility counter enable control */
23531 /* ==================================================================== */
23533 #define SH_TSF_ENABLE_CTL 0x0000000110065280
23534 #define SH_TSF_ENABLE_CTL_MASK 0x000000000000ffff
23535 #define SH_TSF_ENABLE_CTL_INIT 0x0000000000000000
23537 /* SH_TSF_ENABLE_CTL_CTL */
23538 /* Description: Trigger sequencing facility counter enable control */
23539 #define SH_TSF_ENABLE_CTL_CTL_SHFT 0
23540 #define SH_TSF_ENABLE_CTL_CTL_MASK 0x000000000000ffff
23542 /* ==================================================================== */
23543 /* Register "SH_TSF_SOFTWARE_ARM" */
23544 /* Trigger sequencing facility software arm */
23545 /* ==================================================================== */
23547 #define SH_TSF_SOFTWARE_ARM 0x0000000110065300
23548 #define SH_TSF_SOFTWARE_ARM_MASK 0x00000000000000ff
23549 #define SH_TSF_SOFTWARE_ARM_INIT 0x0000000000000000
23551 /* SH_TSF_SOFTWARE_ARM_BIT0 */
23552 /* Description: Trigger sequencing facility software arm bit 0 */
23553 #define SH_TSF_SOFTWARE_ARM_BIT0_SHFT 0
23554 #define SH_TSF_SOFTWARE_ARM_BIT0_MASK 0x0000000000000001
23556 /* SH_TSF_SOFTWARE_ARM_BIT1 */
23557 /* Description: Trigger sequencing facility software arm bit 1 */
23558 #define SH_TSF_SOFTWARE_ARM_BIT1_SHFT 1
23559 #define SH_TSF_SOFTWARE_ARM_BIT1_MASK 0x0000000000000002
23561 /* SH_TSF_SOFTWARE_ARM_BIT2 */
23562 /* Description: Trigger sequencing facility software arm bit 2 */
23563 #define SH_TSF_SOFTWARE_ARM_BIT2_SHFT 2
23564 #define SH_TSF_SOFTWARE_ARM_BIT2_MASK 0x0000000000000004
23566 /* SH_TSF_SOFTWARE_ARM_BIT3 */
23567 /* Description: Trigger sequencing facility software arm bit 3 */
23568 #define SH_TSF_SOFTWARE_ARM_BIT3_SHFT 3
23569 #define SH_TSF_SOFTWARE_ARM_BIT3_MASK 0x0000000000000008
23571 /* SH_TSF_SOFTWARE_ARM_BIT4 */
23572 /* Description: Trigger sequencing facility software arm bit 4 */
23573 #define SH_TSF_SOFTWARE_ARM_BIT4_SHFT 4
23574 #define SH_TSF_SOFTWARE_ARM_BIT4_MASK 0x0000000000000010
23576 /* SH_TSF_SOFTWARE_ARM_BIT5 */
23577 /* Description: Trigger sequencing facility software arm bit 5 */
23578 #define SH_TSF_SOFTWARE_ARM_BIT5_SHFT 5
23579 #define SH_TSF_SOFTWARE_ARM_BIT5_MASK 0x0000000000000020
23581 /* SH_TSF_SOFTWARE_ARM_BIT6 */
23582 /* Description: Trigger sequencing facility software arm bit 6 */
23583 #define SH_TSF_SOFTWARE_ARM_BIT6_SHFT 6
23584 #define SH_TSF_SOFTWARE_ARM_BIT6_MASK 0x0000000000000040
23586 /* SH_TSF_SOFTWARE_ARM_BIT7 */
23587 /* Description: Trigger sequencing facility software arm bit 7 */
23588 #define SH_TSF_SOFTWARE_ARM_BIT7_SHFT 7
23589 #define SH_TSF_SOFTWARE_ARM_BIT7_MASK 0x0000000000000080
23591 /* ==================================================================== */
23592 /* Register "SH_TSF_SOFTWARE_DISARM" */
23593 /* Trigger sequencing facility software disarm */
23594 /* ==================================================================== */
23596 #define SH_TSF_SOFTWARE_DISARM 0x0000000110065380
23597 #define SH_TSF_SOFTWARE_DISARM_MASK 0x00000000000000ff
23598 #define SH_TSF_SOFTWARE_DISARM_INIT 0x0000000000000000
23600 /* SH_TSF_SOFTWARE_DISARM_BIT0 */
23601 /* Description: Trigger sequencing facility software disarm bit 0 */
23602 #define SH_TSF_SOFTWARE_DISARM_BIT0_SHFT 0
23603 #define SH_TSF_SOFTWARE_DISARM_BIT0_MASK 0x0000000000000001
23605 /* SH_TSF_SOFTWARE_DISARM_BIT1 */
23606 /* Description: Trigger sequencing facility software disarm bit 1 */
23607 #define SH_TSF_SOFTWARE_DISARM_BIT1_SHFT 1
23608 #define SH_TSF_SOFTWARE_DISARM_BIT1_MASK 0x0000000000000002
23610 /* SH_TSF_SOFTWARE_DISARM_BIT2 */
23611 /* Description: Trigger sequencing facility software disarm bit 2 */
23612 #define SH_TSF_SOFTWARE_DISARM_BIT2_SHFT 2
23613 #define SH_TSF_SOFTWARE_DISARM_BIT2_MASK 0x0000000000000004
23615 /* SH_TSF_SOFTWARE_DISARM_BIT3 */
23616 /* Description: Trigger sequencing facility software disarm bit 3 */
23617 #define SH_TSF_SOFTWARE_DISARM_BIT3_SHFT 3
23618 #define SH_TSF_SOFTWARE_DISARM_BIT3_MASK 0x0000000000000008
23620 /* SH_TSF_SOFTWARE_DISARM_BIT4 */
23621 /* Description: Trigger sequencing facility software disarm bit 4 */
23622 #define SH_TSF_SOFTWARE_DISARM_BIT4_SHFT 4
23623 #define SH_TSF_SOFTWARE_DISARM_BIT4_MASK 0x0000000000000010
23625 /* SH_TSF_SOFTWARE_DISARM_BIT5 */
23626 /* Description: Trigger sequencing facility software disarm bit 5 */
23627 #define SH_TSF_SOFTWARE_DISARM_BIT5_SHFT 5
23628 #define SH_TSF_SOFTWARE_DISARM_BIT5_MASK 0x0000000000000020
23630 /* SH_TSF_SOFTWARE_DISARM_BIT6 */
23631 /* Description: Trigger sequencing facility software disarm bit 6 */
23632 #define SH_TSF_SOFTWARE_DISARM_BIT6_SHFT 6
23633 #define SH_TSF_SOFTWARE_DISARM_BIT6_MASK 0x0000000000000040
23635 /* SH_TSF_SOFTWARE_DISARM_BIT7 */
23636 /* Description: Trigger sequencing facility software disarm bit 7 */
23637 #define SH_TSF_SOFTWARE_DISARM_BIT7_SHFT 7
23638 #define SH_TSF_SOFTWARE_DISARM_BIT7_MASK 0x0000000000000080
23640 /* ==================================================================== */
23641 /* Register "SH_TSF_SOFTWARE_TRIGGERED" */
23642 /* Trigger sequencing facility software triggered */
23643 /* ==================================================================== */
23645 #define SH_TSF_SOFTWARE_TRIGGERED 0x0000000110065400
23646 #define SH_TSF_SOFTWARE_TRIGGERED_MASK 0x00000000000000ff
23647 #define SH_TSF_SOFTWARE_TRIGGERED_INIT 0x0000000000000000
23649 /* SH_TSF_SOFTWARE_TRIGGERED_BIT0 */
23650 /* Description: Trigger sequencing facility software triggered bit */
23651 #define SH_TSF_SOFTWARE_TRIGGERED_BIT0_SHFT 0
23652 #define SH_TSF_SOFTWARE_TRIGGERED_BIT0_MASK 0x0000000000000001
23654 /* SH_TSF_SOFTWARE_TRIGGERED_BIT1 */
23655 /* Description: Trigger sequencing facility software triggered bit */
23656 #define SH_TSF_SOFTWARE_TRIGGERED_BIT1_SHFT 1
23657 #define SH_TSF_SOFTWARE_TRIGGERED_BIT1_MASK 0x0000000000000002
23659 /* SH_TSF_SOFTWARE_TRIGGERED_BIT2 */
23660 /* Description: Trigger sequencing facility software triggered bit */
23661 #define SH_TSF_SOFTWARE_TRIGGERED_BIT2_SHFT 2
23662 #define SH_TSF_SOFTWARE_TRIGGERED_BIT2_MASK 0x0000000000000004
23664 /* SH_TSF_SOFTWARE_TRIGGERED_BIT3 */
23665 /* Description: Trigger sequencing facility software triggered bit */
23666 #define SH_TSF_SOFTWARE_TRIGGERED_BIT3_SHFT 3
23667 #define SH_TSF_SOFTWARE_TRIGGERED_BIT3_MASK 0x0000000000000008
23669 /* SH_TSF_SOFTWARE_TRIGGERED_BIT4 */
23670 /* Description: Trigger sequencing facility software triggered bit */
23671 #define SH_TSF_SOFTWARE_TRIGGERED_BIT4_SHFT 4
23672 #define SH_TSF_SOFTWARE_TRIGGERED_BIT4_MASK 0x0000000000000010
23674 /* SH_TSF_SOFTWARE_TRIGGERED_BIT5 */
23675 /* Description: Trigger sequencing facility software triggered bit */
23676 #define SH_TSF_SOFTWARE_TRIGGERED_BIT5_SHFT 5
23677 #define SH_TSF_SOFTWARE_TRIGGERED_BIT5_MASK 0x0000000000000020
23679 /* SH_TSF_SOFTWARE_TRIGGERED_BIT6 */
23680 /* Description: Trigger sequencing facility software triggered bit */
23681 #define SH_TSF_SOFTWARE_TRIGGERED_BIT6_SHFT 6
23682 #define SH_TSF_SOFTWARE_TRIGGERED_BIT6_MASK 0x0000000000000040
23684 /* SH_TSF_SOFTWARE_TRIGGERED_BIT7 */
23685 /* Description: Trigger sequencing facility software triggered bit */
23686 #define SH_TSF_SOFTWARE_TRIGGERED_BIT7_SHFT 7
23687 #define SH_TSF_SOFTWARE_TRIGGERED_BIT7_MASK 0x0000000000000080
23689 /* ==================================================================== */
23690 /* Register "SH_TSF_TRIGGER_MASK" */
23691 /* Trigger sequencing facility trigger mask */
23692 /* ==================================================================== */
23694 #define SH_TSF_TRIGGER_MASK 0x0000000110065480
23695 #define SH_TSF_TRIGGER_MASK_MASK 0xffffffffffffffff
23696 #define SH_TSF_TRIGGER_MASK_INIT 0x0000000000000000
23698 /* SH_TSF_TRIGGER_MASK_MASK */
23699 /* Description: Trigger sequencing facility trigger mask */
23700 #define SH_TSF_TRIGGER_MASK_MASK_SHFT 0
23701 #define SH_TSF_TRIGGER_MASK_MASK_MASK 0xffffffffffffffff
23703 /* ==================================================================== */
23704 /* Register "SH_VEC_DATA" */
23705 /* Vector Write Request Message Data */
23706 /* ==================================================================== */
23708 #define SH_VEC_DATA 0x0000000110066000
23709 #define SH_VEC_DATA_MASK 0xffffffffffffffff
23710 #define SH_VEC_DATA_INIT 0x0000000000000000
23712 /* SH_VEC_DATA_DATA */
23713 /* Description: Data */
23714 #define SH_VEC_DATA_DATA_SHFT 0
23715 #define SH_VEC_DATA_DATA_MASK 0xffffffffffffffff
23717 /* ==================================================================== */
23718 /* Register "SH_VEC_PARMS" */
23719 /* Vector Message Parameters Register */
23720 /* ==================================================================== */
23722 #define SH_VEC_PARMS 0x0000000110066080
23723 #define SH_VEC_PARMS_MASK 0xc0003ffffffffffb
23724 #define SH_VEC_PARMS_INIT 0x0000000000000000
23726 /* SH_VEC_PARMS_TYPE */
23727 /* Description: Vector Request Message Type */
23728 #define SH_VEC_PARMS_TYPE_SHFT 0
23729 #define SH_VEC_PARMS_TYPE_MASK 0x0000000000000001
23731 /* SH_VEC_PARMS_NI_PORT */
23732 /* Description: Network Interface Port Select */
23733 #define SH_VEC_PARMS_NI_PORT_SHFT 1
23734 #define SH_VEC_PARMS_NI_PORT_MASK 0x0000000000000002
23736 /* SH_VEC_PARMS_ADDRESS */
23737 /* Description: Address[37:6] */
23738 #define SH_VEC_PARMS_ADDRESS_SHFT 3
23739 #define SH_VEC_PARMS_ADDRESS_MASK 0x00000007fffffff8
23741 /* SH_VEC_PARMS_PIO_ID */
23742 /* Description: PIO ID */
23743 #define SH_VEC_PARMS_PIO_ID_SHFT 35
23744 #define SH_VEC_PARMS_PIO_ID_MASK 0x00003ff800000000
23746 /* SH_VEC_PARMS_START */
23747 /* Description: Start */
23748 #define SH_VEC_PARMS_START_SHFT 62
23749 #define SH_VEC_PARMS_START_MASK 0x4000000000000000
23751 /* SH_VEC_PARMS_BUSY */
23752 /* Description: Busy */
23753 #define SH_VEC_PARMS_BUSY_SHFT 63
23754 #define SH_VEC_PARMS_BUSY_MASK 0x8000000000000000
23756 /* ==================================================================== */
23757 /* Register "SH_VEC_ROUTE" */
23758 /* Vector Request Message Route */
23759 /* ==================================================================== */
23761 #define SH_VEC_ROUTE 0x0000000110066100
23762 #define SH_VEC_ROUTE_MASK 0xffffffffffffffff
23763 #define SH_VEC_ROUTE_INIT 0x0000000000000000
23765 /* SH_VEC_ROUTE_ROUTE */
23766 /* Description: Route */
23767 #define SH_VEC_ROUTE_ROUTE_SHFT 0
23768 #define SH_VEC_ROUTE_ROUTE_MASK 0xffffffffffffffff
23770 /* ==================================================================== */
23771 /* Register "SH_CPU_PERM" */
23772 /* CPU MMR Access Permission Bits */
23773 /* ==================================================================== */
23775 #define SH_CPU_PERM 0x0000000110060000
23776 #define SH_CPU_PERM_MASK 0xffffffffffffffff
23777 #define SH_CPU_PERM_INIT 0xffffffffffffffff
23779 /* SH_CPU_PERM_ACCESS_BITS */
23780 /* Description: Access Bits */
23781 #define SH_CPU_PERM_ACCESS_BITS_SHFT 0
23782 #define SH_CPU_PERM_ACCESS_BITS_MASK 0xffffffffffffffff
23784 /* ==================================================================== */
23785 /* Register "SH_CPU_PERM_OVR" */
23786 /* CPU MMR Access Permission Override */
23787 /* ==================================================================== */
23789 #define SH_CPU_PERM_OVR 0x0000000110060080
23790 #define SH_CPU_PERM_OVR_MASK 0xffffffffffffffff
23791 #define SH_CPU_PERM_OVR_INIT 0x0000000000000000
23793 /* SH_CPU_PERM_OVR_OVERRIDE */
23794 /* Description: Override */
23795 #define SH_CPU_PERM_OVR_OVERRIDE_SHFT 0
23796 #define SH_CPU_PERM_OVR_OVERRIDE_MASK 0xffffffffffffffff
23798 /* ==================================================================== */
23799 /* Register "SH_EXT_IO_PERM" */
23800 /* External IO MMR Access Permission Bits */
23801 /* ==================================================================== */
23803 #define SH_EXT_IO_PERM 0x0000000110060100
23804 #define SH_EXT_IO_PERM_MASK 0xffffffffffffffff
23805 #define SH_EXT_IO_PERM_INIT 0x0000000000000000
23807 /* SH_EXT_IO_PERM_ACCESS_BITS */
23808 /* Description: Access Bits */
23809 #define SH_EXT_IO_PERM_ACCESS_BITS_SHFT 0
23810 #define SH_EXT_IO_PERM_ACCESS_BITS_MASK 0xffffffffffffffff
23812 /* ==================================================================== */
23813 /* Register "SH_EXT_IOI_ACCESS" */
23814 /* External IO Interrupt Access Permission Bits */
23815 /* ==================================================================== */
23817 #define SH_EXT_IOI_ACCESS 0x0000000110060180
23818 #define SH_EXT_IOI_ACCESS_MASK 0xffffffffffffffff
23819 #define SH_EXT_IOI_ACCESS_INIT 0xffffffffffffffff
23821 /* SH_EXT_IOI_ACCESS_ACCESS_BITS */
23822 /* Description: Access Bits */
23823 #define SH_EXT_IOI_ACCESS_ACCESS_BITS_SHFT 0
23824 #define SH_EXT_IOI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff
23826 /* ==================================================================== */
23827 /* Register "SH_GC_FIL_CTRL" */
23828 /* SHub Global Clock Filter Control */
23829 /* ==================================================================== */
23831 #define SH_GC_FIL_CTRL 0x0000000110060200
23832 #define SH_GC_FIL_CTRL_MASK 0x03ff3ff3ff1fff1f
23833 #define SH_GC_FIL_CTRL_INIT 0x0000000000000000
23835 /* SH_GC_FIL_CTRL_OFFSET */
23836 /* Description: Offset */
23837 #define SH_GC_FIL_CTRL_OFFSET_SHFT 0
23838 #define SH_GC_FIL_CTRL_OFFSET_MASK 0x000000000000001f
23840 /* SH_GC_FIL_CTRL_MASK_COUNTER */
23841 /* Description: Mask Counter */
23842 #define SH_GC_FIL_CTRL_MASK_COUNTER_SHFT 8
23843 #define SH_GC_FIL_CTRL_MASK_COUNTER_MASK 0x00000000000fff00
23845 /* SH_GC_FIL_CTRL_MASK_ENABLE */
23846 /* Description: Mask Enable */
23847 #define SH_GC_FIL_CTRL_MASK_ENABLE_SHFT 20
23848 #define SH_GC_FIL_CTRL_MASK_ENABLE_MASK 0x0000000000100000
23850 /* SH_GC_FIL_CTRL_DROPOUT_COUNTER */
23851 /* Description: Dropout Counter */
23852 #define SH_GC_FIL_CTRL_DROPOUT_COUNTER_SHFT 24
23853 #define SH_GC_FIL_CTRL_DROPOUT_COUNTER_MASK 0x00000003ff000000
23855 /* SH_GC_FIL_CTRL_DROPOUT_THRESH */
23856 /* Description: Dropout threshold */
23857 #define SH_GC_FIL_CTRL_DROPOUT_THRESH_SHFT 36
23858 #define SH_GC_FIL_CTRL_DROPOUT_THRESH_MASK 0x00003ff000000000
23860 /* SH_GC_FIL_CTRL_ERROR_COUNTER */
23861 /* Description: Error counter */
23862 #define SH_GC_FIL_CTRL_ERROR_COUNTER_SHFT 48
23863 #define SH_GC_FIL_CTRL_ERROR_COUNTER_MASK 0x03ff000000000000
23865 /* ==================================================================== */
23866 /* Register "SH_GC_SRC_CTRL" */
23867 /* SHub Global Clock Control */
23868 /* ==================================================================== */
23870 #define SH_GC_SRC_CTRL 0x0000000110060280
23871 #define SH_GC_SRC_CTRL_MASK 0x0000000313ff3ff1
23872 #define SH_GC_SRC_CTRL_INIT 0x0000000100000000
23874 /* SH_GC_SRC_CTRL_ENABLE_COUNTER */
23875 /* Description: Enable Counter */
23876 #define SH_GC_SRC_CTRL_ENABLE_COUNTER_SHFT 0
23877 #define SH_GC_SRC_CTRL_ENABLE_COUNTER_MASK 0x0000000000000001
23879 /* SH_GC_SRC_CTRL_MAX_COUNT */
23880 /* Description: Max Count */
23881 #define SH_GC_SRC_CTRL_MAX_COUNT_SHFT 4
23882 #define SH_GC_SRC_CTRL_MAX_COUNT_MASK 0x0000000000003ff0
23884 /* SH_GC_SRC_CTRL_COUNTER */
23885 /* Description: Counter */
23886 #define SH_GC_SRC_CTRL_COUNTER_SHFT 16
23887 #define SH_GC_SRC_CTRL_COUNTER_MASK 0x0000000003ff0000
23889 /* SH_GC_SRC_CTRL_TOGGLE_BIT */
23890 /* Description: Toggle bit */
23891 #define SH_GC_SRC_CTRL_TOGGLE_BIT_SHFT 28
23892 #define SH_GC_SRC_CTRL_TOGGLE_BIT_MASK 0x0000000010000000
23894 /* SH_GC_SRC_CTRL_SOURCE_SEL */
23895 /* Description: Source select (0=ext., 1=Int., 2=SHUB) */
23896 #define SH_GC_SRC_CTRL_SOURCE_SEL_SHFT 32
23897 #define SH_GC_SRC_CTRL_SOURCE_SEL_MASK 0x0000000300000000
23899 /* ==================================================================== */
23900 /* Register "SH_HARD_RESET" */
23901 /* SHub Hard Reset */
23902 /* ==================================================================== */
23904 #define SH_HARD_RESET 0x0000000110060300
23905 #define SH_HARD_RESET_MASK 0x0000000000000001
23906 #define SH_HARD_RESET_INIT 0x0000000000000000
23908 /* SH_HARD_RESET_HARD_RESET */
23909 /* Description: Hard Reset */
23910 #define SH_HARD_RESET_HARD_RESET_SHFT 0
23911 #define SH_HARD_RESET_HARD_RESET_MASK 0x0000000000000001
23913 /* ==================================================================== */
23914 /* Register "SH_IO_PERM" */
23915 /* II MMR Access Permission Bits */
23916 /* ==================================================================== */
23918 #define SH_IO_PERM 0x0000000110060380
23919 #define SH_IO_PERM_MASK 0xffffffffffffffff
23920 #define SH_IO_PERM_INIT 0x0000000000000000
23922 /* SH_IO_PERM_ACCESS_BITS */
23923 /* Description: Access Bits */
23924 #define SH_IO_PERM_ACCESS_BITS_SHFT 0
23925 #define SH_IO_PERM_ACCESS_BITS_MASK 0xffffffffffffffff
23927 /* ==================================================================== */
23928 /* Register "SH_IOI_ACCESS" */
23929 /* II Interrupt Access Permission Bits */
23930 /* ==================================================================== */
23932 #define SH_IOI_ACCESS 0x0000000110060400
23933 #define SH_IOI_ACCESS_MASK 0xffffffffffffffff
23934 #define SH_IOI_ACCESS_INIT 0xffffffffffffffff
23936 /* SH_IOI_ACCESS_ACCESS_BITS */
23937 /* Description: Access Bits */
23938 #define SH_IOI_ACCESS_ACCESS_BITS_SHFT 0
23939 #define SH_IOI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff
23941 /* ==================================================================== */
23942 /* Register "SH_IPI_ACCESS" */
23943 /* CPU interrupt Access Permission Bits */
23944 /* ==================================================================== */
23946 #define SH_IPI_ACCESS 0x0000000110060480
23947 #define SH_IPI_ACCESS_MASK 0xffffffffffffffff
23948 #define SH_IPI_ACCESS_INIT 0xffffffffffffffff
23950 /* SH_IPI_ACCESS_ACCESS_BITS */
23951 /* Description: Access Bits */
23952 #define SH_IPI_ACCESS_ACCESS_BITS_SHFT 0
23953 #define SH_IPI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff
23955 /* ==================================================================== */
23956 /* Register "SH_JTAG_CONFIG" */
23957 /* SHub JTAG configuration */
23958 /* ==================================================================== */
23960 #define SH_JTAG_CONFIG 0x0000000110060500
23961 #define SH_JTAG_CONFIG_MASK 0x00ffffffffffffff
23962 #define SH_JTAG_CONFIG_INIT 0x0000000000000000
23964 /* SH_JTAG_CONFIG_MD_CLK_SEL */
23965 /* Description: Select divide freq of DRAMCLK */
23966 #define SH_JTAG_CONFIG_MD_CLK_SEL_SHFT 0
23967 #define SH_JTAG_CONFIG_MD_CLK_SEL_MASK 0x0000000000000003
23969 /* SH_JTAG_CONFIG_NI_CLK_SEL */
23970 /* Description: Selects clock source for NICLK domain */
23971 #define SH_JTAG_CONFIG_NI_CLK_SEL_SHFT 2
23972 #define SH_JTAG_CONFIG_NI_CLK_SEL_MASK 0x0000000000000004
23974 /* SH_JTAG_CONFIG_II_CLK_SEL */
23975 /* Description: Selects clock source for IOCLK domain */
23976 #define SH_JTAG_CONFIG_II_CLK_SEL_SHFT 3
23977 #define SH_JTAG_CONFIG_II_CLK_SEL_MASK 0x0000000000000018
23979 /* SH_JTAG_CONFIG_WRT90_TARGET */
23980 /* Description: wrt90_target */
23981 #define SH_JTAG_CONFIG_WRT90_TARGET_SHFT 5
23982 #define SH_JTAG_CONFIG_WRT90_TARGET_MASK 0x000000000007ffe0
23984 /* SH_JTAG_CONFIG_WRT90_OVERRIDER */
23985 /* Description: wrt90_overrideR */
23986 #define SH_JTAG_CONFIG_WRT90_OVERRIDER_SHFT 19
23987 #define SH_JTAG_CONFIG_WRT90_OVERRIDER_MASK 0x0000000000080000
23989 /* SH_JTAG_CONFIG_WRT90_OVERRIDE */
23990 /* Description: wrt90_override */
23991 #define SH_JTAG_CONFIG_WRT90_OVERRIDE_SHFT 20
23992 #define SH_JTAG_CONFIG_WRT90_OVERRIDE_MASK 0x0000000000100000
23994 /* SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY */
23995 /* Description: jtag_mci_reset_delay */
23996 #define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_SHFT 21
23997 #define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_MASK 0x0000000001e00000
23999 /* SH_JTAG_CONFIG_JTAG_MCI_TARGET */
24000 /* Description: jtag_mci_target */
24001 #define SH_JTAG_CONFIG_JTAG_MCI_TARGET_SHFT 25
24002 #define SH_JTAG_CONFIG_JTAG_MCI_TARGET_MASK 0x0000007ffe000000
24004 /* SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE */
24005 /* Description: jtag_mci_override */
24006 #define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_SHFT 39
24007 #define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_MASK 0x0000008000000000
24009 /* SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH */
24010 /* Description: 0=depth 8, 1=depth1 */
24011 #define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_SHFT 40
24012 #define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_MASK 0x0000010000000000
24014 /* SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT */
24015 /* Description: Enable sampling of BINIT */
24016 #define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_SHFT 41
24017 #define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_MASK 0x0000020000000000
24019 /* SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING */
24020 #define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_SHFT 42
24021 #define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_MASK 0x0000040000000000
24023 /* SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO */
24024 #define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_SHFT 43
24025 #define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_MASK 0x0000f80000000000
24027 /* SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE */
24028 /* Description: Output tristate control */
24029 #define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_SHFT 48
24030 #define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_MASK 0x000f000000000000
24032 /* SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST */
24033 /* Description: Enables BIST */
24034 #define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_SHFT 52
24035 #define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_MASK 0x0010000000000000
24037 /* SH_JTAG_CONFIG_FSB_CONFIG_AUX */
24038 /* Description: Enables BIST */
24039 #define SH_JTAG_CONFIG_FSB_CONFIG_AUX_SHFT 53
24040 #define SH_JTAG_CONFIG_FSB_CONFIG_AUX_MASK 0x0060000000000000
24042 /* SH_JTAG_CONFIG_GTL_CONFIG_RE */
24043 /* Description: Reference Enable selection for GTL io */
24044 #define SH_JTAG_CONFIG_GTL_CONFIG_RE_SHFT 55
24045 #define SH_JTAG_CONFIG_GTL_CONFIG_RE_MASK 0x0080000000000000
24047 /* ==================================================================== */
24048 /* Register "SH_SHUB_ID" */
24049 /* SHub ID Number */
24050 /* ==================================================================== */
24052 #define SH_SHUB_ID 0x0000000110060580
24053 #define SH_SHUB_ID_MASK 0x011f37ffffffffff
24054 #define SH_SHUB_ID_INIT 0x0010300000000000
24056 /* SH_SHUB_ID_FORCE1 */
24057 /* Description: Must be 1 */
24058 #define SH_SHUB_ID_FORCE1_SHFT 0
24059 #define SH_SHUB_ID_FORCE1_MASK 0x0000000000000001
24061 /* SH_SHUB_ID_MANUFACTURER */
24062 /* Description: Manufacturer */
24063 #define SH_SHUB_ID_MANUFACTURER_SHFT 1
24064 #define SH_SHUB_ID_MANUFACTURER_MASK 0x0000000000000ffe
24066 /* SH_SHUB_ID_PART_NUMBER */
24067 /* Description: Part Number */
24068 #define SH_SHUB_ID_PART_NUMBER_SHFT 12
24069 #define SH_SHUB_ID_PART_NUMBER_MASK 0x000000000ffff000
24071 /* SH_SHUB_ID_REVISION */
24072 /* Description: Revision */
24073 #define SH_SHUB_ID_REVISION_SHFT 28
24074 #define SH_SHUB_ID_REVISION_MASK 0x00000000f0000000
24076 /* SH_SHUB_ID_NODE_ID */
24077 /* Description: Node Identification */
24078 #define SH_SHUB_ID_NODE_ID_SHFT 32
24079 #define SH_SHUB_ID_NODE_ID_MASK 0x000007ff00000000
24081 /* SH_SHUB_ID_SHARING_MODE */
24082 /* Description: Sharing mode (Coherency Domain Size) */
24083 #define SH_SHUB_ID_SHARING_MODE_SHFT 44
24084 #define SH_SHUB_ID_SHARING_MODE_MASK 0x0000300000000000
24086 /* SH_SHUB_ID_NODES_PER_BIT */
24087 /* Description: Nodes per bit definition for MMR access */
24088 #define SH_SHUB_ID_NODES_PER_BIT_SHFT 48
24089 #define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000
24091 /* SH_SHUB_ID_NI_PORT */
24092 /* Description: NI port of vector reference, 0 = NI0, 1 = NI1 */
24093 #define SH_SHUB_ID_NI_PORT_SHFT 56
24094 #define SH_SHUB_ID_NI_PORT_MASK 0x0100000000000000
24096 /* ==================================================================== */
24097 /* Register "SH_SHUBS_PRESENT0" */
24098 /* Shubs 0 - 63 Present. Used for invalidate generation */
24099 /* ==================================================================== */
24101 #define SH_SHUBS_PRESENT0 0x0000000110060600
24102 #define SH_SHUBS_PRESENT0_MASK 0xffffffffffffffff
24103 #define SH_SHUBS_PRESENT0_INIT 0xffffffffffffffff
24105 /* SH_SHUBS_PRESENT0_SHUBS_PRESENT0 */
24106 /* Description: Shubs 0 - 63 Present configuration */
24107 #define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_SHFT 0
24108 #define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_MASK 0xffffffffffffffff
24110 /* ==================================================================== */
24111 /* Register "SH_SHUBS_PRESENT1" */
24112 /* Shubs 64 - 127 Present. Used for invalidate generation */
24113 /* ==================================================================== */
24115 #define SH_SHUBS_PRESENT1 0x0000000110060680
24116 #define SH_SHUBS_PRESENT1_MASK 0xffffffffffffffff
24117 #define SH_SHUBS_PRESENT1_INIT 0xffffffffffffffff
24119 /* SH_SHUBS_PRESENT1_SHUBS_PRESENT1 */
24120 /* Description: Shubs 64 - 127 Present configuration */
24121 #define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_SHFT 0
24122 #define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_MASK 0xffffffffffffffff
24124 /* ==================================================================== */
24125 /* Register "SH_SHUBS_PRESENT2" */
24126 /* Shubs 128 - 191 Present. Used for invalidate generation */
24127 /* ==================================================================== */
24129 #define SH_SHUBS_PRESENT2 0x0000000110060700
24130 #define SH_SHUBS_PRESENT2_MASK 0xffffffffffffffff
24131 #define SH_SHUBS_PRESENT2_INIT 0xffffffffffffffff
24133 /* SH_SHUBS_PRESENT2_SHUBS_PRESENT2 */
24134 /* Description: Shubs 128 - 191 Present configuration */
24135 #define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_SHFT 0
24136 #define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_MASK 0xffffffffffffffff
24138 /* ==================================================================== */
24139 /* Register "SH_SHUBS_PRESENT3" */
24140 /* Shubs 192 - 255 Present. Used for invalidate generation */
24141 /* ==================================================================== */
24143 #define SH_SHUBS_PRESENT3 0x0000000110060780
24144 #define SH_SHUBS_PRESENT3_MASK 0xffffffffffffffff
24145 #define SH_SHUBS_PRESENT3_INIT 0xffffffffffffffff
24147 /* SH_SHUBS_PRESENT3_SHUBS_PRESENT3 */
24148 /* Description: Shubs 192 - 255 Present configuration */
24149 #define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_SHFT 0
24150 #define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_MASK 0xffffffffffffffff
24152 /* ==================================================================== */
24153 /* Register "SH_SOFT_RESET" */
24154 /* SHub Soft Reset */
24155 /* ==================================================================== */
24157 #define SH_SOFT_RESET 0x0000000110060800
24158 #define SH_SOFT_RESET_MASK 0x0000000000000001
24159 #define SH_SOFT_RESET_INIT 0x0000000000000000
24161 /* SH_SOFT_RESET_SOFT_RESET */
24162 /* Description: Soft Reset */
24163 #define SH_SOFT_RESET_SOFT_RESET_SHFT 0
24164 #define SH_SOFT_RESET_SOFT_RESET_MASK 0x0000000000000001
24166 /* ==================================================================== */
24167 /* Register "SH_FIRST_ERROR" */
24168 /* Shub Global First Error Flags */
24169 /* ==================================================================== */
24171 #define SH_FIRST_ERROR 0x0000000110071000
24172 #define SH_FIRST_ERROR_MASK 0x000000000007ffff
24173 #define SH_FIRST_ERROR_INIT 0x0000000000000000
24175 /* SH_FIRST_ERROR_FIRST_ERROR */
24176 /* Description: Chiplet with first error */
24177 #define SH_FIRST_ERROR_FIRST_ERROR_SHFT 0
24178 #define SH_FIRST_ERROR_FIRST_ERROR_MASK 0x000000000007ffff
24180 /* ==================================================================== */
24181 /* Register "SH_II_HW_TIME_STAMP" */
24182 /* II hardware error time stamp */
24183 /* ==================================================================== */
24185 #define SH_II_HW_TIME_STAMP 0x0000000110071080
24186 #define SH_II_HW_TIME_STAMP_MASK 0xffffffffffffffff
24187 #define SH_II_HW_TIME_STAMP_INIT 0x0000000000000000
24189 /* SH_II_HW_TIME_STAMP_TIME */
24190 /* Description: II hardware error time stamp */
24191 #define SH_II_HW_TIME_STAMP_TIME_SHFT 0
24192 #define SH_II_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24194 /* SH_II_HW_TIME_STAMP_VALID */
24195 /* Description: II hardware error time stamp valid */
24196 #define SH_II_HW_TIME_STAMP_VALID_SHFT 63
24197 #define SH_II_HW_TIME_STAMP_VALID_MASK 0x8000000000000000
24199 /* ==================================================================== */
24200 /* Register "SH_LB_HW_TIME_STAMP" */
24201 /* LB hardware error time stamp */
24202 /* ==================================================================== */
24204 #define SH_LB_HW_TIME_STAMP 0x0000000110071100
24205 #define SH_LB_HW_TIME_STAMP_MASK 0xffffffffffffffff
24206 #define SH_LB_HW_TIME_STAMP_INIT 0x0000000000000000
24208 /* SH_LB_HW_TIME_STAMP_TIME */
24209 /* Description: LB hardware error time stamp */
24210 #define SH_LB_HW_TIME_STAMP_TIME_SHFT 0
24211 #define SH_LB_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24213 /* SH_LB_HW_TIME_STAMP_VALID */
24214 /* Description: LB hardware error time stamp valid */
24215 #define SH_LB_HW_TIME_STAMP_VALID_SHFT 63
24216 #define SH_LB_HW_TIME_STAMP_VALID_MASK 0x8000000000000000
24218 /* ==================================================================== */
24219 /* Register "SH_MD_COR_TIME_STAMP" */
24220 /* MD correctable error time stamp */
24221 /* ==================================================================== */
24223 #define SH_MD_COR_TIME_STAMP 0x0000000110071180
24224 #define SH_MD_COR_TIME_STAMP_MASK 0xffffffffffffffff
24225 #define SH_MD_COR_TIME_STAMP_INIT 0x0000000000000000
24227 /* SH_MD_COR_TIME_STAMP_TIME */
24228 /* Description: MD correctable error time stamp */
24229 #define SH_MD_COR_TIME_STAMP_TIME_SHFT 0
24230 #define SH_MD_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24232 /* SH_MD_COR_TIME_STAMP_VALID */
24233 /* Description: MD correctable error time stamp valid */
24234 #define SH_MD_COR_TIME_STAMP_VALID_SHFT 63
24235 #define SH_MD_COR_TIME_STAMP_VALID_MASK 0x8000000000000000
24237 /* ==================================================================== */
24238 /* Register "SH_MD_HW_TIME_STAMP" */
24239 /* MD hardware error time stamp */
24240 /* ==================================================================== */
24242 #define SH_MD_HW_TIME_STAMP 0x0000000110071200
24243 #define SH_MD_HW_TIME_STAMP_MASK 0xffffffffffffffff
24244 #define SH_MD_HW_TIME_STAMP_INIT 0x0000000000000000
24246 /* SH_MD_HW_TIME_STAMP_TIME */
24247 /* Description: MD hardware error time stamp */
24248 #define SH_MD_HW_TIME_STAMP_TIME_SHFT 0
24249 #define SH_MD_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24251 /* SH_MD_HW_TIME_STAMP_VALID */
24252 /* Description: MD hardware error time stamp valid */
24253 #define SH_MD_HW_TIME_STAMP_VALID_SHFT 63
24254 #define SH_MD_HW_TIME_STAMP_VALID_MASK 0x8000000000000000
24256 /* ==================================================================== */
24257 /* Register "SH_MD_UNCOR_TIME_STAMP" */
24258 /* MD uncorrectable error time stamp */
24259 /* ==================================================================== */
24261 #define SH_MD_UNCOR_TIME_STAMP 0x0000000110071280
24262 #define SH_MD_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff
24263 #define SH_MD_UNCOR_TIME_STAMP_INIT 0x0000000000000000
24265 /* SH_MD_UNCOR_TIME_STAMP_TIME */
24266 /* Description: MD uncorrectable error time stamp */
24267 #define SH_MD_UNCOR_TIME_STAMP_TIME_SHFT 0
24268 #define SH_MD_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24270 /* SH_MD_UNCOR_TIME_STAMP_VALID */
24271 /* Description: MD uncorrectable error time stamp valid */
24272 #define SH_MD_UNCOR_TIME_STAMP_VALID_SHFT 63
24273 #define SH_MD_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000
24275 /* ==================================================================== */
24276 /* Register "SH_PI_COR_TIME_STAMP" */
24277 /* PI correctable error time stamp */
24278 /* ==================================================================== */
24280 #define SH_PI_COR_TIME_STAMP 0x0000000110071300
24281 #define SH_PI_COR_TIME_STAMP_MASK 0xffffffffffffffff
24282 #define SH_PI_COR_TIME_STAMP_INIT 0x0000000000000000
24284 /* SH_PI_COR_TIME_STAMP_TIME */
24285 /* Description: PI correctable error time stamp */
24286 #define SH_PI_COR_TIME_STAMP_TIME_SHFT 0
24287 #define SH_PI_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24289 /* SH_PI_COR_TIME_STAMP_VALID */
24290 /* Description: PI correctable error time stamp valid */
24291 #define SH_PI_COR_TIME_STAMP_VALID_SHFT 63
24292 #define SH_PI_COR_TIME_STAMP_VALID_MASK 0x8000000000000000
24294 /* ==================================================================== */
24295 /* Register "SH_PI_HW_TIME_STAMP" */
24296 /* PI hardware error time stamp */
24297 /* ==================================================================== */
24299 #define SH_PI_HW_TIME_STAMP 0x0000000110071380
24300 #define SH_PI_HW_TIME_STAMP_MASK 0xffffffffffffffff
24301 #define SH_PI_HW_TIME_STAMP_INIT 0x0000000000000000
24303 /* SH_PI_HW_TIME_STAMP_TIME */
24304 /* Description: PI hardware error time stamp */
24305 #define SH_PI_HW_TIME_STAMP_TIME_SHFT 0
24306 #define SH_PI_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24308 /* SH_PI_HW_TIME_STAMP_VALID */
24309 /* Description: PI hardware error time stamp valid */
24310 #define SH_PI_HW_TIME_STAMP_VALID_SHFT 63
24311 #define SH_PI_HW_TIME_STAMP_VALID_MASK 0x8000000000000000
24313 /* ==================================================================== */
24314 /* Register "SH_PI_UNCOR_TIME_STAMP" */
24315 /* PI uncorrectable error time stamp */
24316 /* ==================================================================== */
24318 #define SH_PI_UNCOR_TIME_STAMP 0x0000000110071400
24319 #define SH_PI_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff
24320 #define SH_PI_UNCOR_TIME_STAMP_INIT 0x0000000000000000
24322 /* SH_PI_UNCOR_TIME_STAMP_TIME */
24323 /* Description: PI uncorrectable error time stamp */
24324 #define SH_PI_UNCOR_TIME_STAMP_TIME_SHFT 0
24325 #define SH_PI_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24327 /* SH_PI_UNCOR_TIME_STAMP_VALID */
24328 /* Description: PI uncorrectable error time stamp valid */
24329 #define SH_PI_UNCOR_TIME_STAMP_VALID_SHFT 63
24330 #define SH_PI_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000
24332 /* ==================================================================== */
24333 /* Register "SH_PROC0_ADV_TIME_STAMP" */
24334 /* Proc 0 advisory time stamp */
24335 /* ==================================================================== */
24337 #define SH_PROC0_ADV_TIME_STAMP 0x0000000110071480
24338 #define SH_PROC0_ADV_TIME_STAMP_MASK 0xffffffffffffffff
24339 #define SH_PROC0_ADV_TIME_STAMP_INIT 0x0000000000000000
24341 /* SH_PROC0_ADV_TIME_STAMP_TIME */
24342 /* Description: Processor 0 advisory time stamp */
24343 #define SH_PROC0_ADV_TIME_STAMP_TIME_SHFT 0
24344 #define SH_PROC0_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24346 /* SH_PROC0_ADV_TIME_STAMP_VALID */
24347 /* Description: Processor 0 advisory time stamp valid */
24348 #define SH_PROC0_ADV_TIME_STAMP_VALID_SHFT 63
24349 #define SH_PROC0_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000
24351 /* ==================================================================== */
24352 /* Register "SH_PROC0_ERR_TIME_STAMP" */
24353 /* Proc 0 error time stamp */
24354 /* ==================================================================== */
24356 #define SH_PROC0_ERR_TIME_STAMP 0x0000000110071500
24357 #define SH_PROC0_ERR_TIME_STAMP_MASK 0xffffffffffffffff
24358 #define SH_PROC0_ERR_TIME_STAMP_INIT 0x0000000000000000
24360 /* SH_PROC0_ERR_TIME_STAMP_TIME */
24361 /* Description: Processor 0 error time stamp */
24362 #define SH_PROC0_ERR_TIME_STAMP_TIME_SHFT 0
24363 #define SH_PROC0_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24365 /* SH_PROC0_ERR_TIME_STAMP_VALID */
24366 /* Description: Processor 0 error time stamp valid */
24367 #define SH_PROC0_ERR_TIME_STAMP_VALID_SHFT 63
24368 #define SH_PROC0_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000
24370 /* ==================================================================== */
24371 /* Register "SH_PROC1_ADV_TIME_STAMP" */
24372 /* Proc 1 advisory time stamp */
24373 /* ==================================================================== */
24375 #define SH_PROC1_ADV_TIME_STAMP 0x0000000110071580
24376 #define SH_PROC1_ADV_TIME_STAMP_MASK 0xffffffffffffffff
24377 #define SH_PROC1_ADV_TIME_STAMP_INIT 0x0000000000000000
24379 /* SH_PROC1_ADV_TIME_STAMP_TIME */
24380 /* Description: Processor 1 advisory time stamp */
24381 #define SH_PROC1_ADV_TIME_STAMP_TIME_SHFT 0
24382 #define SH_PROC1_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24384 /* SH_PROC1_ADV_TIME_STAMP_VALID */
24385 /* Description: Processor 1 advisory time stamp valid */
24386 #define SH_PROC1_ADV_TIME_STAMP_VALID_SHFT 63
24387 #define SH_PROC1_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000
24389 /* ==================================================================== */
24390 /* Register "SH_PROC1_ERR_TIME_STAMP" */
24391 /* Proc 1 error time stamp */
24392 /* ==================================================================== */
24394 #define SH_PROC1_ERR_TIME_STAMP 0x0000000110071600
24395 #define SH_PROC1_ERR_TIME_STAMP_MASK 0xffffffffffffffff
24396 #define SH_PROC1_ERR_TIME_STAMP_INIT 0x0000000000000000
24398 /* SH_PROC1_ERR_TIME_STAMP_TIME */
24399 /* Description: Processor 1 error time stamp */
24400 #define SH_PROC1_ERR_TIME_STAMP_TIME_SHFT 0
24401 #define SH_PROC1_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24403 /* SH_PROC1_ERR_TIME_STAMP_VALID */
24404 /* Description: Processor 1 error time stamp valid */
24405 #define SH_PROC1_ERR_TIME_STAMP_VALID_SHFT 63
24406 #define SH_PROC1_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000
24408 /* ==================================================================== */
24409 /* Register "SH_PROC2_ADV_TIME_STAMP" */
24410 /* Proc 2 advisory time stamp */
24411 /* ==================================================================== */
24413 #define SH_PROC2_ADV_TIME_STAMP 0x0000000110071680
24414 #define SH_PROC2_ADV_TIME_STAMP_MASK 0xffffffffffffffff
24415 #define SH_PROC2_ADV_TIME_STAMP_INIT 0x0000000000000000
24417 /* SH_PROC2_ADV_TIME_STAMP_TIME */
24418 /* Description: Processor 2 advisory time stamp */
24419 #define SH_PROC2_ADV_TIME_STAMP_TIME_SHFT 0
24420 #define SH_PROC2_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24422 /* SH_PROC2_ADV_TIME_STAMP_VALID */
24423 /* Description: Processor 2 advisory time stamp valid */
24424 #define SH_PROC2_ADV_TIME_STAMP_VALID_SHFT 63
24425 #define SH_PROC2_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000
24427 /* ==================================================================== */
24428 /* Register "SH_PROC2_ERR_TIME_STAMP" */
24429 /* Proc 2 error time stamp */
24430 /* ==================================================================== */
24432 #define SH_PROC2_ERR_TIME_STAMP 0x0000000110071700
24433 #define SH_PROC2_ERR_TIME_STAMP_MASK 0xffffffffffffffff
24434 #define SH_PROC2_ERR_TIME_STAMP_INIT 0x0000000000000000
24436 /* SH_PROC2_ERR_TIME_STAMP_TIME */
24437 /* Description: Processor 2 error time stamp */
24438 #define SH_PROC2_ERR_TIME_STAMP_TIME_SHFT 0
24439 #define SH_PROC2_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24441 /* SH_PROC2_ERR_TIME_STAMP_VALID */
24442 /* Description: Processor 2 error time stamp valid */
24443 #define SH_PROC2_ERR_TIME_STAMP_VALID_SHFT 63
24444 #define SH_PROC2_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000
24446 /* ==================================================================== */
24447 /* Register "SH_PROC3_ADV_TIME_STAMP" */
24448 /* Proc 3 advisory time stamp */
24449 /* ==================================================================== */
24451 #define SH_PROC3_ADV_TIME_STAMP 0x0000000110071780
24452 #define SH_PROC3_ADV_TIME_STAMP_MASK 0xffffffffffffffff
24453 #define SH_PROC3_ADV_TIME_STAMP_INIT 0x0000000000000000
24455 /* SH_PROC3_ADV_TIME_STAMP_TIME */
24456 /* Description: Processor 3 advisory time stamp */
24457 #define SH_PROC3_ADV_TIME_STAMP_TIME_SHFT 0
24458 #define SH_PROC3_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24460 /* SH_PROC3_ADV_TIME_STAMP_VALID */
24461 /* Description: Processor 3 advisory time stamp valid */
24462 #define SH_PROC3_ADV_TIME_STAMP_VALID_SHFT 63
24463 #define SH_PROC3_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000
24465 /* ==================================================================== */
24466 /* Register "SH_PROC3_ERR_TIME_STAMP" */
24467 /* Proc 3 error time stamp */
24468 /* ==================================================================== */
24470 #define SH_PROC3_ERR_TIME_STAMP 0x0000000110071800
24471 #define SH_PROC3_ERR_TIME_STAMP_MASK 0xffffffffffffffff
24472 #define SH_PROC3_ERR_TIME_STAMP_INIT 0x0000000000000000
24474 /* SH_PROC3_ERR_TIME_STAMP_TIME */
24475 /* Description: Processor 3 error time stamp */
24476 #define SH_PROC3_ERR_TIME_STAMP_TIME_SHFT 0
24477 #define SH_PROC3_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24479 /* SH_PROC3_ERR_TIME_STAMP_VALID */
24480 /* Description: Processor 3 error time stamp valid */
24481 #define SH_PROC3_ERR_TIME_STAMP_VALID_SHFT 63
24482 #define SH_PROC3_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000
24484 /* ==================================================================== */
24485 /* Register "SH_XN_COR_TIME_STAMP" */
24486 /* XN correctable error time stamp */
24487 /* ==================================================================== */
24489 #define SH_XN_COR_TIME_STAMP 0x0000000110071880
24490 #define SH_XN_COR_TIME_STAMP_MASK 0xffffffffffffffff
24491 #define SH_XN_COR_TIME_STAMP_INIT 0x0000000000000000
24493 /* SH_XN_COR_TIME_STAMP_TIME */
24494 /* Description: XN correctable error time stamp */
24495 #define SH_XN_COR_TIME_STAMP_TIME_SHFT 0
24496 #define SH_XN_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24498 /* SH_XN_COR_TIME_STAMP_VALID */
24499 /* Description: XN correctable error time stamp valid */
24500 #define SH_XN_COR_TIME_STAMP_VALID_SHFT 63
24501 #define SH_XN_COR_TIME_STAMP_VALID_MASK 0x8000000000000000
24503 /* ==================================================================== */
24504 /* Register "SH_XN_HW_TIME_STAMP" */
24505 /* XN hardware error time stamp */
24506 /* ==================================================================== */
24508 #define SH_XN_HW_TIME_STAMP 0x0000000110071900
24509 #define SH_XN_HW_TIME_STAMP_MASK 0xffffffffffffffff
24510 #define SH_XN_HW_TIME_STAMP_INIT 0x0000000000000000
24512 /* SH_XN_HW_TIME_STAMP_TIME */
24513 /* Description: XN hardware error time stamp */
24514 #define SH_XN_HW_TIME_STAMP_TIME_SHFT 0
24515 #define SH_XN_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24517 /* SH_XN_HW_TIME_STAMP_VALID */
24518 /* Description: XN hardware error time stamp valid */
24519 #define SH_XN_HW_TIME_STAMP_VALID_SHFT 63
24520 #define SH_XN_HW_TIME_STAMP_VALID_MASK 0x8000000000000000
24522 /* ==================================================================== */
24523 /* Register "SH_XN_UNCOR_TIME_STAMP" */
24524 /* XN uncorrectable error time stamp */
24525 /* ==================================================================== */
24527 #define SH_XN_UNCOR_TIME_STAMP 0x0000000110071980
24528 #define SH_XN_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff
24529 #define SH_XN_UNCOR_TIME_STAMP_INIT 0x0000000000000000
24531 /* SH_XN_UNCOR_TIME_STAMP_TIME */
24532 /* Description: XN uncorrectable error time stamp */
24533 #define SH_XN_UNCOR_TIME_STAMP_TIME_SHFT 0
24534 #define SH_XN_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff
24536 /* SH_XN_UNCOR_TIME_STAMP_VALID */
24537 /* Description: XN uncorrectable error time stamp valid */
24538 #define SH_XN_UNCOR_TIME_STAMP_VALID_SHFT 63
24539 #define SH_XN_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000
24541 /* ==================================================================== */
24542 /* Register "SH_DEBUG_PORT" */
24543 /* SHub Debug Port */
24544 /* ==================================================================== */
24546 #define SH_DEBUG_PORT 0x0000000110072000
24547 #define SH_DEBUG_PORT_MASK 0x00000000ffffffff
24548 #define SH_DEBUG_PORT_INIT 0x0000000000000000
24550 /* SH_DEBUG_PORT_DEBUG_NIBBLE0 */
24551 /* Description: Debug port nibble 0 */
24552 #define SH_DEBUG_PORT_DEBUG_NIBBLE0_SHFT 0
24553 #define SH_DEBUG_PORT_DEBUG_NIBBLE0_MASK 0x000000000000000f
24555 /* SH_DEBUG_PORT_DEBUG_NIBBLE1 */
24556 /* Description: Debug port nibble 1 */
24557 #define SH_DEBUG_PORT_DEBUG_NIBBLE1_SHFT 4
24558 #define SH_DEBUG_PORT_DEBUG_NIBBLE1_MASK 0x00000000000000f0
24560 /* SH_DEBUG_PORT_DEBUG_NIBBLE2 */
24561 /* Description: Debug port nibble 2 */
24562 #define SH_DEBUG_PORT_DEBUG_NIBBLE2_SHFT 8
24563 #define SH_DEBUG_PORT_DEBUG_NIBBLE2_MASK 0x0000000000000f00
24565 /* SH_DEBUG_PORT_DEBUG_NIBBLE3 */
24566 /* Description: Debug port nibble 3 */
24567 #define SH_DEBUG_PORT_DEBUG_NIBBLE3_SHFT 12
24568 #define SH_DEBUG_PORT_DEBUG_NIBBLE3_MASK 0x000000000000f000
24570 /* SH_DEBUG_PORT_DEBUG_NIBBLE4 */
24571 /* Description: Debug port nibble 4 */
24572 #define SH_DEBUG_PORT_DEBUG_NIBBLE4_SHFT 16
24573 #define SH_DEBUG_PORT_DEBUG_NIBBLE4_MASK 0x00000000000f0000
24575 /* SH_DEBUG_PORT_DEBUG_NIBBLE5 */
24576 /* Description: Debug port nibble 5 */
24577 #define SH_DEBUG_PORT_DEBUG_NIBBLE5_SHFT 20
24578 #define SH_DEBUG_PORT_DEBUG_NIBBLE5_MASK 0x0000000000f00000
24580 /* SH_DEBUG_PORT_DEBUG_NIBBLE6 */
24581 /* Description: Debug port nibble 6 */
24582 #define SH_DEBUG_PORT_DEBUG_NIBBLE6_SHFT 24
24583 #define SH_DEBUG_PORT_DEBUG_NIBBLE6_MASK 0x000000000f000000
24585 /* SH_DEBUG_PORT_DEBUG_NIBBLE7 */
24586 /* Description: Debug port nibble 7 */
24587 #define SH_DEBUG_PORT_DEBUG_NIBBLE7_SHFT 28
24588 #define SH_DEBUG_PORT_DEBUG_NIBBLE7_MASK 0x00000000f0000000
24590 /* ==================================================================== */
24591 /* Register "SH_II_DEBUG_DATA" */
24592 /* II Debug Data */
24593 /* ==================================================================== */
24595 #define SH_II_DEBUG_DATA 0x0000000110072080
24596 #define SH_II_DEBUG_DATA_MASK 0x00000000ffffffff
24597 #define SH_II_DEBUG_DATA_INIT 0x0000000000000000
24599 /* SH_II_DEBUG_DATA_II_DATA */
24600 /* Description: II debug data */
24601 #define SH_II_DEBUG_DATA_II_DATA_SHFT 0
24602 #define SH_II_DEBUG_DATA_II_DATA_MASK 0x00000000ffffffff
24604 /* ==================================================================== */
24605 /* Register "SH_II_WRAP_DEBUG_DATA" */
24606 /* SHub II Wrapper Debug Data */
24607 /* ==================================================================== */
24609 #define SH_II_WRAP_DEBUG_DATA 0x0000000110072100
24610 #define SH_II_WRAP_DEBUG_DATA_MASK 0x00000000ffffffff
24611 #define SH_II_WRAP_DEBUG_DATA_INIT 0x0000000000000000
24613 /* SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA */
24614 /* Description: II wrapper debug data */
24615 #define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_SHFT 0
24616 #define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_MASK 0x00000000ffffffff
24618 /* ==================================================================== */
24619 /* Register "SH_LB_DEBUG_DATA" */
24620 /* SHub LB Debug Data */
24621 /* ==================================================================== */
24623 #define SH_LB_DEBUG_DATA 0x0000000110072180
24624 #define SH_LB_DEBUG_DATA_MASK 0x00000000ffffffff
24625 #define SH_LB_DEBUG_DATA_INIT 0x0000000000000000
24627 /* SH_LB_DEBUG_DATA_LB_DATA */
24628 /* Description: LB debug data */
24629 #define SH_LB_DEBUG_DATA_LB_DATA_SHFT 0
24630 #define SH_LB_DEBUG_DATA_LB_DATA_MASK 0x00000000ffffffff
24632 /* ==================================================================== */
24633 /* Register "SH_MD_DEBUG_DATA" */
24634 /* SHub MD Debug Data */
24635 /* ==================================================================== */
24637 #define SH_MD_DEBUG_DATA 0x0000000110072200
24638 #define SH_MD_DEBUG_DATA_MASK 0x00000000ffffffff
24639 #define SH_MD_DEBUG_DATA_INIT 0x0000000000000000
24641 /* SH_MD_DEBUG_DATA_MD_DATA */
24642 /* Description: MD debug data */
24643 #define SH_MD_DEBUG_DATA_MD_DATA_SHFT 0
24644 #define SH_MD_DEBUG_DATA_MD_DATA_MASK 0x00000000ffffffff
24646 /* ==================================================================== */
24647 /* Register "SH_PI_DEBUG_DATA" */
24648 /* SHub PI Debug Data */
24649 /* ==================================================================== */
24651 #define SH_PI_DEBUG_DATA 0x0000000110072280
24652 #define SH_PI_DEBUG_DATA_MASK 0x00000000ffffffff
24653 #define SH_PI_DEBUG_DATA_INIT 0x0000000000000000
24655 /* SH_PI_DEBUG_DATA_PI_DATA */
24656 /* Description: PI Debug Data */
24657 #define SH_PI_DEBUG_DATA_PI_DATA_SHFT 0
24658 #define SH_PI_DEBUG_DATA_PI_DATA_MASK 0x00000000ffffffff
24660 /* ==================================================================== */
24661 /* Register "SH_XN_DEBUG_DATA" */
24662 /* SHub XN Debug Data */
24663 /* ==================================================================== */
24665 #define SH_XN_DEBUG_DATA 0x0000000110072300
24666 #define SH_XN_DEBUG_DATA_MASK 0x00000000ffffffff
24667 #define SH_XN_DEBUG_DATA_INIT 0x0000000000000000
24669 /* SH_XN_DEBUG_DATA_XN_DATA */
24670 /* Description: XN debug data */
24671 #define SH_XN_DEBUG_DATA_XN_DATA_SHFT 0
24672 #define SH_XN_DEBUG_DATA_XN_DATA_MASK 0x00000000ffffffff
24674 /* ==================================================================== */
24675 /* Register "SH_TSF_ARMED_STATE" */
24676 /* Trigger sequencing facility arm state */
24677 /* ==================================================================== */
24679 #define SH_TSF_ARMED_STATE 0x0000000110073000
24680 #define SH_TSF_ARMED_STATE_MASK 0x00000000000000ff
24681 #define SH_TSF_ARMED_STATE_INIT 0x0000000000000000
24683 /* SH_TSF_ARMED_STATE_STATE */
24684 /* Description: Trigger sequencing facility armed state */
24685 #define SH_TSF_ARMED_STATE_STATE_SHFT 0
24686 #define SH_TSF_ARMED_STATE_STATE_MASK 0x00000000000000ff
24688 /* ==================================================================== */
24689 /* Register "SH_TSF_COUNTER_VALUE" */
24690 /* Trigger sequencing facility counter value */
24691 /* ==================================================================== */
24693 #define SH_TSF_COUNTER_VALUE 0x0000000110073080
24694 #define SH_TSF_COUNTER_VALUE_MASK 0xffffffffffffffff
24695 #define SH_TSF_COUNTER_VALUE_INIT 0x0000000000000000
24697 /* SH_TSF_COUNTER_VALUE_COUNT_32 */
24698 /* Description: Trigger sequencing facility counter 32 */
24699 #define SH_TSF_COUNTER_VALUE_COUNT_32_SHFT 0
24700 #define SH_TSF_COUNTER_VALUE_COUNT_32_MASK 0x00000000ffffffff
24702 /* SH_TSF_COUNTER_VALUE_COUNT_16 */
24703 /* Description: Trigger sequencing facility counter 16 */
24704 #define SH_TSF_COUNTER_VALUE_COUNT_16_SHFT 32
24705 #define SH_TSF_COUNTER_VALUE_COUNT_16_MASK 0x0000ffff00000000
24707 /* SH_TSF_COUNTER_VALUE_COUNT_8B */
24708 /* Description: Trigger sequencing facility counter 8b */
24709 #define SH_TSF_COUNTER_VALUE_COUNT_8B_SHFT 48
24710 #define SH_TSF_COUNTER_VALUE_COUNT_8B_MASK 0x00ff000000000000
24712 /* SH_TSF_COUNTER_VALUE_COUNT_8A */
24713 /* Description: Trigger sequencing facility counter 8a */
24714 #define SH_TSF_COUNTER_VALUE_COUNT_8A_SHFT 56
24715 #define SH_TSF_COUNTER_VALUE_COUNT_8A_MASK 0xff00000000000000
24717 /* ==================================================================== */
24718 /* Register "SH_TSF_TRIGGERED_STATE" */
24719 /* Trigger sequencing facility triggered state */
24720 /* ==================================================================== */
24722 #define SH_TSF_TRIGGERED_STATE 0x0000000110073100
24723 #define SH_TSF_TRIGGERED_STATE_MASK 0x00000000000000ff
24724 #define SH_TSF_TRIGGERED_STATE_INIT 0x0000000000000000
24726 /* SH_TSF_TRIGGERED_STATE_STATE */
24727 /* Description: Trigger sequencing facility triggered state */
24728 #define SH_TSF_TRIGGERED_STATE_STATE_SHFT 0
24729 #define SH_TSF_TRIGGERED_STATE_STATE_MASK 0x00000000000000ff
24731 /* ==================================================================== */
24732 /* Register "SH_VEC_RDDATA" */
24733 /* Vector Reply Message Data */
24734 /* ==================================================================== */
24736 #define SH_VEC_RDDATA 0x0000000110074000
24737 #define SH_VEC_RDDATA_MASK 0xffffffffffffffff
24738 #define SH_VEC_RDDATA_INIT 0x0000000000000000
24740 /* SH_VEC_RDDATA_DATA */
24741 /* Description: Data */
24742 #define SH_VEC_RDDATA_DATA_SHFT 0
24743 #define SH_VEC_RDDATA_DATA_MASK 0xffffffffffffffff
24745 /* ==================================================================== */
24746 /* Register "SH_VEC_RETURN" */
24747 /* Vector Reply Message Return Route */
24748 /* ==================================================================== */
24750 #define SH_VEC_RETURN 0x0000000110074080
24751 #define SH_VEC_RETURN_MASK 0xffffffffffffffff
24752 #define SH_VEC_RETURN_INIT 0x0000000000000000
24754 /* SH_VEC_RETURN_ROUTE */
24755 /* Description: Route */
24756 #define SH_VEC_RETURN_ROUTE_SHFT 0
24757 #define SH_VEC_RETURN_ROUTE_MASK 0xffffffffffffffff
24759 /* ==================================================================== */
24760 /* Register "SH_VEC_STATUS" */
24761 /* Vector Reply Message Status */
24762 /* ==================================================================== */
24764 #define SH_VEC_STATUS 0x0000000110074100
24765 #define SH_VEC_STATUS_MASK 0xcfffffffffffffff
24766 #define SH_VEC_STATUS_INIT 0x0000000000000000
24768 /* SH_VEC_STATUS_TYPE */
24769 /* Description: Type */
24770 #define SH_VEC_STATUS_TYPE_SHFT 0
24771 #define SH_VEC_STATUS_TYPE_MASK 0x0000000000000007
24773 /* SH_VEC_STATUS_ADDRESS */
24774 /* Description: Address */
24775 #define SH_VEC_STATUS_ADDRESS_SHFT 3
24776 #define SH_VEC_STATUS_ADDRESS_MASK 0x00000007fffffff8
24778 /* SH_VEC_STATUS_PIO_ID */
24779 /* Description: PIO ID */
24780 #define SH_VEC_STATUS_PIO_ID_SHFT 35
24781 #define SH_VEC_STATUS_PIO_ID_MASK 0x00003ff800000000
24783 /* SH_VEC_STATUS_SOURCE */
24784 /* Description: Source */
24785 #define SH_VEC_STATUS_SOURCE_SHFT 46
24786 #define SH_VEC_STATUS_SOURCE_MASK 0x0fffc00000000000
24788 /* SH_VEC_STATUS_OVERRUN */
24789 /* Description: Overrun */
24790 #define SH_VEC_STATUS_OVERRUN_SHFT 62
24791 #define SH_VEC_STATUS_OVERRUN_MASK 0x4000000000000000
24793 /* SH_VEC_STATUS_STATUS_VALID */
24794 /* Description: Status_Valid */
24795 #define SH_VEC_STATUS_STATUS_VALID_SHFT 63
24796 #define SH_VEC_STATUS_STATUS_VALID_MASK 0x8000000000000000
24798 /* ==================================================================== */
24799 /* Register "SH_VEC_STATUS_ALIAS" */
24800 /* Vector Reply Message Status Alias */
24801 /* ==================================================================== */
24803 #define SH_VEC_STATUS_ALIAS 0x0000000110074108
24805 /* ==================================================================== */
24806 /* Register "SH_PERFORMANCE_COUNT0_CONTROL" */
24807 /* Performance Counter 0 Control */
24808 /* ==================================================================== */
24810 #define SH_PERFORMANCE_COUNT0_CONTROL 0x0000000110080000
24811 #define SH_PERFORMANCE_COUNT0_CONTROL_MASK 0x000000000007ffff
24812 #define SH_PERFORMANCE_COUNT0_CONTROL_INIT 0x000000000000b8b8
24814 /* SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS */
24815 /* Description: Counter 0 up stimulus */
24816 #define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_SHFT 0
24817 #define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
24819 /* SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT */
24820 /* Description: Counter 0 up event select (1-greater than, 0-equal) */
24821 #define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_SHFT 5
24822 #define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_MASK 0x0000000000000020
24824 /* SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY */
24825 /* Description: Counter 0 up polarity select (1-negative edge, 0-po */
24827 #define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_SHFT 6
24828 #define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_MASK 0x0000000000000040
24830 /* SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE */
24831 /* Description: Counter 0 up mode select (1-internal, 0-external) */
24832 #define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_SHFT 7
24833 #define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_MASK 0x0000000000000080
24835 /* SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS */
24836 /* Description: Counter 0 down stimulus */
24837 #define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_SHFT 8
24838 #define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
24840 /* SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT */
24841 /* Description: Counter 0 down event select (1-greater than, 0-equa */
24842 #define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_SHFT 13
24843 #define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_MASK 0x0000000000002000
24845 /* SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY */
24846 /* Description: Counter 0 down polarity select (1-negative edge, 0- */
24847 /* positive edge) */
24848 #define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_SHFT 14
24849 #define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_MASK 0x0000000000004000
24851 /* SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE */
24852 /* Description: Counter 0 down mode select (1-internal, 0-external) */
24853 #define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_SHFT 15
24854 #define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_MASK 0x0000000000008000
24856 /* SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE */
24857 /* Description: Counter 0 enable increment */
24858 #define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_SHFT 16
24859 #define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_MASK 0x0000000000010000
24861 /* SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE */
24862 /* Description: Counter 0 enable decrement */
24863 #define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_SHFT 17
24864 #define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
24866 /* SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE */
24867 /* Description: Counter 0 enable peak detection */
24868 #define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_SHFT 18
24869 #define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
24871 /* ==================================================================== */
24872 /* Register "SH_PERFORMANCE_COUNT1_CONTROL" */
24873 /* Performance Counter 1 Control */
24874 /* ==================================================================== */
24876 #define SH_PERFORMANCE_COUNT1_CONTROL 0x0000000110090000
24877 #define SH_PERFORMANCE_COUNT1_CONTROL_MASK 0x000000000007ffff
24878 #define SH_PERFORMANCE_COUNT1_CONTROL_INIT 0x000000000000b8b8
24880 /* SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS */
24881 /* Description: Counter 1 up stimulus */
24882 #define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_SHFT 0
24883 #define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
24885 /* SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT */
24886 /* Description: Counter 1 up event select (1-greater than, 0-equal) */
24887 #define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_SHFT 5
24888 #define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_MASK 0x0000000000000020
24890 /* SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY */
24891 /* Description: Counter 1 up polarity select (1-negative edge, 0-po */
24893 #define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_SHFT 6
24894 #define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_MASK 0x0000000000000040
24896 /* SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE */
24897 /* Description: Counter 1 up mode select (1-internal, 0-external) */
24898 #define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_SHFT 7
24899 #define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_MASK 0x0000000000000080
24901 /* SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS */
24902 /* Description: Counter 1 down stimulus */
24903 #define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_SHFT 8
24904 #define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
24906 /* SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT */
24907 /* Description: Counter 1 down event select (1-greater than, 0-equa */
24908 #define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_SHFT 13
24909 #define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_MASK 0x0000000000002000
24911 /* SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY */
24912 /* Description: Counter 1 down polarity select (1-negative edge, 0- */
24913 /* positive edge) */
24914 #define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_SHFT 14
24915 #define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_MASK 0x0000000000004000
24917 /* SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE */
24918 /* Description: Counter 1 down mode select (1-internal, 0-external) */
24919 #define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_SHFT 15
24920 #define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_MASK 0x0000000000008000
24922 /* SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE */
24923 /* Description: Counter 1 enable increment */
24924 #define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_SHFT 16
24925 #define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_MASK 0x0000000000010000
24927 /* SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE */
24928 /* Description: Counter 1 enable decrement */
24929 #define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_SHFT 17
24930 #define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
24932 /* SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE */
24933 /* Description: Counter 1 enable peak detection */
24934 #define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_SHFT 18
24935 #define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
24937 /* ==================================================================== */
24938 /* Register "SH_PERFORMANCE_COUNT2_CONTROL" */
24939 /* Performance Counter 2 Control */
24940 /* ==================================================================== */
24942 #define SH_PERFORMANCE_COUNT2_CONTROL 0x00000001100a0000
24943 #define SH_PERFORMANCE_COUNT2_CONTROL_MASK 0x000000000007ffff
24944 #define SH_PERFORMANCE_COUNT2_CONTROL_INIT 0x000000000000b8b8
24946 /* SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS */
24947 /* Description: Counter 2 up stimulus */
24948 #define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_SHFT 0
24949 #define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
24951 /* SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT */
24952 /* Description: Counter 2 up event select (1-greater than, 0-equal) */
24953 #define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_SHFT 5
24954 #define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_MASK 0x0000000000000020
24956 /* SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY */
24957 /* Description: Counter 2 up polarity select (1-negative edge, 0-po */
24959 #define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_SHFT 6
24960 #define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_MASK 0x0000000000000040
24962 /* SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE */
24963 /* Description: Counter 2 up mode select (1-internal, 0-external) */
24964 #define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_SHFT 7
24965 #define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_MASK 0x0000000000000080
24967 /* SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS */
24968 /* Description: Counter 2 down stimulus */
24969 #define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_SHFT 8
24970 #define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
24972 /* SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT */
24973 /* Description: Counter 2 down event select (1-greater than, 0-equa */
24974 #define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_SHFT 13
24975 #define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_MASK 0x0000000000002000
24977 /* SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY */
24978 /* Description: Counter 2 down polarity select (1-negative edge, 0- */
24979 /* positive edge) */
24980 #define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_SHFT 14
24981 #define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_MASK 0x0000000000004000
24983 /* SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE */
24984 /* Description: Counter 2 down mode select (1-internal, 0-external) */
24985 #define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_SHFT 15
24986 #define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_MASK 0x0000000000008000
24988 /* SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE */
24989 /* Description: Counter 2 enable increment */
24990 #define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_SHFT 16
24991 #define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_MASK 0x0000000000010000
24993 /* SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE */
24994 /* Description: Counter 2 enable decrement */
24995 #define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_SHFT 17
24996 #define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
24998 /* SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE */
24999 /* Description: Counter 2 enable peak detection */
25000 #define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_SHFT 18
25001 #define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
25003 /* ==================================================================== */
25004 /* Register "SH_PERFORMANCE_COUNT3_CONTROL" */
25005 /* Performance Counter 3 Control */
25006 /* ==================================================================== */
25008 #define SH_PERFORMANCE_COUNT3_CONTROL 0x00000001100b0000
25009 #define SH_PERFORMANCE_COUNT3_CONTROL_MASK 0x000000000007ffff
25010 #define SH_PERFORMANCE_COUNT3_CONTROL_INIT 0x000000000000b8b8
25012 /* SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS */
25013 /* Description: Counter 3 up stimulus */
25014 #define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_SHFT 0
25015 #define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
25017 /* SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT */
25018 /* Description: Counter 3 up event select (1-greater than, 0-equal) */
25019 #define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_SHFT 5
25020 #define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_MASK 0x0000000000000020
25022 /* SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY */
25023 /* Description: Counter 3 up polarity select (1-negative edge, 0-po */
25025 #define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_SHFT 6
25026 #define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_MASK 0x0000000000000040
25028 /* SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE */
25029 /* Description: Counter 3 up mode select (1-internal, 0-external) */
25030 #define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_SHFT 7
25031 #define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_MASK 0x0000000000000080
25033 /* SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS */
25034 /* Description: Counter 3 down stimulus */
25035 #define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_SHFT 8
25036 #define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
25038 /* SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT */
25039 /* Description: Counter 3 down event select (1-greater than, 0-equa */
25040 #define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_SHFT 13
25041 #define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_MASK 0x0000000000002000
25043 /* SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY */
25044 /* Description: Counter 3 down polarity select (1-negative edge, 0- */
25045 /* positive edge) */
25046 #define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_SHFT 14
25047 #define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_MASK 0x0000000000004000
25049 /* SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE */
25050 /* Description: Counter 3 down mode select (1-internal, 0-external) */
25051 #define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_SHFT 15
25052 #define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_MASK 0x0000000000008000
25054 /* SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE */
25055 /* Description: Counter 3 enable increment */
25056 #define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_SHFT 16
25057 #define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_MASK 0x0000000000010000
25059 /* SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE */
25060 /* Description: Counter 3 enable decrement */
25061 #define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_SHFT 17
25062 #define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
25064 /* SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE */
25065 /* Description: Counter 3 enable peak detection */
25066 #define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_SHFT 18
25067 #define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
25069 /* ==================================================================== */
25070 /* Register "SH_PERFORMANCE_COUNT4_CONTROL" */
25071 /* Performance Counter 4 Control */
25072 /* ==================================================================== */
25074 #define SH_PERFORMANCE_COUNT4_CONTROL 0x00000001100c0000
25075 #define SH_PERFORMANCE_COUNT4_CONTROL_MASK 0x000000000007ffff
25076 #define SH_PERFORMANCE_COUNT4_CONTROL_INIT 0x000000000000b8b8
25078 /* SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS */
25079 /* Description: Counter 4 up stimulus */
25080 #define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_SHFT 0
25081 #define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
25083 /* SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT */
25084 /* Description: Counter 4 up event select (1-greater than, 0-equal) */
25085 #define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_SHFT 5
25086 #define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_MASK 0x0000000000000020
25088 /* SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY */
25089 /* Description: Counter 4 up polarity select (1-negative edge, 0-po */
25091 #define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_SHFT 6
25092 #define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_MASK 0x0000000000000040
25094 /* SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE */
25095 /* Description: Counter 4 up mode select (1-internal, 0-external) */
25096 #define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_SHFT 7
25097 #define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_MASK 0x0000000000000080
25099 /* SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS */
25100 /* Description: Counter 4 down stimulus */
25101 #define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_SHFT 8
25102 #define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
25104 /* SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT */
25105 /* Description: Counter 4 down event select (1-greater than, 0-equa */
25106 #define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_SHFT 13
25107 #define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_MASK 0x0000000000002000
25109 /* SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY */
25110 /* Description: Counter 4 down polarity select (1-negative edge, 0- */
25111 /* positive edge) */
25112 #define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_SHFT 14
25113 #define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_MASK 0x0000000000004000
25115 /* SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE */
25116 /* Description: Counter 4 down mode select (1-internal, 0-external) */
25117 #define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_SHFT 15
25118 #define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_MASK 0x0000000000008000
25120 /* SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE */
25121 /* Description: Counter 4 enable increment */
25122 #define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_SHFT 16
25123 #define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_MASK 0x0000000000010000
25125 /* SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE */
25126 /* Description: Counter 4 enable decrement */
25127 #define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_SHFT 17
25128 #define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
25130 /* SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE */
25131 /* Description: Counter 4 enable peak detection */
25132 #define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_SHFT 18
25133 #define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
25135 /* ==================================================================== */
25136 /* Register "SH_PERFORMANCE_COUNT5_CONTROL" */
25137 /* Performance Counter 5 Control */
25138 /* ==================================================================== */
25140 #define SH_PERFORMANCE_COUNT5_CONTROL 0x00000001100d0000
25141 #define SH_PERFORMANCE_COUNT5_CONTROL_MASK 0x000000000007ffff
25142 #define SH_PERFORMANCE_COUNT5_CONTROL_INIT 0x000000000000b8b8
25144 /* SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS */
25145 /* Description: Counter 5 up stimulus */
25146 #define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_SHFT 0
25147 #define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
25149 /* SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT */
25150 /* Description: Counter 5 up event select (1-greater than, 0-equal) */
25151 #define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_SHFT 5
25152 #define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_MASK 0x0000000000000020
25154 /* SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY */
25155 /* Description: Counter 5 up polarity select (1-negative edge, 0-po */
25157 #define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_SHFT 6
25158 #define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_MASK 0x0000000000000040
25160 /* SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE */
25161 /* Description: Counter 5 up mode select (1-internal, 0-external) */
25162 #define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_SHFT 7
25163 #define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_MASK 0x0000000000000080
25165 /* SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS */
25166 /* Description: Counter 5 down stimulus */
25167 #define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_SHFT 8
25168 #define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
25170 /* SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT */
25171 /* Description: Counter 5 down event select (1-greater than, 0-equa */
25172 #define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_SHFT 13
25173 #define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_MASK 0x0000000000002000
25175 /* SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY */
25176 /* Description: Counter 5 down polarity select (1-negative edge, 0- */
25177 /* positive edge) */
25178 #define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_SHFT 14
25179 #define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_MASK 0x0000000000004000
25181 /* SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE */
25182 /* Description: Counter 5 down mode select (1-internal, 0-external) */
25183 #define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_SHFT 15
25184 #define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_MASK 0x0000000000008000
25186 /* SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE */
25187 /* Description: Counter 5 enable increment */
25188 #define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_SHFT 16
25189 #define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_MASK 0x0000000000010000
25191 /* SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE */
25192 /* Description: Counter 5 enable decrement */
25193 #define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_SHFT 17
25194 #define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
25196 /* SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE */
25197 /* Description: Counter 5 enable peak detection */
25198 #define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_SHFT 18
25199 #define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
25201 /* ==================================================================== */
25202 /* Register "SH_PERFORMANCE_COUNT6_CONTROL" */
25203 /* Performance Counter 6 Control */
25204 /* ==================================================================== */
25206 #define SH_PERFORMANCE_COUNT6_CONTROL 0x00000001100e0000
25207 #define SH_PERFORMANCE_COUNT6_CONTROL_MASK 0x000000000007ffff
25208 #define SH_PERFORMANCE_COUNT6_CONTROL_INIT 0x000000000000b8b8
25210 /* SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS */
25211 /* Description: Counter 6 up stimulus */
25212 #define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_SHFT 0
25213 #define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
25215 /* SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT */
25216 /* Description: Counter 6 up event select (1-greater than, 0-equal) */
25217 #define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_SHFT 5
25218 #define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_MASK 0x0000000000000020
25220 /* SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY */
25221 /* Description: Counter 6 up polarity select (1-negative edge, 0-po */
25223 #define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_SHFT 6
25224 #define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_MASK 0x0000000000000040
25226 /* SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE */
25227 /* Description: Counter 6 up mode select (1-internal, 0-external) */
25228 #define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_SHFT 7
25229 #define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_MASK 0x0000000000000080
25231 /* SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS */
25232 /* Description: Counter 6 down stimulus */
25233 #define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_SHFT 8
25234 #define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
25236 /* SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT */
25237 /* Description: Counter 6 down event select (1-greater than, 0-equa */
25238 #define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_SHFT 13
25239 #define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_MASK 0x0000000000002000
25241 /* SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY */
25242 /* Description: Counter 6 down polarity select (1-negative edge, 0- */
25243 /* positive edge) */
25244 #define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_SHFT 14
25245 #define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_MASK 0x0000000000004000
25247 /* SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE */
25248 /* Description: Counter 6 down mode select (1-internal, 0-external) */
25249 #define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_SHFT 15
25250 #define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_MASK 0x0000000000008000
25252 /* SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE */
25253 /* Description: Counter 6 enable increment */
25254 #define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_SHFT 16
25255 #define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_MASK 0x0000000000010000
25257 /* SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE */
25258 /* Description: Counter 6 enable decrement */
25259 #define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_SHFT 17
25260 #define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
25262 /* SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE */
25263 /* Description: Counter 6 enable peak detection */
25264 #define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_SHFT 18
25265 #define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
25267 /* ==================================================================== */
25268 /* Register "SH_PERFORMANCE_COUNT7_CONTROL" */
25269 /* Performance Counter 7 Control */
25270 /* ==================================================================== */
25272 #define SH_PERFORMANCE_COUNT7_CONTROL 0x00000001100f0000
25273 #define SH_PERFORMANCE_COUNT7_CONTROL_MASK 0x000000000007ffff
25274 #define SH_PERFORMANCE_COUNT7_CONTROL_INIT 0x000000000000b8b8
25276 /* SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS */
25277 /* Description: Counter 7 up stimulus */
25278 #define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_SHFT 0
25279 #define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
25281 /* SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT */
25282 /* Description: Counter 7 up event select (1-greater than, 0-equal) */
25283 #define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_SHFT 5
25284 #define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_MASK 0x0000000000000020
25286 /* SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY */
25287 /* Description: Counter 7 up polarity select (1-negative edge, 0-po */
25289 #define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_SHFT 6
25290 #define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_MASK 0x0000000000000040
25292 /* SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE */
25293 /* Description: Counter 7 up mode select (1-internal, 0-external) */
25294 #define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_SHFT 7
25295 #define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_MASK 0x0000000000000080
25297 /* SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS */
25298 /* Description: Counter 7 down stimulus */
25299 #define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_SHFT 8
25300 #define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
25302 /* SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT */
25303 /* Description: Counter 7 down event select (1-greater than, 0-equa */
25304 #define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_SHFT 13
25305 #define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_MASK 0x0000000000002000
25307 /* SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY */
25308 /* Description: Counter 7 down polarity select (1-negative edge, 0- */
25309 /* positive edge) */
25310 #define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_SHFT 14
25311 #define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_MASK 0x0000000000004000
25313 /* SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE */
25314 /* Description: Counter 7 down mode select (1-internal, 0-external) */
25315 #define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_SHFT 15
25316 #define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_MASK 0x0000000000008000
25318 /* SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE */
25319 /* Description: Counter 7 enable increment */
25320 #define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_SHFT 16
25321 #define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_MASK 0x0000000000010000
25323 /* SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE */
25324 /* Description: Counter 7 enable decrement */
25325 #define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_SHFT 17
25326 #define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
25328 /* SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE */
25329 /* Description: Counter 7 enable peak detection */
25330 #define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_SHFT 18
25331 #define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
25333 /* ==================================================================== */
25334 /* Register "SH_PROFILE_DN_CONTROL" */
25335 /* Profile Counter Down Control */
25336 /* ==================================================================== */
25338 #define SH_PROFILE_DN_CONTROL 0x0000000110100000
25339 #define SH_PROFILE_DN_CONTROL_MASK 0x00000000000000ff
25340 #define SH_PROFILE_DN_CONTROL_INIT 0x00000000000000b8
25342 /* SH_PROFILE_DN_CONTROL_STIMULUS */
25343 /* Description: Counter stimulus */
25344 #define SH_PROFILE_DN_CONTROL_STIMULUS_SHFT 0
25345 #define SH_PROFILE_DN_CONTROL_STIMULUS_MASK 0x000000000000001f
25347 /* SH_PROFILE_DN_CONTROL_EVENT */
25348 /* Description: Counter event select (1-greater than, 0-equal) */
25349 #define SH_PROFILE_DN_CONTROL_EVENT_SHFT 5
25350 #define SH_PROFILE_DN_CONTROL_EVENT_MASK 0x0000000000000020
25352 /* SH_PROFILE_DN_CONTROL_POLARITY */
25353 /* Description: Counter polarity select (1-negative edge, 0-positiv */
25355 #define SH_PROFILE_DN_CONTROL_POLARITY_SHFT 6
25356 #define SH_PROFILE_DN_CONTROL_POLARITY_MASK 0x0000000000000040
25358 /* SH_PROFILE_DN_CONTROL_MODE */
25359 /* Description: Counter mode select (1-internal, 0-external) */
25360 #define SH_PROFILE_DN_CONTROL_MODE_SHFT 7
25361 #define SH_PROFILE_DN_CONTROL_MODE_MASK 0x0000000000000080
25363 /* ==================================================================== */
25364 /* Register "SH_PROFILE_PEAK_CONTROL" */
25365 /* Profile Counter Peak Control */
25366 /* ==================================================================== */
25368 #define SH_PROFILE_PEAK_CONTROL 0x0000000110100080
25369 #define SH_PROFILE_PEAK_CONTROL_MASK 0x0000000000000068
25370 #define SH_PROFILE_PEAK_CONTROL_INIT 0x0000000000000060
25372 /* SH_PROFILE_PEAK_CONTROL_STIMULUS */
25373 /* Description: Counter stimulus */
25374 #define SH_PROFILE_PEAK_CONTROL_STIMULUS_SHFT 3
25375 #define SH_PROFILE_PEAK_CONTROL_STIMULUS_MASK 0x0000000000000008
25377 /* SH_PROFILE_PEAK_CONTROL_EVENT */
25378 /* Description: Counter event select (0-greater than, 1-equal) */
25379 #define SH_PROFILE_PEAK_CONTROL_EVENT_SHFT 5
25380 #define SH_PROFILE_PEAK_CONTROL_EVENT_MASK 0x0000000000000020
25382 /* SH_PROFILE_PEAK_CONTROL_POLARITY */
25383 /* Description: Counter polarity select (0-negative edge, 1-positiv */
25385 #define SH_PROFILE_PEAK_CONTROL_POLARITY_SHFT 6
25386 #define SH_PROFILE_PEAK_CONTROL_POLARITY_MASK 0x0000000000000040
25388 /* ==================================================================== */
25389 /* Register "SH_PROFILE_RANGE" */
25390 /* Profile Counter Range */
25391 /* ==================================================================== */
25393 #define SH_PROFILE_RANGE 0x0000000110100100
25394 #define SH_PROFILE_RANGE_MASK 0xffffffffffffffff
25395 #define SH_PROFILE_RANGE_INIT 0x0000000000000000
25397 /* SH_PROFILE_RANGE_RANGE0 */
25398 /* Description: Profiling range 0 */
25399 #define SH_PROFILE_RANGE_RANGE0_SHFT 0
25400 #define SH_PROFILE_RANGE_RANGE0_MASK 0x00000000000000ff
25402 /* SH_PROFILE_RANGE_RANGE1 */
25403 /* Description: Profiling range 1 */
25404 #define SH_PROFILE_RANGE_RANGE1_SHFT 8
25405 #define SH_PROFILE_RANGE_RANGE1_MASK 0x000000000000ff00
25407 /* SH_PROFILE_RANGE_RANGE2 */
25408 /* Description: Profiling range 2 */
25409 #define SH_PROFILE_RANGE_RANGE2_SHFT 16
25410 #define SH_PROFILE_RANGE_RANGE2_MASK 0x0000000000ff0000
25412 /* SH_PROFILE_RANGE_RANGE3 */
25413 /* Description: Profiling range 3 */
25414 #define SH_PROFILE_RANGE_RANGE3_SHFT 24
25415 #define SH_PROFILE_RANGE_RANGE3_MASK 0x00000000ff000000
25417 /* SH_PROFILE_RANGE_RANGE4 */
25418 /* Description: Profiling range 4 */
25419 #define SH_PROFILE_RANGE_RANGE4_SHFT 32
25420 #define SH_PROFILE_RANGE_RANGE4_MASK 0x000000ff00000000
25422 /* SH_PROFILE_RANGE_RANGE5 */
25423 /* Description: Profiling range 5 */
25424 #define SH_PROFILE_RANGE_RANGE5_SHFT 40
25425 #define SH_PROFILE_RANGE_RANGE5_MASK 0x0000ff0000000000
25427 /* SH_PROFILE_RANGE_RANGE6 */
25428 /* Description: Profiling range 6 */
25429 #define SH_PROFILE_RANGE_RANGE6_SHFT 48
25430 #define SH_PROFILE_RANGE_RANGE6_MASK 0x00ff000000000000
25432 /* SH_PROFILE_RANGE_RANGE7 */
25433 /* Description: Profiling range 7 */
25434 #define SH_PROFILE_RANGE_RANGE7_SHFT 56
25435 #define SH_PROFILE_RANGE_RANGE7_MASK 0xff00000000000000
25437 /* ==================================================================== */
25438 /* Register "SH_PROFILE_UP_CONTROL" */
25439 /* Profile Counter Up Control */
25440 /* ==================================================================== */
25442 #define SH_PROFILE_UP_CONTROL 0x0000000110100180
25443 #define SH_PROFILE_UP_CONTROL_MASK 0x00000000000000ff
25444 #define SH_PROFILE_UP_CONTROL_INIT 0x00000000000000b8
25446 /* SH_PROFILE_UP_CONTROL_STIMULUS */
25447 /* Description: Counter stimulus */
25448 #define SH_PROFILE_UP_CONTROL_STIMULUS_SHFT 0
25449 #define SH_PROFILE_UP_CONTROL_STIMULUS_MASK 0x000000000000001f
25451 /* SH_PROFILE_UP_CONTROL_EVENT */
25452 /* Description: Counter event select (1-greater than, 0-equal) */
25453 #define SH_PROFILE_UP_CONTROL_EVENT_SHFT 5
25454 #define SH_PROFILE_UP_CONTROL_EVENT_MASK 0x0000000000000020
25456 /* SH_PROFILE_UP_CONTROL_POLARITY */
25457 /* Description: Counter polarity select (1-negative edge, 0-positiv */
25459 #define SH_PROFILE_UP_CONTROL_POLARITY_SHFT 6
25460 #define SH_PROFILE_UP_CONTROL_POLARITY_MASK 0x0000000000000040
25462 /* SH_PROFILE_UP_CONTROL_MODE */
25463 /* Description: Counter mode select (1-internal, 0-external) */
25464 #define SH_PROFILE_UP_CONTROL_MODE_SHFT 7
25465 #define SH_PROFILE_UP_CONTROL_MODE_MASK 0x0000000000000080
25467 /* ==================================================================== */
25468 /* Register "SH_PERFORMANCE_COUNTER0" */
25469 /* Performance Counter 0 */
25470 /* ==================================================================== */
25472 #define SH_PERFORMANCE_COUNTER0 0x0000000110110000
25473 #define SH_PERFORMANCE_COUNTER0_MASK 0x00000000ffffffff
25474 #define SH_PERFORMANCE_COUNTER0_INIT 0x0000000000000000
25476 /* SH_PERFORMANCE_COUNTER0_COUNT */
25477 /* Description: Counter 0 */
25478 #define SH_PERFORMANCE_COUNTER0_COUNT_SHFT 0
25479 #define SH_PERFORMANCE_COUNTER0_COUNT_MASK 0x00000000ffffffff
25481 /* ==================================================================== */
25482 /* Register "SH_PERFORMANCE_COUNTER1" */
25483 /* Performance Counter 1 */
25484 /* ==================================================================== */
25486 #define SH_PERFORMANCE_COUNTER1 0x0000000110120000
25487 #define SH_PERFORMANCE_COUNTER1_MASK 0x00000000ffffffff
25488 #define SH_PERFORMANCE_COUNTER1_INIT 0x0000000000000000
25490 /* SH_PERFORMANCE_COUNTER1_COUNT */
25491 /* Description: Counter 1 */
25492 #define SH_PERFORMANCE_COUNTER1_COUNT_SHFT 0
25493 #define SH_PERFORMANCE_COUNTER1_COUNT_MASK 0x00000000ffffffff
25495 /* ==================================================================== */
25496 /* Register "SH_PERFORMANCE_COUNTER2" */
25497 /* Performance Counter 2 */
25498 /* ==================================================================== */
25500 #define SH_PERFORMANCE_COUNTER2 0x0000000110130000
25501 #define SH_PERFORMANCE_COUNTER2_MASK 0x00000000ffffffff
25502 #define SH_PERFORMANCE_COUNTER2_INIT 0x0000000000000000
25504 /* SH_PERFORMANCE_COUNTER2_COUNT */
25505 /* Description: Counter 2 */
25506 #define SH_PERFORMANCE_COUNTER2_COUNT_SHFT 0
25507 #define SH_PERFORMANCE_COUNTER2_COUNT_MASK 0x00000000ffffffff
25509 /* ==================================================================== */
25510 /* Register "SH_PERFORMANCE_COUNTER3" */
25511 /* Performance Counter 3 */
25512 /* ==================================================================== */
25514 #define SH_PERFORMANCE_COUNTER3 0x0000000110140000
25515 #define SH_PERFORMANCE_COUNTER3_MASK 0x00000000ffffffff
25516 #define SH_PERFORMANCE_COUNTER3_INIT 0x0000000000000000
25518 /* SH_PERFORMANCE_COUNTER3_COUNT */
25519 /* Description: Counter 3 */
25520 #define SH_PERFORMANCE_COUNTER3_COUNT_SHFT 0
25521 #define SH_PERFORMANCE_COUNTER3_COUNT_MASK 0x00000000ffffffff
25523 /* ==================================================================== */
25524 /* Register "SH_PERFORMANCE_COUNTER4" */
25525 /* Performance Counter 4 */
25526 /* ==================================================================== */
25528 #define SH_PERFORMANCE_COUNTER4 0x0000000110150000
25529 #define SH_PERFORMANCE_COUNTER4_MASK 0x00000000ffffffff
25530 #define SH_PERFORMANCE_COUNTER4_INIT 0x0000000000000000
25532 /* SH_PERFORMANCE_COUNTER4_COUNT */
25533 /* Description: Counter 4 */
25534 #define SH_PERFORMANCE_COUNTER4_COUNT_SHFT 0
25535 #define SH_PERFORMANCE_COUNTER4_COUNT_MASK 0x00000000ffffffff
25537 /* ==================================================================== */
25538 /* Register "SH_PERFORMANCE_COUNTER5" */
25539 /* Performance Counter 5 */
25540 /* ==================================================================== */
25542 #define SH_PERFORMANCE_COUNTER5 0x0000000110160000
25543 #define SH_PERFORMANCE_COUNTER5_MASK 0x00000000ffffffff
25544 #define SH_PERFORMANCE_COUNTER5_INIT 0x0000000000000000
25546 /* SH_PERFORMANCE_COUNTER5_COUNT */
25547 /* Description: Counter 5 */
25548 #define SH_PERFORMANCE_COUNTER5_COUNT_SHFT 0
25549 #define SH_PERFORMANCE_COUNTER5_COUNT_MASK 0x00000000ffffffff
25551 /* ==================================================================== */
25552 /* Register "SH_PERFORMANCE_COUNTER6" */
25553 /* Performance Counter 6 */
25554 /* ==================================================================== */
25556 #define SH_PERFORMANCE_COUNTER6 0x0000000110170000
25557 #define SH_PERFORMANCE_COUNTER6_MASK 0x00000000ffffffff
25558 #define SH_PERFORMANCE_COUNTER6_INIT 0x0000000000000000
25560 /* SH_PERFORMANCE_COUNTER6_COUNT */
25561 /* Description: Counter 6 */
25562 #define SH_PERFORMANCE_COUNTER6_COUNT_SHFT 0
25563 #define SH_PERFORMANCE_COUNTER6_COUNT_MASK 0x00000000ffffffff
25565 /* ==================================================================== */
25566 /* Register "SH_PERFORMANCE_COUNTER7" */
25567 /* Performance Counter 7 */
25568 /* ==================================================================== */
25570 #define SH_PERFORMANCE_COUNTER7 0x0000000110180000
25571 #define SH_PERFORMANCE_COUNTER7_MASK 0x00000000ffffffff
25572 #define SH_PERFORMANCE_COUNTER7_INIT 0x0000000000000000
25574 /* SH_PERFORMANCE_COUNTER7_COUNT */
25575 /* Description: Counter 7 */
25576 #define SH_PERFORMANCE_COUNTER7_COUNT_SHFT 0
25577 #define SH_PERFORMANCE_COUNTER7_COUNT_MASK 0x00000000ffffffff
25579 /* ==================================================================== */
25580 /* Register "SH_PROFILE_COUNTER" */
25581 /* Profile Counter */
25582 /* ==================================================================== */
25584 #define SH_PROFILE_COUNTER 0x0000000110190000
25585 #define SH_PROFILE_COUNTER_MASK 0x00000000000000ff
25586 #define SH_PROFILE_COUNTER_INIT 0x0000000000000000
25588 /* SH_PROFILE_COUNTER_COUNTER */
25589 /* Description: Counter Value */
25590 #define SH_PROFILE_COUNTER_COUNTER_SHFT 0
25591 #define SH_PROFILE_COUNTER_COUNTER_MASK 0x00000000000000ff
25593 /* ==================================================================== */
25594 /* Register "SH_PROFILE_PEAK" */
25595 /* Profile Peak Counter */
25596 /* ==================================================================== */
25598 #define SH_PROFILE_PEAK 0x0000000110190080
25599 #define SH_PROFILE_PEAK_MASK 0x00000000000000ff
25600 #define SH_PROFILE_PEAK_INIT 0x0000000000000000
25602 /* SH_PROFILE_PEAK_COUNTER */
25603 /* Description: Counter Value */
25604 #define SH_PROFILE_PEAK_COUNTER_SHFT 0
25605 #define SH_PROFILE_PEAK_COUNTER_MASK 0x00000000000000ff
25607 /* ==================================================================== */
25608 /* Register "SH_PTC_0" */
25609 /* Puge Translation Cache Message Configuration Information */
25610 /* ==================================================================== */
25612 #define SH_PTC_0 0x00000001101a0000
25613 #define SH_PTC_0_MASK 0x80000000fffffffd
25614 #define SH_PTC_0_INIT 0x0000000000000000
25617 /* Description: Type */
25618 #define SH_PTC_0_A_SHFT 0
25619 #define SH_PTC_0_A_MASK 0x0000000000000001
25622 /* Description: Page Size */
25623 #define SH_PTC_0_PS_SHFT 2
25624 #define SH_PTC_0_PS_MASK 0x00000000000000fc
25627 /* Description: Region ID */
25628 #define SH_PTC_0_RID_SHFT 8
25629 #define SH_PTC_0_RID_MASK 0x00000000ffffff00
25631 /* SH_PTC_0_START */
25632 /* Description: Start */
25633 #define SH_PTC_0_START_SHFT 63
25634 #define SH_PTC_0_START_MASK 0x8000000000000000
25636 /* ==================================================================== */
25637 /* Register "SH_PTC_1" */
25638 /* Puge Translation Cache Message Configuration Information */
25639 /* ==================================================================== */
25641 #define SH_PTC_1 0x00000001101a0080
25642 #define SH_PTC_1_MASK 0x9ffffffffffff000
25643 #define SH_PTC_1_INIT 0x0000000000000000
25646 /* Description: Virtual page number */
25647 #define SH_PTC_1_VPN_SHFT 12
25648 #define SH_PTC_1_VPN_MASK 0x1ffffffffffff000
25650 /* SH_PTC_1_START */
25651 /* Description: PTC_1 Start */
25652 #define SH_PTC_1_START_SHFT 63
25653 #define SH_PTC_1_START_MASK 0x8000000000000000
25655 /* ==================================================================== */
25656 /* Register "SH_PTC_PARMS" */
25657 /* PTC Time-out parmaeters */
25658 /* ==================================================================== */
25660 #define SH_PTC_PARMS 0x00000001101a0100
25661 #define SH_PTC_PARMS_MASK 0x0000000fffffffff
25662 #define SH_PTC_PARMS_INIT 0x00000007ffffffff
25664 /* SH_PTC_PARMS_PTC_TO_WRAP */
25665 /* Description: PTC time-out period */
25666 #define SH_PTC_PARMS_PTC_TO_WRAP_SHFT 0
25667 #define SH_PTC_PARMS_PTC_TO_WRAP_MASK 0x0000000000ffffff
25669 /* SH_PTC_PARMS_PTC_TO_VAL */
25670 /* Description: PTC time-out valid */
25671 #define SH_PTC_PARMS_PTC_TO_VAL_SHFT 24
25672 #define SH_PTC_PARMS_PTC_TO_VAL_MASK 0x0000000fff000000
25674 /* ==================================================================== */
25675 /* Register "SH_INT_CMPA" */
25676 /* RTC Compare Value for Processor A */
25677 /* ==================================================================== */
25679 #define SH_INT_CMPA 0x00000001101b0000
25680 #define SH_INT_CMPA_MASK 0x007fffffffffffff
25681 #define SH_INT_CMPA_INIT 0x0000000000000000
25683 /* SH_INT_CMPA_REAL_TIME_CMPA */
25684 /* Description: Real Time Clock Compare */
25685 #define SH_INT_CMPA_REAL_TIME_CMPA_SHFT 0
25686 #define SH_INT_CMPA_REAL_TIME_CMPA_MASK 0x007fffffffffffff
25688 /* ==================================================================== */
25689 /* Register "SH_INT_CMPB" */
25690 /* RTC Compare Value for Processor B */
25691 /* ==================================================================== */
25693 #define SH_INT_CMPB 0x00000001101b0080
25694 #define SH_INT_CMPB_MASK 0x007fffffffffffff
25695 #define SH_INT_CMPB_INIT 0x0000000000000000
25697 /* SH_INT_CMPB_REAL_TIME_CMPB */
25698 /* Description: Real Time Clock Compare */
25699 #define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
25700 #define SH_INT_CMPB_REAL_TIME_CMPB_MASK 0x007fffffffffffff
25702 /* ==================================================================== */
25703 /* Register "SH_INT_CMPC" */
25704 /* RTC Compare Value for Processor C */
25705 /* ==================================================================== */
25707 #define SH_INT_CMPC 0x00000001101b0100
25708 #define SH_INT_CMPC_MASK 0x007fffffffffffff
25709 #define SH_INT_CMPC_INIT 0x0000000000000000
25711 /* SH_INT_CMPC_REAL_TIME_CMPC */
25712 /* Description: Real Time Clock Compare */
25713 #define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
25714 #define SH_INT_CMPC_REAL_TIME_CMPC_MASK 0x007fffffffffffff
25716 /* ==================================================================== */
25717 /* Register "SH_INT_CMPD" */
25718 /* RTC Compare Value for Processor D */
25719 /* ==================================================================== */
25721 #define SH_INT_CMPD 0x00000001101b0180
25722 #define SH_INT_CMPD_MASK 0x007fffffffffffff
25723 #define SH_INT_CMPD_INIT 0x0000000000000000
25725 /* SH_INT_CMPD_REAL_TIME_CMPD */
25726 /* Description: Real Time Clock Compare */
25727 #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
25728 #define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff
25730 /* ==================================================================== */
25731 /* Register "SH_INT_PROF" */
25732 /* Profile Compare Registers */
25733 /* ==================================================================== */
25735 #define SH_INT_PROF 0x00000001101b0200
25736 #define SH_INT_PROF_MASK 0x00000000ffffffff
25737 #define SH_INT_PROF_INIT 0x0000000000000000
25739 /* SH_INT_PROF_PROFILE_COMPARE */
25740 /* Description: Profile Compare */
25741 #define SH_INT_PROF_PROFILE_COMPARE_SHFT 0
25742 #define SH_INT_PROF_PROFILE_COMPARE_MASK 0x00000000ffffffff
25744 /* ==================================================================== */
25745 /* Register "SH_RTC" */
25746 /* Real-time Clock */
25747 /* ==================================================================== */
25749 #define SH_RTC 0x00000001101c0000UL
25750 #define SH_RTC_MASK 0x007fffffffffffffUL
25751 #define SH_RTC_INIT 0x0000000000000000
25753 /* SH_RTC_REAL_TIME_CLOCK */
25754 /* Description: Real-time Clock */
25755 #define SH_RTC_REAL_TIME_CLOCK_SHFT 0
25756 #define SH_RTC_REAL_TIME_CLOCK_MASK 0x007fffffffffffffUL
25758 /* ==================================================================== */
25759 /* Register "SH_SCRATCH0" */
25760 /* Scratch Register 0 */
25761 /* ==================================================================== */
25763 #define SH_SCRATCH0 0x00000001101d0000
25764 #define SH_SCRATCH0_MASK 0xffffffffffffffff
25765 #define SH_SCRATCH0_INIT 0x0000000000000000
25767 /* SH_SCRATCH0_SCRATCH0 */
25768 /* Description: Scratch register 0 */
25769 #define SH_SCRATCH0_SCRATCH0_SHFT 0
25770 #define SH_SCRATCH0_SCRATCH0_MASK 0xffffffffffffffff
25772 /* ==================================================================== */
25773 /* Register "SH_SCRATCH0_ALIAS" */
25774 /* Scratch Register 0 Alias Address */
25775 /* ==================================================================== */
25777 #define SH_SCRATCH0_ALIAS 0x00000001101d0008
25779 /* ==================================================================== */
25780 /* Register "SH_SCRATCH1" */
25781 /* Scratch Register 1 */
25782 /* ==================================================================== */
25784 #define SH_SCRATCH1 0x00000001101d0080
25785 #define SH_SCRATCH1_MASK 0xffffffffffffffff
25786 #define SH_SCRATCH1_INIT 0x0000000000000000
25788 /* SH_SCRATCH1_SCRATCH1 */
25789 /* Description: Scratch register 1 */
25790 #define SH_SCRATCH1_SCRATCH1_SHFT 0
25791 #define SH_SCRATCH1_SCRATCH1_MASK 0xffffffffffffffff
25793 /* ==================================================================== */
25794 /* Register "SH_SCRATCH1_ALIAS" */
25795 /* Scratch Register 1 Alias Address */
25796 /* ==================================================================== */
25798 #define SH_SCRATCH1_ALIAS 0x00000001101d0088
25800 /* ==================================================================== */
25801 /* Register "SH_SCRATCH2" */
25802 /* Scratch Register 2 */
25803 /* ==================================================================== */
25805 #define SH_SCRATCH2 0x00000001101d0100
25806 #define SH_SCRATCH2_MASK 0xffffffffffffffff
25807 #define SH_SCRATCH2_INIT 0x0000000000000000
25809 /* SH_SCRATCH2_SCRATCH2 */
25810 /* Description: Scratch register 2 */
25811 #define SH_SCRATCH2_SCRATCH2_SHFT 0
25812 #define SH_SCRATCH2_SCRATCH2_MASK 0xffffffffffffffff
25814 /* ==================================================================== */
25815 /* Register "SH_SCRATCH2_ALIAS" */
25816 /* Scratch Register 2 Alias Address */
25817 /* ==================================================================== */
25819 #define SH_SCRATCH2_ALIAS 0x00000001101d0108
25821 /* ==================================================================== */
25822 /* Register "SH_SCRATCH3" */
25823 /* Scratch Register 3 */
25824 /* ==================================================================== */
25826 #define SH_SCRATCH3 0x00000001101d0180
25827 #define SH_SCRATCH3_MASK 0x0000000000000001
25828 #define SH_SCRATCH3_INIT 0x0000000000000000
25830 /* SH_SCRATCH3_SCRATCH3 */
25831 /* Description: Scratch register 3 */
25832 #define SH_SCRATCH3_SCRATCH3_SHFT 0
25833 #define SH_SCRATCH3_SCRATCH3_MASK 0x0000000000000001
25835 /* ==================================================================== */
25836 /* Register "SH_SCRATCH3_ALIAS" */
25837 /* Scratch Register 3 Alias Address */
25838 /* ==================================================================== */
25840 #define SH_SCRATCH3_ALIAS 0x00000001101d0188
25842 /* ==================================================================== */
25843 /* Register "SH_SCRATCH4" */
25844 /* Scratch Register 4 */
25845 /* ==================================================================== */
25847 #define SH_SCRATCH4 0x00000001101d0200
25848 #define SH_SCRATCH4_MASK 0x0000000000000001
25849 #define SH_SCRATCH4_INIT 0x0000000000000000
25851 /* SH_SCRATCH4_SCRATCH4 */
25852 /* Description: Scratch register 4 */
25853 #define SH_SCRATCH4_SCRATCH4_SHFT 0
25854 #define SH_SCRATCH4_SCRATCH4_MASK 0x0000000000000001
25856 /* ==================================================================== */
25857 /* Register "SH_SCRATCH4_ALIAS" */
25858 /* Scratch Register 4 Alias Address */
25859 /* ==================================================================== */
25861 #define SH_SCRATCH4_ALIAS 0x00000001101d0208
25863 /* ==================================================================== */
25864 /* Register "SH_CRB_MESSAGE_CONTROL" */
25865 /* Coherent Request Buffer Message Control */
25866 /* ==================================================================== */
25868 #define SH_CRB_MESSAGE_CONTROL 0x0000000120000000
25869 #define SH_CRB_MESSAGE_CONTROL_MASK 0xffffffff00000fff
25870 #define SH_CRB_MESSAGE_CONTROL_INIT 0x0000000000000006
25872 /* SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE */
25873 /* Description: System Coherence Enabled */
25874 #define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_SHFT 0
25875 #define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_MASK 0x0000000000000001
25877 /* SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE */
25878 /* Description: Speculative Read Requests to Local Memory Enabled */
25879 #define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_SHFT 1
25880 #define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000002
25882 /* SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE */
25883 /* Description: Speculative Read Requests to Remote Memory Enabled */
25884 #define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_SHFT 2
25885 #define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000004
25887 /* SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR */
25888 /* Description: Define color of message */
25889 #define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_SHFT 3
25890 #define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_MASK 0x0000000000000008
25892 /* SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE */
25893 /* Description: Enable color message processing */
25894 #define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_SHFT 4
25895 #define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_MASK 0x0000000000000010
25897 /* SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */
25898 /* Description: Enable FSB RRB Mismatch check */
25899 #define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 5
25900 #define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000020
25902 /* SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */
25903 /* Description: Enable FSB WRB Mismatch check */
25904 #define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 6
25905 #define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000040
25907 /* SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */
25908 /* Description: Enable FSB IRB Mismatch check */
25909 #define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 7
25910 #define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000080
25912 /* SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE */
25913 /* Description: Enable XB RRB Mismatch check */
25914 #define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 8
25915 #define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000100
25917 /* SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE */
25918 /* Description: Enable XB WRB Mismatch check */
25919 #define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 9
25920 #define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000200
25922 /* SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES */
25923 /* Description: ignor residual write data */
25924 #define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_SHFT 10
25925 #define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_MASK 0x0000000000000400
25927 /* SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION */
25928 /* Description: enable IVACK reply consolidation */
25929 #define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_SHFT 11
25930 #define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_MASK 0x0000000000000800
25932 /* SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT */
25933 /* Description: IVACK stall counter */
25934 #define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_SHFT 32
25935 #define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_MASK 0x0000ffff00000000
25937 /* SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL */
25938 /* Description: IVACK throttling limit/timer control */
25939 #define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_SHFT 48
25940 #define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_MASK 0xffff000000000000
25942 /* ==================================================================== */
25943 /* Register "SH_CRB_NACK_LIMIT" */
25944 /* CRB Nack Limit */
25945 /* ==================================================================== */
25947 #define SH_CRB_NACK_LIMIT 0x0000000120000080
25948 #define SH_CRB_NACK_LIMIT_MASK 0x800000000000ffff
25949 #define SH_CRB_NACK_LIMIT_INIT 0x0000000000000000
25951 /* SH_CRB_NACK_LIMIT_LIMIT */
25952 /* Description: Nack Count Limit */
25953 #define SH_CRB_NACK_LIMIT_LIMIT_SHFT 0
25954 #define SH_CRB_NACK_LIMIT_LIMIT_MASK 0x0000000000000fff
25956 /* SH_CRB_NACK_LIMIT_PRI_FREQ */
25957 /* Description: Frequency at which priority count is incremented */
25958 #define SH_CRB_NACK_LIMIT_PRI_FREQ_SHFT 12
25959 #define SH_CRB_NACK_LIMIT_PRI_FREQ_MASK 0x000000000000f000
25961 /* SH_CRB_NACK_LIMIT_ENABLE */
25962 /* Description: Enable NACK limit detection */
25963 #define SH_CRB_NACK_LIMIT_ENABLE_SHFT 63
25964 #define SH_CRB_NACK_LIMIT_ENABLE_MASK 0x8000000000000000
25966 /* ==================================================================== */
25967 /* Register "SH_CRB_TIMEOUT_PRESCALE" */
25968 /* Coherent Request Buffer Timeout Prescale */
25969 /* ==================================================================== */
25971 #define SH_CRB_TIMEOUT_PRESCALE 0x0000000120000100
25972 #define SH_CRB_TIMEOUT_PRESCALE_MASK 0x00000000ffffffff
25973 #define SH_CRB_TIMEOUT_PRESCALE_INIT 0x0000000000000000
25975 /* SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR */
25976 /* Description: CRB Time-out Prescale Factor */
25977 #define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_SHFT 0
25978 #define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_MASK 0x00000000ffffffff
25980 /* ==================================================================== */
25981 /* Register "SH_CRB_TIMEOUT_SKID" */
25982 /* Coherent Request Buffer Timeout Skid Limit */
25983 /* ==================================================================== */
25985 #define SH_CRB_TIMEOUT_SKID 0x0000000120000180
25986 #define SH_CRB_TIMEOUT_SKID_MASK 0x800000000000003f
25987 #define SH_CRB_TIMEOUT_SKID_INIT 0x0000000000000007
25989 /* SH_CRB_TIMEOUT_SKID_SKID */
25990 /* Description: CRB Time-out Skid */
25991 #define SH_CRB_TIMEOUT_SKID_SKID_SHFT 0
25992 #define SH_CRB_TIMEOUT_SKID_SKID_MASK 0x000000000000003f
25994 /* SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT */
25995 /* Description: Reset Skid counter */
25996 #define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_SHFT 63
25997 #define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_MASK 0x8000000000000000
25999 /* ==================================================================== */
26000 /* Register "SH_MEMORY_WRITE_STATUS_0" */
26001 /* Memory Write Status for CPU 0 */
26002 /* ==================================================================== */
26004 #define SH_MEMORY_WRITE_STATUS_0 0x0000000120070000
26005 #define SH_MEMORY_WRITE_STATUS_0_MASK 0x000000000000003f
26006 #define SH_MEMORY_WRITE_STATUS_0_INIT 0x0000000000000000
26008 /* SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT */
26009 /* Description: Pending Write Count */
26010 #define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 0
26011 #define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f
26013 /* ==================================================================== */
26014 /* Register "SH_MEMORY_WRITE_STATUS_1" */
26015 /* Memory Write Status for CPU 1 */
26016 /* ==================================================================== */
26018 #define SH_MEMORY_WRITE_STATUS_1 0x0000000120070080
26019 #define SH_MEMORY_WRITE_STATUS_1_MASK 0x000000000000003f
26020 #define SH_MEMORY_WRITE_STATUS_1_INIT 0x0000000000000000
26022 /* SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT */
26023 /* Description: Pending Write Count */
26024 #define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 0
26025 #define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f
26027 /* ==================================================================== */
26028 /* Register "SH_PIO_WRITE_STATUS_0" */
26029 /* PIO Write Status for CPU 0 */
26030 /* ==================================================================== */
26032 #define SH_PIO_WRITE_STATUS_0 0x0000000120070200
26033 #define SH_PIO_WRITE_STATUS_0_MASK 0xbf03ffffffffffff
26034 #define SH_PIO_WRITE_STATUS_0_INIT 0x8000000000000000
26036 /* SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR */
26037 /* Description: More than one PIO write error occurred */
26038 #define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_SHFT 0
26039 #define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_MASK 0x0000000000000001
26041 /* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */
26042 /* Description: Deaklock response detected */
26043 #define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1
26044 #define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK 0x0000000000000002
26046 /* SH_PIO_WRITE_STATUS_0_WRITE_ERROR */
26047 /* Description: Error response detected */
26048 #define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_SHFT 2
26049 #define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_MASK 0x0000000000000004
26051 /* SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS */
26052 /* Description: Address associated with error response */
26053 #define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_SHFT 3
26054 #define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8
26056 /* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */
26057 /* Description: Count of currently pending PIO writes */
26058 #define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56
26059 #define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x3f00000000000000
26061 /* SH_PIO_WRITE_STATUS_0_WRITES_OK */
26062 /* Description: No pending writes or errors */
26063 #define SH_PIO_WRITE_STATUS_0_WRITES_OK_SHFT 63
26064 #define SH_PIO_WRITE_STATUS_0_WRITES_OK_MASK 0x8000000000000000
26066 /* ==================================================================== */
26067 /* Register "SH_PIO_WRITE_STATUS_1" */
26068 /* PIO Write Status for CPU 1 */
26069 /* ==================================================================== */
26071 #define SH_PIO_WRITE_STATUS_1 0x0000000120070280
26072 #define SH_PIO_WRITE_STATUS_1_MASK 0xbf03ffffffffffff
26073 #define SH_PIO_WRITE_STATUS_1_INIT 0x8000000000000000
26075 /* SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR */
26076 /* Description: More than one PIO write error occurred */
26077 #define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_SHFT 0
26078 #define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_MASK 0x0000000000000001
26080 /* SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK */
26081 /* Description: Deaklock response detected */
26082 #define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_SHFT 1
26083 #define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_MASK 0x0000000000000002
26085 /* SH_PIO_WRITE_STATUS_1_WRITE_ERROR */
26086 /* Description: Error response detected */
26087 #define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_SHFT 2
26088 #define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_MASK 0x0000000000000004
26090 /* SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS */
26091 /* Description: Address associated with error response */
26092 #define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_SHFT 3
26093 #define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8
26095 /* SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT */
26096 /* Description: Count of currently pending PIO writes */
26097 #define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 56
26098 #define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x3f00000000000000
26100 /* SH_PIO_WRITE_STATUS_1_WRITES_OK */
26101 /* Description: No pending writes or errors */
26102 #define SH_PIO_WRITE_STATUS_1_WRITES_OK_SHFT 63
26103 #define SH_PIO_WRITE_STATUS_1_WRITES_OK_MASK 0x8000000000000000
26105 /* ==================================================================== */
26106 /* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */
26107 /* ==================================================================== */
26109 #define SH_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208
26111 /* ==================================================================== */
26112 /* Register "SH_PIO_WRITE_STATUS_1_ALIAS" */
26113 /* ==================================================================== */
26115 #define SH_PIO_WRITE_STATUS_1_ALIAS 0x0000000120070288
26117 /* ==================================================================== */
26118 /* Register "SH_MEMORY_WRITE_STATUS_NON_USER_0" */
26119 /* Memory Write Status for CPU 0. OS access only */
26120 /* ==================================================================== */
26122 #define SH_MEMORY_WRITE_STATUS_NON_USER_0 0x0000000120070400
26123 #define SH_MEMORY_WRITE_STATUS_NON_USER_0_MASK 0x800000000000003f
26124 #define SH_MEMORY_WRITE_STATUS_NON_USER_0_INIT 0x0000000000000000
26126 /* SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT */
26127 /* Description: Pending Write Count */
26128 #define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_SHFT 0
26129 #define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f
26131 /* SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR */
26132 /* Description: Clear pending write count */
26133 #define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_SHFT 63
26134 #define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_MASK 0x8000000000000000
26136 /* ==================================================================== */
26137 /* Register "SH_MEMORY_WRITE_STATUS_NON_USER_1" */
26138 /* Memory Write Status for CPU 1. OS access only */
26139 /* ==================================================================== */
26141 #define SH_MEMORY_WRITE_STATUS_NON_USER_1 0x0000000120070480
26142 #define SH_MEMORY_WRITE_STATUS_NON_USER_1_MASK 0x800000000000003f
26143 #define SH_MEMORY_WRITE_STATUS_NON_USER_1_INIT 0x0000000000000000
26145 /* SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT */
26146 /* Description: Pending Write Count */
26147 #define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_SHFT 0
26148 #define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f
26150 /* SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR */
26151 /* Description: Clear pending write count */
26152 #define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_SHFT 63
26153 #define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_MASK 0x8000000000000000
26155 /* ==================================================================== */
26156 /* Register "SH_MMRBIST_ERR" */
26157 /* Error capture for bist read errors */
26158 /* ==================================================================== */
26160 #define SH_MMRBIST_ERR 0x0000000100000080
26161 #define SH_MMRBIST_ERR_MASK 0x00000071ffffffff
26162 #define SH_MMRBIST_ERR_INIT 0x0000000000000000
26164 /* SH_MMRBIST_ERR_ADDR */
26165 /* Description: dword address of bist error */
26166 #define SH_MMRBIST_ERR_ADDR_SHFT 0
26167 #define SH_MMRBIST_ERR_ADDR_MASK 0x00000001ffffffff
26169 /* SH_MMRBIST_ERR_DETECTED */
26170 /* Description: error detected flag */
26171 #define SH_MMRBIST_ERR_DETECTED_SHFT 36
26172 #define SH_MMRBIST_ERR_DETECTED_MASK 0x0000001000000000
26174 /* SH_MMRBIST_ERR_MULTIPLE_DETECTED */
26175 /* Description: multiple errors detected flag */
26176 #define SH_MMRBIST_ERR_MULTIPLE_DETECTED_SHFT 37
26177 #define SH_MMRBIST_ERR_MULTIPLE_DETECTED_MASK 0x0000002000000000
26179 /* SH_MMRBIST_ERR_CANCELLED */
26180 /* Description: mmr/bist was cancelled */
26181 #define SH_MMRBIST_ERR_CANCELLED_SHFT 38
26182 #define SH_MMRBIST_ERR_CANCELLED_MASK 0x0000004000000000
26184 /* ==================================================================== */
26185 /* Register "SH_MISC_ERR_HDR_LOWER" */
26186 /* Header capture register */
26187 /* ==================================================================== */
26189 #define SH_MISC_ERR_HDR_LOWER 0x0000000100000088
26190 #define SH_MISC_ERR_HDR_LOWER_MASK 0x93fffffffffffff8
26191 #define SH_MISC_ERR_HDR_LOWER_INIT 0x0000000000000000
26193 /* SH_MISC_ERR_HDR_LOWER_ADDR */
26194 /* Description: upper bits of reference address */
26195 #define SH_MISC_ERR_HDR_LOWER_ADDR_SHFT 3
26196 #define SH_MISC_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8
26198 /* SH_MISC_ERR_HDR_LOWER_CMD */
26199 /* Description: command of reference */
26200 #define SH_MISC_ERR_HDR_LOWER_CMD_SHFT 36
26201 #define SH_MISC_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000
26203 /* SH_MISC_ERR_HDR_LOWER_SRC */
26204 /* Description: source node of reference */
26205 #define SH_MISC_ERR_HDR_LOWER_SRC_SHFT 44
26206 #define SH_MISC_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000
26208 /* SH_MISC_ERR_HDR_LOWER_WRITE */
26209 /* Description: reference is a write */
26210 #define SH_MISC_ERR_HDR_LOWER_WRITE_SHFT 60
26211 #define SH_MISC_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000
26213 /* SH_MISC_ERR_HDR_LOWER_VALID */
26214 /* Description: set when capture occurs */
26215 #define SH_MISC_ERR_HDR_LOWER_VALID_SHFT 63
26216 #define SH_MISC_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000
26218 /* ==================================================================== */
26219 /* Register "SH_MISC_ERR_HDR_UPPER" */
26220 /* Error header capture packet and protocol errors */
26221 /* ==================================================================== */
26223 #define SH_MISC_ERR_HDR_UPPER 0x0000000100000090
26224 #define SH_MISC_ERR_HDR_UPPER_MASK 0x000000001ff000ff
26225 #define SH_MISC_ERR_HDR_UPPER_INIT 0x0000000000000000
26227 /* SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL */
26228 /* Description: indicates a directory protocol error captured */
26229 #define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_SHFT 0
26230 #define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_MASK 0x0000000000000001
26232 /* SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD */
26233 /* Description: indicates an illegal command error captured */
26234 #define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_SHFT 1
26235 #define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_MASK 0x0000000000000002
26237 /* SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR */
26238 /* Description: indicates a non-existent memory error captured */
26239 #define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_SHFT 2
26240 #define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_MASK 0x0000000000000004
26242 /* SH_MISC_ERR_HDR_UPPER_RMW_UC */
26243 /* Description: indicates an uncorrectable store rmw */
26244 #define SH_MISC_ERR_HDR_UPPER_RMW_UC_SHFT 3
26245 #define SH_MISC_ERR_HDR_UPPER_RMW_UC_MASK 0x0000000000000008
26247 /* SH_MISC_ERR_HDR_UPPER_RMW_COR */
26248 /* Description: indicates a correctable store rmw */
26249 #define SH_MISC_ERR_HDR_UPPER_RMW_COR_SHFT 4
26250 #define SH_MISC_ERR_HDR_UPPER_RMW_COR_MASK 0x0000000000000010
26252 /* SH_MISC_ERR_HDR_UPPER_DIR_ACC */
26253 /* Description: indicates a data request to directory memory error */
26255 #define SH_MISC_ERR_HDR_UPPER_DIR_ACC_SHFT 5
26256 #define SH_MISC_ERR_HDR_UPPER_DIR_ACC_MASK 0x0000000000000020
26258 /* SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE */
26259 /* Description: indicates a pkt size error from pi */
26260 #define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_SHFT 6
26261 #define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_MASK 0x0000000000000040
26263 /* SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE */
26264 /* Description: indicates a pkt size error from xn */
26265 #define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_SHFT 7
26266 #define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_MASK 0x0000000000000080
26268 /* SH_MISC_ERR_HDR_UPPER_ECHO */
26269 #define SH_MISC_ERR_HDR_UPPER_ECHO_SHFT 20
26270 #define SH_MISC_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000
26272 /* ==================================================================== */
26273 /* Register "SH_DIR_UC_ERR_HDR_LOWER" */
26274 /* Header capture register */
26275 /* ==================================================================== */
26277 #define SH_DIR_UC_ERR_HDR_LOWER 0x0000000100000098
26278 #define SH_DIR_UC_ERR_HDR_LOWER_MASK 0x93fffffffffffff8
26279 #define SH_DIR_UC_ERR_HDR_LOWER_INIT 0x0000000000000000
26281 /* SH_DIR_UC_ERR_HDR_LOWER_ADDR */
26282 /* Description: upper bits of reference address */
26283 #define SH_DIR_UC_ERR_HDR_LOWER_ADDR_SHFT 3
26284 #define SH_DIR_UC_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8
26286 /* SH_DIR_UC_ERR_HDR_LOWER_CMD */
26287 /* Description: command of reference */
26288 #define SH_DIR_UC_ERR_HDR_LOWER_CMD_SHFT 36
26289 #define SH_DIR_UC_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000
26291 /* SH_DIR_UC_ERR_HDR_LOWER_SRC */
26292 /* Description: source node of reference */
26293 #define SH_DIR_UC_ERR_HDR_LOWER_SRC_SHFT 44
26294 #define SH_DIR_UC_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000
26296 /* SH_DIR_UC_ERR_HDR_LOWER_WRITE */
26297 /* Description: reference is a write */
26298 #define SH_DIR_UC_ERR_HDR_LOWER_WRITE_SHFT 60
26299 #define SH_DIR_UC_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000
26301 /* SH_DIR_UC_ERR_HDR_LOWER_VALID */
26302 /* Description: set when capture occurs */
26303 #define SH_DIR_UC_ERR_HDR_LOWER_VALID_SHFT 63
26304 #define SH_DIR_UC_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000
26306 /* ==================================================================== */
26307 /* Register "SH_DIR_UC_ERR_HDR_UPPER" */
26308 /* Error header capture packet and protocol errors */
26309 /* ==================================================================== */
26311 #define SH_DIR_UC_ERR_HDR_UPPER 0x00000001000000a0
26312 #define SH_DIR_UC_ERR_HDR_UPPER_MASK 0x000000001ff00008
26313 #define SH_DIR_UC_ERR_HDR_UPPER_INIT 0x0000000000000000
26315 /* SH_DIR_UC_ERR_HDR_UPPER_DIR_UC */
26316 /* Description: indicates uncorrectable directory error captured */
26317 #define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_SHFT 3
26318 #define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_MASK 0x0000000000000008
26320 /* SH_DIR_UC_ERR_HDR_UPPER_ECHO */
26321 #define SH_DIR_UC_ERR_HDR_UPPER_ECHO_SHFT 20
26322 #define SH_DIR_UC_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000
26324 /* ==================================================================== */
26325 /* Register "SH_DIR_COR_ERR_HDR_LOWER" */
26326 /* Header capture register */
26327 /* ==================================================================== */
26329 #define SH_DIR_COR_ERR_HDR_LOWER 0x00000001000000a8
26330 #define SH_DIR_COR_ERR_HDR_LOWER_MASK 0x93fffffffffffff8
26331 #define SH_DIR_COR_ERR_HDR_LOWER_INIT 0x0000000000000000
26333 /* SH_DIR_COR_ERR_HDR_LOWER_ADDR */
26334 /* Description: upper bits of reference address */
26335 #define SH_DIR_COR_ERR_HDR_LOWER_ADDR_SHFT 3
26336 #define SH_DIR_COR_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8
26338 /* SH_DIR_COR_ERR_HDR_LOWER_CMD */
26339 /* Description: command of reference */
26340 #define SH_DIR_COR_ERR_HDR_LOWER_CMD_SHFT 36
26341 #define SH_DIR_COR_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000
26343 /* SH_DIR_COR_ERR_HDR_LOWER_SRC */
26344 /* Description: source node of reference */
26345 #define SH_DIR_COR_ERR_HDR_LOWER_SRC_SHFT 44
26346 #define SH_DIR_COR_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000
26348 /* SH_DIR_COR_ERR_HDR_LOWER_WRITE */
26349 /* Description: reference is a write */
26350 #define SH_DIR_COR_ERR_HDR_LOWER_WRITE_SHFT 60
26351 #define SH_DIR_COR_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000
26353 /* SH_DIR_COR_ERR_HDR_LOWER_VALID */
26354 /* Description: set when capture occurs */
26355 #define SH_DIR_COR_ERR_HDR_LOWER_VALID_SHFT 63
26356 #define SH_DIR_COR_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000
26358 /* ==================================================================== */
26359 /* Register "SH_DIR_COR_ERR_HDR_UPPER" */
26360 /* Error header capture packet and protocol errors */
26361 /* ==================================================================== */
26363 #define SH_DIR_COR_ERR_HDR_UPPER 0x00000001000000b0
26364 #define SH_DIR_COR_ERR_HDR_UPPER_MASK 0x000000001ff00100
26365 #define SH_DIR_COR_ERR_HDR_UPPER_INIT 0x0000000000000000
26367 /* SH_DIR_COR_ERR_HDR_UPPER_DIR_COR */
26368 /* Description: indicates correctable directory error captured */
26369 #define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_SHFT 8
26370 #define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_MASK 0x0000000000000100
26372 /* SH_DIR_COR_ERR_HDR_UPPER_ECHO */
26373 #define SH_DIR_COR_ERR_HDR_UPPER_ECHO_SHFT 20
26374 #define SH_DIR_COR_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000
26376 /* ==================================================================== */
26377 /* Register "SH_MEM_ERROR_SUMMARY" */
26378 /* Memory error flags */
26379 /* ==================================================================== */
26381 #define SH_MEM_ERROR_SUMMARY 0x00000001000000b8
26382 #define SH_MEM_ERROR_SUMMARY_MASK 0x00000007f77777ff
26383 #define SH_MEM_ERROR_SUMMARY_INIT 0x0000000000000000
26385 /* SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD */
26386 /* Description: illegal command error */
26387 #define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_SHFT 0
26388 #define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_MASK 0x0000000000000001
26390 /* SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR */
26391 /* Description: non-existent memory error */
26392 #define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_SHFT 1
26393 #define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_MASK 0x0000000000000002
26395 /* SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR */
26396 /* Description: directory protocol error in dqlp */
26397 #define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_SHFT 2
26398 #define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_MASK 0x0000000000000004
26400 /* SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR */
26401 /* Description: directory protocol error in dqrp */
26402 #define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_SHFT 3
26403 #define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_MASK 0x0000000000000008
26405 /* SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC */
26406 /* Description: uncorrectable directory error in dqlp */
26407 #define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_SHFT 4
26408 #define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_MASK 0x0000000000000010
26410 /* SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR */
26411 /* Description: correctable directory error in dqlp */
26412 #define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_SHFT 5
26413 #define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_MASK 0x0000000000000020
26415 /* SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC */
26416 /* Description: uncorrectable directory error in dqrp */
26417 #define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_SHFT 6
26418 #define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_MASK 0x0000000000000040
26420 /* SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR */
26421 /* Description: correctable directory error in dqrp */
26422 #define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_SHFT 7
26423 #define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_MASK 0x0000000000000080
26425 /* SH_MEM_ERROR_SUMMARY_ACX_INT_HW */
26426 /* Description: hardware interrupt from acx */
26427 #define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_SHFT 8
26428 #define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_MASK 0x0000000000000100
26430 /* SH_MEM_ERROR_SUMMARY_ACY_INT_HW */
26431 /* Description: hardware interrupt from acy */
26432 #define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_SHFT 9
26433 #define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_MASK 0x0000000000000200
26435 /* SH_MEM_ERROR_SUMMARY_DIR_ACC */
26436 /* Description: directory memory access error */
26437 #define SH_MEM_ERROR_SUMMARY_DIR_ACC_SHFT 10
26438 #define SH_MEM_ERROR_SUMMARY_DIR_ACC_MASK 0x0000000000000400
26440 /* SH_MEM_ERROR_SUMMARY_DQLP_INT_UC */
26441 /* Description: uncorrectable interrupt from dqlp */
26442 #define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_SHFT 12
26443 #define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_MASK 0x0000000000001000
26445 /* SH_MEM_ERROR_SUMMARY_DQLP_INT_COR */
26446 /* Description: correctable interrupt from dqlp */
26447 #define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_SHFT 13
26448 #define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_MASK 0x0000000000002000
26450 /* SH_MEM_ERROR_SUMMARY_DQLP_INT_HW */
26451 /* Description: hardware interrupt from dqlp */
26452 #define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_SHFT 14
26453 #define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_MASK 0x0000000000004000
26455 /* SH_MEM_ERROR_SUMMARY_DQLS_INT_UC */
26456 /* Description: uncorrectable interrupt from dqls */
26457 #define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_SHFT 16
26458 #define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_MASK 0x0000000000010000
26460 /* SH_MEM_ERROR_SUMMARY_DQLS_INT_COR */
26461 /* Description: correctable interrupt from dqls */
26462 #define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_SHFT 17
26463 #define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_MASK 0x0000000000020000
26465 /* SH_MEM_ERROR_SUMMARY_DQLS_INT_HW */
26466 /* Description: hardware interrupt from dqls */
26467 #define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_SHFT 18
26468 #define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_MASK 0x0000000000040000
26470 /* SH_MEM_ERROR_SUMMARY_DQRP_INT_UC */
26471 /* Description: uncorrectable interrupt from dqrp */
26472 #define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_SHFT 20
26473 #define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_MASK 0x0000000000100000
26475 /* SH_MEM_ERROR_SUMMARY_DQRP_INT_COR */
26476 /* Description: correctable interrupt from dqrp */
26477 #define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_SHFT 21
26478 #define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_MASK 0x0000000000200000
26480 /* SH_MEM_ERROR_SUMMARY_DQRP_INT_HW */
26481 /* Description: hardware interrupt from dqrp */
26482 #define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_SHFT 22
26483 #define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_MASK 0x0000000000400000
26485 /* SH_MEM_ERROR_SUMMARY_DQRS_INT_UC */
26486 /* Description: uncorrectable interrupt from dqrs */
26487 #define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_SHFT 24
26488 #define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_MASK 0x0000000001000000
26490 /* SH_MEM_ERROR_SUMMARY_DQRS_INT_COR */
26491 /* Description: correctable interrupt from dqrs */
26492 #define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_SHFT 25
26493 #define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_MASK 0x0000000002000000
26495 /* SH_MEM_ERROR_SUMMARY_DQRS_INT_HW */
26496 /* Description: hardware interrupt from dqrs */
26497 #define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_SHFT 26
26498 #define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_MASK 0x0000000004000000
26500 /* SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW */
26501 /* Description: too many reply packets came from pi */
26502 #define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_SHFT 28
26503 #define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_MASK 0x0000000010000000
26505 /* SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW */
26506 /* Description: too many reply packets came from xn */
26507 #define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_SHFT 29
26508 #define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_MASK 0x0000000020000000
26510 /* SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW */
26511 /* Description: too many request packets came from pi */
26512 #define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_SHFT 30
26513 #define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000
26515 /* SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW */
26516 /* Description: too many request packets came from xn */
26517 #define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_SHFT 31
26518 #define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000
26520 /* SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT */
26521 /* Description: red black scheme did not clean up soon enough */
26522 #define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_SHFT 32
26523 #define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000
26525 /* SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE */
26526 /* Description: received data bearing packet from pi with wrong siz */
26527 #define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_SHFT 33
26528 #define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_MASK 0x0000000200000000
26530 /* SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE */
26531 /* Description: received data bearing packet from xn with wrong siz */
26532 #define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_SHFT 34
26533 #define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_MASK 0x0000000400000000
26535 /* ==================================================================== */
26536 /* Register "SH_MEM_ERROR_SUMMARY_ALIAS" */
26537 /* Memory error flags clear alias */
26538 /* ==================================================================== */
26540 #define SH_MEM_ERROR_SUMMARY_ALIAS 0x00000001000000c0
26542 /* ==================================================================== */
26543 /* Register "SH_MEM_ERROR_OVERFLOW" */
26544 /* Memory error flags */
26545 /* ==================================================================== */
26547 #define SH_MEM_ERROR_OVERFLOW 0x00000001000000c8
26548 #define SH_MEM_ERROR_OVERFLOW_MASK 0x00000007f77777ff
26549 #define SH_MEM_ERROR_OVERFLOW_INIT 0x0000000000000000
26551 /* SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD */
26552 /* Description: illegal command error */
26553 #define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_SHFT 0
26554 #define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_MASK 0x0000000000000001
26556 /* SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR */
26557 /* Description: non-existent memory error */
26558 #define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_SHFT 1
26559 #define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_MASK 0x0000000000000002
26561 /* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR */
26562 /* Description: directory protocol error in dqlp */
26563 #define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_SHFT 2
26564 #define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_MASK 0x0000000000000004
26566 /* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR */
26567 /* Description: directory protocol error in dqrp */
26568 #define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_SHFT 3
26569 #define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_MASK 0x0000000000000008
26571 /* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC */
26572 /* Description: uncorrectable directory error in dqlp */
26573 #define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_SHFT 4
26574 #define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_MASK 0x0000000000000010
26576 /* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR */
26577 /* Description: correctable directory error in dqlp */
26578 #define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_SHFT 5
26579 #define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_MASK 0x0000000000000020
26581 /* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC */
26582 /* Description: uncorrectable directory error in dqrp */
26583 #define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_SHFT 6
26584 #define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_MASK 0x0000000000000040
26586 /* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR */
26587 /* Description: correctable directory error in dqrp */
26588 #define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_SHFT 7
26589 #define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_MASK 0x0000000000000080
26591 /* SH_MEM_ERROR_OVERFLOW_ACX_INT_HW */
26592 /* Description: hardware interrupt from acx */
26593 #define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_SHFT 8
26594 #define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_MASK 0x0000000000000100
26596 /* SH_MEM_ERROR_OVERFLOW_ACY_INT_HW */
26597 /* Description: hardware interrupt from acy */
26598 #define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_SHFT 9
26599 #define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_MASK 0x0000000000000200
26601 /* SH_MEM_ERROR_OVERFLOW_DIR_ACC */
26602 /* Description: directory memory access error */
26603 #define SH_MEM_ERROR_OVERFLOW_DIR_ACC_SHFT 10
26604 #define SH_MEM_ERROR_OVERFLOW_DIR_ACC_MASK 0x0000000000000400
26606 /* SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC */
26607 /* Description: uncorrectable interrupt from dqlp */
26608 #define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_SHFT 12
26609 #define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_MASK 0x0000000000001000
26611 /* SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR */
26612 /* Description: correctable interrupt from dqlp */
26613 #define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_SHFT 13
26614 #define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_MASK 0x0000000000002000
26616 /* SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW */
26617 /* Description: hardware interrupt from dqlp */
26618 #define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_SHFT 14
26619 #define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_MASK 0x0000000000004000
26621 /* SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC */
26622 /* Description: uncorrectable interrupt from dqls */
26623 #define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_SHFT 16
26624 #define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_MASK 0x0000000000010000
26626 /* SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR */
26627 /* Description: correctable interrupt from dqls */
26628 #define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_SHFT 17
26629 #define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_MASK 0x0000000000020000
26631 /* SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW */
26632 /* Description: hardware interrupt from dqls */
26633 #define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_SHFT 18
26634 #define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_MASK 0x0000000000040000
26636 /* SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC */
26637 /* Description: uncorrectable interrupt from dqrp */
26638 #define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_SHFT 20
26639 #define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_MASK 0x0000000000100000
26641 /* SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR */
26642 /* Description: correctable interrupt from dqrp */
26643 #define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_SHFT 21
26644 #define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_MASK 0x0000000000200000
26646 /* SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW */
26647 /* Description: hardware interrupt from dqrp */
26648 #define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_SHFT 22
26649 #define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_MASK 0x0000000000400000
26651 /* SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC */
26652 /* Description: uncorrectable interrupt from dqrs */
26653 #define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_SHFT 24
26654 #define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_MASK 0x0000000001000000
26656 /* SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR */
26657 /* Description: correctable interrupt from dqrs */
26658 #define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_SHFT 25
26659 #define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_MASK 0x0000000002000000
26661 /* SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW */
26662 /* Description: hardware interrupt from dqrs */
26663 #define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_SHFT 26
26664 #define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_MASK 0x0000000004000000
26666 /* SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW */
26667 /* Description: too many reply packets came from pi */
26668 #define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_SHFT 28
26669 #define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_MASK 0x0000000010000000
26671 /* SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW */
26672 /* Description: too many reply packets came from xn */
26673 #define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_SHFT 29
26674 #define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_MASK 0x0000000020000000
26676 /* SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW */
26677 /* Description: too many request packets came from pi */
26678 #define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_SHFT 30
26679 #define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000
26681 /* SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW */
26682 /* Description: too many request packets came from xn */
26683 #define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_SHFT 31
26684 #define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000
26686 /* SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT */
26687 /* Description: red black scheme did not clean up soon enough */
26688 #define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_SHFT 32
26689 #define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000
26691 /* SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE */
26692 /* Description: received data bearing packet from pi with wrong siz */
26693 #define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_SHFT 33
26694 #define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_MASK 0x0000000200000000
26696 /* SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE */
26697 /* Description: received data bearing packet from xn with wrong siz */
26698 #define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_SHFT 34
26699 #define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_MASK 0x0000000400000000
26701 /* ==================================================================== */
26702 /* Register "SH_MEM_ERROR_OVERFLOW_ALIAS" */
26703 /* Memory error flags clear alias */
26704 /* ==================================================================== */
26706 #define SH_MEM_ERROR_OVERFLOW_ALIAS 0x00000001000000d0
26708 /* ==================================================================== */
26709 /* Register "SH_MEM_ERROR_MASK" */
26710 /* Memory error flags */
26711 /* ==================================================================== */
26713 #define SH_MEM_ERROR_MASK 0x00000001000000d8
26714 #define SH_MEM_ERROR_MASK_MASK 0x00000007f77777ff
26715 #define SH_MEM_ERROR_MASK_INIT 0x00000007f77773ff
26717 /* SH_MEM_ERROR_MASK_ILLEGAL_CMD */
26718 /* Description: illegal command error */
26719 #define SH_MEM_ERROR_MASK_ILLEGAL_CMD_SHFT 0
26720 #define SH_MEM_ERROR_MASK_ILLEGAL_CMD_MASK 0x0000000000000001
26722 /* SH_MEM_ERROR_MASK_NONEXIST_ADDR */
26723 /* Description: non-existent memory error */
26724 #define SH_MEM_ERROR_MASK_NONEXIST_ADDR_SHFT 1
26725 #define SH_MEM_ERROR_MASK_NONEXIST_ADDR_MASK 0x0000000000000002
26727 /* SH_MEM_ERROR_MASK_DQLP_DIR_PERR */
26728 /* Description: directory protocol error in dqlp */
26729 #define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_SHFT 2
26730 #define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_MASK 0x0000000000000004
26732 /* SH_MEM_ERROR_MASK_DQRP_DIR_PERR */
26733 /* Description: directory protocol error in dqrp */
26734 #define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_SHFT 3
26735 #define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_MASK 0x0000000000000008
26737 /* SH_MEM_ERROR_MASK_DQLP_DIR_UC */
26738 /* Description: uncorrectable directory error in dqlp */
26739 #define SH_MEM_ERROR_MASK_DQLP_DIR_UC_SHFT 4
26740 #define SH_MEM_ERROR_MASK_DQLP_DIR_UC_MASK 0x0000000000000010
26742 /* SH_MEM_ERROR_MASK_DQLP_DIR_COR */
26743 /* Description: correctable directory error in dqlp */
26744 #define SH_MEM_ERROR_MASK_DQLP_DIR_COR_SHFT 5
26745 #define SH_MEM_ERROR_MASK_DQLP_DIR_COR_MASK 0x0000000000000020
26747 /* SH_MEM_ERROR_MASK_DQRP_DIR_UC */
26748 /* Description: uncorrectable directory error in dqrp */
26749 #define SH_MEM_ERROR_MASK_DQRP_DIR_UC_SHFT 6
26750 #define SH_MEM_ERROR_MASK_DQRP_DIR_UC_MASK 0x0000000000000040
26752 /* SH_MEM_ERROR_MASK_DQRP_DIR_COR */
26753 /* Description: correctable directory error in dqrp */
26754 #define SH_MEM_ERROR_MASK_DQRP_DIR_COR_SHFT 7
26755 #define SH_MEM_ERROR_MASK_DQRP_DIR_COR_MASK 0x0000000000000080
26757 /* SH_MEM_ERROR_MASK_ACX_INT_HW */
26758 /* Description: hardware interrupt from acx */
26759 #define SH_MEM_ERROR_MASK_ACX_INT_HW_SHFT 8
26760 #define SH_MEM_ERROR_MASK_ACX_INT_HW_MASK 0x0000000000000100
26762 /* SH_MEM_ERROR_MASK_ACY_INT_HW */
26763 /* Description: hardware interrupt from acy */
26764 #define SH_MEM_ERROR_MASK_ACY_INT_HW_SHFT 9
26765 #define SH_MEM_ERROR_MASK_ACY_INT_HW_MASK 0x0000000000000200
26767 /* SH_MEM_ERROR_MASK_DIR_ACC */
26768 /* Description: directory memory access error */
26769 #define SH_MEM_ERROR_MASK_DIR_ACC_SHFT 10
26770 #define SH_MEM_ERROR_MASK_DIR_ACC_MASK 0x0000000000000400
26772 /* SH_MEM_ERROR_MASK_DQLP_INT_UC */
26773 /* Description: uncorrectable interrupt from dqlp */
26774 #define SH_MEM_ERROR_MASK_DQLP_INT_UC_SHFT 12
26775 #define SH_MEM_ERROR_MASK_DQLP_INT_UC_MASK 0x0000000000001000
26777 /* SH_MEM_ERROR_MASK_DQLP_INT_COR */
26778 /* Description: correctable interrupt from dqlp */
26779 #define SH_MEM_ERROR_MASK_DQLP_INT_COR_SHFT 13
26780 #define SH_MEM_ERROR_MASK_DQLP_INT_COR_MASK 0x0000000000002000
26782 /* SH_MEM_ERROR_MASK_DQLP_INT_HW */
26783 /* Description: hardware interrupt from dqlp */
26784 #define SH_MEM_ERROR_MASK_DQLP_INT_HW_SHFT 14
26785 #define SH_MEM_ERROR_MASK_DQLP_INT_HW_MASK 0x0000000000004000
26787 /* SH_MEM_ERROR_MASK_DQLS_INT_UC */
26788 /* Description: uncorrectable interrupt from dqls */
26789 #define SH_MEM_ERROR_MASK_DQLS_INT_UC_SHFT 16
26790 #define SH_MEM_ERROR_MASK_DQLS_INT_UC_MASK 0x0000000000010000
26792 /* SH_MEM_ERROR_MASK_DQLS_INT_COR */
26793 /* Description: correctable interrupt from dqls */
26794 #define SH_MEM_ERROR_MASK_DQLS_INT_COR_SHFT 17
26795 #define SH_MEM_ERROR_MASK_DQLS_INT_COR_MASK 0x0000000000020000
26797 /* SH_MEM_ERROR_MASK_DQLS_INT_HW */
26798 /* Description: hardware interrupt from dqls */
26799 #define SH_MEM_ERROR_MASK_DQLS_INT_HW_SHFT 18
26800 #define SH_MEM_ERROR_MASK_DQLS_INT_HW_MASK 0x0000000000040000
26802 /* SH_MEM_ERROR_MASK_DQRP_INT_UC */
26803 /* Description: uncorrectable interrupt from dqrp */
26804 #define SH_MEM_ERROR_MASK_DQRP_INT_UC_SHFT 20
26805 #define SH_MEM_ERROR_MASK_DQRP_INT_UC_MASK 0x0000000000100000
26807 /* SH_MEM_ERROR_MASK_DQRP_INT_COR */
26808 /* Description: correctable interrupt from dqrp */
26809 #define SH_MEM_ERROR_MASK_DQRP_INT_COR_SHFT 21
26810 #define SH_MEM_ERROR_MASK_DQRP_INT_COR_MASK 0x0000000000200000
26812 /* SH_MEM_ERROR_MASK_DQRP_INT_HW */
26813 /* Description: hardware interrupt from dqrp */
26814 #define SH_MEM_ERROR_MASK_DQRP_INT_HW_SHFT 22
26815 #define SH_MEM_ERROR_MASK_DQRP_INT_HW_MASK 0x0000000000400000
26817 /* SH_MEM_ERROR_MASK_DQRS_INT_UC */
26818 /* Description: uncorrectable interrupt from dqrs */
26819 #define SH_MEM_ERROR_MASK_DQRS_INT_UC_SHFT 24
26820 #define SH_MEM_ERROR_MASK_DQRS_INT_UC_MASK 0x0000000001000000
26822 /* SH_MEM_ERROR_MASK_DQRS_INT_COR */
26823 /* Description: correctable interrupt from dqrs */
26824 #define SH_MEM_ERROR_MASK_DQRS_INT_COR_SHFT 25
26825 #define SH_MEM_ERROR_MASK_DQRS_INT_COR_MASK 0x0000000002000000
26827 /* SH_MEM_ERROR_MASK_DQRS_INT_HW */
26828 /* Description: hardware interrupt from dqrs */
26829 #define SH_MEM_ERROR_MASK_DQRS_INT_HW_SHFT 26
26830 #define SH_MEM_ERROR_MASK_DQRS_INT_HW_MASK 0x0000000004000000
26832 /* SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW */
26833 /* Description: too many reply packets came from pi */
26834 #define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_SHFT 28
26835 #define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_MASK 0x0000000010000000
26837 /* SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW */
26838 /* Description: too many reply packets came from xn */
26839 #define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_SHFT 29
26840 #define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_MASK 0x0000000020000000
26842 /* SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW */
26843 /* Description: too many request packets came from pi */
26844 #define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_SHFT 30
26845 #define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000
26847 /* SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW */
26848 /* Description: too many request packets came from xn */
26849 #define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_SHFT 31
26850 #define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000
26852 /* SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT */
26853 /* Description: red black scheme did not clean up soon enough */
26854 #define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_SHFT 32
26855 #define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000
26857 /* SH_MEM_ERROR_MASK_PI_PKT_SIZE */
26858 /* Description: received data bearing packet from pi with wrong siz */
26859 #define SH_MEM_ERROR_MASK_PI_PKT_SIZE_SHFT 33
26860 #define SH_MEM_ERROR_MASK_PI_PKT_SIZE_MASK 0x0000000200000000
26862 /* SH_MEM_ERROR_MASK_XN_PKT_SIZE */
26863 /* Description: received data bearing packet from xn with wrong siz */
26864 #define SH_MEM_ERROR_MASK_XN_PKT_SIZE_SHFT 34
26865 #define SH_MEM_ERROR_MASK_XN_PKT_SIZE_MASK 0x0000000400000000
26867 /* ==================================================================== */
26868 /* Register "SH_X_DIMM_CFG" */
26869 /* AC Mem Config Registers */
26870 /* ==================================================================== */
26872 #define SH_X_DIMM_CFG 0x0000000100010000
26873 #define SH_X_DIMM_CFG_MASK 0x0000000f7f7f7f7f
26874 #define SH_X_DIMM_CFG_INIT 0x000000026f4f2f0f
26876 /* SH_X_DIMM_CFG_DIMM0_SIZE */
26877 /* Description: DIMM 0 DRAM size */
26878 #define SH_X_DIMM_CFG_DIMM0_SIZE_SHFT 0
26879 #define SH_X_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007
26881 /* SH_X_DIMM_CFG_DIMM0_2BK */
26882 /* Description: DIMM 0 has two physical banks */
26883 #define SH_X_DIMM_CFG_DIMM0_2BK_SHFT 3
26884 #define SH_X_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008
26886 /* SH_X_DIMM_CFG_DIMM0_REV */
26887 /* Description: DIMM 0 physical banks reversed */
26888 #define SH_X_DIMM_CFG_DIMM0_REV_SHFT 4
26889 #define SH_X_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010
26891 /* SH_X_DIMM_CFG_DIMM0_CS */
26892 /* Description: DIMM 0 chip select, addr[35:34] match */
26893 #define SH_X_DIMM_CFG_DIMM0_CS_SHFT 5
26894 #define SH_X_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060
26896 /* SH_X_DIMM_CFG_DIMM1_SIZE */
26897 /* Description: DIMM 1 DRAM size */
26898 #define SH_X_DIMM_CFG_DIMM1_SIZE_SHFT 8
26899 #define SH_X_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700
26901 /* SH_X_DIMM_CFG_DIMM1_2BK */
26902 /* Description: DIMM 1 has two physical banks */
26903 #define SH_X_DIMM_CFG_DIMM1_2BK_SHFT 11
26904 #define SH_X_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800
26906 /* SH_X_DIMM_CFG_DIMM1_REV */
26907 /* Description: DIMM 1 physical banks reversed */
26908 #define SH_X_DIMM_CFG_DIMM1_REV_SHFT 12
26909 #define SH_X_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000
26911 /* SH_X_DIMM_CFG_DIMM1_CS */
26912 /* Description: DIMM 1 chip select, addr[35:34] match */
26913 #define SH_X_DIMM_CFG_DIMM1_CS_SHFT 13
26914 #define SH_X_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000
26916 /* SH_X_DIMM_CFG_DIMM2_SIZE */
26917 /* Description: DIMM 2 DRAM size */
26918 #define SH_X_DIMM_CFG_DIMM2_SIZE_SHFT 16
26919 #define SH_X_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000
26921 /* SH_X_DIMM_CFG_DIMM2_2BK */
26922 /* Description: DIMM 2 has two physical banks */
26923 #define SH_X_DIMM_CFG_DIMM2_2BK_SHFT 19
26924 #define SH_X_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000
26926 /* SH_X_DIMM_CFG_DIMM2_REV */
26927 /* Description: DIMM 2 physical banks reversed */
26928 #define SH_X_DIMM_CFG_DIMM2_REV_SHFT 20
26929 #define SH_X_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000
26931 /* SH_X_DIMM_CFG_DIMM2_CS */
26932 /* Description: DIMM 2 chip select, addr[35:34] match */
26933 #define SH_X_DIMM_CFG_DIMM2_CS_SHFT 21
26934 #define SH_X_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000
26936 /* SH_X_DIMM_CFG_DIMM3_SIZE */
26937 /* Description: DIMM 3 DRAM size */
26938 #define SH_X_DIMM_CFG_DIMM3_SIZE_SHFT 24
26939 #define SH_X_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000
26941 /* SH_X_DIMM_CFG_DIMM3_2BK */
26942 /* Description: DIMM 3 has two physical banks */
26943 #define SH_X_DIMM_CFG_DIMM3_2BK_SHFT 27
26944 #define SH_X_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000
26946 /* SH_X_DIMM_CFG_DIMM3_REV */
26947 /* Description: DIMM 3 physical banks reversed */
26948 #define SH_X_DIMM_CFG_DIMM3_REV_SHFT 28
26949 #define SH_X_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000
26951 /* SH_X_DIMM_CFG_DIMM3_CS */
26952 /* Description: DIMM 3 chip select, addr[35:34] match */
26953 #define SH_X_DIMM_CFG_DIMM3_CS_SHFT 29
26954 #define SH_X_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000
26956 /* SH_X_DIMM_CFG_FREQ */
26957 /* Description: DIMM frequency select */
26958 #define SH_X_DIMM_CFG_FREQ_SHFT 32
26959 #define SH_X_DIMM_CFG_FREQ_MASK 0x0000000f00000000
26961 /* ==================================================================== */
26962 /* Register "SH_Y_DIMM_CFG" */
26963 /* AC Mem Config Registers */
26964 /* ==================================================================== */
26966 #define SH_Y_DIMM_CFG 0x0000000100010008
26967 #define SH_Y_DIMM_CFG_MASK 0x0000000f7f7f7f7f
26968 #define SH_Y_DIMM_CFG_INIT 0x000000026f4f2f0f
26970 /* SH_Y_DIMM_CFG_DIMM0_SIZE */
26971 /* Description: DIMM 0 DRAM size */
26972 #define SH_Y_DIMM_CFG_DIMM0_SIZE_SHFT 0
26973 #define SH_Y_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007
26975 /* SH_Y_DIMM_CFG_DIMM0_2BK */
26976 /* Description: DIMM 0 has two physical banks */
26977 #define SH_Y_DIMM_CFG_DIMM0_2BK_SHFT 3
26978 #define SH_Y_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008
26980 /* SH_Y_DIMM_CFG_DIMM0_REV */
26981 /* Description: DIMM 0 physical banks reversed */
26982 #define SH_Y_DIMM_CFG_DIMM0_REV_SHFT 4
26983 #define SH_Y_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010
26985 /* SH_Y_DIMM_CFG_DIMM0_CS */
26986 /* Description: DIMM 0 chip select, addr[35:34] match */
26987 #define SH_Y_DIMM_CFG_DIMM0_CS_SHFT 5
26988 #define SH_Y_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060
26990 /* SH_Y_DIMM_CFG_DIMM1_SIZE */
26991 /* Description: DIMM 1 DRAM size */
26992 #define SH_Y_DIMM_CFG_DIMM1_SIZE_SHFT 8
26993 #define SH_Y_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700
26995 /* SH_Y_DIMM_CFG_DIMM1_2BK */
26996 /* Description: DIMM 1 has two physical banks */
26997 #define SH_Y_DIMM_CFG_DIMM1_2BK_SHFT 11
26998 #define SH_Y_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800
27000 /* SH_Y_DIMM_CFG_DIMM1_REV */
27001 /* Description: DIMM 1 physical banks reversed */
27002 #define SH_Y_DIMM_CFG_DIMM1_REV_SHFT 12
27003 #define SH_Y_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000
27005 /* SH_Y_DIMM_CFG_DIMM1_CS */
27006 /* Description: DIMM 1 chip select, addr[35:34] match */
27007 #define SH_Y_DIMM_CFG_DIMM1_CS_SHFT 13
27008 #define SH_Y_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000
27010 /* SH_Y_DIMM_CFG_DIMM2_SIZE */
27011 /* Description: DIMM 2 DRAM size */
27012 #define SH_Y_DIMM_CFG_DIMM2_SIZE_SHFT 16
27013 #define SH_Y_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000
27015 /* SH_Y_DIMM_CFG_DIMM2_2BK */
27016 /* Description: DIMM 2 has two physical banks */
27017 #define SH_Y_DIMM_CFG_DIMM2_2BK_SHFT 19
27018 #define SH_Y_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000
27020 /* SH_Y_DIMM_CFG_DIMM2_REV */
27021 /* Description: DIMM 2 physical banks reversed */
27022 #define SH_Y_DIMM_CFG_DIMM2_REV_SHFT 20
27023 #define SH_Y_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000
27025 /* SH_Y_DIMM_CFG_DIMM2_CS */
27026 /* Description: DIMM 2 chip select, addr[35:34] match */
27027 #define SH_Y_DIMM_CFG_DIMM2_CS_SHFT 21
27028 #define SH_Y_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000
27030 /* SH_Y_DIMM_CFG_DIMM3_SIZE */
27031 /* Description: DIMM 3 DRAM size */
27032 #define SH_Y_DIMM_CFG_DIMM3_SIZE_SHFT 24
27033 #define SH_Y_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000
27035 /* SH_Y_DIMM_CFG_DIMM3_2BK */
27036 /* Description: DIMM 3 has two physical banks */
27037 #define SH_Y_DIMM_CFG_DIMM3_2BK_SHFT 27
27038 #define SH_Y_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000
27040 /* SH_Y_DIMM_CFG_DIMM3_REV */
27041 /* Description: DIMM 3 physical banks reversed */
27042 #define SH_Y_DIMM_CFG_DIMM3_REV_SHFT 28
27043 #define SH_Y_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000
27045 /* SH_Y_DIMM_CFG_DIMM3_CS */
27046 /* Description: DIMM 3 chip select, addr[35:34] match */
27047 #define SH_Y_DIMM_CFG_DIMM3_CS_SHFT 29
27048 #define SH_Y_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000
27050 /* SH_Y_DIMM_CFG_FREQ */
27051 /* Description: DIMM frequency select */
27052 #define SH_Y_DIMM_CFG_FREQ_SHFT 32
27053 #define SH_Y_DIMM_CFG_FREQ_MASK 0x0000000f00000000
27055 /* ==================================================================== */
27056 /* Register "SH_JNR_DIMM_CFG" */
27057 /* AC Mem Config Registers */
27058 /* ==================================================================== */
27060 #define SH_JNR_DIMM_CFG 0x0000000100010010
27061 #define SH_JNR_DIMM_CFG_MASK 0x0000000f7f7f7f7f
27062 #define SH_JNR_DIMM_CFG_INIT 0x000000026f4f2f0f
27064 /* SH_JNR_DIMM_CFG_DIMM0_SIZE */
27065 /* Description: DIMM 0 DRAM size */
27066 #define SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT 0
27067 #define SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007
27069 /* SH_JNR_DIMM_CFG_DIMM0_2BK */
27070 /* Description: DIMM 0 has two physical banks */
27071 #define SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT 3
27072 #define SH_JNR_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008
27074 /* SH_JNR_DIMM_CFG_DIMM0_REV */
27075 /* Description: DIMM 0 physical banks reversed */
27076 #define SH_JNR_DIMM_CFG_DIMM0_REV_SHFT 4
27077 #define SH_JNR_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010
27079 /* SH_JNR_DIMM_CFG_DIMM0_CS */
27080 /* Description: DIMM 0 chip select, addr[35:34] match */
27081 #define SH_JNR_DIMM_CFG_DIMM0_CS_SHFT 5
27082 #define SH_JNR_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060
27084 /* SH_JNR_DIMM_CFG_DIMM1_SIZE */
27085 /* Description: DIMM 1 DRAM size */
27086 #define SH_JNR_DIMM_CFG_DIMM1_SIZE_SHFT 8
27087 #define SH_JNR_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700
27089 /* SH_JNR_DIMM_CFG_DIMM1_2BK */
27090 /* Description: DIMM 1 has two physical banks */
27091 #define SH_JNR_DIMM_CFG_DIMM1_2BK_SHFT 11
27092 #define SH_JNR_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800
27094 /* SH_JNR_DIMM_CFG_DIMM1_REV */
27095 /* Description: DIMM 1 physical banks reversed */
27096 #define SH_JNR_DIMM_CFG_DIMM1_REV_SHFT 12
27097 #define SH_JNR_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000
27099 /* SH_JNR_DIMM_CFG_DIMM1_CS */
27100 /* Description: DIMM 1 chip select, addr[35:34] match */
27101 #define SH_JNR_DIMM_CFG_DIMM1_CS_SHFT 13
27102 #define SH_JNR_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000
27104 /* SH_JNR_DIMM_CFG_DIMM2_SIZE */
27105 /* Description: DIMM 2 DRAM size */
27106 #define SH_JNR_DIMM_CFG_DIMM2_SIZE_SHFT 16
27107 #define SH_JNR_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000
27109 /* SH_JNR_DIMM_CFG_DIMM2_2BK */
27110 /* Description: DIMM 2 has two physical banks */
27111 #define SH_JNR_DIMM_CFG_DIMM2_2BK_SHFT 19
27112 #define SH_JNR_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000
27114 /* SH_JNR_DIMM_CFG_DIMM2_REV */
27115 /* Description: DIMM 2 physical banks reversed */
27116 #define SH_JNR_DIMM_CFG_DIMM2_REV_SHFT 20
27117 #define SH_JNR_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000
27119 /* SH_JNR_DIMM_CFG_DIMM2_CS */
27120 /* Description: DIMM 2 chip select, addr[35:34] match */
27121 #define SH_JNR_DIMM_CFG_DIMM2_CS_SHFT 21
27122 #define SH_JNR_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000
27124 /* SH_JNR_DIMM_CFG_DIMM3_SIZE */
27125 /* Description: DIMM 3 DRAM size */
27126 #define SH_JNR_DIMM_CFG_DIMM3_SIZE_SHFT 24
27127 #define SH_JNR_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000
27129 /* SH_JNR_DIMM_CFG_DIMM3_2BK */
27130 /* Description: DIMM 3 has two physical banks */
27131 #define SH_JNR_DIMM_CFG_DIMM3_2BK_SHFT 27
27132 #define SH_JNR_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000
27134 /* SH_JNR_DIMM_CFG_DIMM3_REV */
27135 /* Description: DIMM 3 physical banks reversed */
27136 #define SH_JNR_DIMM_CFG_DIMM3_REV_SHFT 28
27137 #define SH_JNR_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000
27139 /* SH_JNR_DIMM_CFG_DIMM3_CS */
27140 /* Description: DIMM 3 chip select, addr[35:34] match */
27141 #define SH_JNR_DIMM_CFG_DIMM3_CS_SHFT 29
27142 #define SH_JNR_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000
27144 /* SH_JNR_DIMM_CFG_FREQ */
27145 /* Description: DIMM frequency select */
27146 #define SH_JNR_DIMM_CFG_FREQ_SHFT 32
27147 #define SH_JNR_DIMM_CFG_FREQ_MASK 0x0000000f00000000
27149 /* ==================================================================== */
27150 /* Register "SH_X_PHASE_CFG" */
27151 /* AC Phase Config Registers */
27152 /* ==================================================================== */
27154 #define SH_X_PHASE_CFG 0x0000000100010018
27155 #define SH_X_PHASE_CFG_MASK 0x7fffffffffffffff
27156 #define SH_X_PHASE_CFG_INIT 0x0000000000000000
27158 /* SH_X_PHASE_CFG_LD_A */
27159 /* Description: Address, control load core clock A latch */
27160 #define SH_X_PHASE_CFG_LD_A_SHFT 0
27161 #define SH_X_PHASE_CFG_LD_A_MASK 0x000000000000001f
27163 /* SH_X_PHASE_CFG_LD_B */
27164 /* Description: Address, control load core clock B latch */
27165 #define SH_X_PHASE_CFG_LD_B_SHFT 5
27166 #define SH_X_PHASE_CFG_LD_B_MASK 0x00000000000003e0
27168 /* SH_X_PHASE_CFG_DQ_LD_A */
27169 /* Description: DATA MCI load core clock A latch */
27170 #define SH_X_PHASE_CFG_DQ_LD_A_SHFT 10
27171 #define SH_X_PHASE_CFG_DQ_LD_A_MASK 0x0000000000007c00
27173 /* SH_X_PHASE_CFG_DQ_LD_B */
27174 /* Description: DATA MCI load core clock B latch */
27175 #define SH_X_PHASE_CFG_DQ_LD_B_SHFT 15
27176 #define SH_X_PHASE_CFG_DQ_LD_B_MASK 0x00000000000f8000
27178 /* SH_X_PHASE_CFG_HOLD */
27179 /* Description: Hold request on core clock phase */
27180 #define SH_X_PHASE_CFG_HOLD_SHFT 20
27181 #define SH_X_PHASE_CFG_HOLD_MASK 0x0000000001f00000
27183 /* SH_X_PHASE_CFG_HOLD_REQ */
27184 /* Description: Hold next request on core clock phase */
27185 #define SH_X_PHASE_CFG_HOLD_REQ_SHFT 25
27186 #define SH_X_PHASE_CFG_HOLD_REQ_MASK 0x000000003e000000
27188 /* SH_X_PHASE_CFG_ADD_CP */
27189 /* Description: add delay clock period to dqct delay chain on phase */
27190 #define SH_X_PHASE_CFG_ADD_CP_SHFT 30
27191 #define SH_X_PHASE_CFG_ADD_CP_MASK 0x00000007c0000000
27193 /* SH_X_PHASE_CFG_BUBBLE_EN */
27194 /* Description: bubble, idle core clock to wait for memory clock */
27195 #define SH_X_PHASE_CFG_BUBBLE_EN_SHFT 35
27196 #define SH_X_PHASE_CFG_BUBBLE_EN_MASK 0x000000f800000000
27198 /* SH_X_PHASE_CFG_PHA_BUBBLE */
27199 /* Description: MMR phaseA bubble value */
27200 #define SH_X_PHASE_CFG_PHA_BUBBLE_SHFT 40
27201 #define SH_X_PHASE_CFG_PHA_BUBBLE_MASK 0x0000070000000000
27203 /* SH_X_PHASE_CFG_PHB_BUBBLE */
27204 /* Description: MMR phaseB bubble value */
27205 #define SH_X_PHASE_CFG_PHB_BUBBLE_SHFT 43
27206 #define SH_X_PHASE_CFG_PHB_BUBBLE_MASK 0x0000380000000000
27208 /* SH_X_PHASE_CFG_PHC_BUBBLE */
27209 /* Description: MMR phaseC bubble value */
27210 #define SH_X_PHASE_CFG_PHC_BUBBLE_SHFT 46
27211 #define SH_X_PHASE_CFG_PHC_BUBBLE_MASK 0x0001c00000000000
27213 /* SH_X_PHASE_CFG_PHD_BUBBLE */
27214 /* Description: MMR phaseD bubble value */
27215 #define SH_X_PHASE_CFG_PHD_BUBBLE_SHFT 49
27216 #define SH_X_PHASE_CFG_PHD_BUBBLE_MASK 0x000e000000000000
27218 /* SH_X_PHASE_CFG_PHE_BUBBLE */
27219 /* Description: MMR phaseE bubble value */
27220 #define SH_X_PHASE_CFG_PHE_BUBBLE_SHFT 52
27221 #define SH_X_PHASE_CFG_PHE_BUBBLE_MASK 0x0070000000000000
27223 /* SH_X_PHASE_CFG_SEL_A */
27224 /* Description: address,control select A memory clock latch */
27225 #define SH_X_PHASE_CFG_SEL_A_SHFT 55
27226 #define SH_X_PHASE_CFG_SEL_A_MASK 0x0780000000000000
27228 /* SH_X_PHASE_CFG_DQ_SEL_A */
27229 /* Description: DATA MCI select A memory clock latch */
27230 #define SH_X_PHASE_CFG_DQ_SEL_A_SHFT 59
27231 #define SH_X_PHASE_CFG_DQ_SEL_A_MASK 0x7800000000000000
27233 /* ==================================================================== */
27234 /* Register "SH_X_CFG" */
27235 /* AC Config Registers */
27236 /* ==================================================================== */
27238 #define SH_X_CFG 0x0000000100010020
27239 #define SH_X_CFG_MASK 0xffffffffffffffff
27240 #define SH_X_CFG_INIT 0x108443103322100c
27242 /* SH_X_CFG_MODE_SERIAL */
27243 /* Description: Arbque arbitration in serial mode */
27244 #define SH_X_CFG_MODE_SERIAL_SHFT 0
27245 #define SH_X_CFG_MODE_SERIAL_MASK 0x0000000000000001
27247 /* SH_X_CFG_DIRC_RANDOM_REPLACEMENT */
27248 /* Description: Directory cache random replacement */
27249 #define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_SHFT 1
27250 #define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_MASK 0x0000000000000002
27252 /* SH_X_CFG_DIR_COUNTER_INIT */
27253 /* Description: Dir counter initial value */
27254 #define SH_X_CFG_DIR_COUNTER_INIT_SHFT 2
27255 #define SH_X_CFG_DIR_COUNTER_INIT_MASK 0x00000000000000fc
27257 /* SH_X_CFG_TA_DLYS */
27258 /* Description: Turn around delays */
27259 #define SH_X_CFG_TA_DLYS_SHFT 8
27260 #define SH_X_CFG_TA_DLYS_MASK 0x000000ffffffff00
27262 /* SH_X_CFG_DA_BB_CLR */
27263 /* Description: Bank busy CPs for a data read request */
27264 #define SH_X_CFG_DA_BB_CLR_SHFT 40
27265 #define SH_X_CFG_DA_BB_CLR_MASK 0x00000f0000000000
27267 /* SH_X_CFG_DC_BB_CLR */
27268 /* Description: Bank busy CPs for a directory cache read request */
27269 #define SH_X_CFG_DC_BB_CLR_SHFT 44
27270 #define SH_X_CFG_DC_BB_CLR_MASK 0x0000f00000000000
27272 /* SH_X_CFG_WT_BB_CLR */
27273 /* Description: Bank busy CPs for all write request */
27274 #define SH_X_CFG_WT_BB_CLR_SHFT 48
27275 #define SH_X_CFG_WT_BB_CLR_MASK 0x000f000000000000
27277 /* SH_X_CFG_SSO_WT_EN */
27278 /* Description: Simultaneous switching enabled on output data pins */
27279 #define SH_X_CFG_SSO_WT_EN_SHFT 52
27280 #define SH_X_CFG_SSO_WT_EN_MASK 0x0010000000000000
27282 /* SH_X_CFG_TRCD2_EN */
27283 /* Description: Trcd, ras to cas delay of 2 CPs enabled */
27284 #define SH_X_CFG_TRCD2_EN_SHFT 53
27285 #define SH_X_CFG_TRCD2_EN_MASK 0x0020000000000000
27287 /* SH_X_CFG_TRCD4_EN */
27288 /* Description: Trcd, ras to case delay of 4 CPs enabled */
27289 #define SH_X_CFG_TRCD4_EN_SHFT 54
27290 #define SH_X_CFG_TRCD4_EN_MASK 0x0040000000000000
27292 /* SH_X_CFG_REQ_CNTR_DIS */
27293 /* Description: Request delay counter disabled */
27294 #define SH_X_CFG_REQ_CNTR_DIS_SHFT 55
27295 #define SH_X_CFG_REQ_CNTR_DIS_MASK 0x0080000000000000
27297 /* SH_X_CFG_REQ_CNTR_VAL */
27298 /* Description: Request counter delay value in CPs */
27299 #define SH_X_CFG_REQ_CNTR_VAL_SHFT 56
27300 #define SH_X_CFG_REQ_CNTR_VAL_MASK 0x3f00000000000000
27302 /* SH_X_CFG_INV_CAS_ADDR */
27303 /* Description: Invert cas address bits 3 to 7 */
27304 #define SH_X_CFG_INV_CAS_ADDR_SHFT 62
27305 #define SH_X_CFG_INV_CAS_ADDR_MASK 0x4000000000000000
27307 /* SH_X_CFG_CLR_DIR_CACHE */
27308 /* Description: Clear directory cache tags */
27309 #define SH_X_CFG_CLR_DIR_CACHE_SHFT 63
27310 #define SH_X_CFG_CLR_DIR_CACHE_MASK 0x8000000000000000
27312 /* ==================================================================== */
27313 /* Register "SH_X_DQCT_CFG" */
27314 /* AC Config Registers */
27315 /* ==================================================================== */
27317 #define SH_X_DQCT_CFG 0x0000000100010028
27318 #define SH_X_DQCT_CFG_MASK 0x0000000000ffffff
27319 #define SH_X_DQCT_CFG_INIT 0x0000000000585418
27321 /* SH_X_DQCT_CFG_RD_SEL */
27322 /* Description: Read data select */
27323 #define SH_X_DQCT_CFG_RD_SEL_SHFT 0
27324 #define SH_X_DQCT_CFG_RD_SEL_MASK 0x000000000000000f
27326 /* SH_X_DQCT_CFG_WT_SEL */
27327 /* Description: Write data select */
27328 #define SH_X_DQCT_CFG_WT_SEL_SHFT 4
27329 #define SH_X_DQCT_CFG_WT_SEL_MASK 0x00000000000000f0
27331 /* SH_X_DQCT_CFG_DTA_RD_SEL */
27332 /* Description: Data ready read select */
27333 #define SH_X_DQCT_CFG_DTA_RD_SEL_SHFT 8
27334 #define SH_X_DQCT_CFG_DTA_RD_SEL_MASK 0x0000000000000f00
27336 /* SH_X_DQCT_CFG_DTA_WT_SEL */
27337 /* Description: Data ready write select */
27338 #define SH_X_DQCT_CFG_DTA_WT_SEL_SHFT 12
27339 #define SH_X_DQCT_CFG_DTA_WT_SEL_MASK 0x000000000000f000
27341 /* SH_X_DQCT_CFG_DIR_RD_SEL */
27342 /* Description: Dir ready read select */
27343 #define SH_X_DQCT_CFG_DIR_RD_SEL_SHFT 16
27344 #define SH_X_DQCT_CFG_DIR_RD_SEL_MASK 0x00000000000f0000
27346 /* SH_X_DQCT_CFG_MDIR_RD_SEL */
27347 /* Description: Dir ready read select */
27348 #define SH_X_DQCT_CFG_MDIR_RD_SEL_SHFT 20
27349 #define SH_X_DQCT_CFG_MDIR_RD_SEL_MASK 0x0000000000f00000
27351 /* ==================================================================== */
27352 /* Register "SH_X_REFRESH_CONTROL" */
27353 /* Refresh Control Register */
27354 /* ==================================================================== */
27356 #define SH_X_REFRESH_CONTROL 0x0000000100010030
27357 #define SH_X_REFRESH_CONTROL_MASK 0x000000000fffffff
27358 #define SH_X_REFRESH_CONTROL_INIT 0x00000000009cc300
27360 /* SH_X_REFRESH_CONTROL_ENABLE */
27361 /* Description: Refresh enable */
27362 #define SH_X_REFRESH_CONTROL_ENABLE_SHFT 0
27363 #define SH_X_REFRESH_CONTROL_ENABLE_MASK 0x00000000000000ff
27365 /* SH_X_REFRESH_CONTROL_INTERVAL */
27366 /* Description: Refresh interval in core CPs */
27367 #define SH_X_REFRESH_CONTROL_INTERVAL_SHFT 8
27368 #define SH_X_REFRESH_CONTROL_INTERVAL_MASK 0x000000000001ff00
27370 /* SH_X_REFRESH_CONTROL_HOLD */
27371 /* Description: Refresh hold */
27372 #define SH_X_REFRESH_CONTROL_HOLD_SHFT 17
27373 #define SH_X_REFRESH_CONTROL_HOLD_MASK 0x00000000007e0000
27375 /* SH_X_REFRESH_CONTROL_INTERLEAVE */
27376 /* Description: Refresh interleave */
27377 #define SH_X_REFRESH_CONTROL_INTERLEAVE_SHFT 23
27378 #define SH_X_REFRESH_CONTROL_INTERLEAVE_MASK 0x0000000000800000
27380 /* SH_X_REFRESH_CONTROL_HALF_RATE */
27381 /* Description: Refresh half rate */
27382 #define SH_X_REFRESH_CONTROL_HALF_RATE_SHFT 24
27383 #define SH_X_REFRESH_CONTROL_HALF_RATE_MASK 0x000000000f000000
27385 /* ==================================================================== */
27386 /* Register "SH_Y_PHASE_CFG" */
27387 /* AC Phase Config Registers */
27388 /* ==================================================================== */
27390 #define SH_Y_PHASE_CFG 0x0000000100010038
27391 #define SH_Y_PHASE_CFG_MASK 0x7fffffffffffffff
27392 #define SH_Y_PHASE_CFG_INIT 0x0000000000000000
27394 /* SH_Y_PHASE_CFG_LD_A */
27395 /* Description: Address, control load core clock A latch */
27396 #define SH_Y_PHASE_CFG_LD_A_SHFT 0
27397 #define SH_Y_PHASE_CFG_LD_A_MASK 0x000000000000001f
27399 /* SH_Y_PHASE_CFG_LD_B */
27400 /* Description: Address, control load core clock B latch */
27401 #define SH_Y_PHASE_CFG_LD_B_SHFT 5
27402 #define SH_Y_PHASE_CFG_LD_B_MASK 0x00000000000003e0
27404 /* SH_Y_PHASE_CFG_DQ_LD_A */
27405 /* Description: DATA MCI load core clock A latch */
27406 #define SH_Y_PHASE_CFG_DQ_LD_A_SHFT 10
27407 #define SH_Y_PHASE_CFG_DQ_LD_A_MASK 0x0000000000007c00
27409 /* SH_Y_PHASE_CFG_DQ_LD_B */
27410 /* Description: DATA MCI load core clock B latch */
27411 #define SH_Y_PHASE_CFG_DQ_LD_B_SHFT 15
27412 #define SH_Y_PHASE_CFG_DQ_LD_B_MASK 0x00000000000f8000
27414 /* SH_Y_PHASE_CFG_HOLD */
27415 /* Description: Hold request on core clock phase */
27416 #define SH_Y_PHASE_CFG_HOLD_SHFT 20
27417 #define SH_Y_PHASE_CFG_HOLD_MASK 0x0000000001f00000
27419 /* SH_Y_PHASE_CFG_HOLD_REQ */
27420 /* Description: Hold next request on core clock phase */
27421 #define SH_Y_PHASE_CFG_HOLD_REQ_SHFT 25
27422 #define SH_Y_PHASE_CFG_HOLD_REQ_MASK 0x000000003e000000
27424 /* SH_Y_PHASE_CFG_ADD_CP */
27425 /* Description: add delay clock period to dqct delay chain on phase */
27426 #define SH_Y_PHASE_CFG_ADD_CP_SHFT 30
27427 #define SH_Y_PHASE_CFG_ADD_CP_MASK 0x00000007c0000000
27429 /* SH_Y_PHASE_CFG_BUBBLE_EN */
27430 /* Description: bubble, idle core clock to wait for memory clock */
27431 #define SH_Y_PHASE_CFG_BUBBLE_EN_SHFT 35
27432 #define SH_Y_PHASE_CFG_BUBBLE_EN_MASK 0x000000f800000000
27434 /* SH_Y_PHASE_CFG_PHA_BUBBLE */
27435 /* Description: MMR phaseA bubble value */
27436 #define SH_Y_PHASE_CFG_PHA_BUBBLE_SHFT 40
27437 #define SH_Y_PHASE_CFG_PHA_BUBBLE_MASK 0x0000070000000000
27439 /* SH_Y_PHASE_CFG_PHB_BUBBLE */
27440 /* Description: MMR phaseB bubble value */
27441 #define SH_Y_PHASE_CFG_PHB_BUBBLE_SHFT 43
27442 #define SH_Y_PHASE_CFG_PHB_BUBBLE_MASK 0x0000380000000000
27444 /* SH_Y_PHASE_CFG_PHC_BUBBLE */
27445 /* Description: MMR phaseC bubble value */
27446 #define SH_Y_PHASE_CFG_PHC_BUBBLE_SHFT 46
27447 #define SH_Y_PHASE_CFG_PHC_BUBBLE_MASK 0x0001c00000000000
27449 /* SH_Y_PHASE_CFG_PHD_BUBBLE */
27450 /* Description: MMR phaseD bubble value */
27451 #define SH_Y_PHASE_CFG_PHD_BUBBLE_SHFT 49
27452 #define SH_Y_PHASE_CFG_PHD_BUBBLE_MASK 0x000e000000000000
27454 /* SH_Y_PHASE_CFG_PHE_BUBBLE */
27455 /* Description: MMR phaseE bubble value */
27456 #define SH_Y_PHASE_CFG_PHE_BUBBLE_SHFT 52
27457 #define SH_Y_PHASE_CFG_PHE_BUBBLE_MASK 0x0070000000000000
27459 /* SH_Y_PHASE_CFG_SEL_A */
27460 /* Description: address,control select A memory clock latch */
27461 #define SH_Y_PHASE_CFG_SEL_A_SHFT 55
27462 #define SH_Y_PHASE_CFG_SEL_A_MASK 0x0780000000000000
27464 /* SH_Y_PHASE_CFG_DQ_SEL_A */
27465 /* Description: DATA MCI select A memory clock latch */
27466 #define SH_Y_PHASE_CFG_DQ_SEL_A_SHFT 59
27467 #define SH_Y_PHASE_CFG_DQ_SEL_A_MASK 0x7800000000000000
27469 /* ==================================================================== */
27470 /* Register "SH_Y_CFG" */
27471 /* AC Config Registers */
27472 /* ==================================================================== */
27474 #define SH_Y_CFG 0x0000000100010040
27475 #define SH_Y_CFG_MASK 0xffffffffffffffff
27476 #define SH_Y_CFG_INIT 0x108443103322100c
27478 /* SH_Y_CFG_MODE_SERIAL */
27479 /* Description: Arbque arbitration in serial mode */
27480 #define SH_Y_CFG_MODE_SERIAL_SHFT 0
27481 #define SH_Y_CFG_MODE_SERIAL_MASK 0x0000000000000001
27483 /* SH_Y_CFG_DIRC_RANDOM_REPLACEMENT */
27484 /* Description: Directory cache random replacement */
27485 #define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_SHFT 1
27486 #define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_MASK 0x0000000000000002
27488 /* SH_Y_CFG_DIR_COUNTER_INIT */
27489 /* Description: Dir counter initial value */
27490 #define SH_Y_CFG_DIR_COUNTER_INIT_SHFT 2
27491 #define SH_Y_CFG_DIR_COUNTER_INIT_MASK 0x00000000000000fc
27493 /* SH_Y_CFG_TA_DLYS */
27494 /* Description: Turn around delays */
27495 #define SH_Y_CFG_TA_DLYS_SHFT 8
27496 #define SH_Y_CFG_TA_DLYS_MASK 0x000000ffffffff00
27498 /* SH_Y_CFG_DA_BB_CLR */
27499 /* Description: Bank busy CPs for a data read request */
27500 #define SH_Y_CFG_DA_BB_CLR_SHFT 40
27501 #define SH_Y_CFG_DA_BB_CLR_MASK 0x00000f0000000000
27503 /* SH_Y_CFG_DC_BB_CLR */
27504 /* Description: Bank busy CPs for a directory cache read request */
27505 #define SH_Y_CFG_DC_BB_CLR_SHFT 44
27506 #define SH_Y_CFG_DC_BB_CLR_MASK 0x0000f00000000000
27508 /* SH_Y_CFG_WT_BB_CLR */
27509 /* Description: Bank busy CPs for all write request */
27510 #define SH_Y_CFG_WT_BB_CLR_SHFT 48
27511 #define SH_Y_CFG_WT_BB_CLR_MASK 0x000f000000000000
27513 /* SH_Y_CFG_SSO_WT_EN */
27514 /* Description: Simultaneous switching enabled on output data pins */
27515 #define SH_Y_CFG_SSO_WT_EN_SHFT 52
27516 #define SH_Y_CFG_SSO_WT_EN_MASK 0x0010000000000000
27518 /* SH_Y_CFG_TRCD2_EN */
27519 /* Description: Trcd, ras to cas delay of 2 CPs enabled */
27520 #define SH_Y_CFG_TRCD2_EN_SHFT 53
27521 #define SH_Y_CFG_TRCD2_EN_MASK 0x0020000000000000
27523 /* SH_Y_CFG_TRCD4_EN */
27524 /* Description: Trcd, ras to case delay of 4 CPs enabled */
27525 #define SH_Y_CFG_TRCD4_EN_SHFT 54
27526 #define SH_Y_CFG_TRCD4_EN_MASK 0x0040000000000000
27528 /* SH_Y_CFG_REQ_CNTR_DIS */
27529 /* Description: Request delay counter disabled */
27530 #define SH_Y_CFG_REQ_CNTR_DIS_SHFT 55
27531 #define SH_Y_CFG_REQ_CNTR_DIS_MASK 0x0080000000000000
27533 /* SH_Y_CFG_REQ_CNTR_VAL */
27534 /* Description: Request counter delay value in CPs */
27535 #define SH_Y_CFG_REQ_CNTR_VAL_SHFT 56
27536 #define SH_Y_CFG_REQ_CNTR_VAL_MASK 0x3f00000000000000
27538 /* SH_Y_CFG_INV_CAS_ADDR */
27539 /* Description: Invert cas address bits 3 to 7 */
27540 #define SH_Y_CFG_INV_CAS_ADDR_SHFT 62
27541 #define SH_Y_CFG_INV_CAS_ADDR_MASK 0x4000000000000000
27543 /* SH_Y_CFG_CLR_DIR_CACHE */
27544 /* Description: Clear directory cache tags */
27545 #define SH_Y_CFG_CLR_DIR_CACHE_SHFT 63
27546 #define SH_Y_CFG_CLR_DIR_CACHE_MASK 0x8000000000000000
27548 /* ==================================================================== */
27549 /* Register "SH_Y_DQCT_CFG" */
27550 /* AC Config Registers */
27551 /* ==================================================================== */
27553 #define SH_Y_DQCT_CFG 0x0000000100010048
27554 #define SH_Y_DQCT_CFG_MASK 0x0000000000ffffff
27555 #define SH_Y_DQCT_CFG_INIT 0x0000000000585418
27557 /* SH_Y_DQCT_CFG_RD_SEL */
27558 /* Description: Read data select */
27559 #define SH_Y_DQCT_CFG_RD_SEL_SHFT 0
27560 #define SH_Y_DQCT_CFG_RD_SEL_MASK 0x000000000000000f
27562 /* SH_Y_DQCT_CFG_WT_SEL */
27563 /* Description: Write data select */
27564 #define SH_Y_DQCT_CFG_WT_SEL_SHFT 4
27565 #define SH_Y_DQCT_CFG_WT_SEL_MASK 0x00000000000000f0
27567 /* SH_Y_DQCT_CFG_DTA_RD_SEL */
27568 /* Description: Data ready read select */
27569 #define SH_Y_DQCT_CFG_DTA_RD_SEL_SHFT 8
27570 #define SH_Y_DQCT_CFG_DTA_RD_SEL_MASK 0x0000000000000f00
27572 /* SH_Y_DQCT_CFG_DTA_WT_SEL */
27573 /* Description: Data ready write select */
27574 #define SH_Y_DQCT_CFG_DTA_WT_SEL_SHFT 12
27575 #define SH_Y_DQCT_CFG_DTA_WT_SEL_MASK 0x000000000000f000
27577 /* SH_Y_DQCT_CFG_DIR_RD_SEL */
27578 /* Description: Dir ready read select */
27579 #define SH_Y_DQCT_CFG_DIR_RD_SEL_SHFT 16
27580 #define SH_Y_DQCT_CFG_DIR_RD_SEL_MASK 0x00000000000f0000
27582 /* SH_Y_DQCT_CFG_MDIR_RD_SEL */
27583 /* Description: Dir ready read select */
27584 #define SH_Y_DQCT_CFG_MDIR_RD_SEL_SHFT 20
27585 #define SH_Y_DQCT_CFG_MDIR_RD_SEL_MASK 0x0000000000f00000
27587 /* ==================================================================== */
27588 /* Register "SH_Y_REFRESH_CONTROL" */
27589 /* Refresh Control Register */
27590 /* ==================================================================== */
27592 #define SH_Y_REFRESH_CONTROL 0x0000000100010050
27593 #define SH_Y_REFRESH_CONTROL_MASK 0x000000000fffffff
27594 #define SH_Y_REFRESH_CONTROL_INIT 0x00000000009cc300
27596 /* SH_Y_REFRESH_CONTROL_ENABLE */
27597 /* Description: Refresh enable */
27598 #define SH_Y_REFRESH_CONTROL_ENABLE_SHFT 0
27599 #define SH_Y_REFRESH_CONTROL_ENABLE_MASK 0x00000000000000ff
27601 /* SH_Y_REFRESH_CONTROL_INTERVAL */
27602 /* Description: Refresh interval in core CPs */
27603 #define SH_Y_REFRESH_CONTROL_INTERVAL_SHFT 8
27604 #define SH_Y_REFRESH_CONTROL_INTERVAL_MASK 0x000000000001ff00
27606 /* SH_Y_REFRESH_CONTROL_HOLD */
27607 /* Description: Refresh hold */
27608 #define SH_Y_REFRESH_CONTROL_HOLD_SHFT 17
27609 #define SH_Y_REFRESH_CONTROL_HOLD_MASK 0x00000000007e0000
27611 /* SH_Y_REFRESH_CONTROL_INTERLEAVE */
27612 /* Description: Refresh interleave */
27613 #define SH_Y_REFRESH_CONTROL_INTERLEAVE_SHFT 23
27614 #define SH_Y_REFRESH_CONTROL_INTERLEAVE_MASK 0x0000000000800000
27616 /* SH_Y_REFRESH_CONTROL_HALF_RATE */
27617 /* Description: Refresh half rate */
27618 #define SH_Y_REFRESH_CONTROL_HALF_RATE_SHFT 24
27619 #define SH_Y_REFRESH_CONTROL_HALF_RATE_MASK 0x000000000f000000
27621 /* ==================================================================== */
27622 /* Register "SH_MEM_RED_BLACK" */
27623 /* MD fairness watchdog timers */
27624 /* ==================================================================== */
27626 #define SH_MEM_RED_BLACK 0x0000000100010058
27627 #define SH_MEM_RED_BLACK_MASK 0x000fffffffffffff
27628 #define SH_MEM_RED_BLACK_INIT 0x0000000040000400
27630 /* SH_MEM_RED_BLACK_TIME */
27631 /* Description: Clocks to tag references with a given color */
27632 #define SH_MEM_RED_BLACK_TIME_SHFT 0
27633 #define SH_MEM_RED_BLACK_TIME_MASK 0x000000000000ffff
27635 /* SH_MEM_RED_BLACK_ERR_TIME */
27636 /* Description: Max clocks to wait after red/black change for old c */
27637 /* olor to clear. */
27638 #define SH_MEM_RED_BLACK_ERR_TIME_SHFT 16
27639 #define SH_MEM_RED_BLACK_ERR_TIME_MASK 0x000fffffffff0000
27641 /* ==================================================================== */
27642 /* Register "SH_MISC_MEM_CFG" */
27643 /* ==================================================================== */
27645 #define SH_MISC_MEM_CFG 0x0000000100010060
27646 #define SH_MISC_MEM_CFG_MASK 0x0013f1f1fff3f3ff
27647 #define SH_MISC_MEM_CFG_INIT 0x0000000000010107
27649 /* SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE */
27650 /* Description: enables the use of express headers from md to pi */
27651 #define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_SHFT 0
27652 #define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_MASK 0x0000000000000001
27654 /* SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE */
27655 /* Description: enables the use of speculative headers from md to p */
27656 #define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_SHFT 1
27657 #define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_MASK 0x0000000000000002
27659 /* SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE */
27660 /* Description: enables bypass path for requests going through ac */
27661 #define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_SHFT 2
27662 #define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_MASK 0x0000000000000004
27664 /* SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI */
27665 /* Description: disables a one clock delay of XN read data */
27666 #define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_SHFT 3
27667 #define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_MASK 0x0000000000000008
27669 /* SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD */
27670 /* Description: point at which data writes get higher priority */
27671 #define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_SHFT 4
27672 #define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_MASK 0x00000000000003f0
27674 /* SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD */
27675 /* Description: point at which dir cache writes get higher priority */
27676 #define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_SHFT 12
27677 #define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_MASK 0x000000000003f000
27679 /* SH_MISC_MEM_CFG_THROTTLE_CNT */
27680 /* Description: number of clocks between accepting references */
27681 #define SH_MISC_MEM_CFG_THROTTLE_CNT_SHFT 20
27682 #define SH_MISC_MEM_CFG_THROTTLE_CNT_MASK 0x000000000ff00000
27684 /* SH_MISC_MEM_CFG_DISABLED_READ_TNUMS */
27685 /* Description: number of read tnums to take out of circulation */
27686 #define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_SHFT 28
27687 #define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_MASK 0x00000001f0000000
27689 /* SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS */
27690 /* Description: number of write tnums to take out of circulation */
27691 #define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_SHFT 36
27692 #define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_MASK 0x000001f000000000
27694 /* SH_MISC_MEM_CFG_DISABLED_VICTIMS */
27695 /* Description: number of dir cache victim buffers to take out of c */
27696 /* irculation in each quadrant of the MD */
27697 #define SH_MISC_MEM_CFG_DISABLED_VICTIMS_SHFT 44
27698 #define SH_MISC_MEM_CFG_DISABLED_VICTIMS_MASK 0x0003f00000000000
27700 /* SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE */
27701 /* Description: enables plane alternating for replies to XN */
27702 #define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_SHFT 52
27703 #define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_MASK 0x0010000000000000
27705 /* ==================================================================== */
27706 /* Register "SH_PIO_RQ_CRD_CTL" */
27707 /* pio_rq Credit Circulation Control */
27708 /* ==================================================================== */
27710 #define SH_PIO_RQ_CRD_CTL 0x0000000100010068
27711 #define SH_PIO_RQ_CRD_CTL_MASK 0x000000000000003f
27712 #define SH_PIO_RQ_CRD_CTL_INIT 0x0000000000000002
27714 /* SH_PIO_RQ_CRD_CTL_DEPTH */
27715 /* Description: Total depth of buffering (in sic packets) */
27716 #define SH_PIO_RQ_CRD_CTL_DEPTH_SHFT 0
27717 #define SH_PIO_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f
27719 /* ==================================================================== */
27720 /* Register "SH_PI_MD_RQ_CRD_CTL" */
27721 /* pi_md_rq Credit Circulation Control */
27722 /* ==================================================================== */
27724 #define SH_PI_MD_RQ_CRD_CTL 0x0000000100010070
27725 #define SH_PI_MD_RQ_CRD_CTL_MASK 0x000000000000003f
27726 #define SH_PI_MD_RQ_CRD_CTL_INIT 0x0000000000000008
27728 /* SH_PI_MD_RQ_CRD_CTL_DEPTH */
27729 /* Description: Total depth of buffering (in sic packets) */
27730 #define SH_PI_MD_RQ_CRD_CTL_DEPTH_SHFT 0
27731 #define SH_PI_MD_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f
27733 /* ==================================================================== */
27734 /* Register "SH_PI_MD_RP_CRD_CTL" */
27735 /* pi_md_rp Credit Circulation Control */
27736 /* ==================================================================== */
27738 #define SH_PI_MD_RP_CRD_CTL 0x0000000100010078
27739 #define SH_PI_MD_RP_CRD_CTL_MASK 0x000000000000003f
27740 #define SH_PI_MD_RP_CRD_CTL_INIT 0x0000000000000004
27742 /* SH_PI_MD_RP_CRD_CTL_DEPTH */
27743 /* Description: Total depth of buffering (in sic packets) */
27744 #define SH_PI_MD_RP_CRD_CTL_DEPTH_SHFT 0
27745 #define SH_PI_MD_RP_CRD_CTL_DEPTH_MASK 0x000000000000003f
27747 /* ==================================================================== */
27748 /* Register "SH_XN_MD_RQ_CRD_CTL" */
27749 /* xn_md_rq Credit Circulation Control */
27750 /* ==================================================================== */
27752 #define SH_XN_MD_RQ_CRD_CTL 0x0000000100010080
27753 #define SH_XN_MD_RQ_CRD_CTL_MASK 0x000000000000003f
27754 #define SH_XN_MD_RQ_CRD_CTL_INIT 0x0000000000000008
27756 /* SH_XN_MD_RQ_CRD_CTL_DEPTH */
27757 /* Description: Total depth of buffering (in sic packets) */
27758 #define SH_XN_MD_RQ_CRD_CTL_DEPTH_SHFT 0
27759 #define SH_XN_MD_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f
27761 /* ==================================================================== */
27762 /* Register "SH_XN_MD_RP_CRD_CTL" */
27763 /* xn_md_rp Credit Circulation Control */
27764 /* ==================================================================== */
27766 #define SH_XN_MD_RP_CRD_CTL 0x0000000100010088
27767 #define SH_XN_MD_RP_CRD_CTL_MASK 0x000000000000003f
27768 #define SH_XN_MD_RP_CRD_CTL_INIT 0x0000000000000004
27770 /* SH_XN_MD_RP_CRD_CTL_DEPTH */
27771 /* Description: Total depth of buffering (in sic packets) */
27772 #define SH_XN_MD_RP_CRD_CTL_DEPTH_SHFT 0
27773 #define SH_XN_MD_RP_CRD_CTL_DEPTH_MASK 0x000000000000003f
27775 /* ==================================================================== */
27776 /* Register "SH_X_TAG0" */
27777 /* AC tag Registers */
27778 /* ==================================================================== */
27780 #define SH_X_TAG0 0x0000000100020000
27781 #define SH_X_TAG0_MASK 0x00000000000fffff
27782 #define SH_X_TAG0_INIT 0x0000000000000000
27784 /* SH_X_TAG0_TAG */
27785 /* Description: Valid + Tag Address */
27786 #define SH_X_TAG0_TAG_SHFT 0
27787 #define SH_X_TAG0_TAG_MASK 0x00000000000fffff
27789 /* ==================================================================== */
27790 /* Register "SH_X_TAG1" */
27791 /* AC tag Registers */
27792 /* ==================================================================== */
27794 #define SH_X_TAG1 0x0000000100020008
27795 #define SH_X_TAG1_MASK 0x00000000000fffff
27796 #define SH_X_TAG1_INIT 0x0000000000000000
27798 /* SH_X_TAG1_TAG */
27799 /* Description: Valid + Tag Address */
27800 #define SH_X_TAG1_TAG_SHFT 0
27801 #define SH_X_TAG1_TAG_MASK 0x00000000000fffff
27803 /* ==================================================================== */
27804 /* Register "SH_X_TAG2" */
27805 /* AC tag Registers */
27806 /* ==================================================================== */
27808 #define SH_X_TAG2 0x0000000100020010
27809 #define SH_X_TAG2_MASK 0x00000000000fffff
27810 #define SH_X_TAG2_INIT 0x0000000000000000
27812 /* SH_X_TAG2_TAG */
27813 /* Description: Valid + Tag Address */
27814 #define SH_X_TAG2_TAG_SHFT 0
27815 #define SH_X_TAG2_TAG_MASK 0x00000000000fffff
27817 /* ==================================================================== */
27818 /* Register "SH_X_TAG3" */
27819 /* AC tag Registers */
27820 /* ==================================================================== */
27822 #define SH_X_TAG3 0x0000000100020018
27823 #define SH_X_TAG3_MASK 0x00000000000fffff
27824 #define SH_X_TAG3_INIT 0x0000000000000000
27826 /* SH_X_TAG3_TAG */
27827 /* Description: Valid + Tag Address */
27828 #define SH_X_TAG3_TAG_SHFT 0
27829 #define SH_X_TAG3_TAG_MASK 0x00000000000fffff
27831 /* ==================================================================== */
27832 /* Register "SH_X_TAG4" */
27833 /* AC tag Registers */
27834 /* ==================================================================== */
27836 #define SH_X_TAG4 0x0000000100020020
27837 #define SH_X_TAG4_MASK 0x00000000000fffff
27838 #define SH_X_TAG4_INIT 0x0000000000000000
27840 /* SH_X_TAG4_TAG */
27841 /* Description: Valid + Tag Address */
27842 #define SH_X_TAG4_TAG_SHFT 0
27843 #define SH_X_TAG4_TAG_MASK 0x00000000000fffff
27845 /* ==================================================================== */
27846 /* Register "SH_X_TAG5" */
27847 /* AC tag Registers */
27848 /* ==================================================================== */
27850 #define SH_X_TAG5 0x0000000100020028
27851 #define SH_X_TAG5_MASK 0x00000000000fffff
27852 #define SH_X_TAG5_INIT 0x0000000000000000
27854 /* SH_X_TAG5_TAG */
27855 /* Description: Valid + Tag Address */
27856 #define SH_X_TAG5_TAG_SHFT 0
27857 #define SH_X_TAG5_TAG_MASK 0x00000000000fffff
27859 /* ==================================================================== */
27860 /* Register "SH_X_TAG6" */
27861 /* AC tag Registers */
27862 /* ==================================================================== */
27864 #define SH_X_TAG6 0x0000000100020030
27865 #define SH_X_TAG6_MASK 0x00000000000fffff
27866 #define SH_X_TAG6_INIT 0x0000000000000000
27868 /* SH_X_TAG6_TAG */
27869 /* Description: Valid + Tag Address */
27870 #define SH_X_TAG6_TAG_SHFT 0
27871 #define SH_X_TAG6_TAG_MASK 0x00000000000fffff
27873 /* ==================================================================== */
27874 /* Register "SH_X_TAG7" */
27875 /* AC tag Registers */
27876 /* ==================================================================== */
27878 #define SH_X_TAG7 0x0000000100020038
27879 #define SH_X_TAG7_MASK 0x00000000000fffff
27880 #define SH_X_TAG7_INIT 0x0000000000000000
27882 /* SH_X_TAG7_TAG */
27883 /* Description: Valid + Tag Address */
27884 #define SH_X_TAG7_TAG_SHFT 0
27885 #define SH_X_TAG7_TAG_MASK 0x00000000000fffff
27887 /* ==================================================================== */
27888 /* Register "SH_Y_TAG0" */
27889 /* AC tag Registers */
27890 /* ==================================================================== */
27892 #define SH_Y_TAG0 0x0000000100020040
27893 #define SH_Y_TAG0_MASK 0x00000000000fffff
27894 #define SH_Y_TAG0_INIT 0x0000000000000000
27896 /* SH_Y_TAG0_TAG */
27897 /* Description: Valid + Tag Address */
27898 #define SH_Y_TAG0_TAG_SHFT 0
27899 #define SH_Y_TAG0_TAG_MASK 0x00000000000fffff
27901 /* ==================================================================== */
27902 /* Register "SH_Y_TAG1" */
27903 /* AC tag Registers */
27904 /* ==================================================================== */
27906 #define SH_Y_TAG1 0x0000000100020048
27907 #define SH_Y_TAG1_MASK 0x00000000000fffff
27908 #define SH_Y_TAG1_INIT 0x0000000000000000
27910 /* SH_Y_TAG1_TAG */
27911 /* Description: Valid + Tag Address */
27912 #define SH_Y_TAG1_TAG_SHFT 0
27913 #define SH_Y_TAG1_TAG_MASK 0x00000000000fffff
27915 /* ==================================================================== */
27916 /* Register "SH_Y_TAG2" */
27917 /* AC tag Registers */
27918 /* ==================================================================== */
27920 #define SH_Y_TAG2 0x0000000100020050
27921 #define SH_Y_TAG2_MASK 0x00000000000fffff
27922 #define SH_Y_TAG2_INIT 0x0000000000000000
27924 /* SH_Y_TAG2_TAG */
27925 /* Description: Valid + Tag Address */
27926 #define SH_Y_TAG2_TAG_SHFT 0
27927 #define SH_Y_TAG2_TAG_MASK 0x00000000000fffff
27929 /* ==================================================================== */
27930 /* Register "SH_Y_TAG3" */
27931 /* AC tag Registers */
27932 /* ==================================================================== */
27934 #define SH_Y_TAG3 0x0000000100020058
27935 #define SH_Y_TAG3_MASK 0x00000000000fffff
27936 #define SH_Y_TAG3_INIT 0x0000000000000000
27938 /* SH_Y_TAG3_TAG */
27939 /* Description: Valid + Tag Address */
27940 #define SH_Y_TAG3_TAG_SHFT 0
27941 #define SH_Y_TAG3_TAG_MASK 0x00000000000fffff
27943 /* ==================================================================== */
27944 /* Register "SH_Y_TAG4" */
27945 /* AC tag Registers */
27946 /* ==================================================================== */
27948 #define SH_Y_TAG4 0x0000000100020060
27949 #define SH_Y_TAG4_MASK 0x00000000000fffff
27950 #define SH_Y_TAG4_INIT 0x0000000000000000
27952 /* SH_Y_TAG4_TAG */
27953 /* Description: Valid + Tag Address */
27954 #define SH_Y_TAG4_TAG_SHFT 0
27955 #define SH_Y_TAG4_TAG_MASK 0x00000000000fffff
27957 /* ==================================================================== */
27958 /* Register "SH_Y_TAG5" */
27959 /* AC tag Registers */
27960 /* ==================================================================== */
27962 #define SH_Y_TAG5 0x0000000100020068
27963 #define SH_Y_TAG5_MASK 0x00000000000fffff
27964 #define SH_Y_TAG5_INIT 0x0000000000000000
27966 /* SH_Y_TAG5_TAG */
27967 /* Description: Valid + Tag Address */
27968 #define SH_Y_TAG5_TAG_SHFT 0
27969 #define SH_Y_TAG5_TAG_MASK 0x00000000000fffff
27971 /* ==================================================================== */
27972 /* Register "SH_Y_TAG6" */
27973 /* AC tag Registers */
27974 /* ==================================================================== */
27976 #define SH_Y_TAG6 0x0000000100020070
27977 #define SH_Y_TAG6_MASK 0x00000000000fffff
27978 #define SH_Y_TAG6_INIT 0x0000000000000000
27980 /* SH_Y_TAG6_TAG */
27981 /* Description: Valid + Tag Address */
27982 #define SH_Y_TAG6_TAG_SHFT 0
27983 #define SH_Y_TAG6_TAG_MASK 0x00000000000fffff
27985 /* ==================================================================== */
27986 /* Register "SH_Y_TAG7" */
27987 /* AC tag Registers */
27988 /* ==================================================================== */
27990 #define SH_Y_TAG7 0x0000000100020078
27991 #define SH_Y_TAG7_MASK 0x00000000000fffff
27992 #define SH_Y_TAG7_INIT 0x0000000000000000
27994 /* SH_Y_TAG7_TAG */
27995 /* Description: Valid + Tag Address */
27996 #define SH_Y_TAG7_TAG_SHFT 0
27997 #define SH_Y_TAG7_TAG_MASK 0x00000000000fffff
27999 /* ==================================================================== */
28000 /* Register "SH_MMRBIST_BASE" */
28001 /* mmr/bist base address */
28002 /* ==================================================================== */
28004 #define SH_MMRBIST_BASE 0x0000000100020080
28005 #define SH_MMRBIST_BASE_MASK 0x0003fffffffffff8
28006 #define SH_MMRBIST_BASE_INIT 0x0000000000000000
28008 /* SH_MMRBIST_BASE_DWORD_ADDR */
28009 /* Description: bits 49:3 of the memory address */
28010 #define SH_MMRBIST_BASE_DWORD_ADDR_SHFT 3
28011 #define SH_MMRBIST_BASE_DWORD_ADDR_MASK 0x0003fffffffffff8
28013 /* ==================================================================== */
28014 /* Register "SH_MMRBIST_CTL" */
28015 /* Bist base address */
28016 /* ==================================================================== */
28018 #define SH_MMRBIST_CTL 0x0000000100020088
28019 #define SH_MMRBIST_CTL_MASK 0x0000177f7fffffff
28020 #define SH_MMRBIST_CTL_INIT 0x0000000000000000
28022 /* SH_MMRBIST_CTL_BLOCK_LENGTH */
28023 /* Description: number of dwords in operation */
28024 #define SH_MMRBIST_CTL_BLOCK_LENGTH_SHFT 0
28025 #define SH_MMRBIST_CTL_BLOCK_LENGTH_MASK 0x000000007fffffff
28027 /* SH_MMRBIST_CTL_CMD */
28028 /* Description: mmr/bist function */
28029 #define SH_MMRBIST_CTL_CMD_SHFT 32
28030 #define SH_MMRBIST_CTL_CMD_MASK 0x0000007f00000000
28032 /* SH_MMRBIST_CTL_IN_PROGRESS */
28033 /* Description: writing a 1 starts operation, hardware clears on co */
28035 #define SH_MMRBIST_CTL_IN_PROGRESS_SHFT 40
28036 #define SH_MMRBIST_CTL_IN_PROGRESS_MASK 0x0000010000000000
28038 /* SH_MMRBIST_CTL_FAIL */
28039 /* Description: mmr/bist had a data or address error */
28040 #define SH_MMRBIST_CTL_FAIL_SHFT 41
28041 #define SH_MMRBIST_CTL_FAIL_MASK 0x0000020000000000
28043 /* SH_MMRBIST_CTL_MEM_IDLE */
28044 /* Description: all memory activity is complete */
28045 #define SH_MMRBIST_CTL_MEM_IDLE_SHFT 42
28046 #define SH_MMRBIST_CTL_MEM_IDLE_MASK 0x0000040000000000
28048 /* SH_MMRBIST_CTL_RESET_STATE */
28049 /* Description: writing a 1 resets mmrbist hardware, hardware clear */
28050 /* s on completion */
28051 #define SH_MMRBIST_CTL_RESET_STATE_SHFT 44
28052 #define SH_MMRBIST_CTL_RESET_STATE_MASK 0x0000100000000000
28054 /* ==================================================================== */
28055 /* Register "SH_MD_DBUG_DATA_CFG" */
28056 /* configuration for md debug data muxes */
28057 /* ==================================================================== */
28059 #define SH_MD_DBUG_DATA_CFG 0x0000000100020100
28060 #define SH_MD_DBUG_DATA_CFG_MASK 0x7777777777777777
28061 #define SH_MD_DBUG_DATA_CFG_INIT 0x0000000000000000
28063 /* SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET */
28064 /* Description: selects which md chiplet drives nibble0 */
28065 #define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_SHFT 0
28066 #define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007
28068 /* SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE */
28069 /* Description: selects which nibble from selected chiplet drives n */
28070 #define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_SHFT 4
28071 #define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_MASK 0x0000000000000070
28073 /* SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET */
28074 /* Description: selects which md chiplet drives nibble1 */
28075 #define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_SHFT 8
28076 #define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700
28078 /* SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE */
28079 /* Description: selects which nibble from selected chiplet drives n */
28080 #define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_SHFT 12
28081 #define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_MASK 0x0000000000007000
28083 /* SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET */
28084 /* Description: selects which md chiplet drives nibble2 */
28085 #define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_SHFT 16
28086 #define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000
28088 /* SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE */
28089 /* Description: selects which nibble from selected chiplet drives n */
28090 #define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_SHFT 20
28091 #define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_MASK 0x0000000000700000
28093 /* SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET */
28094 /* Description: selects which md chiplet drives nibble3 */
28095 #define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_SHFT 24
28096 #define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000
28098 /* SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE */
28099 /* Description: selects which nibble from selected chiplet drives n */
28100 #define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_SHFT 28
28101 #define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_MASK 0x0000000070000000
28103 /* SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET */
28104 /* Description: selects which md chiplet drives nibble4 */
28105 #define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_SHFT 32
28106 #define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000
28108 /* SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE */
28109 /* Description: selects which nibble from selected chiplet drives n */
28110 #define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_SHFT 36
28111 #define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_MASK 0x0000007000000000
28113 /* SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET */
28114 /* Description: selects which md chiplet drives nibble5 */
28115 #define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_SHFT 40
28116 #define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000
28118 /* SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE */
28119 /* Description: selects which nibble from selected chiplet drives n */
28120 #define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_SHFT 44
28121 #define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_MASK 0x0000700000000000
28123 /* SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET */
28124 /* Description: selects which md chiplet drives nibble6 */
28125 #define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_SHFT 48
28126 #define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000
28128 /* SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE */
28129 /* Description: selects which nibble from selected chiplet drives n */
28130 #define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_SHFT 52
28131 #define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_MASK 0x0070000000000000
28133 /* SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET */
28134 /* Description: selects which md chiplet drives nibble7 */
28135 #define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_SHFT 56
28136 #define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000
28138 /* SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE */
28139 /* Description: selects which nibble from selected chiplet drives n */
28140 #define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_SHFT 60
28141 #define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_MASK 0x7000000000000000
28143 /* ==================================================================== */
28144 /* Register "SH_MD_DBUG_TRIGGER_CFG" */
28145 /* configuration for md debug triggers */
28146 /* ==================================================================== */
28148 #define SH_MD_DBUG_TRIGGER_CFG 0x0000000100020108
28149 #define SH_MD_DBUG_TRIGGER_CFG_MASK 0xf777777777777777
28150 #define SH_MD_DBUG_TRIGGER_CFG_INIT 0x0000000000000000
28152 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET */
28153 /* Description: selects which md chiplet drives nibble0 */
28154 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_SHFT 0
28155 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007
28157 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE */
28158 /* Description: selects which nibble from selected chiplet drives n */
28159 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_SHFT 4
28160 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_MASK 0x0000000000000070
28162 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET */
28163 /* Description: selects which md chiplet drives nibble1 */
28164 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_SHFT 8
28165 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700
28167 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE */
28168 /* Description: selects which nibble from selected chiplet drives n */
28169 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_SHFT 12
28170 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_MASK 0x0000000000007000
28172 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET */
28173 /* Description: selects which md chiplet drives nibble2 */
28174 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_SHFT 16
28175 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000
28177 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE */
28178 /* Description: selects which nibble from selected chiplet drives n */
28179 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_SHFT 20
28180 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_MASK 0x0000000000700000
28182 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET */
28183 /* Description: selects which md chiplet drives nibble3 */
28184 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_SHFT 24
28185 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000
28187 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE */
28188 /* Description: selects which nibble from selected chiplet drives n */
28189 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_SHFT 28
28190 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_MASK 0x0000000070000000
28192 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET */
28193 /* Description: selects which md chiplet drives nibble4 */
28194 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_SHFT 32
28195 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000
28197 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE */
28198 /* Description: selects which nibble from selected chiplet drives n */
28199 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_SHFT 36
28200 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_MASK 0x0000007000000000
28202 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET */
28203 /* Description: selects which md chiplet drives nibble5 */
28204 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_SHFT 40
28205 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000
28207 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE */
28208 /* Description: selects which nibble from selected chiplet drives n */
28209 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_SHFT 44
28210 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_MASK 0x0000700000000000
28212 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET */
28213 /* Description: selects which md chiplet drives nibble6 */
28214 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_SHFT 48
28215 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000
28217 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE */
28218 /* Description: selects which nibble from selected chiplet drives n */
28219 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_SHFT 52
28220 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_MASK 0x0070000000000000
28222 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET */
28223 /* Description: selects which md chiplet drives nibble7 */
28224 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_SHFT 56
28225 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000
28227 /* SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE */
28228 /* Description: selects which nibble from selected chiplet drives n */
28229 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_SHFT 60
28230 #define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_MASK 0x7000000000000000
28232 /* SH_MD_DBUG_TRIGGER_CFG_ENABLE */
28233 /* Description: enables triggering on pattern match */
28234 #define SH_MD_DBUG_TRIGGER_CFG_ENABLE_SHFT 63
28235 #define SH_MD_DBUG_TRIGGER_CFG_ENABLE_MASK 0x8000000000000000
28237 /* ==================================================================== */
28238 /* Register "SH_MD_DBUG_COMPARE" */
28239 /* md debug compare pattern and mask */
28240 /* ==================================================================== */
28242 #define SH_MD_DBUG_COMPARE 0x0000000100020110
28243 #define SH_MD_DBUG_COMPARE_MASK 0xffffffffffffffff
28244 #define SH_MD_DBUG_COMPARE_INIT 0x0000000000000000
28246 /* SH_MD_DBUG_COMPARE_PATTERN */
28247 /* Description: pattern against which to compare dbug data for trig */
28248 #define SH_MD_DBUG_COMPARE_PATTERN_SHFT 0
28249 #define SH_MD_DBUG_COMPARE_PATTERN_MASK 0x00000000ffffffff
28251 /* SH_MD_DBUG_COMPARE_MASK */
28252 /* Description: bits to include in compare of dbug data for trigger */
28253 #define SH_MD_DBUG_COMPARE_MASK_SHFT 32
28254 #define SH_MD_DBUG_COMPARE_MASK_MASK 0xffffffff00000000
28256 /* ==================================================================== */
28257 /* Register "SH_X_MOD_DBUG_SEL" */
28258 /* MD acx debug select */
28259 /* ==================================================================== */
28261 #define SH_X_MOD_DBUG_SEL 0x0000000100020118
28262 #define SH_X_MOD_DBUG_SEL_MASK 0x03ffffffffffffff
28263 #define SH_X_MOD_DBUG_SEL_INIT 0x0000000000000000
28265 /* SH_X_MOD_DBUG_SEL_TAG_SEL */
28266 /* Description: tagmgr select */
28267 #define SH_X_MOD_DBUG_SEL_TAG_SEL_SHFT 0
28268 #define SH_X_MOD_DBUG_SEL_TAG_SEL_MASK 0x00000000000000ff
28270 /* SH_X_MOD_DBUG_SEL_WBQ_SEL */
28271 /* Description: wbqtg select */
28272 #define SH_X_MOD_DBUG_SEL_WBQ_SEL_SHFT 8
28273 #define SH_X_MOD_DBUG_SEL_WBQ_SEL_MASK 0x000000000000ff00
28275 /* SH_X_MOD_DBUG_SEL_ARB_SEL */
28276 /* Description: arbque select */
28277 #define SH_X_MOD_DBUG_SEL_ARB_SEL_SHFT 16
28278 #define SH_X_MOD_DBUG_SEL_ARB_SEL_MASK 0x0000000000ff0000
28280 /* SH_X_MOD_DBUG_SEL_ATL_SEL */
28281 /* Description: aintl select */
28282 #define SH_X_MOD_DBUG_SEL_ATL_SEL_SHFT 24
28283 #define SH_X_MOD_DBUG_SEL_ATL_SEL_MASK 0x00000007ff000000
28285 /* SH_X_MOD_DBUG_SEL_ATR_SEL */
28286 /* Description: aintr select */
28287 #define SH_X_MOD_DBUG_SEL_ATR_SEL_SHFT 35
28288 #define SH_X_MOD_DBUG_SEL_ATR_SEL_MASK 0x00003ff800000000
28290 /* SH_X_MOD_DBUG_SEL_DQL_SEL */
28291 /* Description: dqctr select */
28292 #define SH_X_MOD_DBUG_SEL_DQL_SEL_SHFT 46
28293 #define SH_X_MOD_DBUG_SEL_DQL_SEL_MASK 0x000fc00000000000
28295 /* SH_X_MOD_DBUG_SEL_DQR_SEL */
28296 /* Description: dqctl select */
28297 #define SH_X_MOD_DBUG_SEL_DQR_SEL_SHFT 52
28298 #define SH_X_MOD_DBUG_SEL_DQR_SEL_MASK 0x03f0000000000000
28300 /* ==================================================================== */
28301 /* Register "SH_X_DBUG_SEL" */
28302 /* MD acx debug select */
28303 /* ==================================================================== */
28305 #define SH_X_DBUG_SEL 0x0000000100020120
28306 #define SH_X_DBUG_SEL_MASK 0x0000000000ffffff
28307 #define SH_X_DBUG_SEL_INIT 0x0000000000000000
28309 /* SH_X_DBUG_SEL_DBG_SEL */
28310 /* Description: debug select */
28311 #define SH_X_DBUG_SEL_DBG_SEL_SHFT 0
28312 #define SH_X_DBUG_SEL_DBG_SEL_MASK 0x0000000000ffffff
28314 /* ==================================================================== */
28315 /* Register "SH_X_LADDR_CMP" */
28316 /* MD acx address compare */
28317 /* ==================================================================== */
28319 #define SH_X_LADDR_CMP 0x0000000100020128
28320 #define SH_X_LADDR_CMP_MASK 0x0fffffff0fffffff
28321 #define SH_X_LADDR_CMP_INIT 0x0000000000000000
28323 /* SH_X_LADDR_CMP_CMP_VAL */
28324 /* Description: Compare value */
28325 #define SH_X_LADDR_CMP_CMP_VAL_SHFT 0
28326 #define SH_X_LADDR_CMP_CMP_VAL_MASK 0x000000000fffffff
28328 /* SH_X_LADDR_CMP_MASK_VAL */
28329 /* Description: Mask value */
28330 #define SH_X_LADDR_CMP_MASK_VAL_SHFT 32
28331 #define SH_X_LADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000
28333 /* ==================================================================== */
28334 /* Register "SH_X_RADDR_CMP" */
28335 /* MD acx address compare */
28336 /* ==================================================================== */
28338 #define SH_X_RADDR_CMP 0x0000000100020130
28339 #define SH_X_RADDR_CMP_MASK 0x0fffffff0fffffff
28340 #define SH_X_RADDR_CMP_INIT 0x0000000000000000
28342 /* SH_X_RADDR_CMP_CMP_VAL */
28343 /* Description: Compare value */
28344 #define SH_X_RADDR_CMP_CMP_VAL_SHFT 0
28345 #define SH_X_RADDR_CMP_CMP_VAL_MASK 0x000000000fffffff
28347 /* SH_X_RADDR_CMP_MASK_VAL */
28348 /* Description: Mask value */
28349 #define SH_X_RADDR_CMP_MASK_VAL_SHFT 32
28350 #define SH_X_RADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000
28352 /* ==================================================================== */
28353 /* Register "SH_X_TAG_CMP" */
28354 /* MD acx tagmgr compare */
28355 /* ==================================================================== */
28357 #define SH_X_TAG_CMP 0x0000000100020138
28358 #define SH_X_TAG_CMP_MASK 0x007fffffffffffff
28359 #define SH_X_TAG_CMP_INIT 0x0000000000000000
28361 /* SH_X_TAG_CMP_CMD */
28362 /* Description: Command compare value */
28363 #define SH_X_TAG_CMP_CMD_SHFT 0
28364 #define SH_X_TAG_CMP_CMD_MASK 0x00000000000000ff
28366 /* SH_X_TAG_CMP_ADDR */
28367 /* Description: Address compare value */
28368 #define SH_X_TAG_CMP_ADDR_SHFT 8
28369 #define SH_X_TAG_CMP_ADDR_MASK 0x000001ffffffff00
28371 /* SH_X_TAG_CMP_SRC */
28372 /* Description: Source compare value */
28373 #define SH_X_TAG_CMP_SRC_SHFT 41
28374 #define SH_X_TAG_CMP_SRC_MASK 0x007ffe0000000000
28376 /* ==================================================================== */
28377 /* Register "SH_X_TAG_MASK" */
28378 /* MD acx tagmgr mask */
28379 /* ==================================================================== */
28381 #define SH_X_TAG_MASK 0x0000000100020140
28382 #define SH_X_TAG_MASK_MASK 0x007fffffffffffff
28383 #define SH_X_TAG_MASK_INIT 0x0000000000000000
28385 /* SH_X_TAG_MASK_CMD */
28386 /* Description: Command compare value */
28387 #define SH_X_TAG_MASK_CMD_SHFT 0
28388 #define SH_X_TAG_MASK_CMD_MASK 0x00000000000000ff
28390 /* SH_X_TAG_MASK_ADDR */
28391 /* Description: Address compare value */
28392 #define SH_X_TAG_MASK_ADDR_SHFT 8
28393 #define SH_X_TAG_MASK_ADDR_MASK 0x000001ffffffff00
28395 /* SH_X_TAG_MASK_SRC */
28396 /* Description: Source compare value */
28397 #define SH_X_TAG_MASK_SRC_SHFT 41
28398 #define SH_X_TAG_MASK_SRC_MASK 0x007ffe0000000000
28400 /* ==================================================================== */
28401 /* Register "SH_Y_MOD_DBUG_SEL" */
28402 /* MD acy debug select */
28403 /* ==================================================================== */
28405 #define SH_Y_MOD_DBUG_SEL 0x0000000100020148
28406 #define SH_Y_MOD_DBUG_SEL_MASK 0x03ffffffffffffff
28407 #define SH_Y_MOD_DBUG_SEL_INIT 0x0000000000000000
28409 /* SH_Y_MOD_DBUG_SEL_TAG_SEL */
28410 /* Description: tagmgr select */
28411 #define SH_Y_MOD_DBUG_SEL_TAG_SEL_SHFT 0
28412 #define SH_Y_MOD_DBUG_SEL_TAG_SEL_MASK 0x00000000000000ff
28414 /* SH_Y_MOD_DBUG_SEL_WBQ_SEL */
28415 /* Description: wbqtg select */
28416 #define SH_Y_MOD_DBUG_SEL_WBQ_SEL_SHFT 8
28417 #define SH_Y_MOD_DBUG_SEL_WBQ_SEL_MASK 0x000000000000ff00
28419 /* SH_Y_MOD_DBUG_SEL_ARB_SEL */
28420 /* Description: arbque select */
28421 #define SH_Y_MOD_DBUG_SEL_ARB_SEL_SHFT 16
28422 #define SH_Y_MOD_DBUG_SEL_ARB_SEL_MASK 0x0000000000ff0000
28424 /* SH_Y_MOD_DBUG_SEL_ATL_SEL */
28425 /* Description: aintl select */
28426 #define SH_Y_MOD_DBUG_SEL_ATL_SEL_SHFT 24
28427 #define SH_Y_MOD_DBUG_SEL_ATL_SEL_MASK 0x00000007ff000000
28429 /* SH_Y_MOD_DBUG_SEL_ATR_SEL */
28430 /* Description: aintr select */
28431 #define SH_Y_MOD_DBUG_SEL_ATR_SEL_SHFT 35
28432 #define SH_Y_MOD_DBUG_SEL_ATR_SEL_MASK 0x00003ff800000000
28434 /* SH_Y_MOD_DBUG_SEL_DQL_SEL */
28435 /* Description: dqctr select */
28436 #define SH_Y_MOD_DBUG_SEL_DQL_SEL_SHFT 46
28437 #define SH_Y_MOD_DBUG_SEL_DQL_SEL_MASK 0x000fc00000000000
28439 /* SH_Y_MOD_DBUG_SEL_DQR_SEL */
28440 /* Description: dqctl select */
28441 #define SH_Y_MOD_DBUG_SEL_DQR_SEL_SHFT 52
28442 #define SH_Y_MOD_DBUG_SEL_DQR_SEL_MASK 0x03f0000000000000
28444 /* ==================================================================== */
28445 /* Register "SH_Y_DBUG_SEL" */
28446 /* MD acy debug select */
28447 /* ==================================================================== */
28449 #define SH_Y_DBUG_SEL 0x0000000100020150
28450 #define SH_Y_DBUG_SEL_MASK 0x0000000000ffffff
28451 #define SH_Y_DBUG_SEL_INIT 0x0000000000000000
28453 /* SH_Y_DBUG_SEL_DBG_SEL */
28454 /* Description: debug select */
28455 #define SH_Y_DBUG_SEL_DBG_SEL_SHFT 0
28456 #define SH_Y_DBUG_SEL_DBG_SEL_MASK 0x0000000000ffffff
28458 /* ==================================================================== */
28459 /* Register "SH_Y_LADDR_CMP" */
28460 /* MD acy address compare */
28461 /* ==================================================================== */
28463 #define SH_Y_LADDR_CMP 0x0000000100020158
28464 #define SH_Y_LADDR_CMP_MASK 0x0fffffff0fffffff
28465 #define SH_Y_LADDR_CMP_INIT 0x0000000000000000
28467 /* SH_Y_LADDR_CMP_CMP_VAL */
28468 /* Description: Compare value */
28469 #define SH_Y_LADDR_CMP_CMP_VAL_SHFT 0
28470 #define SH_Y_LADDR_CMP_CMP_VAL_MASK 0x000000000fffffff
28472 /* SH_Y_LADDR_CMP_MASK_VAL */
28473 /* Description: Mask value */
28474 #define SH_Y_LADDR_CMP_MASK_VAL_SHFT 32
28475 #define SH_Y_LADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000
28477 /* ==================================================================== */
28478 /* Register "SH_Y_RADDR_CMP" */
28479 /* MD acy address compare */
28480 /* ==================================================================== */
28482 #define SH_Y_RADDR_CMP 0x0000000100020160
28483 #define SH_Y_RADDR_CMP_MASK 0x0fffffff0fffffff
28484 #define SH_Y_RADDR_CMP_INIT 0x0000000000000000
28486 /* SH_Y_RADDR_CMP_CMP_VAL */
28487 /* Description: Compare value */
28488 #define SH_Y_RADDR_CMP_CMP_VAL_SHFT 0
28489 #define SH_Y_RADDR_CMP_CMP_VAL_MASK 0x000000000fffffff
28491 /* SH_Y_RADDR_CMP_MASK_VAL */
28492 /* Description: Mask value */
28493 #define SH_Y_RADDR_CMP_MASK_VAL_SHFT 32
28494 #define SH_Y_RADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000
28496 /* ==================================================================== */
28497 /* Register "SH_Y_TAG_CMP" */
28498 /* MD acy tagmgr compare */
28499 /* ==================================================================== */
28501 #define SH_Y_TAG_CMP 0x0000000100020168
28502 #define SH_Y_TAG_CMP_MASK 0x007fffffffffffff
28503 #define SH_Y_TAG_CMP_INIT 0x0000000000000000
28505 /* SH_Y_TAG_CMP_CMD */
28506 /* Description: Command compare value */
28507 #define SH_Y_TAG_CMP_CMD_SHFT 0
28508 #define SH_Y_TAG_CMP_CMD_MASK 0x00000000000000ff
28510 /* SH_Y_TAG_CMP_ADDR */
28511 /* Description: Address compare value */
28512 #define SH_Y_TAG_CMP_ADDR_SHFT 8
28513 #define SH_Y_TAG_CMP_ADDR_MASK 0x000001ffffffff00
28515 /* SH_Y_TAG_CMP_SRC */
28516 /* Description: Source compare value */
28517 #define SH_Y_TAG_CMP_SRC_SHFT 41
28518 #define SH_Y_TAG_CMP_SRC_MASK 0x007ffe0000000000
28520 /* ==================================================================== */
28521 /* Register "SH_Y_TAG_MASK" */
28522 /* MD acy tagmgr mask */
28523 /* ==================================================================== */
28525 #define SH_Y_TAG_MASK 0x0000000100020170
28526 #define SH_Y_TAG_MASK_MASK 0x007fffffffffffff
28527 #define SH_Y_TAG_MASK_INIT 0x0000000000000000
28529 /* SH_Y_TAG_MASK_CMD */
28530 /* Description: Command compare value */
28531 #define SH_Y_TAG_MASK_CMD_SHFT 0
28532 #define SH_Y_TAG_MASK_CMD_MASK 0x00000000000000ff
28534 /* SH_Y_TAG_MASK_ADDR */
28535 /* Description: Address compare value */
28536 #define SH_Y_TAG_MASK_ADDR_SHFT 8
28537 #define SH_Y_TAG_MASK_ADDR_MASK 0x000001ffffffff00
28539 /* SH_Y_TAG_MASK_SRC */
28540 /* Description: Source compare value */
28541 #define SH_Y_TAG_MASK_SRC_SHFT 41
28542 #define SH_Y_TAG_MASK_SRC_MASK 0x007ffe0000000000
28544 /* ==================================================================== */
28545 /* Register "SH_MD_JNR_DBUG_DATA_CFG" */
28546 /* configuration for md jnr debug data muxes */
28547 /* ==================================================================== */
28549 #define SH_MD_JNR_DBUG_DATA_CFG 0x0000000100020178
28550 #define SH_MD_JNR_DBUG_DATA_CFG_MASK 0x0000000077777777
28551 #define SH_MD_JNR_DBUG_DATA_CFG_INIT 0x0000000000000000
28553 /* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL */
28554 /* Description: selects which nibble drives nibble0 */
28555 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_SHFT 0
28556 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_MASK 0x0000000000000007
28558 /* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL */
28559 /* Description: selects which nibble drives nibble1 */
28560 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_SHFT 4
28561 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_MASK 0x0000000000000070
28563 /* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL */
28564 /* Description: selects which nibble drives nibble2 */
28565 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_SHFT 8
28566 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_MASK 0x0000000000000700
28568 /* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL */
28569 /* Description: selects which nibble drives nibble3 */
28570 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_SHFT 12
28571 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_MASK 0x0000000000007000
28573 /* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL */
28574 /* Description: selects which nibble drives nibble4 */
28575 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_SHFT 16
28576 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_MASK 0x0000000000070000
28578 /* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL */
28579 /* Description: selects which nibble drives nibble5 */
28580 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_SHFT 20
28581 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_MASK 0x0000000000700000
28583 /* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL */
28584 /* Description: selects which nibble drives nibble6 */
28585 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_SHFT 24
28586 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_MASK 0x0000000007000000
28588 /* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL */
28589 /* Description: selects which nibble drives nibble7 */
28590 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_SHFT 28
28591 #define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_MASK 0x0000000070000000
28593 /* ==================================================================== */
28594 /* Register "SH_MD_LAST_CREDIT" */
28595 /* captures last credit values on reset */
28596 /* ==================================================================== */
28598 #define SH_MD_LAST_CREDIT 0x0000000100020180
28599 #define SH_MD_LAST_CREDIT_MASK 0x0000003f3f3f3f3f
28600 #define SH_MD_LAST_CREDIT_INIT 0x0000000000000000
28602 /* SH_MD_LAST_CREDIT_RQ_TO_PI */
28603 /* Description: capture of request credits to pi */
28604 #define SH_MD_LAST_CREDIT_RQ_TO_PI_SHFT 0
28605 #define SH_MD_LAST_CREDIT_RQ_TO_PI_MASK 0x000000000000003f
28607 /* SH_MD_LAST_CREDIT_RP_TO_PI */
28608 /* Description: capture of reply credits to pi */
28609 #define SH_MD_LAST_CREDIT_RP_TO_PI_SHFT 8
28610 #define SH_MD_LAST_CREDIT_RP_TO_PI_MASK 0x0000000000003f00
28612 /* SH_MD_LAST_CREDIT_RQ_TO_XN */
28613 /* Description: capture of request credits to xn */
28614 #define SH_MD_LAST_CREDIT_RQ_TO_XN_SHFT 16
28615 #define SH_MD_LAST_CREDIT_RQ_TO_XN_MASK 0x00000000003f0000
28617 /* SH_MD_LAST_CREDIT_RP_TO_XN */
28618 /* Description: capture of reply credits to xn */
28619 #define SH_MD_LAST_CREDIT_RP_TO_XN_SHFT 24
28620 #define SH_MD_LAST_CREDIT_RP_TO_XN_MASK 0x000000003f000000
28622 /* SH_MD_LAST_CREDIT_TO_LB */
28623 /* Description: capture of credits to pi */
28624 #define SH_MD_LAST_CREDIT_TO_LB_SHFT 32
28625 #define SH_MD_LAST_CREDIT_TO_LB_MASK 0x0000003f00000000
28627 /* ==================================================================== */
28628 /* Register "SH_MEM_CAPTURE_ADDR" */
28629 /* Address capture address register */
28630 /* ==================================================================== */
28632 #define SH_MEM_CAPTURE_ADDR 0x0000000100020300
28633 #define SH_MEM_CAPTURE_ADDR_MASK 0x00000ffffffffff8
28634 #define SH_MEM_CAPTURE_ADDR_INIT 0x0000000000000000
28636 /* SH_MEM_CAPTURE_ADDR_ADDR */
28637 /* Description: upper bits of address */
28638 #define SH_MEM_CAPTURE_ADDR_ADDR_SHFT 3
28639 #define SH_MEM_CAPTURE_ADDR_ADDR_MASK 0x0000000ffffffff8
28641 /* SH_MEM_CAPTURE_ADDR_CMD */
28642 /* Description: command of reference */
28643 #define SH_MEM_CAPTURE_ADDR_CMD_SHFT 36
28644 #define SH_MEM_CAPTURE_ADDR_CMD_MASK 0x00000ff000000000
28646 /* ==================================================================== */
28647 /* Register "SH_MEM_CAPTURE_MASK" */
28648 /* Address capture mask register */
28649 /* ==================================================================== */
28651 #define SH_MEM_CAPTURE_MASK 0x0000000100020308
28652 #define SH_MEM_CAPTURE_MASK_MASK 0x00003ffffffffff8
28653 #define SH_MEM_CAPTURE_MASK_INIT 0x0000000000000000
28655 /* SH_MEM_CAPTURE_MASK_ADDR */
28656 /* Description: upper bits of address */
28657 #define SH_MEM_CAPTURE_MASK_ADDR_SHFT 3
28658 #define SH_MEM_CAPTURE_MASK_ADDR_MASK 0x0000000ffffffff8
28660 /* SH_MEM_CAPTURE_MASK_CMD */
28661 /* Description: command of reference */
28662 #define SH_MEM_CAPTURE_MASK_CMD_SHFT 36
28663 #define SH_MEM_CAPTURE_MASK_CMD_MASK 0x00000ff000000000
28665 /* SH_MEM_CAPTURE_MASK_ENABLE_LOCAL */
28666 /* Description: capture references originating locally */
28667 #define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_SHFT 44
28668 #define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_MASK 0x0000100000000000
28670 /* SH_MEM_CAPTURE_MASK_ENABLE_REMOTE */
28671 /* Description: capture references originating remotely */
28672 #define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_SHFT 45
28673 #define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_MASK 0x0000200000000000
28675 /* ==================================================================== */
28676 /* Register "SH_MEM_CAPTURE_HDR" */
28677 /* Address capture header register */
28678 /* ==================================================================== */
28680 #define SH_MEM_CAPTURE_HDR 0x0000000100020310
28681 #define SH_MEM_CAPTURE_HDR_MASK 0xfffffffffffffff8
28682 #define SH_MEM_CAPTURE_HDR_INIT 0x0000000000000000
28684 /* SH_MEM_CAPTURE_HDR_ADDR */
28685 /* Description: upper bits of reference address */
28686 #define SH_MEM_CAPTURE_HDR_ADDR_SHFT 3
28687 #define SH_MEM_CAPTURE_HDR_ADDR_MASK 0x0000000ffffffff8
28689 /* SH_MEM_CAPTURE_HDR_CMD */
28690 /* Description: command of reference */
28691 #define SH_MEM_CAPTURE_HDR_CMD_SHFT 36
28692 #define SH_MEM_CAPTURE_HDR_CMD_MASK 0x00000ff000000000
28694 /* SH_MEM_CAPTURE_HDR_SRC */
28695 /* Description: source node of reference */
28696 #define SH_MEM_CAPTURE_HDR_SRC_SHFT 44
28697 #define SH_MEM_CAPTURE_HDR_SRC_MASK 0x03fff00000000000
28699 /* SH_MEM_CAPTURE_HDR_CNTR */
28700 /* Description: increments on every capture */
28701 #define SH_MEM_CAPTURE_HDR_CNTR_SHFT 58
28702 #define SH_MEM_CAPTURE_HDR_CNTR_MASK 0xfc00000000000000
28704 /* ==================================================================== */
28705 /* Register "SH_MD_DQLP_MMR_DIR_CONFIG" */
28706 /* DQ directory config register */
28707 /* ==================================================================== */
28709 #define SH_MD_DQLP_MMR_DIR_CONFIG 0x0000000100030000
28710 #define SH_MD_DQLP_MMR_DIR_CONFIG_MASK 0x000000000000001f
28711 #define SH_MD_DQLP_MMR_DIR_CONFIG_INIT 0x0000000000000010
28713 /* SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE */
28714 /* Description: system size code */
28715 #define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_SHFT 0
28716 #define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_MASK 0x0000000000000007
28718 /* SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC */
28719 /* Description: enable directory ecc correction */
28720 #define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3
28721 #define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008
28723 /* SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS */
28724 /* Description: enable local poisoning for dir table fall-through */
28725 #define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4
28726 #define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010
28728 /* ==================================================================== */
28729 /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC0" */
28730 /* node [63:0] presence bits */
28731 /* ==================================================================== */
28733 #define SH_MD_DQLP_MMR_DIR_PRESVEC0 0x0000000100030100
28734 #define SH_MD_DQLP_MMR_DIR_PRESVEC0_MASK 0xffffffffffffffff
28735 #define SH_MD_DQLP_MMR_DIR_PRESVEC0_INIT 0x0000000000000000
28737 /* SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC */
28738 /* Description: node presence bits, 1=present */
28739 #define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_SHFT 0
28740 #define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_MASK 0xffffffffffffffff
28742 /* ==================================================================== */
28743 /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC1" */
28744 /* node [127:64] presence bits */
28745 /* ==================================================================== */
28747 #define SH_MD_DQLP_MMR_DIR_PRESVEC1 0x0000000100030110
28748 #define SH_MD_DQLP_MMR_DIR_PRESVEC1_MASK 0xffffffffffffffff
28749 #define SH_MD_DQLP_MMR_DIR_PRESVEC1_INIT 0x0000000000000000
28751 /* SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC */
28752 /* Description: node presence bits, 1=present */
28753 #define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_SHFT 0
28754 #define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_MASK 0xffffffffffffffff
28756 /* ==================================================================== */
28757 /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC2" */
28758 /* node [191:128] presence bits */
28759 /* ==================================================================== */
28761 #define SH_MD_DQLP_MMR_DIR_PRESVEC2 0x0000000100030120
28762 #define SH_MD_DQLP_MMR_DIR_PRESVEC2_MASK 0xffffffffffffffff
28763 #define SH_MD_DQLP_MMR_DIR_PRESVEC2_INIT 0x0000000000000000
28765 /* SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC */
28766 /* Description: node presence bits, 1=present */
28767 #define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_SHFT 0
28768 #define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_MASK 0xffffffffffffffff
28770 /* ==================================================================== */
28771 /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC3" */
28772 /* node [255:192] presence bits */
28773 /* ==================================================================== */
28775 #define SH_MD_DQLP_MMR_DIR_PRESVEC3 0x0000000100030130
28776 #define SH_MD_DQLP_MMR_DIR_PRESVEC3_MASK 0xffffffffffffffff
28777 #define SH_MD_DQLP_MMR_DIR_PRESVEC3_INIT 0x0000000000000000
28779 /* SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC */
28780 /* Description: node presence bits, 1=present */
28781 #define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_SHFT 0
28782 #define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_MASK 0xffffffffffffffff
28784 /* ==================================================================== */
28785 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC0" */
28786 /* local vector for acc=0 */
28787 /* ==================================================================== */
28789 #define SH_MD_DQLP_MMR_DIR_LOCVEC0 0x0000000100030200
28790 #define SH_MD_DQLP_MMR_DIR_LOCVEC0_MASK 0xffffffffffffffff
28791 #define SH_MD_DQLP_MMR_DIR_LOCVEC0_INIT 0x0000000000000000
28793 /* SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC */
28794 /* Description: 1 node is local */
28795 #define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_SHFT 0
28796 #define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_MASK 0xffffffffffffffff
28798 /* ==================================================================== */
28799 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC1" */
28800 /* local vector for acc=1 */
28801 /* ==================================================================== */
28803 #define SH_MD_DQLP_MMR_DIR_LOCVEC1 0x0000000100030210
28804 #define SH_MD_DQLP_MMR_DIR_LOCVEC1_MASK 0xffffffffffffffff
28805 #define SH_MD_DQLP_MMR_DIR_LOCVEC1_INIT 0x0000000000000000
28807 /* SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC */
28808 /* Description: 1 node is local */
28809 #define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_SHFT 0
28810 #define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_MASK 0xffffffffffffffff
28812 /* ==================================================================== */
28813 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC2" */
28814 /* local vector for acc=2 */
28815 /* ==================================================================== */
28817 #define SH_MD_DQLP_MMR_DIR_LOCVEC2 0x0000000100030220
28818 #define SH_MD_DQLP_MMR_DIR_LOCVEC2_MASK 0xffffffffffffffff
28819 #define SH_MD_DQLP_MMR_DIR_LOCVEC2_INIT 0x0000000000000000
28821 /* SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC */
28822 /* Description: 1 node is local */
28823 #define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_SHFT 0
28824 #define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_MASK 0xffffffffffffffff
28826 /* ==================================================================== */
28827 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC3" */
28828 /* local vector for acc=3 */
28829 /* ==================================================================== */
28831 #define SH_MD_DQLP_MMR_DIR_LOCVEC3 0x0000000100030230
28832 #define SH_MD_DQLP_MMR_DIR_LOCVEC3_MASK 0xffffffffffffffff
28833 #define SH_MD_DQLP_MMR_DIR_LOCVEC3_INIT 0x0000000000000000
28835 /* SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC */
28836 /* Description: 1 node is local */
28837 #define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_SHFT 0
28838 #define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_MASK 0xffffffffffffffff
28840 /* ==================================================================== */
28841 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC4" */
28842 /* local vector for acc=4 */
28843 /* ==================================================================== */
28845 #define SH_MD_DQLP_MMR_DIR_LOCVEC4 0x0000000100030240
28846 #define SH_MD_DQLP_MMR_DIR_LOCVEC4_MASK 0xffffffffffffffff
28847 #define SH_MD_DQLP_MMR_DIR_LOCVEC4_INIT 0x0000000000000000
28849 /* SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC */
28850 /* Description: 1 node is local */
28851 #define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_SHFT 0
28852 #define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_MASK 0xffffffffffffffff
28854 /* ==================================================================== */
28855 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC5" */
28856 /* local vector for acc=5 */
28857 /* ==================================================================== */
28859 #define SH_MD_DQLP_MMR_DIR_LOCVEC5 0x0000000100030250
28860 #define SH_MD_DQLP_MMR_DIR_LOCVEC5_MASK 0xffffffffffffffff
28861 #define SH_MD_DQLP_MMR_DIR_LOCVEC5_INIT 0x0000000000000000
28863 /* SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC */
28864 /* Description: 1 node is local */
28865 #define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_SHFT 0
28866 #define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_MASK 0xffffffffffffffff
28868 /* ==================================================================== */
28869 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC6" */
28870 /* local vector for acc=6 */
28871 /* ==================================================================== */
28873 #define SH_MD_DQLP_MMR_DIR_LOCVEC6 0x0000000100030260
28874 #define SH_MD_DQLP_MMR_DIR_LOCVEC6_MASK 0xffffffffffffffff
28875 #define SH_MD_DQLP_MMR_DIR_LOCVEC6_INIT 0x0000000000000000
28877 /* SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC */
28878 /* Description: 1 node is local */
28879 #define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_SHFT 0
28880 #define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_MASK 0xffffffffffffffff
28882 /* ==================================================================== */
28883 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC7" */
28884 /* local vector for acc=7 */
28885 /* ==================================================================== */
28887 #define SH_MD_DQLP_MMR_DIR_LOCVEC7 0x0000000100030270
28888 #define SH_MD_DQLP_MMR_DIR_LOCVEC7_MASK 0xffffffffffffffff
28889 #define SH_MD_DQLP_MMR_DIR_LOCVEC7_INIT 0x0000000000000000
28891 /* SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC */
28892 /* Description: 1 node is local */
28893 #define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_SHFT 0
28894 #define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_MASK 0xffffffffffffffff
28896 /* ==================================================================== */
28897 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
28898 /* privilege vector for acc=0 */
28899 /* ==================================================================== */
28901 #define SH_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300
28902 #define SH_MD_DQLP_MMR_DIR_PRIVEC0_MASK 0x000000000fffffff
28903 #define SH_MD_DQLP_MMR_DIR_PRIVEC0_INIT 0x0000000000000000
28905 /* SH_MD_DQLP_MMR_DIR_PRIVEC0_IN */
28906 /* Description: in partition privileges, locvec bit=1 */
28907 #define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_SHFT 0
28908 #define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_MASK 0x0000000000003fff
28910 /* SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT */
28911 /* Description: out of partition privileges, locvec bit=0 */
28912 #define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_SHFT 14
28913 #define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_MASK 0x000000000fffc000
28915 /* ==================================================================== */
28916 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC1" */
28917 /* privilege vector for acc=1 */
28918 /* ==================================================================== */
28920 #define SH_MD_DQLP_MMR_DIR_PRIVEC1 0x0000000100030310
28921 #define SH_MD_DQLP_MMR_DIR_PRIVEC1_MASK 0x000000000fffffff
28922 #define SH_MD_DQLP_MMR_DIR_PRIVEC1_INIT 0x0000000000000000
28924 /* SH_MD_DQLP_MMR_DIR_PRIVEC1_IN */
28925 /* Description: in partition privileges, locvec bit=1 */
28926 #define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_SHFT 0
28927 #define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_MASK 0x0000000000003fff
28929 /* SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT */
28930 /* Description: out of partition privileges, locvec bit=0 */
28931 #define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_SHFT 14
28932 #define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_MASK 0x000000000fffc000
28934 /* ==================================================================== */
28935 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC2" */
28936 /* privilege vector for acc=2 */
28937 /* ==================================================================== */
28939 #define SH_MD_DQLP_MMR_DIR_PRIVEC2 0x0000000100030320
28940 #define SH_MD_DQLP_MMR_DIR_PRIVEC2_MASK 0x000000000fffffff
28941 #define SH_MD_DQLP_MMR_DIR_PRIVEC2_INIT 0x0000000000000000
28943 /* SH_MD_DQLP_MMR_DIR_PRIVEC2_IN */
28944 /* Description: in partition privileges, locvec bit=1 */
28945 #define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_SHFT 0
28946 #define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_MASK 0x0000000000003fff
28948 /* SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT */
28949 /* Description: out of partition privileges, locvec bit=0 */
28950 #define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_SHFT 14
28951 #define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_MASK 0x000000000fffc000
28953 /* ==================================================================== */
28954 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC3" */
28955 /* privilege vector for acc=3 */
28956 /* ==================================================================== */
28958 #define SH_MD_DQLP_MMR_DIR_PRIVEC3 0x0000000100030330
28959 #define SH_MD_DQLP_MMR_DIR_PRIVEC3_MASK 0x000000000fffffff
28960 #define SH_MD_DQLP_MMR_DIR_PRIVEC3_INIT 0x0000000000000000
28962 /* SH_MD_DQLP_MMR_DIR_PRIVEC3_IN */
28963 /* Description: in partition privileges, locvec bit=1 */
28964 #define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_SHFT 0
28965 #define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_MASK 0x0000000000003fff
28967 /* SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT */
28968 /* Description: out of partition privileges, locvec bit=0 */
28969 #define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_SHFT 14
28970 #define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_MASK 0x000000000fffc000
28972 /* ==================================================================== */
28973 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC4" */
28974 /* privilege vector for acc=4 */
28975 /* ==================================================================== */
28977 #define SH_MD_DQLP_MMR_DIR_PRIVEC4 0x0000000100030340
28978 #define SH_MD_DQLP_MMR_DIR_PRIVEC4_MASK 0x000000000fffffff
28979 #define SH_MD_DQLP_MMR_DIR_PRIVEC4_INIT 0x0000000000000000
28981 /* SH_MD_DQLP_MMR_DIR_PRIVEC4_IN */
28982 /* Description: in partition privileges, locvec bit=1 */
28983 #define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_SHFT 0
28984 #define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_MASK 0x0000000000003fff
28986 /* SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT */
28987 /* Description: out of partition privileges, locvec bit=0 */
28988 #define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_SHFT 14
28989 #define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_MASK 0x000000000fffc000
28991 /* ==================================================================== */
28992 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC5" */
28993 /* privilege vector for acc=5 */
28994 /* ==================================================================== */
28996 #define SH_MD_DQLP_MMR_DIR_PRIVEC5 0x0000000100030350
28997 #define SH_MD_DQLP_MMR_DIR_PRIVEC5_MASK 0x000000000fffffff
28998 #define SH_MD_DQLP_MMR_DIR_PRIVEC5_INIT 0x0000000000000000
29000 /* SH_MD_DQLP_MMR_DIR_PRIVEC5_IN */
29001 /* Description: in partition privileges, locvec bit=1 */
29002 #define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_SHFT 0
29003 #define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_MASK 0x0000000000003fff
29005 /* SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT */
29006 /* Description: out of partition privileges, locvec bit=0 */
29007 #define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_SHFT 14
29008 #define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_MASK 0x000000000fffc000
29010 /* ==================================================================== */
29011 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC6" */
29012 /* privilege vector for acc=6 */
29013 /* ==================================================================== */
29015 #define SH_MD_DQLP_MMR_DIR_PRIVEC6 0x0000000100030360
29016 #define SH_MD_DQLP_MMR_DIR_PRIVEC6_MASK 0x000000000fffffff
29017 #define SH_MD_DQLP_MMR_DIR_PRIVEC6_INIT 0x0000000000000000
29019 /* SH_MD_DQLP_MMR_DIR_PRIVEC6_IN */
29020 /* Description: in partition privileges, locvec bit=1 */
29021 #define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_SHFT 0
29022 #define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_MASK 0x0000000000003fff
29024 /* SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT */
29025 /* Description: out of partition privileges, locvec bit=0 */
29026 #define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_SHFT 14
29027 #define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_MASK 0x000000000fffc000
29029 /* ==================================================================== */
29030 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC7" */
29031 /* privilege vector for acc=7 */
29032 /* ==================================================================== */
29034 #define SH_MD_DQLP_MMR_DIR_PRIVEC7 0x0000000100030370
29035 #define SH_MD_DQLP_MMR_DIR_PRIVEC7_MASK 0x000000000fffffff
29036 #define SH_MD_DQLP_MMR_DIR_PRIVEC7_INIT 0x0000000000000000
29038 /* SH_MD_DQLP_MMR_DIR_PRIVEC7_IN */
29039 /* Description: in partition privileges, locvec bit=1 */
29040 #define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_SHFT 0
29041 #define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_MASK 0x0000000000003fff
29043 /* SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT */
29044 /* Description: out of partition privileges, locvec bit=0 */
29045 #define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_SHFT 14
29046 #define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_MASK 0x000000000fffc000
29048 /* ==================================================================== */
29049 /* Register "SH_MD_DQLP_MMR_DIR_TIMER" */
29050 /* MD SXRO timer */
29051 /* ==================================================================== */
29053 #define SH_MD_DQLP_MMR_DIR_TIMER 0x0000000100030400
29054 #define SH_MD_DQLP_MMR_DIR_TIMER_MASK 0x00000000003fffff
29055 #define SH_MD_DQLP_MMR_DIR_TIMER_INIT 0x0000000000000000
29057 /* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV */
29058 /* Description: timer divide register */
29059 #define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_SHFT 0
29060 #define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_MASK 0x0000000000000fff
29062 /* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN */
29063 /* Description: timer enable */
29064 #define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_SHFT 12
29065 #define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_MASK 0x0000000000001000
29067 /* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR */
29068 /* Description: value of current timer */
29069 #define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_SHFT 13
29070 #define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_MASK 0x00000000003fe000
29072 /* ==================================================================== */
29073 /* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY" */
29074 /* directory pio write data */
29075 /* ==================================================================== */
29077 #define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY 0x0000000100031000
29078 #define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_MASK 0x03ffffffffffffff
29079 #define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_INIT 0x0000000000000000
29081 /* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA */
29082 /* Description: directory entry A */
29083 #define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0
29084 #define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff
29086 /* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB */
29087 /* Description: directory entry B */
29088 #define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26
29089 #define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000
29091 /* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI */
29092 /* Description: directory priority */
29093 #define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT 52
29094 #define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_MASK 0x0070000000000000
29096 /* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC */
29097 /* Description: directory access bits */
29098 #define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT 55
29099 #define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_MASK 0x0380000000000000
29101 /* ==================================================================== */
29102 /* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC" */
29103 /* directory ecc register */
29104 /* ==================================================================== */
29106 #define SH_MD_DQLP_MMR_PIOWD_DIR_ECC 0x0000000100031010
29107 #define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_MASK 0x0000000000003fff
29108 #define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_INIT 0x0000000000000000
29110 /* SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA */
29111 /* Description: XOR bits for directory ECC group 1 */
29112 #define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_SHFT 0
29113 #define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_MASK 0x000000000000007f
29115 /* SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB */
29116 /* Description: XOR bits for directory ECC group 2 */
29117 #define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_SHFT 7
29118 #define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_MASK 0x0000000000003f80
29120 /* ==================================================================== */
29121 /* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY" */
29122 /* x directory pio read data */
29123 /* ==================================================================== */
29125 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY 0x0000000100032000
29126 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_MASK 0x0fffffffffffffff
29127 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_INIT 0x0000000000000000
29129 /* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA */
29130 /* Description: directory entry A */
29131 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0
29132 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
29134 /* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB */
29135 /* Description: directory entry B */
29136 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26
29137 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
29139 /* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI */
29140 /* Description: directory priority */
29141 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52
29142 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000
29144 /* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC */
29145 /* Description: directory access bits */
29146 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55
29147 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000
29149 /* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR */
29150 /* Description: correctable ecc error */
29151 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58
29152 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000
29154 /* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC */
29155 /* Description: uncorrectable ecc error */
29156 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59
29157 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000
29159 /* ==================================================================== */
29160 /* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC" */
29161 /* x directory ecc */
29162 /* ==================================================================== */
29164 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC 0x0000000100032010
29165 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_MASK 0x0000000000003fff
29166 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_INIT 0x0000000000000000
29168 /* SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA */
29169 /* Description: group 1 ecc */
29170 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0
29171 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f
29173 /* SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB */
29174 /* Description: group 2 ecc */
29175 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7
29176 #define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80
29178 /* ==================================================================== */
29179 /* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY" */
29180 /* y directory pio read data */
29181 /* ==================================================================== */
29183 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY 0x0000000100032800
29184 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_MASK 0x0fffffffffffffff
29185 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_INIT 0x0000000000000000
29187 /* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA */
29188 /* Description: directory entry A */
29189 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0
29190 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
29192 /* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB */
29193 /* Description: directory entry B */
29194 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26
29195 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
29197 /* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI */
29198 /* Description: directory priority */
29199 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52
29200 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000
29202 /* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC */
29203 /* Description: directory access bits */
29204 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55
29205 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000
29207 /* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR */
29208 /* Description: correctable ecc error */
29209 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58
29210 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000
29212 /* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC */
29213 /* Description: uncorrectable ecc error */
29214 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59
29215 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000
29217 /* ==================================================================== */
29218 /* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC" */
29219 /* y directory ecc */
29220 /* ==================================================================== */
29222 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC 0x0000000100032810
29223 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_MASK 0x0000000000003fff
29224 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_INIT 0x0000000000000000
29226 /* SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA */
29227 /* Description: group 1 ecc */
29228 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0
29229 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f
29231 /* SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB */
29232 /* Description: group 2 ecc */
29233 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7
29234 #define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80
29236 /* ==================================================================== */
29237 /* Register "SH_MD_DQLP_MMR_XCERR1" */
29238 /* correctable dir ecc group 1 error register */
29239 /* ==================================================================== */
29241 #define SH_MD_DQLP_MMR_XCERR1 0x0000000100033000
29242 #define SH_MD_DQLP_MMR_XCERR1_MASK 0x0000007fffffffff
29243 #define SH_MD_DQLP_MMR_XCERR1_INIT 0x0000000000000000
29245 /* SH_MD_DQLP_MMR_XCERR1_GRP1 */
29246 /* Description: ecc group 1 bits */
29247 #define SH_MD_DQLP_MMR_XCERR1_GRP1_SHFT 0
29248 #define SH_MD_DQLP_MMR_XCERR1_GRP1_MASK 0x0000000fffffffff
29250 /* SH_MD_DQLP_MMR_XCERR1_VAL */
29251 /* Description: correctable ecc error in group 1 bits */
29252 #define SH_MD_DQLP_MMR_XCERR1_VAL_SHFT 36
29253 #define SH_MD_DQLP_MMR_XCERR1_VAL_MASK 0x0000001000000000
29255 /* SH_MD_DQLP_MMR_XCERR1_MORE */
29256 /* Description: more than one correctable ecc error in group 1 */
29257 #define SH_MD_DQLP_MMR_XCERR1_MORE_SHFT 37
29258 #define SH_MD_DQLP_MMR_XCERR1_MORE_MASK 0x0000002000000000
29260 /* SH_MD_DQLP_MMR_XCERR1_ARM */
29261 /* Description: writing 1 arms uncorrectable ecc error capture */
29262 #define SH_MD_DQLP_MMR_XCERR1_ARM_SHFT 38
29263 #define SH_MD_DQLP_MMR_XCERR1_ARM_MASK 0x0000004000000000
29265 /* ==================================================================== */
29266 /* Register "SH_MD_DQLP_MMR_XCERR2" */
29267 /* correctable dir ecc group 2 error register */
29268 /* ==================================================================== */
29270 #define SH_MD_DQLP_MMR_XCERR2 0x0000000100033010
29271 #define SH_MD_DQLP_MMR_XCERR2_MASK 0x0000003fffffffff
29272 #define SH_MD_DQLP_MMR_XCERR2_INIT 0x0000000000000000
29274 /* SH_MD_DQLP_MMR_XCERR2_GRP2 */
29275 /* Description: ecc group 2 bits */
29276 #define SH_MD_DQLP_MMR_XCERR2_GRP2_SHFT 0
29277 #define SH_MD_DQLP_MMR_XCERR2_GRP2_MASK 0x0000000fffffffff
29279 /* SH_MD_DQLP_MMR_XCERR2_VAL */
29280 /* Description: correctable ecc error in group 2 bits */
29281 #define SH_MD_DQLP_MMR_XCERR2_VAL_SHFT 36
29282 #define SH_MD_DQLP_MMR_XCERR2_VAL_MASK 0x0000001000000000
29284 /* SH_MD_DQLP_MMR_XCERR2_MORE */
29285 /* Description: more than one correctable ecc error in group 2 */
29286 #define SH_MD_DQLP_MMR_XCERR2_MORE_SHFT 37
29287 #define SH_MD_DQLP_MMR_XCERR2_MORE_MASK 0x0000002000000000
29289 /* ==================================================================== */
29290 /* Register "SH_MD_DQLP_MMR_XUERR1" */
29291 /* uncorrectable dir ecc group 1 error register */
29292 /* ==================================================================== */
29294 #define SH_MD_DQLP_MMR_XUERR1 0x0000000100033020
29295 #define SH_MD_DQLP_MMR_XUERR1_MASK 0x0000007fffffffff
29296 #define SH_MD_DQLP_MMR_XUERR1_INIT 0x0000000000000000
29298 /* SH_MD_DQLP_MMR_XUERR1_GRP1 */
29299 /* Description: ecc group 1 bits */
29300 #define SH_MD_DQLP_MMR_XUERR1_GRP1_SHFT 0
29301 #define SH_MD_DQLP_MMR_XUERR1_GRP1_MASK 0x0000000fffffffff
29303 /* SH_MD_DQLP_MMR_XUERR1_VAL */
29304 /* Description: uncorrectable ecc error in group 1 bits */
29305 #define SH_MD_DQLP_MMR_XUERR1_VAL_SHFT 36
29306 #define SH_MD_DQLP_MMR_XUERR1_VAL_MASK 0x0000001000000000
29308 /* SH_MD_DQLP_MMR_XUERR1_MORE */
29309 /* Description: more than one uncorrectable ecc error in group 1 */
29310 #define SH_MD_DQLP_MMR_XUERR1_MORE_SHFT 37
29311 #define SH_MD_DQLP_MMR_XUERR1_MORE_MASK 0x0000002000000000
29313 /* SH_MD_DQLP_MMR_XUERR1_ARM */
29314 /* Description: writing 1 arms uncorrectable ecc error capture */
29315 #define SH_MD_DQLP_MMR_XUERR1_ARM_SHFT 38
29316 #define SH_MD_DQLP_MMR_XUERR1_ARM_MASK 0x0000004000000000
29318 /* ==================================================================== */
29319 /* Register "SH_MD_DQLP_MMR_XUERR2" */
29320 /* uncorrectable dir ecc group 2 error register */
29321 /* ==================================================================== */
29323 #define SH_MD_DQLP_MMR_XUERR2 0x0000000100033030
29324 #define SH_MD_DQLP_MMR_XUERR2_MASK 0x0000003fffffffff
29325 #define SH_MD_DQLP_MMR_XUERR2_INIT 0x0000000000000000
29327 /* SH_MD_DQLP_MMR_XUERR2_GRP2 */
29328 /* Description: ecc group 2 bits */
29329 #define SH_MD_DQLP_MMR_XUERR2_GRP2_SHFT 0
29330 #define SH_MD_DQLP_MMR_XUERR2_GRP2_MASK 0x0000000fffffffff
29332 /* SH_MD_DQLP_MMR_XUERR2_VAL */
29333 /* Description: uncorrectable ecc error in group 2 bits */
29334 #define SH_MD_DQLP_MMR_XUERR2_VAL_SHFT 36
29335 #define SH_MD_DQLP_MMR_XUERR2_VAL_MASK 0x0000001000000000
29337 /* SH_MD_DQLP_MMR_XUERR2_MORE */
29338 /* Description: more than one uncorrectable ecc error in group 2 */
29339 #define SH_MD_DQLP_MMR_XUERR2_MORE_SHFT 37
29340 #define SH_MD_DQLP_MMR_XUERR2_MORE_MASK 0x0000002000000000
29342 /* ==================================================================== */
29343 /* Register "SH_MD_DQLP_MMR_XPERR" */
29344 /* protocol error register */
29345 /* ==================================================================== */
29347 #define SH_MD_DQLP_MMR_XPERR 0x0000000100033040
29348 #define SH_MD_DQLP_MMR_XPERR_MASK 0x7fffffffffffffff
29349 #define SH_MD_DQLP_MMR_XPERR_INIT 0x0000000000000000
29351 /* SH_MD_DQLP_MMR_XPERR_DIR */
29352 /* Description: directory entry */
29353 #define SH_MD_DQLP_MMR_XPERR_DIR_SHFT 0
29354 #define SH_MD_DQLP_MMR_XPERR_DIR_MASK 0x0000000003ffffff
29356 /* SH_MD_DQLP_MMR_XPERR_CMD */
29357 /* Description: incoming command */
29358 #define SH_MD_DQLP_MMR_XPERR_CMD_SHFT 26
29359 #define SH_MD_DQLP_MMR_XPERR_CMD_MASK 0x00000003fc000000
29361 /* SH_MD_DQLP_MMR_XPERR_SRC */
29362 /* Description: source node of dir operation */
29363 #define SH_MD_DQLP_MMR_XPERR_SRC_SHFT 34
29364 #define SH_MD_DQLP_MMR_XPERR_SRC_MASK 0x0000fffc00000000
29366 /* SH_MD_DQLP_MMR_XPERR_PRIGE */
29367 /* Description: priority was greater-equal */
29368 #define SH_MD_DQLP_MMR_XPERR_PRIGE_SHFT 48
29369 #define SH_MD_DQLP_MMR_XPERR_PRIGE_MASK 0x0001000000000000
29371 /* SH_MD_DQLP_MMR_XPERR_PRIV */
29372 /* Description: access privilege bit */
29373 #define SH_MD_DQLP_MMR_XPERR_PRIV_SHFT 49
29374 #define SH_MD_DQLP_MMR_XPERR_PRIV_MASK 0x0002000000000000
29376 /* SH_MD_DQLP_MMR_XPERR_COR */
29377 /* Description: correctable ecc error */
29378 #define SH_MD_DQLP_MMR_XPERR_COR_SHFT 50
29379 #define SH_MD_DQLP_MMR_XPERR_COR_MASK 0x0004000000000000
29381 /* SH_MD_DQLP_MMR_XPERR_UNC */
29382 /* Description: uncorrectable ecc error */
29383 #define SH_MD_DQLP_MMR_XPERR_UNC_SHFT 51
29384 #define SH_MD_DQLP_MMR_XPERR_UNC_MASK 0x0008000000000000
29386 /* SH_MD_DQLP_MMR_XPERR_MYBIT */
29387 /* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */
29388 #define SH_MD_DQLP_MMR_XPERR_MYBIT_SHFT 52
29389 #define SH_MD_DQLP_MMR_XPERR_MYBIT_MASK 0x0ff0000000000000
29391 /* SH_MD_DQLP_MMR_XPERR_VAL */
29392 /* Description: protocol error info valid */
29393 #define SH_MD_DQLP_MMR_XPERR_VAL_SHFT 60
29394 #define SH_MD_DQLP_MMR_XPERR_VAL_MASK 0x1000000000000000
29396 /* SH_MD_DQLP_MMR_XPERR_MORE */
29397 /* Description: more than one protocol error */
29398 #define SH_MD_DQLP_MMR_XPERR_MORE_SHFT 61
29399 #define SH_MD_DQLP_MMR_XPERR_MORE_MASK 0x2000000000000000
29401 /* SH_MD_DQLP_MMR_XPERR_ARM */
29402 /* Description: writing 1 arms error capture */
29403 #define SH_MD_DQLP_MMR_XPERR_ARM_SHFT 62
29404 #define SH_MD_DQLP_MMR_XPERR_ARM_MASK 0x4000000000000000
29406 /* ==================================================================== */
29407 /* Register "SH_MD_DQLP_MMR_YCERR1" */
29408 /* correctable dir ecc group 1 error register */
29409 /* ==================================================================== */
29411 #define SH_MD_DQLP_MMR_YCERR1 0x0000000100033800
29412 #define SH_MD_DQLP_MMR_YCERR1_MASK 0x0000007fffffffff
29413 #define SH_MD_DQLP_MMR_YCERR1_INIT 0x0000000000000000
29415 /* SH_MD_DQLP_MMR_YCERR1_GRP1 */
29416 /* Description: ecc group 1 bits */
29417 #define SH_MD_DQLP_MMR_YCERR1_GRP1_SHFT 0
29418 #define SH_MD_DQLP_MMR_YCERR1_GRP1_MASK 0x0000000fffffffff
29420 /* SH_MD_DQLP_MMR_YCERR1_VAL */
29421 /* Description: correctable ecc error in group 1 bits */
29422 #define SH_MD_DQLP_MMR_YCERR1_VAL_SHFT 36
29423 #define SH_MD_DQLP_MMR_YCERR1_VAL_MASK 0x0000001000000000
29425 /* SH_MD_DQLP_MMR_YCERR1_MORE */
29426 /* Description: more than one correctable ecc error in group 1 */
29427 #define SH_MD_DQLP_MMR_YCERR1_MORE_SHFT 37
29428 #define SH_MD_DQLP_MMR_YCERR1_MORE_MASK 0x0000002000000000
29430 /* SH_MD_DQLP_MMR_YCERR1_ARM */
29431 /* Description: writing 1 arms uncorrectable ecc error capture */
29432 #define SH_MD_DQLP_MMR_YCERR1_ARM_SHFT 38
29433 #define SH_MD_DQLP_MMR_YCERR1_ARM_MASK 0x0000004000000000
29435 /* ==================================================================== */
29436 /* Register "SH_MD_DQLP_MMR_YCERR2" */
29437 /* correctable dir ecc group 2 error register */
29438 /* ==================================================================== */
29440 #define SH_MD_DQLP_MMR_YCERR2 0x0000000100033810
29441 #define SH_MD_DQLP_MMR_YCERR2_MASK 0x0000003fffffffff
29442 #define SH_MD_DQLP_MMR_YCERR2_INIT 0x0000000000000000
29444 /* SH_MD_DQLP_MMR_YCERR2_GRP2 */
29445 /* Description: ecc group 2 bits */
29446 #define SH_MD_DQLP_MMR_YCERR2_GRP2_SHFT 0
29447 #define SH_MD_DQLP_MMR_YCERR2_GRP2_MASK 0x0000000fffffffff
29449 /* SH_MD_DQLP_MMR_YCERR2_VAL */
29450 /* Description: correctable ecc error in group 2 bits */
29451 #define SH_MD_DQLP_MMR_YCERR2_VAL_SHFT 36
29452 #define SH_MD_DQLP_MMR_YCERR2_VAL_MASK 0x0000001000000000
29454 /* SH_MD_DQLP_MMR_YCERR2_MORE */
29455 /* Description: more than one correctable ecc error in group 2 */
29456 #define SH_MD_DQLP_MMR_YCERR2_MORE_SHFT 37
29457 #define SH_MD_DQLP_MMR_YCERR2_MORE_MASK 0x0000002000000000
29459 /* ==================================================================== */
29460 /* Register "SH_MD_DQLP_MMR_YUERR1" */
29461 /* uncorrectable dir ecc group 1 error register */
29462 /* ==================================================================== */
29464 #define SH_MD_DQLP_MMR_YUERR1 0x0000000100033820
29465 #define SH_MD_DQLP_MMR_YUERR1_MASK 0x0000007fffffffff
29466 #define SH_MD_DQLP_MMR_YUERR1_INIT 0x0000000000000000
29468 /* SH_MD_DQLP_MMR_YUERR1_GRP1 */
29469 /* Description: ecc group 1 bits */
29470 #define SH_MD_DQLP_MMR_YUERR1_GRP1_SHFT 0
29471 #define SH_MD_DQLP_MMR_YUERR1_GRP1_MASK 0x0000000fffffffff
29473 /* SH_MD_DQLP_MMR_YUERR1_VAL */
29474 /* Description: uncorrectable ecc error in group 1 bits */
29475 #define SH_MD_DQLP_MMR_YUERR1_VAL_SHFT 36
29476 #define SH_MD_DQLP_MMR_YUERR1_VAL_MASK 0x0000001000000000
29478 /* SH_MD_DQLP_MMR_YUERR1_MORE */
29479 /* Description: more than one uncorrectable ecc error in group 1 */
29480 #define SH_MD_DQLP_MMR_YUERR1_MORE_SHFT 37
29481 #define SH_MD_DQLP_MMR_YUERR1_MORE_MASK 0x0000002000000000
29483 /* SH_MD_DQLP_MMR_YUERR1_ARM */
29484 /* Description: writing 1 arms uncorrectable ecc error capture */
29485 #define SH_MD_DQLP_MMR_YUERR1_ARM_SHFT 38
29486 #define SH_MD_DQLP_MMR_YUERR1_ARM_MASK 0x0000004000000000
29488 /* ==================================================================== */
29489 /* Register "SH_MD_DQLP_MMR_YUERR2" */
29490 /* uncorrectable dir ecc group 2 error register */
29491 /* ==================================================================== */
29493 #define SH_MD_DQLP_MMR_YUERR2 0x0000000100033830
29494 #define SH_MD_DQLP_MMR_YUERR2_MASK 0x0000003fffffffff
29495 #define SH_MD_DQLP_MMR_YUERR2_INIT 0x0000000000000000
29497 /* SH_MD_DQLP_MMR_YUERR2_GRP2 */
29498 /* Description: ecc group 2 bits */
29499 #define SH_MD_DQLP_MMR_YUERR2_GRP2_SHFT 0
29500 #define SH_MD_DQLP_MMR_YUERR2_GRP2_MASK 0x0000000fffffffff
29502 /* SH_MD_DQLP_MMR_YUERR2_VAL */
29503 /* Description: uncorrectable ecc error in group 2 bits */
29504 #define SH_MD_DQLP_MMR_YUERR2_VAL_SHFT 36
29505 #define SH_MD_DQLP_MMR_YUERR2_VAL_MASK 0x0000001000000000
29507 /* SH_MD_DQLP_MMR_YUERR2_MORE */
29508 /* Description: more than one uncorrectable ecc error in group 2 */
29509 #define SH_MD_DQLP_MMR_YUERR2_MORE_SHFT 37
29510 #define SH_MD_DQLP_MMR_YUERR2_MORE_MASK 0x0000002000000000
29512 /* ==================================================================== */
29513 /* Register "SH_MD_DQLP_MMR_YPERR" */
29514 /* protocol error register */
29515 /* ==================================================================== */
29517 #define SH_MD_DQLP_MMR_YPERR 0x0000000100033840
29518 #define SH_MD_DQLP_MMR_YPERR_MASK 0x7fffffffffffffff
29519 #define SH_MD_DQLP_MMR_YPERR_INIT 0x0000000000000000
29521 /* SH_MD_DQLP_MMR_YPERR_DIR */
29522 /* Description: directory entry */
29523 #define SH_MD_DQLP_MMR_YPERR_DIR_SHFT 0
29524 #define SH_MD_DQLP_MMR_YPERR_DIR_MASK 0x0000000003ffffff
29526 /* SH_MD_DQLP_MMR_YPERR_CMD */
29527 /* Description: incoming command */
29528 #define SH_MD_DQLP_MMR_YPERR_CMD_SHFT 26
29529 #define SH_MD_DQLP_MMR_YPERR_CMD_MASK 0x00000003fc000000
29531 /* SH_MD_DQLP_MMR_YPERR_SRC */
29532 /* Description: source node of dir operation */
29533 #define SH_MD_DQLP_MMR_YPERR_SRC_SHFT 34
29534 #define SH_MD_DQLP_MMR_YPERR_SRC_MASK 0x0000fffc00000000
29536 /* SH_MD_DQLP_MMR_YPERR_PRIGE */
29537 /* Description: priority was greater-equal */
29538 #define SH_MD_DQLP_MMR_YPERR_PRIGE_SHFT 48
29539 #define SH_MD_DQLP_MMR_YPERR_PRIGE_MASK 0x0001000000000000
29541 /* SH_MD_DQLP_MMR_YPERR_PRIV */
29542 /* Description: access privilege bit */
29543 #define SH_MD_DQLP_MMR_YPERR_PRIV_SHFT 49
29544 #define SH_MD_DQLP_MMR_YPERR_PRIV_MASK 0x0002000000000000
29546 /* SH_MD_DQLP_MMR_YPERR_COR */
29547 /* Description: correctable ecc error */
29548 #define SH_MD_DQLP_MMR_YPERR_COR_SHFT 50
29549 #define SH_MD_DQLP_MMR_YPERR_COR_MASK 0x0004000000000000
29551 /* SH_MD_DQLP_MMR_YPERR_UNC */
29552 /* Description: uncorrectable ecc error */
29553 #define SH_MD_DQLP_MMR_YPERR_UNC_SHFT 51
29554 #define SH_MD_DQLP_MMR_YPERR_UNC_MASK 0x0008000000000000
29556 /* SH_MD_DQLP_MMR_YPERR_MYBIT */
29557 /* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */
29558 #define SH_MD_DQLP_MMR_YPERR_MYBIT_SHFT 52
29559 #define SH_MD_DQLP_MMR_YPERR_MYBIT_MASK 0x0ff0000000000000
29561 /* SH_MD_DQLP_MMR_YPERR_VAL */
29562 /* Description: protocol error info valid */
29563 #define SH_MD_DQLP_MMR_YPERR_VAL_SHFT 60
29564 #define SH_MD_DQLP_MMR_YPERR_VAL_MASK 0x1000000000000000
29566 /* SH_MD_DQLP_MMR_YPERR_MORE */
29567 /* Description: more than one protocol error */
29568 #define SH_MD_DQLP_MMR_YPERR_MORE_SHFT 61
29569 #define SH_MD_DQLP_MMR_YPERR_MORE_MASK 0x2000000000000000
29571 /* SH_MD_DQLP_MMR_YPERR_ARM */
29572 /* Description: writing 1 arms error capture */
29573 #define SH_MD_DQLP_MMR_YPERR_ARM_SHFT 62
29574 #define SH_MD_DQLP_MMR_YPERR_ARM_MASK 0x4000000000000000
29576 /* ==================================================================== */
29577 /* Register "SH_MD_DQLP_MMR_DIR_CMDTRIG" */
29579 /* ==================================================================== */
29581 #define SH_MD_DQLP_MMR_DIR_CMDTRIG 0x0000000100034000
29582 #define SH_MD_DQLP_MMR_DIR_CMDTRIG_MASK 0x00000000ffffffff
29583 #define SH_MD_DQLP_MMR_DIR_CMDTRIG_INIT 0x0000000000000000
29585 /* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0 */
29586 /* Description: command trigger 0 */
29587 #define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_SHFT 0
29588 #define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_MASK 0x00000000000000ff
29590 /* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1 */
29591 /* Description: command trigger 1 */
29592 #define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_SHFT 8
29593 #define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_MASK 0x000000000000ff00
29595 /* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2 */
29596 /* Description: command trigger 2 */
29597 #define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_SHFT 16
29598 #define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_MASK 0x0000000000ff0000
29600 /* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3 */
29601 /* Description: command trigger 3 */
29602 #define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_SHFT 24
29603 #define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_MASK 0x00000000ff000000
29605 /* ==================================================================== */
29606 /* Register "SH_MD_DQLP_MMR_DIR_TBLTRIG" */
29607 /* dir table trigger */
29608 /* ==================================================================== */
29610 #define SH_MD_DQLP_MMR_DIR_TBLTRIG 0x0000000100034010
29611 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_MASK 0x000003ffffffffff
29612 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_INIT 0x0000000000000000
29614 /* SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC */
29615 /* Description: source of request */
29616 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_SHFT 0
29617 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_MASK 0x0000000000003fff
29619 /* SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD */
29620 /* Description: incoming request */
29621 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_SHFT 14
29622 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_MASK 0x00000000003fc000
29624 /* SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC */
29625 /* Description: uncorrectable error, privilege bit */
29626 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_SHFT 22
29627 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_MASK 0x0000000000c00000
29629 /* SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE */
29630 /* Description: priority greater-equal */
29631 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_SHFT 24
29632 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_MASK 0x0000000001000000
29634 /* SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST */
29635 /* Description: shrd,sxro,sub-state */
29636 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_SHFT 25
29637 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_MASK 0x00000003fe000000
29639 /* SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT */
29640 /* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */
29641 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_SHFT 34
29642 #define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_MASK 0x000003fc00000000
29644 /* ==================================================================== */
29645 /* Register "SH_MD_DQLP_MMR_DIR_TBLMASK" */
29646 /* dir table trigger mask */
29647 /* ==================================================================== */
29649 #define SH_MD_DQLP_MMR_DIR_TBLMASK 0x0000000100034020
29650 #define SH_MD_DQLP_MMR_DIR_TBLMASK_MASK 0x000003ffffffffff
29651 #define SH_MD_DQLP_MMR_DIR_TBLMASK_INIT 0x0000000000000000
29653 /* SH_MD_DQLP_MMR_DIR_TBLMASK_SRC */
29654 /* Description: source of request */
29655 #define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_SHFT 0
29656 #define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_MASK 0x0000000000003fff
29658 /* SH_MD_DQLP_MMR_DIR_TBLMASK_CMD */
29659 /* Description: incoming request */
29660 #define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_SHFT 14
29661 #define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_MASK 0x00000000003fc000
29663 /* SH_MD_DQLP_MMR_DIR_TBLMASK_ACC */
29664 /* Description: uncorrectable error, privilege bit */
29665 #define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_SHFT 22
29666 #define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_MASK 0x0000000000c00000
29668 /* SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE */
29669 /* Description: priority greater-equal */
29670 #define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_SHFT 24
29671 #define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_MASK 0x0000000001000000
29673 /* SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST */
29674 /* Description: shrd,sxro,sub-state */
29675 #define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_SHFT 25
29676 #define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_MASK 0x00000003fe000000
29678 /* SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT */
29679 /* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */
29680 #define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_SHFT 34
29681 #define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_MASK 0x000003fc00000000
29683 /* ==================================================================== */
29684 /* Register "SH_MD_DQLP_MMR_XBIST_H" */
29685 /* rising edge bist/fill pattern */
29686 /* ==================================================================== */
29688 #define SH_MD_DQLP_MMR_XBIST_H 0x0000000100038000
29689 #define SH_MD_DQLP_MMR_XBIST_H_MASK 0x00000700ffffffff
29690 #define SH_MD_DQLP_MMR_XBIST_H_INIT 0x0000000000000000
29692 /* SH_MD_DQLP_MMR_XBIST_H_PAT */
29693 /* Description: data pattern */
29694 #define SH_MD_DQLP_MMR_XBIST_H_PAT_SHFT 0
29695 #define SH_MD_DQLP_MMR_XBIST_H_PAT_MASK 0x00000000ffffffff
29697 /* SH_MD_DQLP_MMR_XBIST_H_INV */
29698 /* Description: invert data pattern in next cycle */
29699 #define SH_MD_DQLP_MMR_XBIST_H_INV_SHFT 40
29700 #define SH_MD_DQLP_MMR_XBIST_H_INV_MASK 0x0000010000000000
29702 /* SH_MD_DQLP_MMR_XBIST_H_ROT */
29703 /* Description: rotate left data pattern in next cycle */
29704 #define SH_MD_DQLP_MMR_XBIST_H_ROT_SHFT 41
29705 #define SH_MD_DQLP_MMR_XBIST_H_ROT_MASK 0x0000020000000000
29707 /* SH_MD_DQLP_MMR_XBIST_H_ARM */
29708 /* Description: writing 1 arms data miscompare capture */
29709 #define SH_MD_DQLP_MMR_XBIST_H_ARM_SHFT 42
29710 #define SH_MD_DQLP_MMR_XBIST_H_ARM_MASK 0x0000040000000000
29712 /* ==================================================================== */
29713 /* Register "SH_MD_DQLP_MMR_XBIST_L" */
29714 /* falling edge bist/fill pattern */
29715 /* ==================================================================== */
29717 #define SH_MD_DQLP_MMR_XBIST_L 0x0000000100038010
29718 #define SH_MD_DQLP_MMR_XBIST_L_MASK 0x00000300ffffffff
29719 #define SH_MD_DQLP_MMR_XBIST_L_INIT 0x0000000000000000
29721 /* SH_MD_DQLP_MMR_XBIST_L_PAT */
29722 /* Description: data pattern */
29723 #define SH_MD_DQLP_MMR_XBIST_L_PAT_SHFT 0
29724 #define SH_MD_DQLP_MMR_XBIST_L_PAT_MASK 0x00000000ffffffff
29726 /* SH_MD_DQLP_MMR_XBIST_L_INV */
29727 /* Description: invert data pattern in next cycle */
29728 #define SH_MD_DQLP_MMR_XBIST_L_INV_SHFT 40
29729 #define SH_MD_DQLP_MMR_XBIST_L_INV_MASK 0x0000010000000000
29731 /* SH_MD_DQLP_MMR_XBIST_L_ROT */
29732 /* Description: rotate left data pattern in next cycle */
29733 #define SH_MD_DQLP_MMR_XBIST_L_ROT_SHFT 41
29734 #define SH_MD_DQLP_MMR_XBIST_L_ROT_MASK 0x0000020000000000
29736 /* ==================================================================== */
29737 /* Register "SH_MD_DQLP_MMR_XBIST_ERR_H" */
29738 /* rising edge bist error pattern */
29739 /* ==================================================================== */
29741 #define SH_MD_DQLP_MMR_XBIST_ERR_H 0x0000000100038020
29742 #define SH_MD_DQLP_MMR_XBIST_ERR_H_MASK 0x00000300ffffffff
29743 #define SH_MD_DQLP_MMR_XBIST_ERR_H_INIT 0x0000000000000000
29745 /* SH_MD_DQLP_MMR_XBIST_ERR_H_PAT */
29746 /* Description: data pattern */
29747 #define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_SHFT 0
29748 #define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_MASK 0x00000000ffffffff
29750 /* SH_MD_DQLP_MMR_XBIST_ERR_H_VAL */
29751 /* Description: bist data miscompare */
29752 #define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_SHFT 40
29753 #define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000
29755 /* SH_MD_DQLP_MMR_XBIST_ERR_H_MORE */
29756 /* Description: more than one bist data miscompare */
29757 #define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_SHFT 41
29758 #define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000
29760 /* ==================================================================== */
29761 /* Register "SH_MD_DQLP_MMR_XBIST_ERR_L" */
29762 /* falling edge bist error pattern */
29763 /* ==================================================================== */
29765 #define SH_MD_DQLP_MMR_XBIST_ERR_L 0x0000000100038030
29766 #define SH_MD_DQLP_MMR_XBIST_ERR_L_MASK 0x00000300ffffffff
29767 #define SH_MD_DQLP_MMR_XBIST_ERR_L_INIT 0x0000000000000000
29769 /* SH_MD_DQLP_MMR_XBIST_ERR_L_PAT */
29770 /* Description: data pattern */
29771 #define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_SHFT 0
29772 #define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_MASK 0x00000000ffffffff
29774 /* SH_MD_DQLP_MMR_XBIST_ERR_L_VAL */
29775 /* Description: bist data miscompare */
29776 #define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_SHFT 40
29777 #define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000
29779 /* SH_MD_DQLP_MMR_XBIST_ERR_L_MORE */
29780 /* Description: more than one bist data miscompare */
29781 #define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_SHFT 41
29782 #define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000
29784 /* ==================================================================== */
29785 /* Register "SH_MD_DQLP_MMR_YBIST_H" */
29786 /* rising edge bist/fill pattern */
29787 /* ==================================================================== */
29789 #define SH_MD_DQLP_MMR_YBIST_H 0x0000000100038800
29790 #define SH_MD_DQLP_MMR_YBIST_H_MASK 0x00000700ffffffff
29791 #define SH_MD_DQLP_MMR_YBIST_H_INIT 0x0000000000000000
29793 /* SH_MD_DQLP_MMR_YBIST_H_PAT */
29794 /* Description: data pattern */
29795 #define SH_MD_DQLP_MMR_YBIST_H_PAT_SHFT 0
29796 #define SH_MD_DQLP_MMR_YBIST_H_PAT_MASK 0x00000000ffffffff
29798 /* SH_MD_DQLP_MMR_YBIST_H_INV */
29799 /* Description: invert data pattern in next cycle */
29800 #define SH_MD_DQLP_MMR_YBIST_H_INV_SHFT 40
29801 #define SH_MD_DQLP_MMR_YBIST_H_INV_MASK 0x0000010000000000
29803 /* SH_MD_DQLP_MMR_YBIST_H_ROT */
29804 /* Description: rotate left data pattern in next cycle */
29805 #define SH_MD_DQLP_MMR_YBIST_H_ROT_SHFT 41
29806 #define SH_MD_DQLP_MMR_YBIST_H_ROT_MASK 0x0000020000000000
29808 /* SH_MD_DQLP_MMR_YBIST_H_ARM */
29809 /* Description: writing 1 arms data miscompare capture */
29810 #define SH_MD_DQLP_MMR_YBIST_H_ARM_SHFT 42
29811 #define SH_MD_DQLP_MMR_YBIST_H_ARM_MASK 0x0000040000000000
29813 /* ==================================================================== */
29814 /* Register "SH_MD_DQLP_MMR_YBIST_L" */
29815 /* falling edge bist/fill pattern */
29816 /* ==================================================================== */
29818 #define SH_MD_DQLP_MMR_YBIST_L 0x0000000100038810
29819 #define SH_MD_DQLP_MMR_YBIST_L_MASK 0x00000300ffffffff
29820 #define SH_MD_DQLP_MMR_YBIST_L_INIT 0x0000000000000000
29822 /* SH_MD_DQLP_MMR_YBIST_L_PAT */
29823 /* Description: data pattern */
29824 #define SH_MD_DQLP_MMR_YBIST_L_PAT_SHFT 0
29825 #define SH_MD_DQLP_MMR_YBIST_L_PAT_MASK 0x00000000ffffffff
29827 /* SH_MD_DQLP_MMR_YBIST_L_INV */
29828 /* Description: invert data pattern in next cycle */
29829 #define SH_MD_DQLP_MMR_YBIST_L_INV_SHFT 40
29830 #define SH_MD_DQLP_MMR_YBIST_L_INV_MASK 0x0000010000000000
29832 /* SH_MD_DQLP_MMR_YBIST_L_ROT */
29833 /* Description: rotate left data pattern in next cycle */
29834 #define SH_MD_DQLP_MMR_YBIST_L_ROT_SHFT 41
29835 #define SH_MD_DQLP_MMR_YBIST_L_ROT_MASK 0x0000020000000000
29837 /* ==================================================================== */
29838 /* Register "SH_MD_DQLP_MMR_YBIST_ERR_H" */
29839 /* rising edge bist error pattern */
29840 /* ==================================================================== */
29842 #define SH_MD_DQLP_MMR_YBIST_ERR_H 0x0000000100038820
29843 #define SH_MD_DQLP_MMR_YBIST_ERR_H_MASK 0x00000300ffffffff
29844 #define SH_MD_DQLP_MMR_YBIST_ERR_H_INIT 0x0000000000000000
29846 /* SH_MD_DQLP_MMR_YBIST_ERR_H_PAT */
29847 /* Description: data pattern */
29848 #define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_SHFT 0
29849 #define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_MASK 0x00000000ffffffff
29851 /* SH_MD_DQLP_MMR_YBIST_ERR_H_VAL */
29852 /* Description: bist data miscompare */
29853 #define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_SHFT 40
29854 #define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000
29856 /* SH_MD_DQLP_MMR_YBIST_ERR_H_MORE */
29857 /* Description: more than one bist data miscompare */
29858 #define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_SHFT 41
29859 #define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000
29861 /* ==================================================================== */
29862 /* Register "SH_MD_DQLP_MMR_YBIST_ERR_L" */
29863 /* falling edge bist error pattern */
29864 /* ==================================================================== */
29866 #define SH_MD_DQLP_MMR_YBIST_ERR_L 0x0000000100038830
29867 #define SH_MD_DQLP_MMR_YBIST_ERR_L_MASK 0x00000300ffffffff
29868 #define SH_MD_DQLP_MMR_YBIST_ERR_L_INIT 0x0000000000000000
29870 /* SH_MD_DQLP_MMR_YBIST_ERR_L_PAT */
29871 /* Description: data pattern */
29872 #define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_SHFT 0
29873 #define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_MASK 0x00000000ffffffff
29875 /* SH_MD_DQLP_MMR_YBIST_ERR_L_VAL */
29876 /* Description: bist data miscompare */
29877 #define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_SHFT 40
29878 #define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000
29880 /* SH_MD_DQLP_MMR_YBIST_ERR_L_MORE */
29881 /* Description: more than one bist data miscompare */
29882 #define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_SHFT 41
29883 #define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000
29885 /* ==================================================================== */
29886 /* Register "SH_MD_DQLS_MMR_XBIST_H" */
29887 /* rising edge bist/fill pattern */
29888 /* ==================================================================== */
29890 #define SH_MD_DQLS_MMR_XBIST_H 0x0000000100048000
29891 #define SH_MD_DQLS_MMR_XBIST_H_MASK 0x000007ffffffffff
29892 #define SH_MD_DQLS_MMR_XBIST_H_INIT 0x0000000000000000
29894 /* SH_MD_DQLS_MMR_XBIST_H_PAT */
29895 /* Description: data pattern */
29896 #define SH_MD_DQLS_MMR_XBIST_H_PAT_SHFT 0
29897 #define SH_MD_DQLS_MMR_XBIST_H_PAT_MASK 0x000000ffffffffff
29899 /* SH_MD_DQLS_MMR_XBIST_H_INV */
29900 /* Description: invert data pattern in next cycle */
29901 #define SH_MD_DQLS_MMR_XBIST_H_INV_SHFT 40
29902 #define SH_MD_DQLS_MMR_XBIST_H_INV_MASK 0x0000010000000000
29904 /* SH_MD_DQLS_MMR_XBIST_H_ROT */
29905 /* Description: rotate left data pattern in next cycle */
29906 #define SH_MD_DQLS_MMR_XBIST_H_ROT_SHFT 41
29907 #define SH_MD_DQLS_MMR_XBIST_H_ROT_MASK 0x0000020000000000
29909 /* SH_MD_DQLS_MMR_XBIST_H_ARM */
29910 /* Description: writing 1 arms data miscompare capture */
29911 #define SH_MD_DQLS_MMR_XBIST_H_ARM_SHFT 42
29912 #define SH_MD_DQLS_MMR_XBIST_H_ARM_MASK 0x0000040000000000
29914 /* ==================================================================== */
29915 /* Register "SH_MD_DQLS_MMR_XBIST_L" */
29916 /* falling edge bist/fill pattern */
29917 /* ==================================================================== */
29919 #define SH_MD_DQLS_MMR_XBIST_L 0x0000000100048010
29920 #define SH_MD_DQLS_MMR_XBIST_L_MASK 0x000003ffffffffff
29921 #define SH_MD_DQLS_MMR_XBIST_L_INIT 0x0000000000000000
29923 /* SH_MD_DQLS_MMR_XBIST_L_PAT */
29924 /* Description: data pattern */
29925 #define SH_MD_DQLS_MMR_XBIST_L_PAT_SHFT 0
29926 #define SH_MD_DQLS_MMR_XBIST_L_PAT_MASK 0x000000ffffffffff
29928 /* SH_MD_DQLS_MMR_XBIST_L_INV */
29929 /* Description: invert data pattern in next cycle */
29930 #define SH_MD_DQLS_MMR_XBIST_L_INV_SHFT 40
29931 #define SH_MD_DQLS_MMR_XBIST_L_INV_MASK 0x0000010000000000
29933 /* SH_MD_DQLS_MMR_XBIST_L_ROT */
29934 /* Description: rotate left data pattern in next cycle */
29935 #define SH_MD_DQLS_MMR_XBIST_L_ROT_SHFT 41
29936 #define SH_MD_DQLS_MMR_XBIST_L_ROT_MASK 0x0000020000000000
29938 /* ==================================================================== */
29939 /* Register "SH_MD_DQLS_MMR_XBIST_ERR_H" */
29940 /* rising edge bist error pattern */
29941 /* ==================================================================== */
29943 #define SH_MD_DQLS_MMR_XBIST_ERR_H 0x0000000100048020
29944 #define SH_MD_DQLS_MMR_XBIST_ERR_H_MASK 0x000003ffffffffff
29945 #define SH_MD_DQLS_MMR_XBIST_ERR_H_INIT 0x0000000000000000
29947 /* SH_MD_DQLS_MMR_XBIST_ERR_H_PAT */
29948 /* Description: data pattern */
29949 #define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_SHFT 0
29950 #define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_MASK 0x000000ffffffffff
29952 /* SH_MD_DQLS_MMR_XBIST_ERR_H_VAL */
29953 /* Description: bist data miscompare */
29954 #define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_SHFT 40
29955 #define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000
29957 /* SH_MD_DQLS_MMR_XBIST_ERR_H_MORE */
29958 /* Description: more than one bist data miscompare */
29959 #define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_SHFT 41
29960 #define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000
29962 /* ==================================================================== */
29963 /* Register "SH_MD_DQLS_MMR_XBIST_ERR_L" */
29964 /* falling edge bist error pattern */
29965 /* ==================================================================== */
29967 #define SH_MD_DQLS_MMR_XBIST_ERR_L 0x0000000100048030
29968 #define SH_MD_DQLS_MMR_XBIST_ERR_L_MASK 0x000003ffffffffff
29969 #define SH_MD_DQLS_MMR_XBIST_ERR_L_INIT 0x0000000000000000
29971 /* SH_MD_DQLS_MMR_XBIST_ERR_L_PAT */
29972 /* Description: data pattern */
29973 #define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_SHFT 0
29974 #define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_MASK 0x000000ffffffffff
29976 /* SH_MD_DQLS_MMR_XBIST_ERR_L_VAL */
29977 /* Description: bist data miscompare */
29978 #define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_SHFT 40
29979 #define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000
29981 /* SH_MD_DQLS_MMR_XBIST_ERR_L_MORE */
29982 /* Description: more than one bist data miscompare */
29983 #define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_SHFT 41
29984 #define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000
29986 /* ==================================================================== */
29987 /* Register "SH_MD_DQLS_MMR_YBIST_H" */
29988 /* rising edge bist/fill pattern */
29989 /* ==================================================================== */
29991 #define SH_MD_DQLS_MMR_YBIST_H 0x0000000100048800
29992 #define SH_MD_DQLS_MMR_YBIST_H_MASK 0x000007ffffffffff
29993 #define SH_MD_DQLS_MMR_YBIST_H_INIT 0x0000000000000000
29995 /* SH_MD_DQLS_MMR_YBIST_H_PAT */
29996 /* Description: data pattern */
29997 #define SH_MD_DQLS_MMR_YBIST_H_PAT_SHFT 0
29998 #define SH_MD_DQLS_MMR_YBIST_H_PAT_MASK 0x000000ffffffffff
30000 /* SH_MD_DQLS_MMR_YBIST_H_INV */
30001 /* Description: invert data pattern in next cycle */
30002 #define SH_MD_DQLS_MMR_YBIST_H_INV_SHFT 40
30003 #define SH_MD_DQLS_MMR_YBIST_H_INV_MASK 0x0000010000000000
30005 /* SH_MD_DQLS_MMR_YBIST_H_ROT */
30006 /* Description: rotate left data pattern in next cycle */
30007 #define SH_MD_DQLS_MMR_YBIST_H_ROT_SHFT 41
30008 #define SH_MD_DQLS_MMR_YBIST_H_ROT_MASK 0x0000020000000000
30010 /* SH_MD_DQLS_MMR_YBIST_H_ARM */
30011 /* Description: writing 1 arms data miscompare capture */
30012 #define SH_MD_DQLS_MMR_YBIST_H_ARM_SHFT 42
30013 #define SH_MD_DQLS_MMR_YBIST_H_ARM_MASK 0x0000040000000000
30015 /* ==================================================================== */
30016 /* Register "SH_MD_DQLS_MMR_YBIST_L" */
30017 /* falling edge bist/fill pattern */
30018 /* ==================================================================== */
30020 #define SH_MD_DQLS_MMR_YBIST_L 0x0000000100048810
30021 #define SH_MD_DQLS_MMR_YBIST_L_MASK 0x000003ffffffffff
30022 #define SH_MD_DQLS_MMR_YBIST_L_INIT 0x0000000000000000
30024 /* SH_MD_DQLS_MMR_YBIST_L_PAT */
30025 /* Description: data pattern */
30026 #define SH_MD_DQLS_MMR_YBIST_L_PAT_SHFT 0
30027 #define SH_MD_DQLS_MMR_YBIST_L_PAT_MASK 0x000000ffffffffff
30029 /* SH_MD_DQLS_MMR_YBIST_L_INV */
30030 /* Description: invert data pattern in next cycle */
30031 #define SH_MD_DQLS_MMR_YBIST_L_INV_SHFT 40
30032 #define SH_MD_DQLS_MMR_YBIST_L_INV_MASK 0x0000010000000000
30034 /* SH_MD_DQLS_MMR_YBIST_L_ROT */
30035 /* Description: rotate left data pattern in next cycle */
30036 #define SH_MD_DQLS_MMR_YBIST_L_ROT_SHFT 41
30037 #define SH_MD_DQLS_MMR_YBIST_L_ROT_MASK 0x0000020000000000
30039 /* ==================================================================== */
30040 /* Register "SH_MD_DQLS_MMR_YBIST_ERR_H" */
30041 /* rising edge bist error pattern */
30042 /* ==================================================================== */
30044 #define SH_MD_DQLS_MMR_YBIST_ERR_H 0x0000000100048820
30045 #define SH_MD_DQLS_MMR_YBIST_ERR_H_MASK 0x000003ffffffffff
30046 #define SH_MD_DQLS_MMR_YBIST_ERR_H_INIT 0x0000000000000000
30048 /* SH_MD_DQLS_MMR_YBIST_ERR_H_PAT */
30049 /* Description: data pattern */
30050 #define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_SHFT 0
30051 #define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_MASK 0x000000ffffffffff
30053 /* SH_MD_DQLS_MMR_YBIST_ERR_H_VAL */
30054 /* Description: bist data miscompare */
30055 #define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_SHFT 40
30056 #define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000
30058 /* SH_MD_DQLS_MMR_YBIST_ERR_H_MORE */
30059 /* Description: more than one bist data miscompare */
30060 #define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_SHFT 41
30061 #define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000
30063 /* ==================================================================== */
30064 /* Register "SH_MD_DQLS_MMR_YBIST_ERR_L" */
30065 /* falling edge bist error pattern */
30066 /* ==================================================================== */
30068 #define SH_MD_DQLS_MMR_YBIST_ERR_L 0x0000000100048830
30069 #define SH_MD_DQLS_MMR_YBIST_ERR_L_MASK 0x000003ffffffffff
30070 #define SH_MD_DQLS_MMR_YBIST_ERR_L_INIT 0x0000000000000000
30072 /* SH_MD_DQLS_MMR_YBIST_ERR_L_PAT */
30073 /* Description: data pattern */
30074 #define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_SHFT 0
30075 #define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_MASK 0x000000ffffffffff
30077 /* SH_MD_DQLS_MMR_YBIST_ERR_L_VAL */
30078 /* Description: bist data miscompare */
30079 #define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_SHFT 40
30080 #define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000
30082 /* SH_MD_DQLS_MMR_YBIST_ERR_L_MORE */
30083 /* Description: more than one bist data miscompare */
30084 #define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_SHFT 41
30085 #define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000
30087 /* ==================================================================== */
30088 /* Register "SH_MD_DQLS_MMR_JNR_DEBUG" */
30089 /* joiner/fct debug configuration */
30090 /* ==================================================================== */
30092 #define SH_MD_DQLS_MMR_JNR_DEBUG 0x0000000100049000
30093 #define SH_MD_DQLS_MMR_JNR_DEBUG_MASK 0x0000000000000003
30094 #define SH_MD_DQLS_MMR_JNR_DEBUG_INIT 0x0000000000000000
30096 /* SH_MD_DQLS_MMR_JNR_DEBUG_PX */
30097 /* Description: select 0=pi 1=xn side */
30098 #define SH_MD_DQLS_MMR_JNR_DEBUG_PX_SHFT 0
30099 #define SH_MD_DQLS_MMR_JNR_DEBUG_PX_MASK 0x0000000000000001
30101 /* SH_MD_DQLS_MMR_JNR_DEBUG_RW */
30102 /* Description: select 0=read 1=write side */
30103 #define SH_MD_DQLS_MMR_JNR_DEBUG_RW_SHFT 1
30104 #define SH_MD_DQLS_MMR_JNR_DEBUG_RW_MASK 0x0000000000000002
30106 /* ==================================================================== */
30107 /* Register "SH_MD_DQLS_MMR_XAMOPW_ERR" */
30108 /* amo/partial rmw ecc error register */
30109 /* ==================================================================== */
30111 #define SH_MD_DQLS_MMR_XAMOPW_ERR 0x000000010004a000
30112 #define SH_MD_DQLS_MMR_XAMOPW_ERR_MASK 0x0000000103ff03ff
30113 #define SH_MD_DQLS_MMR_XAMOPW_ERR_INIT 0x0000000000000000
30115 /* SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN */
30116 /* Description: store data syndrome */
30117 #define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_SHFT 0
30118 #define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_MASK 0x00000000000000ff
30120 /* SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR */
30121 /* Description: correctable ecc errror on store data */
30122 #define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_SHFT 8
30123 #define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_MASK 0x0000000000000100
30125 /* SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC */
30126 /* Description: uncorrectable ecc errror on store data */
30127 #define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_SHFT 9
30128 #define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_MASK 0x0000000000000200
30130 /* SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN */
30131 /* Description: memory read data syndrome */
30132 #define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_SHFT 16
30133 #define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_MASK 0x0000000000ff0000
30135 /* SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR */
30136 /* Description: correctable ecc errror on read data */
30137 #define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_SHFT 24
30138 #define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_MASK 0x0000000001000000
30140 /* SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC */
30141 /* Description: uncorrectable ecc errror on read data */
30142 #define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_SHFT 25
30143 #define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_MASK 0x0000000002000000
30145 /* SH_MD_DQLS_MMR_XAMOPW_ERR_ARM */
30146 /* Description: writing 1 arms ecc error capture */
30147 #define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_SHFT 32
30148 #define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_MASK 0x0000000100000000
30150 /* ==================================================================== */
30151 /* Register "SH_MD_DQRP_MMR_DIR_CONFIG" */
30152 /* DQ directory config register */
30153 /* ==================================================================== */
30155 #define SH_MD_DQRP_MMR_DIR_CONFIG 0x0000000100050000
30156 #define SH_MD_DQRP_MMR_DIR_CONFIG_MASK 0x000000000000001f
30157 #define SH_MD_DQRP_MMR_DIR_CONFIG_INIT 0x0000000000000010
30159 /* SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE */
30160 /* Description: system size code */
30161 #define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_SHFT 0
30162 #define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_MASK 0x0000000000000007
30164 /* SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC */
30165 /* Description: enable directory ecc correction */
30166 #define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3
30167 #define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008
30169 /* SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS */
30170 /* Description: enable local poisoning for dir table fall-through */
30171 #define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4
30172 #define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010
30174 /* ==================================================================== */
30175 /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC0" */
30176 /* node [63:0] presence bits */
30177 /* ==================================================================== */
30179 #define SH_MD_DQRP_MMR_DIR_PRESVEC0 0x0000000100050100
30180 #define SH_MD_DQRP_MMR_DIR_PRESVEC0_MASK 0xffffffffffffffff
30181 #define SH_MD_DQRP_MMR_DIR_PRESVEC0_INIT 0x0000000000000000
30183 /* SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC */
30184 /* Description: node presence bits, 1=present */
30185 #define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_SHFT 0
30186 #define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_MASK 0xffffffffffffffff
30188 /* ==================================================================== */
30189 /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC1" */
30190 /* node [127:64] presence bits */
30191 /* ==================================================================== */
30193 #define SH_MD_DQRP_MMR_DIR_PRESVEC1 0x0000000100050110
30194 #define SH_MD_DQRP_MMR_DIR_PRESVEC1_MASK 0xffffffffffffffff
30195 #define SH_MD_DQRP_MMR_DIR_PRESVEC1_INIT 0x0000000000000000
30197 /* SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC */
30198 /* Description: node presence bits, 1=present */
30199 #define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_SHFT 0
30200 #define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_MASK 0xffffffffffffffff
30202 /* ==================================================================== */
30203 /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC2" */
30204 /* node [191:128] presence bits */
30205 /* ==================================================================== */
30207 #define SH_MD_DQRP_MMR_DIR_PRESVEC2 0x0000000100050120
30208 #define SH_MD_DQRP_MMR_DIR_PRESVEC2_MASK 0xffffffffffffffff
30209 #define SH_MD_DQRP_MMR_DIR_PRESVEC2_INIT 0x0000000000000000
30211 /* SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC */
30212 /* Description: node presence bits, 1=present */
30213 #define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_SHFT 0
30214 #define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_MASK 0xffffffffffffffff
30216 /* ==================================================================== */
30217 /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC3" */
30218 /* node [255:192] presence bits */
30219 /* ==================================================================== */
30221 #define SH_MD_DQRP_MMR_DIR_PRESVEC3 0x0000000100050130
30222 #define SH_MD_DQRP_MMR_DIR_PRESVEC3_MASK 0xffffffffffffffff
30223 #define SH_MD_DQRP_MMR_DIR_PRESVEC3_INIT 0x0000000000000000
30225 /* SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC */
30226 /* Description: node presence bits, 1=present */
30227 #define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_SHFT 0
30228 #define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_MASK 0xffffffffffffffff
30230 /* ==================================================================== */
30231 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC0" */
30232 /* local vector for acc=0 */
30233 /* ==================================================================== */
30235 #define SH_MD_DQRP_MMR_DIR_LOCVEC0 0x0000000100050200
30236 #define SH_MD_DQRP_MMR_DIR_LOCVEC0_MASK 0xffffffffffffffff
30237 #define SH_MD_DQRP_MMR_DIR_LOCVEC0_INIT 0x0000000000000000
30239 /* SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC */
30240 /* Description: 1 node is local */
30241 #define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_SHFT 0
30242 #define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_MASK 0xffffffffffffffff
30244 /* ==================================================================== */
30245 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC1" */
30246 /* local vector for acc=1 */
30247 /* ==================================================================== */
30249 #define SH_MD_DQRP_MMR_DIR_LOCVEC1 0x0000000100050210
30250 #define SH_MD_DQRP_MMR_DIR_LOCVEC1_MASK 0xffffffffffffffff
30251 #define SH_MD_DQRP_MMR_DIR_LOCVEC1_INIT 0x0000000000000000
30253 /* SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC */
30254 /* Description: 1 node is local */
30255 #define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_SHFT 0
30256 #define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_MASK 0xffffffffffffffff
30258 /* ==================================================================== */
30259 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC2" */
30260 /* local vector for acc=2 */
30261 /* ==================================================================== */
30263 #define SH_MD_DQRP_MMR_DIR_LOCVEC2 0x0000000100050220
30264 #define SH_MD_DQRP_MMR_DIR_LOCVEC2_MASK 0xffffffffffffffff
30265 #define SH_MD_DQRP_MMR_DIR_LOCVEC2_INIT 0x0000000000000000
30267 /* SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC */
30268 /* Description: 1 node is local */
30269 #define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_SHFT 0
30270 #define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_MASK 0xffffffffffffffff
30272 /* ==================================================================== */
30273 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC3" */
30274 /* local vector for acc=3 */
30275 /* ==================================================================== */
30277 #define SH_MD_DQRP_MMR_DIR_LOCVEC3 0x0000000100050230
30278 #define SH_MD_DQRP_MMR_DIR_LOCVEC3_MASK 0xffffffffffffffff
30279 #define SH_MD_DQRP_MMR_DIR_LOCVEC3_INIT 0x0000000000000000
30281 /* SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC */
30282 /* Description: 1 node is local */
30283 #define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_SHFT 0
30284 #define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_MASK 0xffffffffffffffff
30286 /* ==================================================================== */
30287 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC4" */
30288 /* local vector for acc=4 */
30289 /* ==================================================================== */
30291 #define SH_MD_DQRP_MMR_DIR_LOCVEC4 0x0000000100050240
30292 #define SH_MD_DQRP_MMR_DIR_LOCVEC4_MASK 0xffffffffffffffff
30293 #define SH_MD_DQRP_MMR_DIR_LOCVEC4_INIT 0x0000000000000000
30295 /* SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC */
30296 /* Description: 1 node is local */
30297 #define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_SHFT 0
30298 #define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_MASK 0xffffffffffffffff
30300 /* ==================================================================== */
30301 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC5" */
30302 /* local vector for acc=5 */
30303 /* ==================================================================== */
30305 #define SH_MD_DQRP_MMR_DIR_LOCVEC5 0x0000000100050250
30306 #define SH_MD_DQRP_MMR_DIR_LOCVEC5_MASK 0xffffffffffffffff
30307 #define SH_MD_DQRP_MMR_DIR_LOCVEC5_INIT 0x0000000000000000
30309 /* SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC */
30310 /* Description: 1 node is local */
30311 #define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_SHFT 0
30312 #define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_MASK 0xffffffffffffffff
30314 /* ==================================================================== */
30315 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC6" */
30316 /* local vector for acc=6 */
30317 /* ==================================================================== */
30319 #define SH_MD_DQRP_MMR_DIR_LOCVEC6 0x0000000100050260
30320 #define SH_MD_DQRP_MMR_DIR_LOCVEC6_MASK 0xffffffffffffffff
30321 #define SH_MD_DQRP_MMR_DIR_LOCVEC6_INIT 0x0000000000000000
30323 /* SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC */
30324 /* Description: 1 node is local */
30325 #define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_SHFT 0
30326 #define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_MASK 0xffffffffffffffff
30328 /* ==================================================================== */
30329 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC7" */
30330 /* local vector for acc=7 */
30331 /* ==================================================================== */
30333 #define SH_MD_DQRP_MMR_DIR_LOCVEC7 0x0000000100050270
30334 #define SH_MD_DQRP_MMR_DIR_LOCVEC7_MASK 0xffffffffffffffff
30335 #define SH_MD_DQRP_MMR_DIR_LOCVEC7_INIT 0x0000000000000000
30337 /* SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC */
30338 /* Description: 1 node is local */
30339 #define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_SHFT 0
30340 #define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_MASK 0xffffffffffffffff
30342 /* ==================================================================== */
30343 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
30344 /* privilege vector for acc=0 */
30345 /* ==================================================================== */
30347 #define SH_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300
30348 #define SH_MD_DQRP_MMR_DIR_PRIVEC0_MASK 0x000000000fffffff
30349 #define SH_MD_DQRP_MMR_DIR_PRIVEC0_INIT 0x0000000000000000
30351 /* SH_MD_DQRP_MMR_DIR_PRIVEC0_IN */
30352 /* Description: in partition privileges, locvec bit=1 */
30353 #define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_SHFT 0
30354 #define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_MASK 0x0000000000003fff
30356 /* SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT */
30357 /* Description: out of partition privileges, locvec bit=0 */
30358 #define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_SHFT 14
30359 #define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_MASK 0x000000000fffc000
30361 /* ==================================================================== */
30362 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC1" */
30363 /* privilege vector for acc=1 */
30364 /* ==================================================================== */
30366 #define SH_MD_DQRP_MMR_DIR_PRIVEC1 0x0000000100050310
30367 #define SH_MD_DQRP_MMR_DIR_PRIVEC1_MASK 0x000000000fffffff
30368 #define SH_MD_DQRP_MMR_DIR_PRIVEC1_INIT 0x0000000000000000
30370 /* SH_MD_DQRP_MMR_DIR_PRIVEC1_IN */
30371 /* Description: in partition privileges, locvec bit=1 */
30372 #define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_SHFT 0
30373 #define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_MASK 0x0000000000003fff
30375 /* SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT */
30376 /* Description: out of partition privileges, locvec bit=0 */
30377 #define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_SHFT 14
30378 #define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_MASK 0x000000000fffc000
30380 /* ==================================================================== */
30381 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC2" */
30382 /* privilege vector for acc=2 */
30383 /* ==================================================================== */
30385 #define SH_MD_DQRP_MMR_DIR_PRIVEC2 0x0000000100050320
30386 #define SH_MD_DQRP_MMR_DIR_PRIVEC2_MASK 0x000000000fffffff
30387 #define SH_MD_DQRP_MMR_DIR_PRIVEC2_INIT 0x0000000000000000
30389 /* SH_MD_DQRP_MMR_DIR_PRIVEC2_IN */
30390 /* Description: in partition privileges, locvec bit=1 */
30391 #define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_SHFT 0
30392 #define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_MASK 0x0000000000003fff
30394 /* SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT */
30395 /* Description: out of partition privileges, locvec bit=0 */
30396 #define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_SHFT 14
30397 #define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_MASK 0x000000000fffc000
30399 /* ==================================================================== */
30400 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC3" */
30401 /* privilege vector for acc=3 */
30402 /* ==================================================================== */
30404 #define SH_MD_DQRP_MMR_DIR_PRIVEC3 0x0000000100050330
30405 #define SH_MD_DQRP_MMR_DIR_PRIVEC3_MASK 0x000000000fffffff
30406 #define SH_MD_DQRP_MMR_DIR_PRIVEC3_INIT 0x0000000000000000
30408 /* SH_MD_DQRP_MMR_DIR_PRIVEC3_IN */
30409 /* Description: in partition privileges, locvec bit=1 */
30410 #define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_SHFT 0
30411 #define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_MASK 0x0000000000003fff
30413 /* SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT */
30414 /* Description: out of partition privileges, locvec bit=0 */
30415 #define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_SHFT 14
30416 #define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_MASK 0x000000000fffc000
30418 /* ==================================================================== */
30419 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC4" */
30420 /* privilege vector for acc=4 */
30421 /* ==================================================================== */
30423 #define SH_MD_DQRP_MMR_DIR_PRIVEC4 0x0000000100050340
30424 #define SH_MD_DQRP_MMR_DIR_PRIVEC4_MASK 0x000000000fffffff
30425 #define SH_MD_DQRP_MMR_DIR_PRIVEC4_INIT 0x0000000000000000
30427 /* SH_MD_DQRP_MMR_DIR_PRIVEC4_IN */
30428 /* Description: in partition privileges, locvec bit=1 */
30429 #define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_SHFT 0
30430 #define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_MASK 0x0000000000003fff
30432 /* SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT */
30433 /* Description: out of partition privileges, locvec bit=0 */
30434 #define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_SHFT 14
30435 #define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_MASK 0x000000000fffc000
30437 /* ==================================================================== */
30438 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC5" */
30439 /* privilege vector for acc=5 */
30440 /* ==================================================================== */
30442 #define SH_MD_DQRP_MMR_DIR_PRIVEC5 0x0000000100050350
30443 #define SH_MD_DQRP_MMR_DIR_PRIVEC5_MASK 0x000000000fffffff
30444 #define SH_MD_DQRP_MMR_DIR_PRIVEC5_INIT 0x0000000000000000
30446 /* SH_MD_DQRP_MMR_DIR_PRIVEC5_IN */
30447 /* Description: in partition privileges, locvec bit=1 */
30448 #define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_SHFT 0
30449 #define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_MASK 0x0000000000003fff
30451 /* SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT */
30452 /* Description: out of partition privileges, locvec bit=0 */
30453 #define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_SHFT 14
30454 #define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_MASK 0x000000000fffc000
30456 /* ==================================================================== */
30457 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC6" */
30458 /* privilege vector for acc=6 */
30459 /* ==================================================================== */
30461 #define SH_MD_DQRP_MMR_DIR_PRIVEC6 0x0000000100050360
30462 #define SH_MD_DQRP_MMR_DIR_PRIVEC6_MASK 0x000000000fffffff
30463 #define SH_MD_DQRP_MMR_DIR_PRIVEC6_INIT 0x0000000000000000
30465 /* SH_MD_DQRP_MMR_DIR_PRIVEC6_IN */
30466 /* Description: in partition privileges, locvec bit=1 */
30467 #define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_SHFT 0
30468 #define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_MASK 0x0000000000003fff
30470 /* SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT */
30471 /* Description: out of partition privileges, locvec bit=0 */
30472 #define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_SHFT 14
30473 #define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_MASK 0x000000000fffc000
30475 /* ==================================================================== */
30476 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC7" */
30477 /* privilege vector for acc=7 */
30478 /* ==================================================================== */
30480 #define SH_MD_DQRP_MMR_DIR_PRIVEC7 0x0000000100050370
30481 #define SH_MD_DQRP_MMR_DIR_PRIVEC7_MASK 0x000000000fffffff
30482 #define SH_MD_DQRP_MMR_DIR_PRIVEC7_INIT 0x0000000000000000
30484 /* SH_MD_DQRP_MMR_DIR_PRIVEC7_IN */
30485 /* Description: in partition privileges, locvec bit=1 */
30486 #define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_SHFT 0
30487 #define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_MASK 0x0000000000003fff
30489 /* SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT */
30490 /* Description: out of partition privileges, locvec bit=0 */
30491 #define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_SHFT 14
30492 #define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_MASK 0x000000000fffc000
30494 /* ==================================================================== */
30495 /* Register "SH_MD_DQRP_MMR_DIR_TIMER" */
30496 /* MD SXRO timer */
30497 /* ==================================================================== */
30499 #define SH_MD_DQRP_MMR_DIR_TIMER 0x0000000100050400
30500 #define SH_MD_DQRP_MMR_DIR_TIMER_MASK 0x00000000003fffff
30501 #define SH_MD_DQRP_MMR_DIR_TIMER_INIT 0x0000000000000000
30503 /* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV */
30504 /* Description: timer divide register */
30505 #define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_SHFT 0
30506 #define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_MASK 0x0000000000000fff
30508 /* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN */
30509 /* Description: timer enable */
30510 #define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_SHFT 12
30511 #define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_MASK 0x0000000000001000
30513 /* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR */
30514 /* Description: value of current timer */
30515 #define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_SHFT 13
30516 #define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_MASK 0x00000000003fe000
30518 /* ==================================================================== */
30519 /* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY" */
30520 /* directory pio write data */
30521 /* ==================================================================== */
30523 #define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY 0x0000000100051000
30524 #define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_MASK 0x03ffffffffffffff
30525 #define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_INIT 0x0000000000000000
30527 /* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA */
30528 /* Description: directory entry A */
30529 #define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0
30530 #define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff
30532 /* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB */
30533 /* Description: directory entry B */
30534 #define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26
30535 #define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000
30537 /* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI */
30538 /* Description: directory priority */
30539 #define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT 52
30540 #define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_MASK 0x0070000000000000
30542 /* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC */
30543 /* Description: directory access bits */
30544 #define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT 55
30545 #define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_MASK 0x0380000000000000
30547 /* ==================================================================== */
30548 /* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC" */
30549 /* directory ecc register */
30550 /* ==================================================================== */
30552 #define SH_MD_DQRP_MMR_PIOWD_DIR_ECC 0x0000000100051010
30553 #define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_MASK 0x0000000000003fff
30554 #define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_INIT 0x0000000000000000
30556 /* SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA */
30557 /* Description: XOR bits for directory ECC group 1 */
30558 #define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_SHFT 0
30559 #define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_MASK 0x000000000000007f
30561 /* SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB */
30562 /* Description: XOR bits for directory ECC group 2 */
30563 #define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_SHFT 7
30564 #define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_MASK 0x0000000000003f80
30566 /* ==================================================================== */
30567 /* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY" */
30568 /* x directory pio read data */
30569 /* ==================================================================== */
30571 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY 0x0000000100052000
30572 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_MASK 0x0fffffffffffffff
30573 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_INIT 0x0000000000000000
30575 /* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA */
30576 /* Description: directory entry A */
30577 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0
30578 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
30580 /* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB */
30581 /* Description: directory entry B */
30582 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26
30583 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
30585 /* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI */
30586 /* Description: directory priority */
30587 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52
30588 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000
30590 /* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC */
30591 /* Description: directory access bits */
30592 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55
30593 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000
30595 /* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR */
30596 /* Description: correctable ecc error */
30597 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58
30598 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000
30600 /* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC */
30601 /* Description: uncorrectable ecc error */
30602 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59
30603 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000
30605 /* ==================================================================== */
30606 /* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC" */
30607 /* x directory ecc */
30608 /* ==================================================================== */
30610 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC 0x0000000100052010
30611 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_MASK 0x0000000000003fff
30612 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_INIT 0x0000000000000000
30614 /* SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA */
30615 /* Description: group 1 ecc */
30616 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0
30617 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f
30619 /* SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB */
30620 /* Description: group 2 ecc */
30621 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7
30622 #define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80
30624 /* ==================================================================== */
30625 /* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY" */
30626 /* y directory pio read data */
30627 /* ==================================================================== */
30629 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY 0x0000000100052800
30630 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_MASK 0x0fffffffffffffff
30631 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_INIT 0x0000000000000000
30633 /* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA */
30634 /* Description: directory entry A */
30635 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0
30636 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
30638 /* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB */
30639 /* Description: directory entry B */
30640 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26
30641 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
30643 /* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI */
30644 /* Description: directory priority */
30645 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52
30646 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000
30648 /* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC */
30649 /* Description: directory access bits */
30650 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55
30651 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000
30653 /* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR */
30654 /* Description: correctable ecc error */
30655 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58
30656 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000
30658 /* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC */
30659 /* Description: uncorrectable ecc error */
30660 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59
30661 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000
30663 /* ==================================================================== */
30664 /* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC" */
30665 /* y directory ecc */
30666 /* ==================================================================== */
30668 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC 0x0000000100052810
30669 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_MASK 0x0000000000003fff
30670 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_INIT 0x0000000000000000
30672 /* SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA */
30673 /* Description: group 1 ecc */
30674 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0
30675 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f
30677 /* SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB */
30678 /* Description: group 2 ecc */
30679 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7
30680 #define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80
30682 /* ==================================================================== */
30683 /* Register "SH_MD_DQRP_MMR_XCERR1" */
30684 /* correctable dir ecc group 1 error register */
30685 /* ==================================================================== */
30687 #define SH_MD_DQRP_MMR_XCERR1 0x0000000100053000
30688 #define SH_MD_DQRP_MMR_XCERR1_MASK 0x0000007fffffffff
30689 #define SH_MD_DQRP_MMR_XCERR1_INIT 0x0000000000000000
30691 /* SH_MD_DQRP_MMR_XCERR1_GRP1 */
30692 /* Description: ecc group 1 bits */
30693 #define SH_MD_DQRP_MMR_XCERR1_GRP1_SHFT 0
30694 #define SH_MD_DQRP_MMR_XCERR1_GRP1_MASK 0x0000000fffffffff
30696 /* SH_MD_DQRP_MMR_XCERR1_VAL */
30697 /* Description: correctable ecc error in group 1 bits */
30698 #define SH_MD_DQRP_MMR_XCERR1_VAL_SHFT 36
30699 #define SH_MD_DQRP_MMR_XCERR1_VAL_MASK 0x0000001000000000
30701 /* SH_MD_DQRP_MMR_XCERR1_MORE */
30702 /* Description: more than one correctable ecc error in group 1 */
30703 #define SH_MD_DQRP_MMR_XCERR1_MORE_SHFT 37
30704 #define SH_MD_DQRP_MMR_XCERR1_MORE_MASK 0x0000002000000000
30706 /* SH_MD_DQRP_MMR_XCERR1_ARM */
30707 /* Description: writing 1 arms uncorrectable ecc error capture */
30708 #define SH_MD_DQRP_MMR_XCERR1_ARM_SHFT 38
30709 #define SH_MD_DQRP_MMR_XCERR1_ARM_MASK 0x0000004000000000
30711 /* ==================================================================== */
30712 /* Register "SH_MD_DQRP_MMR_XCERR2" */
30713 /* correctable dir ecc group 2 error register */
30714 /* ==================================================================== */
30716 #define SH_MD_DQRP_MMR_XCERR2 0x0000000100053010
30717 #define SH_MD_DQRP_MMR_XCERR2_MASK 0x0000003fffffffff
30718 #define SH_MD_DQRP_MMR_XCERR2_INIT 0x0000000000000000
30720 /* SH_MD_DQRP_MMR_XCERR2_GRP2 */
30721 /* Description: ecc group 2 bits */
30722 #define SH_MD_DQRP_MMR_XCERR2_GRP2_SHFT 0
30723 #define SH_MD_DQRP_MMR_XCERR2_GRP2_MASK 0x0000000fffffffff
30725 /* SH_MD_DQRP_MMR_XCERR2_VAL */
30726 /* Description: correctable ecc error in group 2 bits */
30727 #define SH_MD_DQRP_MMR_XCERR2_VAL_SHFT 36
30728 #define SH_MD_DQRP_MMR_XCERR2_VAL_MASK 0x0000001000000000
30730 /* SH_MD_DQRP_MMR_XCERR2_MORE */
30731 /* Description: more than one correctable ecc error in group 2 */
30732 #define SH_MD_DQRP_MMR_XCERR2_MORE_SHFT 37
30733 #define SH_MD_DQRP_MMR_XCERR2_MORE_MASK 0x0000002000000000
30735 /* ==================================================================== */
30736 /* Register "SH_MD_DQRP_MMR_XUERR1" */
30737 /* uncorrectable dir ecc group 1 error register */
30738 /* ==================================================================== */
30740 #define SH_MD_DQRP_MMR_XUERR1 0x0000000100053020
30741 #define SH_MD_DQRP_MMR_XUERR1_MASK 0x0000007fffffffff
30742 #define SH_MD_DQRP_MMR_XUERR1_INIT 0x0000000000000000
30744 /* SH_MD_DQRP_MMR_XUERR1_GRP1 */
30745 /* Description: ecc group 1 bits */
30746 #define SH_MD_DQRP_MMR_XUERR1_GRP1_SHFT 0
30747 #define SH_MD_DQRP_MMR_XUERR1_GRP1_MASK 0x0000000fffffffff
30749 /* SH_MD_DQRP_MMR_XUERR1_VAL */
30750 /* Description: uncorrectable ecc error in group 1 bits */
30751 #define SH_MD_DQRP_MMR_XUERR1_VAL_SHFT 36
30752 #define SH_MD_DQRP_MMR_XUERR1_VAL_MASK 0x0000001000000000
30754 /* SH_MD_DQRP_MMR_XUERR1_MORE */
30755 /* Description: more than one uncorrectable ecc error in group 1 */
30756 #define SH_MD_DQRP_MMR_XUERR1_MORE_SHFT 37
30757 #define SH_MD_DQRP_MMR_XUERR1_MORE_MASK 0x0000002000000000
30759 /* SH_MD_DQRP_MMR_XUERR1_ARM */
30760 /* Description: writing 1 arms uncorrectable ecc error capture */
30761 #define SH_MD_DQRP_MMR_XUERR1_ARM_SHFT 38
30762 #define SH_MD_DQRP_MMR_XUERR1_ARM_MASK 0x0000004000000000
30764 /* ==================================================================== */
30765 /* Register "SH_MD_DQRP_MMR_XUERR2" */
30766 /* uncorrectable dir ecc group 2 error register */
30767 /* ==================================================================== */
30769 #define SH_MD_DQRP_MMR_XUERR2 0x0000000100053030
30770 #define SH_MD_DQRP_MMR_XUERR2_MASK 0x0000003fffffffff
30771 #define SH_MD_DQRP_MMR_XUERR2_INIT 0x0000000000000000
30773 /* SH_MD_DQRP_MMR_XUERR2_GRP2 */
30774 /* Description: ecc group 2 bits */
30775 #define SH_MD_DQRP_MMR_XUERR2_GRP2_SHFT 0
30776 #define SH_MD_DQRP_MMR_XUERR2_GRP2_MASK 0x0000000fffffffff
30778 /* SH_MD_DQRP_MMR_XUERR2_VAL */
30779 /* Description: uncorrectable ecc error in group 2 bits */
30780 #define SH_MD_DQRP_MMR_XUERR2_VAL_SHFT 36
30781 #define SH_MD_DQRP_MMR_XUERR2_VAL_MASK 0x0000001000000000
30783 /* SH_MD_DQRP_MMR_XUERR2_MORE */
30784 /* Description: more than one uncorrectable ecc error in group 2 */
30785 #define SH_MD_DQRP_MMR_XUERR2_MORE_SHFT 37
30786 #define SH_MD_DQRP_MMR_XUERR2_MORE_MASK 0x0000002000000000
30788 /* ==================================================================== */
30789 /* Register "SH_MD_DQRP_MMR_XPERR" */
30790 /* protocol error register */
30791 /* ==================================================================== */
30793 #define SH_MD_DQRP_MMR_XPERR 0x0000000100053040
30794 #define SH_MD_DQRP_MMR_XPERR_MASK 0x7fffffffffffffff
30795 #define SH_MD_DQRP_MMR_XPERR_INIT 0x0000000000000000
30797 /* SH_MD_DQRP_MMR_XPERR_DIR */
30798 /* Description: directory entry */
30799 #define SH_MD_DQRP_MMR_XPERR_DIR_SHFT 0
30800 #define SH_MD_DQRP_MMR_XPERR_DIR_MASK 0x0000000003ffffff
30802 /* SH_MD_DQRP_MMR_XPERR_CMD */
30803 /* Description: incoming command */
30804 #define SH_MD_DQRP_MMR_XPERR_CMD_SHFT 26
30805 #define SH_MD_DQRP_MMR_XPERR_CMD_MASK 0x00000003fc000000
30807 /* SH_MD_DQRP_MMR_XPERR_SRC */
30808 /* Description: source node of dir operation */
30809 #define SH_MD_DQRP_MMR_XPERR_SRC_SHFT 34
30810 #define SH_MD_DQRP_MMR_XPERR_SRC_MASK 0x0000fffc00000000
30812 /* SH_MD_DQRP_MMR_XPERR_PRIGE */
30813 /* Description: priority was greater-equal */
30814 #define SH_MD_DQRP_MMR_XPERR_PRIGE_SHFT 48
30815 #define SH_MD_DQRP_MMR_XPERR_PRIGE_MASK 0x0001000000000000
30817 /* SH_MD_DQRP_MMR_XPERR_PRIV */
30818 /* Description: access privilege bit */
30819 #define SH_MD_DQRP_MMR_XPERR_PRIV_SHFT 49
30820 #define SH_MD_DQRP_MMR_XPERR_PRIV_MASK 0x0002000000000000
30822 /* SH_MD_DQRP_MMR_XPERR_COR */
30823 /* Description: correctable ecc error */
30824 #define SH_MD_DQRP_MMR_XPERR_COR_SHFT 50
30825 #define SH_MD_DQRP_MMR_XPERR_COR_MASK 0x0004000000000000
30827 /* SH_MD_DQRP_MMR_XPERR_UNC */
30828 /* Description: uncorrectable ecc error */
30829 #define SH_MD_DQRP_MMR_XPERR_UNC_SHFT 51
30830 #define SH_MD_DQRP_MMR_XPERR_UNC_MASK 0x0008000000000000
30832 /* SH_MD_DQRP_MMR_XPERR_MYBIT */
30833 /* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */
30834 #define SH_MD_DQRP_MMR_XPERR_MYBIT_SHFT 52
30835 #define SH_MD_DQRP_MMR_XPERR_MYBIT_MASK 0x0ff0000000000000
30837 /* SH_MD_DQRP_MMR_XPERR_VAL */
30838 /* Description: protocol error info valid */
30839 #define SH_MD_DQRP_MMR_XPERR_VAL_SHFT 60
30840 #define SH_MD_DQRP_MMR_XPERR_VAL_MASK 0x1000000000000000
30842 /* SH_MD_DQRP_MMR_XPERR_MORE */
30843 /* Description: more than one protocol error */
30844 #define SH_MD_DQRP_MMR_XPERR_MORE_SHFT 61
30845 #define SH_MD_DQRP_MMR_XPERR_MORE_MASK 0x2000000000000000
30847 /* SH_MD_DQRP_MMR_XPERR_ARM */
30848 /* Description: writing 1 arms error capture */
30849 #define SH_MD_DQRP_MMR_XPERR_ARM_SHFT 62
30850 #define SH_MD_DQRP_MMR_XPERR_ARM_MASK 0x4000000000000000
30852 /* ==================================================================== */
30853 /* Register "SH_MD_DQRP_MMR_YCERR1" */
30854 /* correctable dir ecc group 1 error register */
30855 /* ==================================================================== */
30857 #define SH_MD_DQRP_MMR_YCERR1 0x0000000100053800
30858 #define SH_MD_DQRP_MMR_YCERR1_MASK 0x0000007fffffffff
30859 #define SH_MD_DQRP_MMR_YCERR1_INIT 0x0000000000000000
30861 /* SH_MD_DQRP_MMR_YCERR1_GRP1 */
30862 /* Description: ecc group 1 bits */
30863 #define SH_MD_DQRP_MMR_YCERR1_GRP1_SHFT 0
30864 #define SH_MD_DQRP_MMR_YCERR1_GRP1_MASK 0x0000000fffffffff
30866 /* SH_MD_DQRP_MMR_YCERR1_VAL */
30867 /* Description: correctable ecc error in group 1 bits */
30868 #define SH_MD_DQRP_MMR_YCERR1_VAL_SHFT 36
30869 #define SH_MD_DQRP_MMR_YCERR1_VAL_MASK 0x0000001000000000
30871 /* SH_MD_DQRP_MMR_YCERR1_MORE */
30872 /* Description: more than one correctable ecc error in group 1 */
30873 #define SH_MD_DQRP_MMR_YCERR1_MORE_SHFT 37
30874 #define SH_MD_DQRP_MMR_YCERR1_MORE_MASK 0x0000002000000000
30876 /* SH_MD_DQRP_MMR_YCERR1_ARM */
30877 /* Description: writing 1 arms uncorrectable ecc error capture */
30878 #define SH_MD_DQRP_MMR_YCERR1_ARM_SHFT 38
30879 #define SH_MD_DQRP_MMR_YCERR1_ARM_MASK 0x0000004000000000
30881 /* ==================================================================== */
30882 /* Register "SH_MD_DQRP_MMR_YCERR2" */
30883 /* correctable dir ecc group 2 error register */
30884 /* ==================================================================== */
30886 #define SH_MD_DQRP_MMR_YCERR2 0x0000000100053810
30887 #define SH_MD_DQRP_MMR_YCERR2_MASK 0x0000003fffffffff
30888 #define SH_MD_DQRP_MMR_YCERR2_INIT 0x0000000000000000
30890 /* SH_MD_DQRP_MMR_YCERR2_GRP2 */
30891 /* Description: ecc group 2 bits */
30892 #define SH_MD_DQRP_MMR_YCERR2_GRP2_SHFT 0
30893 #define SH_MD_DQRP_MMR_YCERR2_GRP2_MASK 0x0000000fffffffff
30895 /* SH_MD_DQRP_MMR_YCERR2_VAL */
30896 /* Description: correctable ecc error in group 2 bits */
30897 #define SH_MD_DQRP_MMR_YCERR2_VAL_SHFT 36
30898 #define SH_MD_DQRP_MMR_YCERR2_VAL_MASK 0x0000001000000000
30900 /* SH_MD_DQRP_MMR_YCERR2_MORE */
30901 /* Description: more than one correctable ecc error in group 2 */
30902 #define SH_MD_DQRP_MMR_YCERR2_MORE_SHFT 37
30903 #define SH_MD_DQRP_MMR_YCERR2_MORE_MASK 0x0000002000000000
30905 /* ==================================================================== */
30906 /* Register "SH_MD_DQRP_MMR_YUERR1" */
30907 /* uncorrectable dir ecc group 1 error register */
30908 /* ==================================================================== */
30910 #define SH_MD_DQRP_MMR_YUERR1 0x0000000100053820
30911 #define SH_MD_DQRP_MMR_YUERR1_MASK 0x0000007fffffffff
30912 #define SH_MD_DQRP_MMR_YUERR1_INIT 0x0000000000000000
30914 /* SH_MD_DQRP_MMR_YUERR1_GRP1 */
30915 /* Description: ecc group 1 bits */
30916 #define SH_MD_DQRP_MMR_YUERR1_GRP1_SHFT 0
30917 #define SH_MD_DQRP_MMR_YUERR1_GRP1_MASK 0x0000000fffffffff
30919 /* SH_MD_DQRP_MMR_YUERR1_VAL */
30920 /* Description: uncorrectable ecc error in group 1 bits */
30921 #define SH_MD_DQRP_MMR_YUERR1_VAL_SHFT 36
30922 #define SH_MD_DQRP_MMR_YUERR1_VAL_MASK 0x0000001000000000
30924 /* SH_MD_DQRP_MMR_YUERR1_MORE */
30925 /* Description: more than one uncorrectable ecc error in group 1 */
30926 #define SH_MD_DQRP_MMR_YUERR1_MORE_SHFT 37
30927 #define SH_MD_DQRP_MMR_YUERR1_MORE_MASK 0x0000002000000000
30929 /* SH_MD_DQRP_MMR_YUERR1_ARM */
30930 /* Description: writing 1 arms uncorrectable ecc error capture */
30931 #define SH_MD_DQRP_MMR_YUERR1_ARM_SHFT 38
30932 #define SH_MD_DQRP_MMR_YUERR1_ARM_MASK 0x0000004000000000
30934 /* ==================================================================== */
30935 /* Register "SH_MD_DQRP_MMR_YUERR2" */
30936 /* uncorrectable dir ecc group 2 error register */
30937 /* ==================================================================== */
30939 #define SH_MD_DQRP_MMR_YUERR2 0x0000000100053830
30940 #define SH_MD_DQRP_MMR_YUERR2_MASK 0x0000003fffffffff
30941 #define SH_MD_DQRP_MMR_YUERR2_INIT 0x0000000000000000
30943 /* SH_MD_DQRP_MMR_YUERR2_GRP2 */
30944 /* Description: ecc group 2 bits */
30945 #define SH_MD_DQRP_MMR_YUERR2_GRP2_SHFT 0
30946 #define SH_MD_DQRP_MMR_YUERR2_GRP2_MASK 0x0000000fffffffff
30948 /* SH_MD_DQRP_MMR_YUERR2_VAL */
30949 /* Description: uncorrectable ecc error in group 2 bits */
30950 #define SH_MD_DQRP_MMR_YUERR2_VAL_SHFT 36
30951 #define SH_MD_DQRP_MMR_YUERR2_VAL_MASK 0x0000001000000000
30953 /* SH_MD_DQRP_MMR_YUERR2_MORE */
30954 /* Description: more than one uncorrectable ecc error in group 2 */
30955 #define SH_MD_DQRP_MMR_YUERR2_MORE_SHFT 37
30956 #define SH_MD_DQRP_MMR_YUERR2_MORE_MASK 0x0000002000000000
30958 /* ==================================================================== */
30959 /* Register "SH_MD_DQRP_MMR_YPERR" */
30960 /* protocol error register */
30961 /* ==================================================================== */
30963 #define SH_MD_DQRP_MMR_YPERR 0x0000000100053840
30964 #define SH_MD_DQRP_MMR_YPERR_MASK 0x7fffffffffffffff
30965 #define SH_MD_DQRP_MMR_YPERR_INIT 0x0000000000000000
30967 /* SH_MD_DQRP_MMR_YPERR_DIR */
30968 /* Description: directory entry */
30969 #define SH_MD_DQRP_MMR_YPERR_DIR_SHFT 0
30970 #define SH_MD_DQRP_MMR_YPERR_DIR_MASK 0x0000000003ffffff
30972 /* SH_MD_DQRP_MMR_YPERR_CMD */
30973 /* Description: incoming command */
30974 #define SH_MD_DQRP_MMR_YPERR_CMD_SHFT 26
30975 #define SH_MD_DQRP_MMR_YPERR_CMD_MASK 0x00000003fc000000
30977 /* SH_MD_DQRP_MMR_YPERR_SRC */
30978 /* Description: source node of dir operation */
30979 #define SH_MD_DQRP_MMR_YPERR_SRC_SHFT 34
30980 #define SH_MD_DQRP_MMR_YPERR_SRC_MASK 0x0000fffc00000000
30982 /* SH_MD_DQRP_MMR_YPERR_PRIGE */
30983 /* Description: priority was greater-equal */
30984 #define SH_MD_DQRP_MMR_YPERR_PRIGE_SHFT 48
30985 #define SH_MD_DQRP_MMR_YPERR_PRIGE_MASK 0x0001000000000000
30987 /* SH_MD_DQRP_MMR_YPERR_PRIV */
30988 /* Description: access privilege bit */
30989 #define SH_MD_DQRP_MMR_YPERR_PRIV_SHFT 49
30990 #define SH_MD_DQRP_MMR_YPERR_PRIV_MASK 0x0002000000000000
30992 /* SH_MD_DQRP_MMR_YPERR_COR */
30993 /* Description: correctable ecc error */
30994 #define SH_MD_DQRP_MMR_YPERR_COR_SHFT 50
30995 #define SH_MD_DQRP_MMR_YPERR_COR_MASK 0x0004000000000000
30997 /* SH_MD_DQRP_MMR_YPERR_UNC */
30998 /* Description: uncorrectable ecc error */
30999 #define SH_MD_DQRP_MMR_YPERR_UNC_SHFT 51
31000 #define SH_MD_DQRP_MMR_YPERR_UNC_MASK 0x0008000000000000
31002 /* SH_MD_DQRP_MMR_YPERR_MYBIT */
31003 /* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */
31004 #define SH_MD_DQRP_MMR_YPERR_MYBIT_SHFT 52
31005 #define SH_MD_DQRP_MMR_YPERR_MYBIT_MASK 0x0ff0000000000000
31007 /* SH_MD_DQRP_MMR_YPERR_VAL */
31008 /* Description: protocol error info valid */
31009 #define SH_MD_DQRP_MMR_YPERR_VAL_SHFT 60
31010 #define SH_MD_DQRP_MMR_YPERR_VAL_MASK 0x1000000000000000
31012 /* SH_MD_DQRP_MMR_YPERR_MORE */
31013 /* Description: more than one protocol error */
31014 #define SH_MD_DQRP_MMR_YPERR_MORE_SHFT 61
31015 #define SH_MD_DQRP_MMR_YPERR_MORE_MASK 0x2000000000000000
31017 /* SH_MD_DQRP_MMR_YPERR_ARM */
31018 /* Description: writing 1 arms error capture */
31019 #define SH_MD_DQRP_MMR_YPERR_ARM_SHFT 62
31020 #define SH_MD_DQRP_MMR_YPERR_ARM_MASK 0x4000000000000000
31022 /* ==================================================================== */
31023 /* Register "SH_MD_DQRP_MMR_DIR_CMDTRIG" */
31025 /* ==================================================================== */
31027 #define SH_MD_DQRP_MMR_DIR_CMDTRIG 0x0000000100054000
31028 #define SH_MD_DQRP_MMR_DIR_CMDTRIG_MASK 0x00000000ffffffff
31029 #define SH_MD_DQRP_MMR_DIR_CMDTRIG_INIT 0x0000000000000000
31031 /* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0 */
31032 /* Description: command trigger 0 */
31033 #define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_SHFT 0
31034 #define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_MASK 0x00000000000000ff
31036 /* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1 */
31037 /* Description: command trigger 1 */
31038 #define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_SHFT 8
31039 #define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_MASK 0x000000000000ff00
31041 /* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2 */
31042 /* Description: command trigger 2 */
31043 #define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_SHFT 16
31044 #define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_MASK 0x0000000000ff0000
31046 /* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3 */
31047 /* Description: command trigger 3 */
31048 #define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_SHFT 24
31049 #define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_MASK 0x00000000ff000000
31051 /* ==================================================================== */
31052 /* Register "SH_MD_DQRP_MMR_DIR_TBLTRIG" */
31053 /* dir table trigger */
31054 /* ==================================================================== */
31056 #define SH_MD_DQRP_MMR_DIR_TBLTRIG 0x0000000100054010
31057 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_MASK 0x000003ffffffffff
31058 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_INIT 0x0000000000000000
31060 /* SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC */
31061 /* Description: source of request */
31062 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_SHFT 0
31063 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_MASK 0x0000000000003fff
31065 /* SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD */
31066 /* Description: incoming request */
31067 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_SHFT 14
31068 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_MASK 0x00000000003fc000
31070 /* SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC */
31071 /* Description: uncorrectable error, privilege bit */
31072 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_SHFT 22
31073 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_MASK 0x0000000000c00000
31075 /* SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE */
31076 /* Description: priority greater-equal */
31077 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_SHFT 24
31078 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_MASK 0x0000000001000000
31080 /* SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST */
31081 /* Description: shrd,sxro,sub-state */
31082 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_SHFT 25
31083 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_MASK 0x00000003fe000000
31085 /* SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT */
31086 /* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */
31087 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_SHFT 34
31088 #define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_MASK 0x000003fc00000000
31090 /* ==================================================================== */
31091 /* Register "SH_MD_DQRP_MMR_DIR_TBLMASK" */
31092 /* dir table trigger mask */
31093 /* ==================================================================== */
31095 #define SH_MD_DQRP_MMR_DIR_TBLMASK 0x0000000100054020
31096 #define SH_MD_DQRP_MMR_DIR_TBLMASK_MASK 0x000003ffffffffff
31097 #define SH_MD_DQRP_MMR_DIR_TBLMASK_INIT 0x0000000000000000
31099 /* SH_MD_DQRP_MMR_DIR_TBLMASK_SRC */
31100 /* Description: source of request */
31101 #define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_SHFT 0
31102 #define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_MASK 0x0000000000003fff
31104 /* SH_MD_DQRP_MMR_DIR_TBLMASK_CMD */
31105 /* Description: incoming request */
31106 #define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_SHFT 14
31107 #define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_MASK 0x00000000003fc000
31109 /* SH_MD_DQRP_MMR_DIR_TBLMASK_ACC */
31110 /* Description: uncorrectable error, privilege bit */
31111 #define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_SHFT 22
31112 #define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_MASK 0x0000000000c00000
31114 /* SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE */
31115 /* Description: priority greater-equal */
31116 #define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_SHFT 24
31117 #define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_MASK 0x0000000001000000
31119 /* SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST */
31120 /* Description: shrd,sxro,sub-state */
31121 #define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_SHFT 25
31122 #define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_MASK 0x00000003fe000000
31124 /* SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT */
31125 /* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */
31126 #define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_SHFT 34
31127 #define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_MASK 0x000003fc00000000
31129 /* ==================================================================== */
31130 /* Register "SH_MD_DQRP_MMR_XBIST_H" */
31131 /* rising edge bist/fill pattern */
31132 /* ==================================================================== */
31134 #define SH_MD_DQRP_MMR_XBIST_H 0x0000000100058000
31135 #define SH_MD_DQRP_MMR_XBIST_H_MASK 0x00000700ffffffff
31136 #define SH_MD_DQRP_MMR_XBIST_H_INIT 0x0000000000000000
31138 /* SH_MD_DQRP_MMR_XBIST_H_PAT */
31139 /* Description: data pattern */
31140 #define SH_MD_DQRP_MMR_XBIST_H_PAT_SHFT 0
31141 #define SH_MD_DQRP_MMR_XBIST_H_PAT_MASK 0x00000000ffffffff
31143 /* SH_MD_DQRP_MMR_XBIST_H_INV */
31144 /* Description: invert data pattern in next cycle */
31145 #define SH_MD_DQRP_MMR_XBIST_H_INV_SHFT 40
31146 #define SH_MD_DQRP_MMR_XBIST_H_INV_MASK 0x0000010000000000
31148 /* SH_MD_DQRP_MMR_XBIST_H_ROT */
31149 /* Description: rotate left data pattern in next cycle */
31150 #define SH_MD_DQRP_MMR_XBIST_H_ROT_SHFT 41
31151 #define SH_MD_DQRP_MMR_XBIST_H_ROT_MASK 0x0000020000000000
31153 /* SH_MD_DQRP_MMR_XBIST_H_ARM */
31154 /* Description: writing 1 arms data miscompare capture */
31155 #define SH_MD_DQRP_MMR_XBIST_H_ARM_SHFT 42
31156 #define SH_MD_DQRP_MMR_XBIST_H_ARM_MASK 0x0000040000000000
31158 /* ==================================================================== */
31159 /* Register "SH_MD_DQRP_MMR_XBIST_L" */
31160 /* falling edge bist/fill pattern */
31161 /* ==================================================================== */
31163 #define SH_MD_DQRP_MMR_XBIST_L 0x0000000100058010
31164 #define SH_MD_DQRP_MMR_XBIST_L_MASK 0x00000300ffffffff
31165 #define SH_MD_DQRP_MMR_XBIST_L_INIT 0x0000000000000000
31167 /* SH_MD_DQRP_MMR_XBIST_L_PAT */
31168 /* Description: data pattern */
31169 #define SH_MD_DQRP_MMR_XBIST_L_PAT_SHFT 0
31170 #define SH_MD_DQRP_MMR_XBIST_L_PAT_MASK 0x00000000ffffffff
31172 /* SH_MD_DQRP_MMR_XBIST_L_INV */
31173 /* Description: invert data pattern in next cycle */
31174 #define SH_MD_DQRP_MMR_XBIST_L_INV_SHFT 40
31175 #define SH_MD_DQRP_MMR_XBIST_L_INV_MASK 0x0000010000000000
31177 /* SH_MD_DQRP_MMR_XBIST_L_ROT */
31178 /* Description: rotate left data pattern in next cycle */
31179 #define SH_MD_DQRP_MMR_XBIST_L_ROT_SHFT 41
31180 #define SH_MD_DQRP_MMR_XBIST_L_ROT_MASK 0x0000020000000000
31182 /* ==================================================================== */
31183 /* Register "SH_MD_DQRP_MMR_XBIST_ERR_H" */
31184 /* rising edge bist error pattern */
31185 /* ==================================================================== */
31187 #define SH_MD_DQRP_MMR_XBIST_ERR_H 0x0000000100058020
31188 #define SH_MD_DQRP_MMR_XBIST_ERR_H_MASK 0x00000300ffffffff
31189 #define SH_MD_DQRP_MMR_XBIST_ERR_H_INIT 0x0000000000000000
31191 /* SH_MD_DQRP_MMR_XBIST_ERR_H_PAT */
31192 /* Description: data pattern */
31193 #define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_SHFT 0
31194 #define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_MASK 0x00000000ffffffff
31196 /* SH_MD_DQRP_MMR_XBIST_ERR_H_VAL */
31197 /* Description: bist data miscompare */
31198 #define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_SHFT 40
31199 #define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000
31201 /* SH_MD_DQRP_MMR_XBIST_ERR_H_MORE */
31202 /* Description: more than one bist data miscompare */
31203 #define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_SHFT 41
31204 #define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000
31206 /* ==================================================================== */
31207 /* Register "SH_MD_DQRP_MMR_XBIST_ERR_L" */
31208 /* falling edge bist error pattern */
31209 /* ==================================================================== */
31211 #define SH_MD_DQRP_MMR_XBIST_ERR_L 0x0000000100058030
31212 #define SH_MD_DQRP_MMR_XBIST_ERR_L_MASK 0x00000300ffffffff
31213 #define SH_MD_DQRP_MMR_XBIST_ERR_L_INIT 0x0000000000000000
31215 /* SH_MD_DQRP_MMR_XBIST_ERR_L_PAT */
31216 /* Description: data pattern */
31217 #define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_SHFT 0
31218 #define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_MASK 0x00000000ffffffff
31220 /* SH_MD_DQRP_MMR_XBIST_ERR_L_VAL */
31221 /* Description: bist data miscompare */
31222 #define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_SHFT 40
31223 #define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000
31225 /* SH_MD_DQRP_MMR_XBIST_ERR_L_MORE */
31226 /* Description: more than one bist data miscompare */
31227 #define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_SHFT 41
31228 #define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000
31230 /* ==================================================================== */
31231 /* Register "SH_MD_DQRP_MMR_YBIST_H" */
31232 /* rising edge bist/fill pattern */
31233 /* ==================================================================== */
31235 #define SH_MD_DQRP_MMR_YBIST_H 0x0000000100058800
31236 #define SH_MD_DQRP_MMR_YBIST_H_MASK 0x00000700ffffffff
31237 #define SH_MD_DQRP_MMR_YBIST_H_INIT 0x0000000000000000
31239 /* SH_MD_DQRP_MMR_YBIST_H_PAT */
31240 /* Description: data pattern */
31241 #define SH_MD_DQRP_MMR_YBIST_H_PAT_SHFT 0
31242 #define SH_MD_DQRP_MMR_YBIST_H_PAT_MASK 0x00000000ffffffff
31244 /* SH_MD_DQRP_MMR_YBIST_H_INV */
31245 /* Description: invert data pattern in next cycle */
31246 #define SH_MD_DQRP_MMR_YBIST_H_INV_SHFT 40
31247 #define SH_MD_DQRP_MMR_YBIST_H_INV_MASK 0x0000010000000000
31249 /* SH_MD_DQRP_MMR_YBIST_H_ROT */
31250 /* Description: rotate left data pattern in next cycle */
31251 #define SH_MD_DQRP_MMR_YBIST_H_ROT_SHFT 41
31252 #define SH_MD_DQRP_MMR_YBIST_H_ROT_MASK 0x0000020000000000
31254 /* SH_MD_DQRP_MMR_YBIST_H_ARM */
31255 /* Description: writing 1 arms data miscompare capture */
31256 #define SH_MD_DQRP_MMR_YBIST_H_ARM_SHFT 42
31257 #define SH_MD_DQRP_MMR_YBIST_H_ARM_MASK 0x0000040000000000
31259 /* ==================================================================== */
31260 /* Register "SH_MD_DQRP_MMR_YBIST_L" */
31261 /* falling edge bist/fill pattern */
31262 /* ==================================================================== */
31264 #define SH_MD_DQRP_MMR_YBIST_L 0x0000000100058810
31265 #define SH_MD_DQRP_MMR_YBIST_L_MASK 0x00000300ffffffff
31266 #define SH_MD_DQRP_MMR_YBIST_L_INIT 0x0000000000000000
31268 /* SH_MD_DQRP_MMR_YBIST_L_PAT */
31269 /* Description: data pattern */
31270 #define SH_MD_DQRP_MMR_YBIST_L_PAT_SHFT 0
31271 #define SH_MD_DQRP_MMR_YBIST_L_PAT_MASK 0x00000000ffffffff
31273 /* SH_MD_DQRP_MMR_YBIST_L_INV */
31274 /* Description: invert data pattern in next cycle */
31275 #define SH_MD_DQRP_MMR_YBIST_L_INV_SHFT 40
31276 #define SH_MD_DQRP_MMR_YBIST_L_INV_MASK 0x0000010000000000
31278 /* SH_MD_DQRP_MMR_YBIST_L_ROT */
31279 /* Description: rotate left data pattern in next cycle */
31280 #define SH_MD_DQRP_MMR_YBIST_L_ROT_SHFT 41
31281 #define SH_MD_DQRP_MMR_YBIST_L_ROT_MASK 0x0000020000000000
31283 /* ==================================================================== */
31284 /* Register "SH_MD_DQRP_MMR_YBIST_ERR_H" */
31285 /* rising edge bist error pattern */
31286 /* ==================================================================== */
31288 #define SH_MD_DQRP_MMR_YBIST_ERR_H 0x0000000100058820
31289 #define SH_MD_DQRP_MMR_YBIST_ERR_H_MASK 0x00000300ffffffff
31290 #define SH_MD_DQRP_MMR_YBIST_ERR_H_INIT 0x0000000000000000
31292 /* SH_MD_DQRP_MMR_YBIST_ERR_H_PAT */
31293 /* Description: data pattern */
31294 #define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_SHFT 0
31295 #define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_MASK 0x00000000ffffffff
31297 /* SH_MD_DQRP_MMR_YBIST_ERR_H_VAL */
31298 /* Description: bist data miscompare */
31299 #define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_SHFT 40
31300 #define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000
31302 /* SH_MD_DQRP_MMR_YBIST_ERR_H_MORE */
31303 /* Description: more than one bist data miscompare */
31304 #define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_SHFT 41
31305 #define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000
31307 /* ==================================================================== */
31308 /* Register "SH_MD_DQRP_MMR_YBIST_ERR_L" */
31309 /* falling edge bist error pattern */
31310 /* ==================================================================== */
31312 #define SH_MD_DQRP_MMR_YBIST_ERR_L 0x0000000100058830
31313 #define SH_MD_DQRP_MMR_YBIST_ERR_L_MASK 0x00000300ffffffff
31314 #define SH_MD_DQRP_MMR_YBIST_ERR_L_INIT 0x0000000000000000
31316 /* SH_MD_DQRP_MMR_YBIST_ERR_L_PAT */
31317 /* Description: data pattern */
31318 #define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_SHFT 0
31319 #define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_MASK 0x00000000ffffffff
31321 /* SH_MD_DQRP_MMR_YBIST_ERR_L_VAL */
31322 /* Description: bist data miscompare */
31323 #define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_SHFT 40
31324 #define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000
31326 /* SH_MD_DQRP_MMR_YBIST_ERR_L_MORE */
31327 /* Description: more than one bist data miscompare */
31328 #define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_SHFT 41
31329 #define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000
31331 /* ==================================================================== */
31332 /* Register "SH_MD_DQRS_MMR_XBIST_H" */
31333 /* rising edge bist/fill pattern */
31334 /* ==================================================================== */
31336 #define SH_MD_DQRS_MMR_XBIST_H 0x0000000100068000
31337 #define SH_MD_DQRS_MMR_XBIST_H_MASK 0x000007ffffffffff
31338 #define SH_MD_DQRS_MMR_XBIST_H_INIT 0x0000000000000000
31340 /* SH_MD_DQRS_MMR_XBIST_H_PAT */
31341 /* Description: data pattern */
31342 #define SH_MD_DQRS_MMR_XBIST_H_PAT_SHFT 0
31343 #define SH_MD_DQRS_MMR_XBIST_H_PAT_MASK 0x000000ffffffffff
31345 /* SH_MD_DQRS_MMR_XBIST_H_INV */
31346 /* Description: invert data pattern in next cycle */
31347 #define SH_MD_DQRS_MMR_XBIST_H_INV_SHFT 40
31348 #define SH_MD_DQRS_MMR_XBIST_H_INV_MASK 0x0000010000000000
31350 /* SH_MD_DQRS_MMR_XBIST_H_ROT */
31351 /* Description: rotate left data pattern in next cycle */
31352 #define SH_MD_DQRS_MMR_XBIST_H_ROT_SHFT 41
31353 #define SH_MD_DQRS_MMR_XBIST_H_ROT_MASK 0x0000020000000000
31355 /* SH_MD_DQRS_MMR_XBIST_H_ARM */
31356 /* Description: writing 1 arms data miscompare capture */
31357 #define SH_MD_DQRS_MMR_XBIST_H_ARM_SHFT 42
31358 #define SH_MD_DQRS_MMR_XBIST_H_ARM_MASK 0x0000040000000000
31360 /* ==================================================================== */
31361 /* Register "SH_MD_DQRS_MMR_XBIST_L" */
31362 /* falling edge bist/fill pattern */
31363 /* ==================================================================== */
31365 #define SH_MD_DQRS_MMR_XBIST_L 0x0000000100068010
31366 #define SH_MD_DQRS_MMR_XBIST_L_MASK 0x000003ffffffffff
31367 #define SH_MD_DQRS_MMR_XBIST_L_INIT 0x0000000000000000
31369 /* SH_MD_DQRS_MMR_XBIST_L_PAT */
31370 /* Description: data pattern */
31371 #define SH_MD_DQRS_MMR_XBIST_L_PAT_SHFT 0
31372 #define SH_MD_DQRS_MMR_XBIST_L_PAT_MASK 0x000000ffffffffff
31374 /* SH_MD_DQRS_MMR_XBIST_L_INV */
31375 /* Description: invert data pattern in next cycle */
31376 #define SH_MD_DQRS_MMR_XBIST_L_INV_SHFT 40
31377 #define SH_MD_DQRS_MMR_XBIST_L_INV_MASK 0x0000010000000000
31379 /* SH_MD_DQRS_MMR_XBIST_L_ROT */
31380 /* Description: rotate left data pattern in next cycle */
31381 #define SH_MD_DQRS_MMR_XBIST_L_ROT_SHFT 41
31382 #define SH_MD_DQRS_MMR_XBIST_L_ROT_MASK 0x0000020000000000
31384 /* ==================================================================== */
31385 /* Register "SH_MD_DQRS_MMR_XBIST_ERR_H" */
31386 /* rising edge bist error pattern */
31387 /* ==================================================================== */
31389 #define SH_MD_DQRS_MMR_XBIST_ERR_H 0x0000000100068020
31390 #define SH_MD_DQRS_MMR_XBIST_ERR_H_MASK 0x000003ffffffffff
31391 #define SH_MD_DQRS_MMR_XBIST_ERR_H_INIT 0x0000000000000000
31393 /* SH_MD_DQRS_MMR_XBIST_ERR_H_PAT */
31394 /* Description: data pattern */
31395 #define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_SHFT 0
31396 #define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_MASK 0x000000ffffffffff
31398 /* SH_MD_DQRS_MMR_XBIST_ERR_H_VAL */
31399 /* Description: bist data miscompare */
31400 #define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_SHFT 40
31401 #define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000
31403 /* SH_MD_DQRS_MMR_XBIST_ERR_H_MORE */
31404 /* Description: more than one bist data miscompare */
31405 #define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_SHFT 41
31406 #define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000
31408 /* ==================================================================== */
31409 /* Register "SH_MD_DQRS_MMR_XBIST_ERR_L" */
31410 /* falling edge bist error pattern */
31411 /* ==================================================================== */
31413 #define SH_MD_DQRS_MMR_XBIST_ERR_L 0x0000000100068030
31414 #define SH_MD_DQRS_MMR_XBIST_ERR_L_MASK 0x000003ffffffffff
31415 #define SH_MD_DQRS_MMR_XBIST_ERR_L_INIT 0x0000000000000000
31417 /* SH_MD_DQRS_MMR_XBIST_ERR_L_PAT */
31418 /* Description: data pattern */
31419 #define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_SHFT 0
31420 #define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_MASK 0x000000ffffffffff
31422 /* SH_MD_DQRS_MMR_XBIST_ERR_L_VAL */
31423 /* Description: bist data miscompare */
31424 #define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_SHFT 40
31425 #define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000
31427 /* SH_MD_DQRS_MMR_XBIST_ERR_L_MORE */
31428 /* Description: more than one bist data miscompare */
31429 #define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_SHFT 41
31430 #define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000
31432 /* ==================================================================== */
31433 /* Register "SH_MD_DQRS_MMR_YBIST_H" */
31434 /* rising edge bist/fill pattern */
31435 /* ==================================================================== */
31437 #define SH_MD_DQRS_MMR_YBIST_H 0x0000000100068800
31438 #define SH_MD_DQRS_MMR_YBIST_H_MASK 0x000007ffffffffff
31439 #define SH_MD_DQRS_MMR_YBIST_H_INIT 0x0000000000000000
31441 /* SH_MD_DQRS_MMR_YBIST_H_PAT */
31442 /* Description: data pattern */
31443 #define SH_MD_DQRS_MMR_YBIST_H_PAT_SHFT 0
31444 #define SH_MD_DQRS_MMR_YBIST_H_PAT_MASK 0x000000ffffffffff
31446 /* SH_MD_DQRS_MMR_YBIST_H_INV */
31447 /* Description: invert data pattern in next cycle */
31448 #define SH_MD_DQRS_MMR_YBIST_H_INV_SHFT 40
31449 #define SH_MD_DQRS_MMR_YBIST_H_INV_MASK 0x0000010000000000
31451 /* SH_MD_DQRS_MMR_YBIST_H_ROT */
31452 /* Description: rotate left data pattern in next cycle */
31453 #define SH_MD_DQRS_MMR_YBIST_H_ROT_SHFT 41
31454 #define SH_MD_DQRS_MMR_YBIST_H_ROT_MASK 0x0000020000000000
31456 /* SH_MD_DQRS_MMR_YBIST_H_ARM */
31457 /* Description: writing 1 arms data miscompare capture */
31458 #define SH_MD_DQRS_MMR_YBIST_H_ARM_SHFT 42
31459 #define SH_MD_DQRS_MMR_YBIST_H_ARM_MASK 0x0000040000000000
31461 /* ==================================================================== */
31462 /* Register "SH_MD_DQRS_MMR_YBIST_L" */
31463 /* falling edge bist/fill pattern */
31464 /* ==================================================================== */
31466 #define SH_MD_DQRS_MMR_YBIST_L 0x0000000100068810
31467 #define SH_MD_DQRS_MMR_YBIST_L_MASK 0x000003ffffffffff
31468 #define SH_MD_DQRS_MMR_YBIST_L_INIT 0x0000000000000000
31470 /* SH_MD_DQRS_MMR_YBIST_L_PAT */
31471 /* Description: data pattern */
31472 #define SH_MD_DQRS_MMR_YBIST_L_PAT_SHFT 0
31473 #define SH_MD_DQRS_MMR_YBIST_L_PAT_MASK 0x000000ffffffffff
31475 /* SH_MD_DQRS_MMR_YBIST_L_INV */
31476 /* Description: invert data pattern in next cycle */
31477 #define SH_MD_DQRS_MMR_YBIST_L_INV_SHFT 40
31478 #define SH_MD_DQRS_MMR_YBIST_L_INV_MASK 0x0000010000000000
31480 /* SH_MD_DQRS_MMR_YBIST_L_ROT */
31481 /* Description: rotate left data pattern in next cycle */
31482 #define SH_MD_DQRS_MMR_YBIST_L_ROT_SHFT 41
31483 #define SH_MD_DQRS_MMR_YBIST_L_ROT_MASK 0x0000020000000000
31485 /* ==================================================================== */
31486 /* Register "SH_MD_DQRS_MMR_YBIST_ERR_H" */
31487 /* rising edge bist error pattern */
31488 /* ==================================================================== */
31490 #define SH_MD_DQRS_MMR_YBIST_ERR_H 0x0000000100068820
31491 #define SH_MD_DQRS_MMR_YBIST_ERR_H_MASK 0x000003ffffffffff
31492 #define SH_MD_DQRS_MMR_YBIST_ERR_H_INIT 0x0000000000000000
31494 /* SH_MD_DQRS_MMR_YBIST_ERR_H_PAT */
31495 /* Description: data pattern */
31496 #define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_SHFT 0
31497 #define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_MASK 0x000000ffffffffff
31499 /* SH_MD_DQRS_MMR_YBIST_ERR_H_VAL */
31500 /* Description: bist data miscompare */
31501 #define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_SHFT 40
31502 #define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000
31504 /* SH_MD_DQRS_MMR_YBIST_ERR_H_MORE */
31505 /* Description: more than one bist data miscompare */
31506 #define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_SHFT 41
31507 #define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000
31509 /* ==================================================================== */
31510 /* Register "SH_MD_DQRS_MMR_YBIST_ERR_L" */
31511 /* falling edge bist error pattern */
31512 /* ==================================================================== */
31514 #define SH_MD_DQRS_MMR_YBIST_ERR_L 0x0000000100068830
31515 #define SH_MD_DQRS_MMR_YBIST_ERR_L_MASK 0x000003ffffffffff
31516 #define SH_MD_DQRS_MMR_YBIST_ERR_L_INIT 0x0000000000000000
31518 /* SH_MD_DQRS_MMR_YBIST_ERR_L_PAT */
31519 /* Description: data pattern */
31520 #define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_SHFT 0
31521 #define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_MASK 0x000000ffffffffff
31523 /* SH_MD_DQRS_MMR_YBIST_ERR_L_VAL */
31524 /* Description: bist data miscompare */
31525 #define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_SHFT 40
31526 #define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000
31528 /* SH_MD_DQRS_MMR_YBIST_ERR_L_MORE */
31529 /* Description: more than one bist data miscompare */
31530 #define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_SHFT 41
31531 #define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000
31533 /* ==================================================================== */
31534 /* Register "SH_MD_DQRS_MMR_JNR_DEBUG" */
31535 /* joiner/fct debug configuration */
31536 /* ==================================================================== */
31538 #define SH_MD_DQRS_MMR_JNR_DEBUG 0x0000000100069000
31539 #define SH_MD_DQRS_MMR_JNR_DEBUG_MASK 0x0000000000000003
31540 #define SH_MD_DQRS_MMR_JNR_DEBUG_INIT 0x0000000000000000
31542 /* SH_MD_DQRS_MMR_JNR_DEBUG_PX */
31543 /* Description: select 0=pi 1=xn side */
31544 #define SH_MD_DQRS_MMR_JNR_DEBUG_PX_SHFT 0
31545 #define SH_MD_DQRS_MMR_JNR_DEBUG_PX_MASK 0x0000000000000001
31547 /* SH_MD_DQRS_MMR_JNR_DEBUG_RW */
31548 /* Description: select 0=read 1=write side */
31549 #define SH_MD_DQRS_MMR_JNR_DEBUG_RW_SHFT 1
31550 #define SH_MD_DQRS_MMR_JNR_DEBUG_RW_MASK 0x0000000000000002
31552 /* ==================================================================== */
31553 /* Register "SH_MD_DQRS_MMR_YAMOPW_ERR" */
31554 /* amo/partial rmw ecc error register */
31555 /* ==================================================================== */
31557 #define SH_MD_DQRS_MMR_YAMOPW_ERR 0x000000010006a000
31558 #define SH_MD_DQRS_MMR_YAMOPW_ERR_MASK 0x0000000103ff03ff
31559 #define SH_MD_DQRS_MMR_YAMOPW_ERR_INIT 0x0000000000000000
31561 /* SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN */
31562 /* Description: store data syndrome */
31563 #define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_SHFT 0
31564 #define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_MASK 0x00000000000000ff
31566 /* SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR */
31567 /* Description: correctable ecc errror on store data */
31568 #define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_SHFT 8
31569 #define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_MASK 0x0000000000000100
31571 /* SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC */
31572 /* Description: uncorrectable ecc errror on store data */
31573 #define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_SHFT 9
31574 #define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_MASK 0x0000000000000200
31576 /* SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN */
31577 /* Description: memory read data syndrome */
31578 #define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_SHFT 16
31579 #define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_MASK 0x0000000000ff0000
31581 /* SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR */
31582 /* Description: correctable ecc errror on read data */
31583 #define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_SHFT 24
31584 #define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_MASK 0x0000000001000000
31586 /* SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC */
31587 /* Description: uncorrectable ecc errror on read data */
31588 #define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_SHFT 25
31589 #define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_MASK 0x0000000002000000
31591 /* SH_MD_DQRS_MMR_YAMOPW_ERR_ARM */
31592 /* Description: writing 1 arms ecc error capture */
31593 #define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_SHFT 32
31594 #define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_MASK 0x0000000100000000
31597 #endif /* _ASM_IA64_SN_SN2_SHUB_MMR_H */