3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved.
10 #ifndef _ASM_IA64_SN_SN2_SHUB_MMR_T_H
11 #define _ASM_IA64_SN_SN2_SHUB_MMR_T_H
13 #include <asm/sn/arch.h>
15 /* ==================================================================== */
16 /* Register "SH_FSB_BINIT_CONTROL" */
17 /* FSB BINIT# Control */
18 /* ==================================================================== */
20 typedef union sh_fsb_binit_control_u {
21 mmr_t sh_fsb_binit_control_regval;
24 mmr_t reserved_0 : 63;
25 } sh_fsb_binit_control_s;
26 } sh_fsb_binit_control_u_t;
28 /* ==================================================================== */
29 /* Register "SH_FSB_RESET_CONTROL" */
30 /* FSB Reset Control */
31 /* ==================================================================== */
33 typedef union sh_fsb_reset_control_u {
34 mmr_t sh_fsb_reset_control_regval;
37 mmr_t reserved_0 : 63;
38 } sh_fsb_reset_control_s;
39 } sh_fsb_reset_control_u_t;
41 /* ==================================================================== */
42 /* Register "SH_FSB_SYSTEM_AGENT_CONFIG" */
43 /* FSB System Agent Configuration */
44 /* ==================================================================== */
46 typedef union sh_fsb_system_agent_config_u {
47 mmr_t sh_fsb_system_agent_config_regval;
49 mmr_t rcnt_scnt_en : 1;
51 mmr_t berr_assert_en : 1;
52 mmr_t berr_sampling_en : 1;
53 mmr_t binit_assert_en : 1;
54 mmr_t bnr_throttling_en : 1;
55 mmr_t short_hang_en : 1;
56 mmr_t inta_rsp_data : 8;
57 mmr_t io_trans_rsp : 1;
58 mmr_t xtpr_trans_rsp : 1;
59 mmr_t inta_trans_rsp : 1;
62 mmr_t serialize_fsb_en : 1;
64 mmr_t binit_event_enables : 14;
65 mmr_t reserved_3 : 18;
66 } sh_fsb_system_agent_config_s;
67 } sh_fsb_system_agent_config_u_t;
69 /* ==================================================================== */
70 /* Register "SH_FSB_VGA_REMAP" */
71 /* FSB VGA Address Space Remap */
72 /* ==================================================================== */
74 typedef union sh_fsb_vga_remap_u {
75 mmr_t sh_fsb_vga_remap_regval;
77 mmr_t reserved_0 : 17;
81 mmr_t reserved_1 : 13;
82 mmr_t vga_remapping_enabled : 1;
85 } sh_fsb_vga_remap_u_t;
87 /* ==================================================================== */
88 /* Register "SH_FSB_RESET_STATUS" */
89 /* FSB Reset Status */
90 /* ==================================================================== */
92 typedef union sh_fsb_reset_status_u {
93 mmr_t sh_fsb_reset_status_regval;
95 mmr_t reset_in_progress : 1;
96 mmr_t reserved_0 : 63;
97 } sh_fsb_reset_status_s;
98 } sh_fsb_reset_status_u_t;
100 /* ==================================================================== */
101 /* Register "SH_FSB_SYMMETRIC_AGENT_STATUS" */
102 /* FSB Symmetric Agent Status */
103 /* ==================================================================== */
105 typedef union sh_fsb_symmetric_agent_status_u {
106 mmr_t sh_fsb_symmetric_agent_status_regval;
108 mmr_t cpu_0_active : 1;
109 mmr_t cpu_1_active : 1;
110 mmr_t cpus_ready : 1;
111 mmr_t reserved_0 : 61;
112 } sh_fsb_symmetric_agent_status_s;
113 } sh_fsb_symmetric_agent_status_u_t;
115 /* ==================================================================== */
116 /* Register "SH_GFX_CREDIT_COUNT_0" */
117 /* Graphics-write Credit Count for CPU 0 */
118 /* ==================================================================== */
120 typedef union sh_gfx_credit_count_0_u {
121 mmr_t sh_gfx_credit_count_0_regval;
124 mmr_t reserved_0 : 43;
125 mmr_t reset_gfx_state : 1;
126 } sh_gfx_credit_count_0_s;
127 } sh_gfx_credit_count_0_u_t;
129 /* ==================================================================== */
130 /* Register "SH_GFX_CREDIT_COUNT_1" */
131 /* Graphics-write Credit Count for CPU 1 */
132 /* ==================================================================== */
134 typedef union sh_gfx_credit_count_1_u {
135 mmr_t sh_gfx_credit_count_1_regval;
138 mmr_t reserved_0 : 43;
139 mmr_t reset_gfx_state : 1;
140 } sh_gfx_credit_count_1_s;
141 } sh_gfx_credit_count_1_u_t;
143 /* ==================================================================== */
144 /* Register "SH_GFX_MODE_CNTRL_0" */
145 /* Graphics credit mode amd message ordering for CPU 0 */
146 /* ==================================================================== */
148 typedef union sh_gfx_mode_cntrl_0_u {
149 mmr_t sh_gfx_mode_cntrl_0_regval;
151 mmr_t dword_credits : 1;
152 mmr_t mixed_mode_credits : 1;
153 mmr_t relaxed_ordering : 1;
154 mmr_t reserved_0 : 61;
155 } sh_gfx_mode_cntrl_0_s;
156 } sh_gfx_mode_cntrl_0_u_t;
158 /* ==================================================================== */
159 /* Register "SH_GFX_MODE_CNTRL_1" */
160 /* Graphics credit mode amd message ordering for CPU 1 */
161 /* ==================================================================== */
163 typedef union sh_gfx_mode_cntrl_1_u {
164 mmr_t sh_gfx_mode_cntrl_1_regval;
166 mmr_t dword_credits : 1;
167 mmr_t mixed_mode_credits : 1;
168 mmr_t relaxed_ordering : 1;
169 mmr_t reserved_0 : 61;
170 } sh_gfx_mode_cntrl_1_s;
171 } sh_gfx_mode_cntrl_1_u_t;
173 /* ==================================================================== */
174 /* Register "SH_GFX_SKID_CREDIT_COUNT_0" */
175 /* Graphics-write Skid Credit Count for CPU 0 */
176 /* ==================================================================== */
178 typedef union sh_gfx_skid_credit_count_0_u {
179 mmr_t sh_gfx_skid_credit_count_0_regval;
182 mmr_t reserved_0 : 44;
183 } sh_gfx_skid_credit_count_0_s;
184 } sh_gfx_skid_credit_count_0_u_t;
186 /* ==================================================================== */
187 /* Register "SH_GFX_SKID_CREDIT_COUNT_1" */
188 /* Graphics-write Skid Credit Count for CPU 1 */
189 /* ==================================================================== */
191 typedef union sh_gfx_skid_credit_count_1_u {
192 mmr_t sh_gfx_skid_credit_count_1_regval;
195 mmr_t reserved_0 : 44;
196 } sh_gfx_skid_credit_count_1_s;
197 } sh_gfx_skid_credit_count_1_u_t;
199 /* ==================================================================== */
200 /* Register "SH_GFX_STALL_LIMIT_0" */
201 /* Graphics-write Stall Limit for CPU 0 */
202 /* ==================================================================== */
204 typedef union sh_gfx_stall_limit_0_u {
205 mmr_t sh_gfx_stall_limit_0_regval;
208 mmr_t reserved_0 : 38;
209 } sh_gfx_stall_limit_0_s;
210 } sh_gfx_stall_limit_0_u_t;
212 /* ==================================================================== */
213 /* Register "SH_GFX_STALL_LIMIT_1" */
214 /* Graphics-write Stall Limit for CPU 1 */
215 /* ==================================================================== */
217 typedef union sh_gfx_stall_limit_1_u {
218 mmr_t sh_gfx_stall_limit_1_regval;
221 mmr_t reserved_0 : 38;
222 } sh_gfx_stall_limit_1_s;
223 } sh_gfx_stall_limit_1_u_t;
225 /* ==================================================================== */
226 /* Register "SH_GFX_STALL_TIMER_0" */
227 /* Graphics-write Stall Timer for CPU 0 */
228 /* ==================================================================== */
230 typedef union sh_gfx_stall_timer_0_u {
231 mmr_t sh_gfx_stall_timer_0_regval;
233 mmr_t timer_value : 26;
234 mmr_t reserved_0 : 38;
235 } sh_gfx_stall_timer_0_s;
236 } sh_gfx_stall_timer_0_u_t;
238 /* ==================================================================== */
239 /* Register "SH_GFX_STALL_TIMER_1" */
240 /* Graphics-write Stall Timer for CPU 1 */
241 /* ==================================================================== */
243 typedef union sh_gfx_stall_timer_1_u {
244 mmr_t sh_gfx_stall_timer_1_regval;
246 mmr_t timer_value : 26;
247 mmr_t reserved_0 : 38;
248 } sh_gfx_stall_timer_1_s;
249 } sh_gfx_stall_timer_1_u_t;
251 /* ==================================================================== */
252 /* Register "SH_GFX_WINDOW_0" */
253 /* Graphics-write Window for CPU 0 */
254 /* ==================================================================== */
256 typedef union sh_gfx_window_0_u {
257 mmr_t sh_gfx_window_0_regval;
259 mmr_t reserved_0 : 24;
260 mmr_t base_addr : 12;
261 mmr_t reserved_1 : 27;
262 mmr_t gfx_window_en : 1;
264 } sh_gfx_window_0_u_t;
266 /* ==================================================================== */
267 /* Register "SH_GFX_WINDOW_1" */
268 /* Graphics-write Window for CPU 1 */
269 /* ==================================================================== */
271 typedef union sh_gfx_window_1_u {
272 mmr_t sh_gfx_window_1_regval;
274 mmr_t reserved_0 : 24;
275 mmr_t base_addr : 12;
276 mmr_t reserved_1 : 27;
277 mmr_t gfx_window_en : 1;
279 } sh_gfx_window_1_u_t;
281 /* ==================================================================== */
282 /* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0" */
283 /* Graphics-write Interrupt Limit for CPU 0 */
284 /* ==================================================================== */
286 typedef union sh_gfx_interrupt_timer_limit_0_u {
287 mmr_t sh_gfx_interrupt_timer_limit_0_regval;
289 mmr_t interrupt_timer_limit : 8;
290 mmr_t reserved_0 : 56;
291 } sh_gfx_interrupt_timer_limit_0_s;
292 } sh_gfx_interrupt_timer_limit_0_u_t;
294 /* ==================================================================== */
295 /* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1" */
296 /* Graphics-write Interrupt Limit for CPU 1 */
297 /* ==================================================================== */
299 typedef union sh_gfx_interrupt_timer_limit_1_u {
300 mmr_t sh_gfx_interrupt_timer_limit_1_regval;
302 mmr_t interrupt_timer_limit : 8;
303 mmr_t reserved_0 : 56;
304 } sh_gfx_interrupt_timer_limit_1_s;
305 } sh_gfx_interrupt_timer_limit_1_u_t;
307 /* ==================================================================== */
308 /* Register "SH_GFX_WRITE_STATUS_0" */
309 /* Graphics Write Status for CPU 0 */
310 /* ==================================================================== */
312 typedef union sh_gfx_write_status_0_u {
313 mmr_t sh_gfx_write_status_0_regval;
316 mmr_t reserved_0 : 62;
317 mmr_t re_enable_gfx_stall : 1;
318 } sh_gfx_write_status_0_s;
319 } sh_gfx_write_status_0_u_t;
321 /* ==================================================================== */
322 /* Register "SH_GFX_WRITE_STATUS_1" */
323 /* Graphics Write Status for CPU 1 */
324 /* ==================================================================== */
326 typedef union sh_gfx_write_status_1_u {
327 mmr_t sh_gfx_write_status_1_regval;
330 mmr_t reserved_0 : 62;
331 mmr_t re_enable_gfx_stall : 1;
332 } sh_gfx_write_status_1_s;
333 } sh_gfx_write_status_1_u_t;
335 /* ==================================================================== */
336 /* Register "SH_II_INT0" */
337 /* SHub II Interrupt 0 Registers */
338 /* ==================================================================== */
340 typedef union sh_ii_int0_u {
341 mmr_t sh_ii_int0_regval;
345 mmr_t reserved_0 : 55;
349 /* ==================================================================== */
350 /* Register "SH_II_INT0_CONFIG" */
351 /* SHub II Interrupt 0 Config Registers */
352 /* ==================================================================== */
354 typedef union sh_ii_int0_config_u {
355 mmr_t sh_ii_int0_config_regval;
360 mmr_t reserved_0 : 1;
362 mmr_t reserved_1 : 14;
363 } sh_ii_int0_config_s;
364 } sh_ii_int0_config_u_t;
366 /* ==================================================================== */
367 /* Register "SH_II_INT0_ENABLE" */
368 /* SHub II Interrupt 0 Enable Registers */
369 /* ==================================================================== */
371 typedef union sh_ii_int0_enable_u {
372 mmr_t sh_ii_int0_enable_regval;
375 mmr_t reserved_0 : 63;
376 } sh_ii_int0_enable_s;
377 } sh_ii_int0_enable_u_t;
379 /* ==================================================================== */
380 /* Register "SH_II_INT1" */
381 /* SHub II Interrupt 1 Registers */
382 /* ==================================================================== */
384 typedef union sh_ii_int1_u {
385 mmr_t sh_ii_int1_regval;
389 mmr_t reserved_0 : 55;
393 /* ==================================================================== */
394 /* Register "SH_II_INT1_CONFIG" */
395 /* SHub II Interrupt 1 Config Registers */
396 /* ==================================================================== */
398 typedef union sh_ii_int1_config_u {
399 mmr_t sh_ii_int1_config_regval;
404 mmr_t reserved_0 : 1;
406 mmr_t reserved_1 : 14;
407 } sh_ii_int1_config_s;
408 } sh_ii_int1_config_u_t;
410 /* ==================================================================== */
411 /* Register "SH_II_INT1_ENABLE" */
412 /* SHub II Interrupt 1 Enable Registers */
413 /* ==================================================================== */
415 typedef union sh_ii_int1_enable_u {
416 mmr_t sh_ii_int1_enable_regval;
419 mmr_t reserved_0 : 63;
420 } sh_ii_int1_enable_s;
421 } sh_ii_int1_enable_u_t;
423 /* ==================================================================== */
424 /* Register "SH_INT_NODE_ID_CONFIG" */
425 /* SHub Interrupt Node ID Configuration */
426 /* ==================================================================== */
428 typedef union sh_int_node_id_config_u {
429 mmr_t sh_int_node_id_config_regval;
433 mmr_t reserved_0 : 52;
434 } sh_int_node_id_config_s;
435 } sh_int_node_id_config_u_t;
437 /* ==================================================================== */
438 /* Register "SH_IPI_INT" */
439 /* SHub Inter-Processor Interrupt Registers */
440 /* ==================================================================== */
442 typedef union sh_ipi_int_u {
443 mmr_t sh_ipi_int_regval;
448 mmr_t reserved_0 : 1;
450 mmr_t reserved_1 : 2;
452 mmr_t reserved_2 : 3;
457 /* ==================================================================== */
458 /* Register "SH_IPI_INT_ENABLE" */
459 /* SHub Inter-Processor Interrupt Enable Registers */
460 /* ==================================================================== */
462 typedef union sh_ipi_int_enable_u {
463 mmr_t sh_ipi_int_enable_regval;
465 mmr_t pio_enable : 1;
466 mmr_t reserved_0 : 63;
467 } sh_ipi_int_enable_s;
468 } sh_ipi_int_enable_u_t;
470 /* ==================================================================== */
471 /* Register "SH_LOCAL_INT0_CONFIG" */
472 /* SHub Local Interrupt 0 Registers */
473 /* ==================================================================== */
475 typedef union sh_local_int0_config_u {
476 mmr_t sh_local_int0_config_regval;
481 mmr_t reserved_0 : 1;
483 mmr_t reserved_1 : 2;
485 mmr_t reserved_2 : 4;
486 } sh_local_int0_config_s;
487 } sh_local_int0_config_u_t;
489 /* ==================================================================== */
490 /* Register "SH_LOCAL_INT0_ENABLE" */
491 /* SHub Local Interrupt 0 Enable */
492 /* ==================================================================== */
494 typedef union sh_local_int0_enable_u {
495 mmr_t sh_local_int0_enable_regval;
505 mmr_t pi_uce_int : 1;
506 mmr_t md_uce_int : 1;
507 mmr_t xn_uce_int : 1;
508 mmr_t reserved_0 : 1;
509 mmr_t system_shutdown_int : 1;
511 mmr_t l1_nmi_int : 1;
512 mmr_t stop_clock : 1;
513 mmr_t reserved_1 : 48;
514 } sh_local_int0_enable_s;
515 } sh_local_int0_enable_u_t;
517 /* ==================================================================== */
518 /* Register "SH_LOCAL_INT1_CONFIG" */
519 /* SHub Local Interrupt 1 Registers */
520 /* ==================================================================== */
522 typedef union sh_local_int1_config_u {
523 mmr_t sh_local_int1_config_regval;
528 mmr_t reserved_0 : 1;
530 mmr_t reserved_1 : 2;
532 mmr_t reserved_2 : 4;
533 } sh_local_int1_config_s;
534 } sh_local_int1_config_u_t;
536 /* ==================================================================== */
537 /* Register "SH_LOCAL_INT1_ENABLE" */
538 /* SHub Local Interrupt 1 Enable */
539 /* ==================================================================== */
541 typedef union sh_local_int1_enable_u {
542 mmr_t sh_local_int1_enable_regval;
552 mmr_t pi_uce_int : 1;
553 mmr_t md_uce_int : 1;
554 mmr_t xn_uce_int : 1;
555 mmr_t reserved_0 : 1;
556 mmr_t system_shutdown_int : 1;
558 mmr_t l1_nmi_int : 1;
559 mmr_t stop_clock : 1;
560 mmr_t reserved_1 : 48;
561 } sh_local_int1_enable_s;
562 } sh_local_int1_enable_u_t;
564 /* ==================================================================== */
565 /* Register "SH_LOCAL_INT2_CONFIG" */
566 /* SHub Local Interrupt 2 Registers */
567 /* ==================================================================== */
569 typedef union sh_local_int2_config_u {
570 mmr_t sh_local_int2_config_regval;
575 mmr_t reserved_0 : 1;
577 mmr_t reserved_1 : 2;
579 mmr_t reserved_2 : 4;
580 } sh_local_int2_config_s;
581 } sh_local_int2_config_u_t;
583 /* ==================================================================== */
584 /* Register "SH_LOCAL_INT2_ENABLE" */
585 /* SHub Local Interrupt 2 Enable */
586 /* ==================================================================== */
588 typedef union sh_local_int2_enable_u {
589 mmr_t sh_local_int2_enable_regval;
599 mmr_t pi_uce_int : 1;
600 mmr_t md_uce_int : 1;
601 mmr_t xn_uce_int : 1;
602 mmr_t reserved_0 : 1;
603 mmr_t system_shutdown_int : 1;
605 mmr_t l1_nmi_int : 1;
606 mmr_t stop_clock : 1;
607 mmr_t reserved_1 : 48;
608 } sh_local_int2_enable_s;
609 } sh_local_int2_enable_u_t;
611 /* ==================================================================== */
612 /* Register "SH_LOCAL_INT3_CONFIG" */
613 /* SHub Local Interrupt 3 Registers */
614 /* ==================================================================== */
616 typedef union sh_local_int3_config_u {
617 mmr_t sh_local_int3_config_regval;
622 mmr_t reserved_0 : 1;
624 mmr_t reserved_1 : 2;
626 mmr_t reserved_2 : 4;
627 } sh_local_int3_config_s;
628 } sh_local_int3_config_u_t;
630 /* ==================================================================== */
631 /* Register "SH_LOCAL_INT3_ENABLE" */
632 /* SHub Local Interrupt 3 Enable */
633 /* ==================================================================== */
635 typedef union sh_local_int3_enable_u {
636 mmr_t sh_local_int3_enable_regval;
646 mmr_t pi_uce_int : 1;
647 mmr_t md_uce_int : 1;
648 mmr_t xn_uce_int : 1;
649 mmr_t reserved_0 : 1;
650 mmr_t system_shutdown_int : 1;
652 mmr_t l1_nmi_int : 1;
653 mmr_t stop_clock : 1;
654 mmr_t reserved_1 : 48;
655 } sh_local_int3_enable_s;
656 } sh_local_int3_enable_u_t;
658 /* ==================================================================== */
659 /* Register "SH_LOCAL_INT4_CONFIG" */
660 /* SHub Local Interrupt 4 Registers */
661 /* ==================================================================== */
663 typedef union sh_local_int4_config_u {
664 mmr_t sh_local_int4_config_regval;
669 mmr_t reserved_0 : 1;
671 mmr_t reserved_1 : 2;
673 mmr_t reserved_2 : 4;
674 } sh_local_int4_config_s;
675 } sh_local_int4_config_u_t;
677 /* ==================================================================== */
678 /* Register "SH_LOCAL_INT4_ENABLE" */
679 /* SHub Local Interrupt 4 Enable */
680 /* ==================================================================== */
682 typedef union sh_local_int4_enable_u {
683 mmr_t sh_local_int4_enable_regval;
693 mmr_t pi_uce_int : 1;
694 mmr_t md_uce_int : 1;
695 mmr_t xn_uce_int : 1;
696 mmr_t reserved_0 : 1;
697 mmr_t system_shutdown_int : 1;
699 mmr_t l1_nmi_int : 1;
700 mmr_t stop_clock : 1;
701 mmr_t reserved_1 : 48;
702 } sh_local_int4_enable_s;
703 } sh_local_int4_enable_u_t;
705 /* ==================================================================== */
706 /* Register "SH_LOCAL_INT5_CONFIG" */
707 /* SHub Local Interrupt 5 Registers */
708 /* ==================================================================== */
710 typedef union sh_local_int5_config_u {
711 mmr_t sh_local_int5_config_regval;
716 mmr_t reserved_0 : 1;
718 mmr_t reserved_1 : 2;
720 mmr_t reserved_2 : 4;
721 } sh_local_int5_config_s;
722 } sh_local_int5_config_u_t;
724 /* ==================================================================== */
725 /* Register "SH_LOCAL_INT5_ENABLE" */
726 /* SHub Local Interrupt 5 Enable */
727 /* ==================================================================== */
729 typedef union sh_local_int5_enable_u {
730 mmr_t sh_local_int5_enable_regval;
740 mmr_t pi_uce_int : 1;
741 mmr_t md_uce_int : 1;
742 mmr_t xn_uce_int : 1;
743 mmr_t reserved_0 : 1;
744 mmr_t system_shutdown_int : 1;
746 mmr_t l1_nmi_int : 1;
747 mmr_t stop_clock : 1;
748 mmr_t reserved_1 : 48;
749 } sh_local_int5_enable_s;
750 } sh_local_int5_enable_u_t;
752 /* ==================================================================== */
753 /* Register "SH_PROC0_ERR_INT_CONFIG" */
754 /* SHub Processor 0 Error Interrupt Registers */
755 /* ==================================================================== */
757 typedef union sh_proc0_err_int_config_u {
758 mmr_t sh_proc0_err_int_config_regval;
763 mmr_t reserved_0 : 1;
765 mmr_t reserved_1 : 2;
767 mmr_t reserved_2 : 4;
768 } sh_proc0_err_int_config_s;
769 } sh_proc0_err_int_config_u_t;
771 /* ==================================================================== */
772 /* Register "SH_PROC1_ERR_INT_CONFIG" */
773 /* SHub Processor 1 Error Interrupt Registers */
774 /* ==================================================================== */
776 typedef union sh_proc1_err_int_config_u {
777 mmr_t sh_proc1_err_int_config_regval;
782 mmr_t reserved_0 : 1;
784 mmr_t reserved_1 : 2;
786 mmr_t reserved_2 : 4;
787 } sh_proc1_err_int_config_s;
788 } sh_proc1_err_int_config_u_t;
790 /* ==================================================================== */
791 /* Register "SH_PROC2_ERR_INT_CONFIG" */
792 /* SHub Processor 2 Error Interrupt Registers */
793 /* ==================================================================== */
795 typedef union sh_proc2_err_int_config_u {
796 mmr_t sh_proc2_err_int_config_regval;
801 mmr_t reserved_0 : 1;
803 mmr_t reserved_1 : 2;
805 mmr_t reserved_2 : 4;
806 } sh_proc2_err_int_config_s;
807 } sh_proc2_err_int_config_u_t;
809 /* ==================================================================== */
810 /* Register "SH_PROC3_ERR_INT_CONFIG" */
811 /* SHub Processor 3 Error Interrupt Registers */
812 /* ==================================================================== */
814 typedef union sh_proc3_err_int_config_u {
815 mmr_t sh_proc3_err_int_config_regval;
820 mmr_t reserved_0 : 1;
822 mmr_t reserved_1 : 2;
824 mmr_t reserved_2 : 4;
825 } sh_proc3_err_int_config_s;
826 } sh_proc3_err_int_config_u_t;
828 /* ==================================================================== */
829 /* Register "SH_PROC0_ADV_INT_CONFIG" */
830 /* SHub Processor 0 Advisory Interrupt Registers */
831 /* ==================================================================== */
833 typedef union sh_proc0_adv_int_config_u {
834 mmr_t sh_proc0_adv_int_config_regval;
839 mmr_t reserved_0 : 1;
841 mmr_t reserved_1 : 2;
843 mmr_t reserved_2 : 4;
844 } sh_proc0_adv_int_config_s;
845 } sh_proc0_adv_int_config_u_t;
847 /* ==================================================================== */
848 /* Register "SH_PROC1_ADV_INT_CONFIG" */
849 /* SHub Processor 1 Advisory Interrupt Registers */
850 /* ==================================================================== */
852 typedef union sh_proc1_adv_int_config_u {
853 mmr_t sh_proc1_adv_int_config_regval;
858 mmr_t reserved_0 : 1;
860 mmr_t reserved_1 : 2;
862 mmr_t reserved_2 : 4;
863 } sh_proc1_adv_int_config_s;
864 } sh_proc1_adv_int_config_u_t;
866 /* ==================================================================== */
867 /* Register "SH_PROC2_ADV_INT_CONFIG" */
868 /* SHub Processor 2 Advisory Interrupt Registers */
869 /* ==================================================================== */
871 typedef union sh_proc2_adv_int_config_u {
872 mmr_t sh_proc2_adv_int_config_regval;
877 mmr_t reserved_0 : 1;
879 mmr_t reserved_1 : 2;
881 mmr_t reserved_2 : 4;
882 } sh_proc2_adv_int_config_s;
883 } sh_proc2_adv_int_config_u_t;
885 /* ==================================================================== */
886 /* Register "SH_PROC3_ADV_INT_CONFIG" */
887 /* SHub Processor 3 Advisory Interrupt Registers */
888 /* ==================================================================== */
890 typedef union sh_proc3_adv_int_config_u {
891 mmr_t sh_proc3_adv_int_config_regval;
896 mmr_t reserved_0 : 1;
898 mmr_t reserved_1 : 2;
900 mmr_t reserved_2 : 4;
901 } sh_proc3_adv_int_config_s;
902 } sh_proc3_adv_int_config_u_t;
904 /* ==================================================================== */
905 /* Register "SH_PROC0_ERR_INT_ENABLE" */
906 /* SHub Processor 0 Error Interrupt Enable Registers */
907 /* ==================================================================== */
909 typedef union sh_proc0_err_int_enable_u {
910 mmr_t sh_proc0_err_int_enable_regval;
912 mmr_t proc0_err_enable : 1;
913 mmr_t reserved_0 : 63;
914 } sh_proc0_err_int_enable_s;
915 } sh_proc0_err_int_enable_u_t;
917 /* ==================================================================== */
918 /* Register "SH_PROC1_ERR_INT_ENABLE" */
919 /* SHub Processor 1 Error Interrupt Enable Registers */
920 /* ==================================================================== */
922 typedef union sh_proc1_err_int_enable_u {
923 mmr_t sh_proc1_err_int_enable_regval;
925 mmr_t proc1_err_enable : 1;
926 mmr_t reserved_0 : 63;
927 } sh_proc1_err_int_enable_s;
928 } sh_proc1_err_int_enable_u_t;
930 /* ==================================================================== */
931 /* Register "SH_PROC2_ERR_INT_ENABLE" */
932 /* SHub Processor 2 Error Interrupt Enable Registers */
933 /* ==================================================================== */
935 typedef union sh_proc2_err_int_enable_u {
936 mmr_t sh_proc2_err_int_enable_regval;
938 mmr_t proc2_err_enable : 1;
939 mmr_t reserved_0 : 63;
940 } sh_proc2_err_int_enable_s;
941 } sh_proc2_err_int_enable_u_t;
943 /* ==================================================================== */
944 /* Register "SH_PROC3_ERR_INT_ENABLE" */
945 /* SHub Processor 3 Error Interrupt Enable Registers */
946 /* ==================================================================== */
948 typedef union sh_proc3_err_int_enable_u {
949 mmr_t sh_proc3_err_int_enable_regval;
951 mmr_t proc3_err_enable : 1;
952 mmr_t reserved_0 : 63;
953 } sh_proc3_err_int_enable_s;
954 } sh_proc3_err_int_enable_u_t;
956 /* ==================================================================== */
957 /* Register "SH_PROC0_ADV_INT_ENABLE" */
958 /* SHub Processor 0 Advisory Interrupt Enable Registers */
959 /* ==================================================================== */
961 typedef union sh_proc0_adv_int_enable_u {
962 mmr_t sh_proc0_adv_int_enable_regval;
964 mmr_t proc0_adv_enable : 1;
965 mmr_t reserved_0 : 63;
966 } sh_proc0_adv_int_enable_s;
967 } sh_proc0_adv_int_enable_u_t;
969 /* ==================================================================== */
970 /* Register "SH_PROC1_ADV_INT_ENABLE" */
971 /* SHub Processor 1 Advisory Interrupt Enable Registers */
972 /* ==================================================================== */
974 typedef union sh_proc1_adv_int_enable_u {
975 mmr_t sh_proc1_adv_int_enable_regval;
977 mmr_t proc1_adv_enable : 1;
978 mmr_t reserved_0 : 63;
979 } sh_proc1_adv_int_enable_s;
980 } sh_proc1_adv_int_enable_u_t;
982 /* ==================================================================== */
983 /* Register "SH_PROC2_ADV_INT_ENABLE" */
984 /* SHub Processor 2 Advisory Interrupt Enable Registers */
985 /* ==================================================================== */
987 typedef union sh_proc2_adv_int_enable_u {
988 mmr_t sh_proc2_adv_int_enable_regval;
990 mmr_t proc2_adv_enable : 1;
991 mmr_t reserved_0 : 63;
992 } sh_proc2_adv_int_enable_s;
993 } sh_proc2_adv_int_enable_u_t;
995 /* ==================================================================== */
996 /* Register "SH_PROC3_ADV_INT_ENABLE" */
997 /* SHub Processor 3 Advisory Interrupt Enable Registers */
998 /* ==================================================================== */
1000 typedef union sh_proc3_adv_int_enable_u {
1001 mmr_t sh_proc3_adv_int_enable_regval;
1003 mmr_t proc3_adv_enable : 1;
1004 mmr_t reserved_0 : 63;
1005 } sh_proc3_adv_int_enable_s;
1006 } sh_proc3_adv_int_enable_u_t;
1008 /* ==================================================================== */
1009 /* Register "SH_PROFILE_INT_CONFIG" */
1010 /* SHub Profile Interrupt Configuration Registers */
1011 /* ==================================================================== */
1013 typedef union sh_profile_int_config_u {
1014 mmr_t sh_profile_int_config_regval;
1019 mmr_t reserved_0 : 1;
1021 mmr_t reserved_1 : 2;
1023 mmr_t reserved_2 : 4;
1024 } sh_profile_int_config_s;
1025 } sh_profile_int_config_u_t;
1027 /* ==================================================================== */
1028 /* Register "SH_PROFILE_INT_ENABLE" */
1029 /* SHub Profile Interrupt Enable Registers */
1030 /* ==================================================================== */
1032 typedef union sh_profile_int_enable_u {
1033 mmr_t sh_profile_int_enable_regval;
1035 mmr_t profile_enable : 1;
1036 mmr_t reserved_0 : 63;
1037 } sh_profile_int_enable_s;
1038 } sh_profile_int_enable_u_t;
1040 /* ==================================================================== */
1041 /* Register "SH_RTC0_INT_CONFIG" */
1042 /* SHub RTC 0 Interrupt Config Registers */
1043 /* ==================================================================== */
1045 typedef union sh_rtc0_int_config_u {
1046 mmr_t sh_rtc0_int_config_regval;
1051 mmr_t reserved_0 : 1;
1053 mmr_t reserved_1 : 2;
1055 mmr_t reserved_2 : 4;
1056 } sh_rtc0_int_config_s;
1057 } sh_rtc0_int_config_u_t;
1059 /* ==================================================================== */
1060 /* Register "SH_RTC0_INT_ENABLE" */
1061 /* SHub RTC 0 Interrupt Enable Registers */
1062 /* ==================================================================== */
1064 typedef union sh_rtc0_int_enable_u {
1065 mmr_t sh_rtc0_int_enable_regval;
1067 mmr_t rtc0_enable : 1;
1068 mmr_t reserved_0 : 63;
1069 } sh_rtc0_int_enable_s;
1070 } sh_rtc0_int_enable_u_t;
1072 /* ==================================================================== */
1073 /* Register "SH_RTC1_INT_CONFIG" */
1074 /* SHub RTC 1 Interrupt Config Registers */
1075 /* ==================================================================== */
1077 typedef union sh_rtc1_int_config_u {
1078 mmr_t sh_rtc1_int_config_regval;
1083 mmr_t reserved_0 : 1;
1085 mmr_t reserved_1 : 2;
1087 mmr_t reserved_2 : 4;
1088 } sh_rtc1_int_config_s;
1089 } sh_rtc1_int_config_u_t;
1091 /* ==================================================================== */
1092 /* Register "SH_RTC1_INT_ENABLE" */
1093 /* SHub RTC 1 Interrupt Enable Registers */
1094 /* ==================================================================== */
1096 typedef union sh_rtc1_int_enable_u {
1097 mmr_t sh_rtc1_int_enable_regval;
1099 mmr_t rtc1_enable : 1;
1100 mmr_t reserved_0 : 63;
1101 } sh_rtc1_int_enable_s;
1102 } sh_rtc1_int_enable_u_t;
1104 /* ==================================================================== */
1105 /* Register "SH_RTC2_INT_CONFIG" */
1106 /* SHub RTC 2 Interrupt Config Registers */
1107 /* ==================================================================== */
1109 typedef union sh_rtc2_int_config_u {
1110 mmr_t sh_rtc2_int_config_regval;
1115 mmr_t reserved_0 : 1;
1117 mmr_t reserved_1 : 2;
1119 mmr_t reserved_2 : 4;
1120 } sh_rtc2_int_config_s;
1121 } sh_rtc2_int_config_u_t;
1123 /* ==================================================================== */
1124 /* Register "SH_RTC2_INT_ENABLE" */
1125 /* SHub RTC 2 Interrupt Enable Registers */
1126 /* ==================================================================== */
1128 typedef union sh_rtc2_int_enable_u {
1129 mmr_t sh_rtc2_int_enable_regval;
1131 mmr_t rtc2_enable : 1;
1132 mmr_t reserved_0 : 63;
1133 } sh_rtc2_int_enable_s;
1134 } sh_rtc2_int_enable_u_t;
1136 /* ==================================================================== */
1137 /* Register "SH_RTC3_INT_CONFIG" */
1138 /* SHub RTC 3 Interrupt Config Registers */
1139 /* ==================================================================== */
1141 typedef union sh_rtc3_int_config_u {
1142 mmr_t sh_rtc3_int_config_regval;
1147 mmr_t reserved_0 : 1;
1149 mmr_t reserved_1 : 2;
1151 mmr_t reserved_2 : 4;
1152 } sh_rtc3_int_config_s;
1153 } sh_rtc3_int_config_u_t;
1155 /* ==================================================================== */
1156 /* Register "SH_RTC3_INT_ENABLE" */
1157 /* SHub RTC 3 Interrupt Enable Registers */
1158 /* ==================================================================== */
1160 typedef union sh_rtc3_int_enable_u {
1161 mmr_t sh_rtc3_int_enable_regval;
1163 mmr_t rtc3_enable : 1;
1164 mmr_t reserved_0 : 63;
1165 } sh_rtc3_int_enable_s;
1166 } sh_rtc3_int_enable_u_t;
1168 /* ==================================================================== */
1169 /* Register "SH_EVENT_OCCURRED" */
1170 /* SHub Interrupt Event Occurred */
1171 /* ==================================================================== */
1173 typedef union sh_event_occurred_u {
1174 mmr_t sh_event_occurred_regval;
1176 mmr_t pi_hw_int : 1;
1177 mmr_t md_hw_int : 1;
1178 mmr_t xn_hw_int : 1;
1179 mmr_t lb_hw_int : 1;
1180 mmr_t ii_hw_int : 1;
1181 mmr_t pi_ce_int : 1;
1182 mmr_t md_ce_int : 1;
1183 mmr_t xn_ce_int : 1;
1184 mmr_t pi_uce_int : 1;
1185 mmr_t md_uce_int : 1;
1186 mmr_t xn_uce_int : 1;
1187 mmr_t proc0_adv_int : 1;
1188 mmr_t proc1_adv_int : 1;
1189 mmr_t proc2_adv_int : 1;
1190 mmr_t proc3_adv_int : 1;
1191 mmr_t proc0_err_int : 1;
1192 mmr_t proc1_err_int : 1;
1193 mmr_t proc2_err_int : 1;
1194 mmr_t proc3_err_int : 1;
1195 mmr_t system_shutdown_int : 1;
1197 mmr_t l1_nmi_int : 1;
1198 mmr_t stop_clock : 1;
1203 mmr_t profile_int : 1;
1207 mmr_t reserved_0 : 33;
1208 } sh_event_occurred_s;
1209 } sh_event_occurred_u_t;
1211 /* ==================================================================== */
1212 /* Register "SH_EVENT_OVERFLOW" */
1213 /* SHub Interrupt Event Occurred Overflow */
1214 /* ==================================================================== */
1216 typedef union sh_event_overflow_u {
1217 mmr_t sh_event_overflow_regval;
1219 mmr_t pi_hw_int : 1;
1220 mmr_t md_hw_int : 1;
1221 mmr_t xn_hw_int : 1;
1222 mmr_t lb_hw_int : 1;
1223 mmr_t ii_hw_int : 1;
1224 mmr_t pi_ce_int : 1;
1225 mmr_t md_ce_int : 1;
1226 mmr_t xn_ce_int : 1;
1227 mmr_t pi_uce_int : 1;
1228 mmr_t md_uce_int : 1;
1229 mmr_t xn_uce_int : 1;
1230 mmr_t proc0_adv_int : 1;
1231 mmr_t proc1_adv_int : 1;
1232 mmr_t proc2_adv_int : 1;
1233 mmr_t proc3_adv_int : 1;
1234 mmr_t proc0_err_int : 1;
1235 mmr_t proc1_err_int : 1;
1236 mmr_t proc2_err_int : 1;
1237 mmr_t proc3_err_int : 1;
1238 mmr_t system_shutdown_int : 1;
1240 mmr_t l1_nmi_int : 1;
1241 mmr_t stop_clock : 1;
1246 mmr_t profile_int : 1;
1247 mmr_t reserved_0 : 36;
1248 } sh_event_overflow_s;
1249 } sh_event_overflow_u_t;
1251 /* ==================================================================== */
1252 /* Register "SH_JUNK_BUS_TIME" */
1253 /* Junk Bus Timing */
1254 /* ==================================================================== */
1256 typedef union sh_junk_bus_time_u {
1257 mmr_t sh_junk_bus_time_regval;
1259 mmr_t fprom_setup_hold : 8;
1260 mmr_t fprom_enable : 8;
1261 mmr_t uart_setup_hold : 8;
1262 mmr_t uart_enable : 8;
1263 mmr_t reserved_0 : 32;
1264 } sh_junk_bus_time_s;
1265 } sh_junk_bus_time_u_t;
1267 /* ==================================================================== */
1268 /* Register "SH_JUNK_LATCH_TIME" */
1269 /* Junk Bus Latch Timing */
1270 /* ==================================================================== */
1272 typedef union sh_junk_latch_time_u {
1273 mmr_t sh_junk_latch_time_regval;
1275 mmr_t setup_hold : 3;
1276 mmr_t reserved_0 : 61;
1277 } sh_junk_latch_time_s;
1278 } sh_junk_latch_time_u_t;
1280 /* ==================================================================== */
1281 /* Register "SH_JUNK_NACK_RESET" */
1282 /* Junk Bus Nack Counter Reset */
1283 /* ==================================================================== */
1285 typedef union sh_junk_nack_reset_u {
1286 mmr_t sh_junk_nack_reset_regval;
1289 mmr_t reserved_0 : 63;
1290 } sh_junk_nack_reset_s;
1291 } sh_junk_nack_reset_u_t;
1293 /* ==================================================================== */
1294 /* Register "SH_JUNK_BUS_LED0" */
1296 /* ==================================================================== */
1298 typedef union sh_junk_bus_led0_u {
1299 mmr_t sh_junk_bus_led0_regval;
1301 mmr_t led0_data : 8;
1302 mmr_t reserved_0 : 56;
1303 } sh_junk_bus_led0_s;
1304 } sh_junk_bus_led0_u_t;
1306 /* ==================================================================== */
1307 /* Register "SH_JUNK_BUS_LED1" */
1309 /* ==================================================================== */
1311 typedef union sh_junk_bus_led1_u {
1312 mmr_t sh_junk_bus_led1_regval;
1314 mmr_t led1_data : 8;
1315 mmr_t reserved_0 : 56;
1316 } sh_junk_bus_led1_s;
1317 } sh_junk_bus_led1_u_t;
1319 /* ==================================================================== */
1320 /* Register "SH_JUNK_BUS_LED2" */
1322 /* ==================================================================== */
1324 typedef union sh_junk_bus_led2_u {
1325 mmr_t sh_junk_bus_led2_regval;
1327 mmr_t led2_data : 8;
1328 mmr_t reserved_0 : 56;
1329 } sh_junk_bus_led2_s;
1330 } sh_junk_bus_led2_u_t;
1332 /* ==================================================================== */
1333 /* Register "SH_JUNK_BUS_LED3" */
1335 /* ==================================================================== */
1337 typedef union sh_junk_bus_led3_u {
1338 mmr_t sh_junk_bus_led3_regval;
1340 mmr_t led3_data : 8;
1341 mmr_t reserved_0 : 56;
1342 } sh_junk_bus_led3_s;
1343 } sh_junk_bus_led3_u_t;
1345 /* ==================================================================== */
1346 /* Register "SH_JUNK_ERROR_STATUS" */
1347 /* Junk Bus Error Status */
1348 /* ==================================================================== */
1350 typedef union sh_junk_error_status_u {
1351 mmr_t sh_junk_error_status_regval;
1354 mmr_t reserved_0 : 1;
1358 mmr_t reserved_1 : 3;
1359 } sh_junk_error_status_s;
1360 } sh_junk_error_status_u_t;
1362 /* ==================================================================== */
1363 /* Register "SH_NI0_LLP_STAT" */
1364 /* This register describes the LLP status. */
1365 /* ==================================================================== */
1367 typedef union sh_ni0_llp_stat_u {
1368 mmr_t sh_ni0_llp_stat_regval;
1370 mmr_t link_reset_state : 4;
1371 mmr_t reserved_0 : 60;
1372 } sh_ni0_llp_stat_s;
1373 } sh_ni0_llp_stat_u_t;
1375 /* ==================================================================== */
1376 /* Register "SH_NI0_LLP_RESET" */
1377 /* Writing issues a reset to the network interface */
1378 /* ==================================================================== */
1380 typedef union sh_ni0_llp_reset_u {
1381 mmr_t sh_ni0_llp_reset_regval;
1385 mmr_t reserved_0 : 62;
1386 } sh_ni0_llp_reset_s;
1387 } sh_ni0_llp_reset_u_t;
1389 /* ==================================================================== */
1390 /* Register "SH_NI0_LLP_RESET_EN" */
1391 /* Controls LLP warm reset propagation */
1392 /* ==================================================================== */
1394 typedef union sh_ni0_llp_reset_en_u {
1395 mmr_t sh_ni0_llp_reset_en_regval;
1398 mmr_t reserved_0 : 63;
1399 } sh_ni0_llp_reset_en_s;
1400 } sh_ni0_llp_reset_en_u_t;
1402 /* ==================================================================== */
1403 /* Register "SH_NI0_LLP_CHAN_MODE" */
1404 /* Sets the signaling mode of LLP and channel */
1405 /* ==================================================================== */
1407 typedef union sh_ni0_llp_chan_mode_u {
1408 mmr_t sh_ni0_llp_chan_mode_regval;
1410 mmr_t bitmode32 : 1;
1411 mmr_t ac_encode : 1;
1412 mmr_t enable_tuning : 1;
1413 mmr_t enable_rmt_ft_upd : 1;
1414 mmr_t enable_clkquad : 1;
1415 mmr_t reserved_0 : 59;
1416 } sh_ni0_llp_chan_mode_s;
1417 } sh_ni0_llp_chan_mode_u_t;
1419 /* ==================================================================== */
1420 /* Register "SH_NI0_LLP_CONFIG" */
1421 /* Sets the configuration of LLP and channel */
1422 /* ==================================================================== */
1424 typedef union sh_ni0_llp_config_u {
1425 mmr_t sh_ni0_llp_config_regval;
1427 mmr_t maxburst : 10;
1428 mmr_t maxretry : 10;
1429 mmr_t nulltimeout : 6;
1430 mmr_t ftu_time : 12;
1431 mmr_t reserved_0 : 26;
1432 } sh_ni0_llp_config_s;
1433 } sh_ni0_llp_config_u_t;
1435 /* ==================================================================== */
1436 /* Register "SH_NI0_LLP_TEST_CTL" */
1437 /* ==================================================================== */
1439 typedef union sh_ni0_llp_test_ctl_u {
1440 mmr_t sh_ni0_llp_test_ctl_regval;
1443 mmr_t send_test_mode : 2;
1444 mmr_t reserved_0 : 2;
1446 mmr_t reserved_1 : 2;
1447 mmr_t lfsr_mode : 2;
1448 mmr_t noise_mode : 2;
1449 mmr_t armcapture : 1;
1450 mmr_t capturecbonly : 1;
1451 mmr_t sendcberror : 1;
1452 mmr_t sendsnerror : 1;
1453 mmr_t fakesnerror : 1;
1456 mmr_t reserved_2 : 1;
1457 } sh_ni0_llp_test_ctl_s;
1458 } sh_ni0_llp_test_ctl_u_t;
1460 /* ==================================================================== */
1461 /* Register "SH_NI0_LLP_CAPT_WD1" */
1462 /* low order 64-bit captured word */
1463 /* ==================================================================== */
1465 typedef union sh_ni0_llp_capt_wd1_u {
1466 mmr_t sh_ni0_llp_capt_wd1_regval;
1469 } sh_ni0_llp_capt_wd1_s;
1470 } sh_ni0_llp_capt_wd1_u_t;
1472 /* ==================================================================== */
1473 /* Register "SH_NI0_LLP_CAPT_WD2" */
1474 /* high order 64-bit captured word */
1475 /* ==================================================================== */
1477 typedef union sh_ni0_llp_capt_wd2_u {
1478 mmr_t sh_ni0_llp_capt_wd2_regval;
1481 } sh_ni0_llp_capt_wd2_s;
1482 } sh_ni0_llp_capt_wd2_u_t;
1484 /* ==================================================================== */
1485 /* Register "SH_NI0_LLP_CAPT_SBCB" */
1486 /* captured sideband, sequence, and CRC */
1487 /* ==================================================================== */
1489 typedef union sh_ni0_llp_capt_sbcb_u {
1490 mmr_t sh_ni0_llp_capt_sbcb_regval;
1492 mmr_t capturedrcvsbsn : 16;
1493 mmr_t capturedrcvcrc : 16;
1494 mmr_t sentallcberrors : 1;
1495 mmr_t sentallsnerrors : 1;
1496 mmr_t fakedallsnerrors : 1;
1497 mmr_t chargeoverflow : 1;
1498 mmr_t chargeunderflow : 1;
1499 mmr_t reserved_0 : 27;
1500 } sh_ni0_llp_capt_sbcb_s;
1501 } sh_ni0_llp_capt_sbcb_u_t;
1503 /* ==================================================================== */
1504 /* Register "SH_NI0_LLP_ERR" */
1505 /* ==================================================================== */
1507 typedef union sh_ni0_llp_err_u {
1508 mmr_t sh_ni0_llp_err_regval;
1510 mmr_t rx_sn_err_count : 8;
1511 mmr_t rx_cb_err_count : 8;
1512 mmr_t retry_count : 8;
1513 mmr_t retry_timeout : 1;
1514 mmr_t rcv_link_reset : 1;
1516 mmr_t power_not_ok : 1;
1517 mmr_t wire_cnt : 24;
1518 mmr_t wire_overflow : 1;
1519 mmr_t reserved_0 : 11;
1521 } sh_ni0_llp_err_u_t;
1523 /* ==================================================================== */
1524 /* Register "SH_NI1_LLP_STAT" */
1525 /* This register describes the LLP status. */
1526 /* ==================================================================== */
1528 typedef union sh_ni1_llp_stat_u {
1529 mmr_t sh_ni1_llp_stat_regval;
1531 mmr_t link_reset_state : 4;
1532 mmr_t reserved_0 : 60;
1533 } sh_ni1_llp_stat_s;
1534 } sh_ni1_llp_stat_u_t;
1536 /* ==================================================================== */
1537 /* Register "SH_NI1_LLP_RESET" */
1538 /* Writing issues a reset to the network interface */
1539 /* ==================================================================== */
1541 typedef union sh_ni1_llp_reset_u {
1542 mmr_t sh_ni1_llp_reset_regval;
1546 mmr_t reserved_0 : 62;
1547 } sh_ni1_llp_reset_s;
1548 } sh_ni1_llp_reset_u_t;
1550 /* ==================================================================== */
1551 /* Register "SH_NI1_LLP_RESET_EN" */
1552 /* Controls LLP warm reset propagation */
1553 /* ==================================================================== */
1555 typedef union sh_ni1_llp_reset_en_u {
1556 mmr_t sh_ni1_llp_reset_en_regval;
1559 mmr_t reserved_0 : 63;
1560 } sh_ni1_llp_reset_en_s;
1561 } sh_ni1_llp_reset_en_u_t;
1563 /* ==================================================================== */
1564 /* Register "SH_NI1_LLP_CHAN_MODE" */
1565 /* Sets the signaling mode of LLP and channel */
1566 /* ==================================================================== */
1568 typedef union sh_ni1_llp_chan_mode_u {
1569 mmr_t sh_ni1_llp_chan_mode_regval;
1571 mmr_t bitmode32 : 1;
1572 mmr_t ac_encode : 1;
1573 mmr_t enable_tuning : 1;
1574 mmr_t enable_rmt_ft_upd : 1;
1575 mmr_t enable_clkquad : 1;
1576 mmr_t reserved_0 : 59;
1577 } sh_ni1_llp_chan_mode_s;
1578 } sh_ni1_llp_chan_mode_u_t;
1580 /* ==================================================================== */
1581 /* Register "SH_NI1_LLP_CONFIG" */
1582 /* Sets the configuration of LLP and channel */
1583 /* ==================================================================== */
1585 typedef union sh_ni1_llp_config_u {
1586 mmr_t sh_ni1_llp_config_regval;
1588 mmr_t maxburst : 10;
1589 mmr_t maxretry : 10;
1590 mmr_t nulltimeout : 6;
1591 mmr_t ftu_time : 12;
1592 mmr_t reserved_0 : 26;
1593 } sh_ni1_llp_config_s;
1594 } sh_ni1_llp_config_u_t;
1596 /* ==================================================================== */
1597 /* Register "SH_NI1_LLP_TEST_CTL" */
1598 /* ==================================================================== */
1600 typedef union sh_ni1_llp_test_ctl_u {
1601 mmr_t sh_ni1_llp_test_ctl_regval;
1604 mmr_t send_test_mode : 2;
1605 mmr_t reserved_0 : 2;
1607 mmr_t reserved_1 : 2;
1608 mmr_t lfsr_mode : 2;
1609 mmr_t noise_mode : 2;
1610 mmr_t armcapture : 1;
1611 mmr_t capturecbonly : 1;
1612 mmr_t sendcberror : 1;
1613 mmr_t sendsnerror : 1;
1614 mmr_t fakesnerror : 1;
1617 mmr_t reserved_2 : 1;
1618 } sh_ni1_llp_test_ctl_s;
1619 } sh_ni1_llp_test_ctl_u_t;
1621 /* ==================================================================== */
1622 /* Register "SH_NI1_LLP_CAPT_WD1" */
1623 /* low order 64-bit captured word */
1624 /* ==================================================================== */
1626 typedef union sh_ni1_llp_capt_wd1_u {
1627 mmr_t sh_ni1_llp_capt_wd1_regval;
1630 } sh_ni1_llp_capt_wd1_s;
1631 } sh_ni1_llp_capt_wd1_u_t;
1633 /* ==================================================================== */
1634 /* Register "SH_NI1_LLP_CAPT_WD2" */
1635 /* high order 64-bit captured word */
1636 /* ==================================================================== */
1638 typedef union sh_ni1_llp_capt_wd2_u {
1639 mmr_t sh_ni1_llp_capt_wd2_regval;
1642 } sh_ni1_llp_capt_wd2_s;
1643 } sh_ni1_llp_capt_wd2_u_t;
1645 /* ==================================================================== */
1646 /* Register "SH_NI1_LLP_CAPT_SBCB" */
1647 /* captured sideband, sequence, and CRC */
1648 /* ==================================================================== */
1650 typedef union sh_ni1_llp_capt_sbcb_u {
1651 mmr_t sh_ni1_llp_capt_sbcb_regval;
1653 mmr_t capturedrcvsbsn : 16;
1654 mmr_t capturedrcvcrc : 16;
1655 mmr_t sentallcberrors : 1;
1656 mmr_t sentallsnerrors : 1;
1657 mmr_t fakedallsnerrors : 1;
1658 mmr_t chargeoverflow : 1;
1659 mmr_t chargeunderflow : 1;
1660 mmr_t reserved_0 : 27;
1661 } sh_ni1_llp_capt_sbcb_s;
1662 } sh_ni1_llp_capt_sbcb_u_t;
1664 /* ==================================================================== */
1665 /* Register "SH_NI1_LLP_ERR" */
1666 /* ==================================================================== */
1668 typedef union sh_ni1_llp_err_u {
1669 mmr_t sh_ni1_llp_err_regval;
1671 mmr_t rx_sn_err_count : 8;
1672 mmr_t rx_cb_err_count : 8;
1673 mmr_t retry_count : 8;
1674 mmr_t retry_timeout : 1;
1675 mmr_t rcv_link_reset : 1;
1677 mmr_t power_not_ok : 1;
1678 mmr_t wire_cnt : 24;
1679 mmr_t wire_overflow : 1;
1680 mmr_t reserved_0 : 11;
1682 } sh_ni1_llp_err_u_t;
1684 /* ==================================================================== */
1685 /* Register "SH_XNNI0_LLP_TO_FIFO02_FLOW" */
1686 /* ==================================================================== */
1688 typedef union sh_xnni0_llp_to_fifo02_flow_u {
1689 mmr_t sh_xnni0_llp_to_fifo02_flow_regval;
1691 mmr_t debit_vc0_withhold : 6;
1692 mmr_t reserved_0 : 1;
1693 mmr_t debit_vc0_force_cred : 1;
1694 mmr_t debit_vc2_withhold : 6;
1695 mmr_t reserved_1 : 1;
1696 mmr_t debit_vc2_force_cred : 1;
1697 mmr_t reserved_2 : 8;
1698 mmr_t credit_vc0_dyn : 6;
1699 mmr_t reserved_3 : 2;
1700 mmr_t credit_vc0_cap : 6;
1701 mmr_t reserved_4 : 10;
1702 mmr_t credit_vc2_dyn : 6;
1703 mmr_t reserved_5 : 2;
1704 mmr_t credit_vc2_cap : 6;
1705 mmr_t reserved_6 : 2;
1706 } sh_xnni0_llp_to_fifo02_flow_s;
1707 } sh_xnni0_llp_to_fifo02_flow_u_t;
1709 /* ==================================================================== */
1710 /* Register "SH_XNNI0_LLP_TO_FIFO13_FLOW" */
1711 /* ==================================================================== */
1713 typedef union sh_xnni0_llp_to_fifo13_flow_u {
1714 mmr_t sh_xnni0_llp_to_fifo13_flow_regval;
1716 mmr_t debit_vc0_withhold : 6;
1717 mmr_t reserved_0 : 1;
1718 mmr_t debit_vc0_force_cred : 1;
1719 mmr_t debit_vc2_withhold : 6;
1720 mmr_t reserved_1 : 1;
1721 mmr_t debit_vc2_force_cred : 1;
1722 mmr_t reserved_2 : 8;
1723 mmr_t credit_vc0_dyn : 6;
1724 mmr_t reserved_3 : 2;
1725 mmr_t credit_vc0_cap : 6;
1726 mmr_t reserved_4 : 10;
1727 mmr_t credit_vc2_dyn : 6;
1728 mmr_t reserved_5 : 2;
1729 mmr_t credit_vc2_cap : 6;
1730 mmr_t reserved_6 : 2;
1731 } sh_xnni0_llp_to_fifo13_flow_s;
1732 } sh_xnni0_llp_to_fifo13_flow_u_t;
1734 /* ==================================================================== */
1735 /* Register "SH_XNNI0_LLP_DEBIT_FLOW" */
1736 /* ==================================================================== */
1738 typedef union sh_xnni0_llp_debit_flow_u {
1739 mmr_t sh_xnni0_llp_debit_flow_regval;
1741 mmr_t debit_vc0_dyn : 5;
1742 mmr_t reserved_0 : 3;
1743 mmr_t debit_vc0_cap : 5;
1744 mmr_t reserved_1 : 3;
1745 mmr_t debit_vc1_dyn : 5;
1746 mmr_t reserved_2 : 3;
1747 mmr_t debit_vc1_cap : 5;
1748 mmr_t reserved_3 : 3;
1749 mmr_t debit_vc2_dyn : 5;
1750 mmr_t reserved_4 : 3;
1751 mmr_t debit_vc2_cap : 5;
1752 mmr_t reserved_5 : 3;
1753 mmr_t debit_vc3_dyn : 5;
1754 mmr_t reserved_6 : 3;
1755 mmr_t debit_vc3_cap : 5;
1756 mmr_t reserved_7 : 3;
1757 } sh_xnni0_llp_debit_flow_s;
1758 } sh_xnni0_llp_debit_flow_u_t;
1760 /* ==================================================================== */
1761 /* Register "SH_XNNI0_LINK_0_FLOW" */
1762 /* ==================================================================== */
1764 typedef union sh_xnni0_link_0_flow_u {
1765 mmr_t sh_xnni0_link_0_flow_regval;
1767 mmr_t debit_vc0_withhold : 6;
1768 mmr_t reserved_0 : 1;
1769 mmr_t debit_vc0_force_cred : 1;
1770 mmr_t credit_vc0_test : 7;
1771 mmr_t reserved_1 : 1;
1772 mmr_t credit_vc0_dyn : 7;
1773 mmr_t reserved_2 : 1;
1774 mmr_t credit_vc0_cap : 7;
1775 mmr_t reserved_3 : 33;
1776 } sh_xnni0_link_0_flow_s;
1777 } sh_xnni0_link_0_flow_u_t;
1779 /* ==================================================================== */
1780 /* Register "SH_XNNI0_LINK_1_FLOW" */
1781 /* ==================================================================== */
1783 typedef union sh_xnni0_link_1_flow_u {
1784 mmr_t sh_xnni0_link_1_flow_regval;
1786 mmr_t debit_vc1_withhold : 6;
1787 mmr_t reserved_0 : 1;
1788 mmr_t debit_vc1_force_cred : 1;
1789 mmr_t credit_vc1_test : 7;
1790 mmr_t reserved_1 : 1;
1791 mmr_t credit_vc1_dyn : 7;
1792 mmr_t reserved_2 : 1;
1793 mmr_t credit_vc1_cap : 7;
1794 mmr_t reserved_3 : 33;
1795 } sh_xnni0_link_1_flow_s;
1796 } sh_xnni0_link_1_flow_u_t;
1798 /* ==================================================================== */
1799 /* Register "SH_XNNI0_LINK_2_FLOW" */
1800 /* ==================================================================== */
1802 typedef union sh_xnni0_link_2_flow_u {
1803 mmr_t sh_xnni0_link_2_flow_regval;
1805 mmr_t debit_vc2_withhold : 6;
1806 mmr_t reserved_0 : 1;
1807 mmr_t debit_vc2_force_cred : 1;
1808 mmr_t credit_vc2_test : 7;
1809 mmr_t reserved_1 : 1;
1810 mmr_t credit_vc2_dyn : 7;
1811 mmr_t reserved_2 : 1;
1812 mmr_t credit_vc2_cap : 7;
1813 mmr_t reserved_3 : 33;
1814 } sh_xnni0_link_2_flow_s;
1815 } sh_xnni0_link_2_flow_u_t;
1817 /* ==================================================================== */
1818 /* Register "SH_XNNI0_LINK_3_FLOW" */
1819 /* ==================================================================== */
1821 typedef union sh_xnni0_link_3_flow_u {
1822 mmr_t sh_xnni0_link_3_flow_regval;
1824 mmr_t debit_vc3_withhold : 6;
1825 mmr_t reserved_0 : 1;
1826 mmr_t debit_vc3_force_cred : 1;
1827 mmr_t credit_vc3_test : 7;
1828 mmr_t reserved_1 : 1;
1829 mmr_t credit_vc3_dyn : 7;
1830 mmr_t reserved_2 : 1;
1831 mmr_t credit_vc3_cap : 7;
1832 mmr_t reserved_3 : 33;
1833 } sh_xnni0_link_3_flow_s;
1834 } sh_xnni0_link_3_flow_u_t;
1836 /* ==================================================================== */
1837 /* Register "SH_XNNI1_LLP_TO_FIFO02_FLOW" */
1838 /* ==================================================================== */
1840 typedef union sh_xnni1_llp_to_fifo02_flow_u {
1841 mmr_t sh_xnni1_llp_to_fifo02_flow_regval;
1843 mmr_t debit_vc0_withhold : 6;
1844 mmr_t reserved_0 : 1;
1845 mmr_t debit_vc0_force_cred : 1;
1846 mmr_t debit_vc2_withhold : 6;
1847 mmr_t reserved_1 : 1;
1848 mmr_t debit_vc2_force_cred : 1;
1849 mmr_t reserved_2 : 8;
1850 mmr_t credit_vc0_dyn : 6;
1851 mmr_t reserved_3 : 2;
1852 mmr_t credit_vc0_cap : 6;
1853 mmr_t reserved_4 : 10;
1854 mmr_t credit_vc2_dyn : 6;
1855 mmr_t reserved_5 : 2;
1856 mmr_t credit_vc2_cap : 6;
1857 mmr_t reserved_6 : 2;
1858 } sh_xnni1_llp_to_fifo02_flow_s;
1859 } sh_xnni1_llp_to_fifo02_flow_u_t;
1861 /* ==================================================================== */
1862 /* Register "SH_XNNI1_LLP_TO_FIFO13_FLOW" */
1863 /* ==================================================================== */
1865 typedef union sh_xnni1_llp_to_fifo13_flow_u {
1866 mmr_t sh_xnni1_llp_to_fifo13_flow_regval;
1868 mmr_t debit_vc0_withhold : 6;
1869 mmr_t reserved_0 : 1;
1870 mmr_t debit_vc0_force_cred : 1;
1871 mmr_t debit_vc2_withhold : 6;
1872 mmr_t reserved_1 : 1;
1873 mmr_t debit_vc2_force_cred : 1;
1874 mmr_t reserved_2 : 8;
1875 mmr_t credit_vc0_dyn : 6;
1876 mmr_t reserved_3 : 2;
1877 mmr_t credit_vc0_cap : 6;
1878 mmr_t reserved_4 : 10;
1879 mmr_t credit_vc2_dyn : 6;
1880 mmr_t reserved_5 : 2;
1881 mmr_t credit_vc2_cap : 6;
1882 mmr_t reserved_6 : 2;
1883 } sh_xnni1_llp_to_fifo13_flow_s;
1884 } sh_xnni1_llp_to_fifo13_flow_u_t;
1886 /* ==================================================================== */
1887 /* Register "SH_XNNI1_LLP_DEBIT_FLOW" */
1888 /* ==================================================================== */
1890 typedef union sh_xnni1_llp_debit_flow_u {
1891 mmr_t sh_xnni1_llp_debit_flow_regval;
1893 mmr_t debit_vc0_dyn : 5;
1894 mmr_t reserved_0 : 3;
1895 mmr_t debit_vc0_cap : 5;
1896 mmr_t reserved_1 : 3;
1897 mmr_t debit_vc1_dyn : 5;
1898 mmr_t reserved_2 : 3;
1899 mmr_t debit_vc1_cap : 5;
1900 mmr_t reserved_3 : 3;
1901 mmr_t debit_vc2_dyn : 5;
1902 mmr_t reserved_4 : 3;
1903 mmr_t debit_vc2_cap : 5;
1904 mmr_t reserved_5 : 3;
1905 mmr_t debit_vc3_dyn : 5;
1906 mmr_t reserved_6 : 3;
1907 mmr_t debit_vc3_cap : 5;
1908 mmr_t reserved_7 : 3;
1909 } sh_xnni1_llp_debit_flow_s;
1910 } sh_xnni1_llp_debit_flow_u_t;
1912 /* ==================================================================== */
1913 /* Register "SH_XNNI1_LINK_0_FLOW" */
1914 /* ==================================================================== */
1916 typedef union sh_xnni1_link_0_flow_u {
1917 mmr_t sh_xnni1_link_0_flow_regval;
1919 mmr_t debit_vc0_withhold : 6;
1920 mmr_t reserved_0 : 1;
1921 mmr_t debit_vc0_force_cred : 1;
1922 mmr_t credit_vc0_test : 7;
1923 mmr_t reserved_1 : 1;
1924 mmr_t credit_vc0_dyn : 7;
1925 mmr_t reserved_2 : 1;
1926 mmr_t credit_vc0_cap : 7;
1927 mmr_t reserved_3 : 33;
1928 } sh_xnni1_link_0_flow_s;
1929 } sh_xnni1_link_0_flow_u_t;
1931 /* ==================================================================== */
1932 /* Register "SH_XNNI1_LINK_1_FLOW" */
1933 /* ==================================================================== */
1935 typedef union sh_xnni1_link_1_flow_u {
1936 mmr_t sh_xnni1_link_1_flow_regval;
1938 mmr_t debit_vc1_withhold : 6;
1939 mmr_t reserved_0 : 1;
1940 mmr_t debit_vc1_force_cred : 1;
1941 mmr_t credit_vc1_test : 7;
1942 mmr_t reserved_1 : 1;
1943 mmr_t credit_vc1_dyn : 7;
1944 mmr_t reserved_2 : 1;
1945 mmr_t credit_vc1_cap : 7;
1946 mmr_t reserved_3 : 33;
1947 } sh_xnni1_link_1_flow_s;
1948 } sh_xnni1_link_1_flow_u_t;
1950 /* ==================================================================== */
1951 /* Register "SH_XNNI1_LINK_2_FLOW" */
1952 /* ==================================================================== */
1954 typedef union sh_xnni1_link_2_flow_u {
1955 mmr_t sh_xnni1_link_2_flow_regval;
1957 mmr_t debit_vc2_withhold : 6;
1958 mmr_t reserved_0 : 1;
1959 mmr_t debit_vc2_force_cred : 1;
1960 mmr_t credit_vc2_test : 7;
1961 mmr_t reserved_1 : 1;
1962 mmr_t credit_vc2_dyn : 7;
1963 mmr_t reserved_2 : 1;
1964 mmr_t credit_vc2_cap : 7;
1965 mmr_t reserved_3 : 33;
1966 } sh_xnni1_link_2_flow_s;
1967 } sh_xnni1_link_2_flow_u_t;
1969 /* ==================================================================== */
1970 /* Register "SH_XNNI1_LINK_3_FLOW" */
1971 /* ==================================================================== */
1973 typedef union sh_xnni1_link_3_flow_u {
1974 mmr_t sh_xnni1_link_3_flow_regval;
1976 mmr_t debit_vc3_withhold : 6;
1977 mmr_t reserved_0 : 1;
1978 mmr_t debit_vc3_force_cred : 1;
1979 mmr_t credit_vc3_test : 7;
1980 mmr_t reserved_1 : 1;
1981 mmr_t credit_vc3_dyn : 7;
1982 mmr_t reserved_2 : 1;
1983 mmr_t credit_vc3_cap : 7;
1984 mmr_t reserved_3 : 33;
1985 } sh_xnni1_link_3_flow_s;
1986 } sh_xnni1_link_3_flow_u_t;
1988 /* ==================================================================== */
1989 /* Register "SH_IILB_LOCAL_TABLE" */
1990 /* local lookup table */
1991 /* ==================================================================== */
1993 typedef union sh_iilb_local_table_u {
1994 mmr_t sh_iilb_local_table_regval;
1999 mmr_t reserved_0 : 57;
2001 } sh_iilb_local_table_s;
2002 } sh_iilb_local_table_u_t;
2004 /* ==================================================================== */
2005 /* Register "SH_IILB_GLOBAL_TABLE" */
2006 /* global lookup table */
2007 /* ==================================================================== */
2009 typedef union sh_iilb_global_table_u {
2010 mmr_t sh_iilb_global_table_regval;
2015 mmr_t reserved_0 : 57;
2017 } sh_iilb_global_table_s;
2018 } sh_iilb_global_table_u_t;
2020 /* ==================================================================== */
2021 /* Register "SH_IILB_OVER_RIDE_TABLE" */
2022 /* If enabled, bypass the Global/Local tables */
2023 /* ==================================================================== */
2025 typedef union sh_iilb_over_ride_table_u {
2026 mmr_t sh_iilb_over_ride_table_regval;
2031 mmr_t reserved_0 : 57;
2033 } sh_iilb_over_ride_table_s;
2034 } sh_iilb_over_ride_table_u_t;
2036 /* ==================================================================== */
2037 /* Register "SH_IILB_RSP_PLANE_HINT" */
2038 /* If enabled, invert incoming response only plane hint bit before lo */
2039 /* ==================================================================== */
2041 typedef union sh_iilb_rsp_plane_hint_u {
2042 mmr_t sh_iilb_rsp_plane_hint_regval;
2044 mmr_t reserved_0 : 64;
2045 } sh_iilb_rsp_plane_hint_s;
2046 } sh_iilb_rsp_plane_hint_u_t;
2048 /* ==================================================================== */
2049 /* Register "SH_PI_LOCAL_TABLE" */
2050 /* local lookup table */
2051 /* ==================================================================== */
2053 typedef union sh_pi_local_table_u {
2054 mmr_t sh_pi_local_table_regval;
2059 mmr_t reserved_0 : 2;
2063 mmr_t reserved_1 : 49;
2065 } sh_pi_local_table_s;
2066 } sh_pi_local_table_u_t;
2068 /* ==================================================================== */
2069 /* Register "SH_PI_GLOBAL_TABLE" */
2070 /* global lookup table */
2071 /* ==================================================================== */
2073 typedef union sh_pi_global_table_u {
2074 mmr_t sh_pi_global_table_regval;
2079 mmr_t reserved_0 : 2;
2083 mmr_t reserved_1 : 49;
2085 } sh_pi_global_table_s;
2086 } sh_pi_global_table_u_t;
2088 /* ==================================================================== */
2089 /* Register "SH_PI_OVER_RIDE_TABLE" */
2090 /* If enabled, bypass the Global/Local tables */
2091 /* ==================================================================== */
2093 typedef union sh_pi_over_ride_table_u {
2094 mmr_t sh_pi_over_ride_table_regval;
2099 mmr_t reserved_0 : 2;
2103 mmr_t reserved_1 : 49;
2105 } sh_pi_over_ride_table_s;
2106 } sh_pi_over_ride_table_u_t;
2108 /* ==================================================================== */
2109 /* Register "SH_PI_RSP_PLANE_HINT" */
2110 /* If enabled, invert incoming response only plane hint bit before lo */
2111 /* ==================================================================== */
2113 typedef union sh_pi_rsp_plane_hint_u {
2114 mmr_t sh_pi_rsp_plane_hint_regval;
2117 mmr_t reserved_0 : 63;
2118 } sh_pi_rsp_plane_hint_s;
2119 } sh_pi_rsp_plane_hint_u_t;
2121 /* ==================================================================== */
2122 /* Register "SH_NI0_LOCAL_TABLE" */
2123 /* local lookup table */
2124 /* ==================================================================== */
2126 typedef union sh_ni0_local_table_u {
2127 mmr_t sh_ni0_local_table_regval;
2131 mmr_t reserved_0 : 58;
2133 } sh_ni0_local_table_s;
2134 } sh_ni0_local_table_u_t;
2136 /* ==================================================================== */
2137 /* Register "SH_NI0_GLOBAL_TABLE" */
2138 /* global lookup table */
2139 /* ==================================================================== */
2141 typedef union sh_ni0_global_table_u {
2142 mmr_t sh_ni0_global_table_regval;
2146 mmr_t reserved_0 : 58;
2148 } sh_ni0_global_table_s;
2149 } sh_ni0_global_table_u_t;
2151 /* ==================================================================== */
2152 /* Register "SH_NI0_OVER_RIDE_TABLE" */
2153 /* If enabled, bypass the Global/Local tables */
2154 /* ==================================================================== */
2156 typedef union sh_ni0_over_ride_table_u {
2157 mmr_t sh_ni0_over_ride_table_regval;
2161 mmr_t reserved_0 : 58;
2163 } sh_ni0_over_ride_table_s;
2164 } sh_ni0_over_ride_table_u_t;
2166 /* ==================================================================== */
2167 /* Register "SH_NI0_RSP_PLANE_HINT" */
2168 /* If enabled, invert incoming response only plane hint bit before lo */
2169 /* ==================================================================== */
2171 typedef union sh_ni0_rsp_plane_hint_u {
2172 mmr_t sh_ni0_rsp_plane_hint_regval;
2174 mmr_t reserved_0 : 64;
2175 } sh_ni0_rsp_plane_hint_s;
2176 } sh_ni0_rsp_plane_hint_u_t;
2178 /* ==================================================================== */
2179 /* Register "SH_NI1_LOCAL_TABLE" */
2180 /* local lookup table */
2181 /* ==================================================================== */
2183 typedef union sh_ni1_local_table_u {
2184 mmr_t sh_ni1_local_table_regval;
2188 mmr_t reserved_0 : 58;
2190 } sh_ni1_local_table_s;
2191 } sh_ni1_local_table_u_t;
2193 /* ==================================================================== */
2194 /* Register "SH_NI1_GLOBAL_TABLE" */
2195 /* global lookup table */
2196 /* ==================================================================== */
2198 typedef union sh_ni1_global_table_u {
2199 mmr_t sh_ni1_global_table_regval;
2203 mmr_t reserved_0 : 58;
2205 } sh_ni1_global_table_s;
2206 } sh_ni1_global_table_u_t;
2208 /* ==================================================================== */
2209 /* Register "SH_NI1_OVER_RIDE_TABLE" */
2210 /* If enabled, bypass the Global/Local tables */
2211 /* ==================================================================== */
2213 typedef union sh_ni1_over_ride_table_u {
2214 mmr_t sh_ni1_over_ride_table_regval;
2218 mmr_t reserved_0 : 58;
2220 } sh_ni1_over_ride_table_s;
2221 } sh_ni1_over_ride_table_u_t;
2223 /* ==================================================================== */
2224 /* Register "SH_NI1_RSP_PLANE_HINT" */
2225 /* If enabled, invert incoming response only plane hint bit before lo */
2226 /* ==================================================================== */
2228 typedef union sh_ni1_rsp_plane_hint_u {
2229 mmr_t sh_ni1_rsp_plane_hint_regval;
2231 mmr_t reserved_0 : 64;
2232 } sh_ni1_rsp_plane_hint_s;
2233 } sh_ni1_rsp_plane_hint_u_t;
2235 /* ==================================================================== */
2236 /* Register "SH_MD_LOCAL_TABLE" */
2237 /* local lookup table */
2238 /* ==================================================================== */
2240 typedef union sh_md_local_table_u {
2241 mmr_t sh_md_local_table_regval;
2246 mmr_t reserved_0 : 2;
2250 mmr_t reserved_1 : 49;
2252 } sh_md_local_table_s;
2253 } sh_md_local_table_u_t;
2255 /* ==================================================================== */
2256 /* Register "SH_MD_GLOBAL_TABLE" */
2257 /* global lookup table */
2258 /* ==================================================================== */
2260 typedef union sh_md_global_table_u {
2261 mmr_t sh_md_global_table_regval;
2266 mmr_t reserved_0 : 2;
2270 mmr_t reserved_1 : 49;
2272 } sh_md_global_table_s;
2273 } sh_md_global_table_u_t;
2275 /* ==================================================================== */
2276 /* Register "SH_MD_OVER_RIDE_TABLE" */
2277 /* If enabled, bypass the Global/Local tables */
2278 /* ==================================================================== */
2280 typedef union sh_md_over_ride_table_u {
2281 mmr_t sh_md_over_ride_table_regval;
2286 mmr_t reserved_0 : 2;
2290 mmr_t reserved_1 : 49;
2292 } sh_md_over_ride_table_s;
2293 } sh_md_over_ride_table_u_t;
2295 /* ==================================================================== */
2296 /* Register "SH_MD_RSP_PLANE_HINT" */
2297 /* If enabled, invert incoming response only plane hint bit before lo */
2298 /* ==================================================================== */
2300 typedef union sh_md_rsp_plane_hint_u {
2301 mmr_t sh_md_rsp_plane_hint_regval;
2304 mmr_t reserved_0 : 63;
2305 } sh_md_rsp_plane_hint_s;
2306 } sh_md_rsp_plane_hint_u_t;
2308 /* ==================================================================== */
2309 /* Register "SH_LB_LIQ_CTL" */
2310 /* Local Block LIQ Control */
2311 /* ==================================================================== */
2313 typedef union sh_lb_liq_ctl_u {
2314 mmr_t sh_lb_liq_ctl_regval;
2316 mmr_t liq_req_ctl : 5;
2317 mmr_t reserved_0 : 3;
2318 mmr_t liq_rpl_ctl : 4;
2319 mmr_t reserved_1 : 4;
2320 mmr_t force_rq_credit : 1;
2321 mmr_t force_rp_credit : 1;
2322 mmr_t force_linvv_credit : 1;
2323 mmr_t reserved_2 : 45;
2325 } sh_lb_liq_ctl_u_t;
2327 /* ==================================================================== */
2328 /* Register "SH_LB_LOQ_CTL" */
2329 /* Local Block LOQ Control */
2330 /* ==================================================================== */
2332 typedef union sh_lb_loq_ctl_u {
2333 mmr_t sh_lb_loq_ctl_regval;
2335 mmr_t loq_req_ctl : 1;
2336 mmr_t loq_rpl_ctl : 1;
2337 mmr_t reserved_0 : 62;
2339 } sh_lb_loq_ctl_u_t;
2341 /* ==================================================================== */
2342 /* Register "SH_LB_MAX_REP_CREDIT_CNT" */
2343 /* Maximum number of reply credits from XN */
2344 /* ==================================================================== */
2346 typedef union sh_lb_max_rep_credit_cnt_u {
2347 mmr_t sh_lb_max_rep_credit_cnt_regval;
2350 mmr_t reserved_0 : 59;
2351 } sh_lb_max_rep_credit_cnt_s;
2352 } sh_lb_max_rep_credit_cnt_u_t;
2354 /* ==================================================================== */
2355 /* Register "SH_LB_MAX_REQ_CREDIT_CNT" */
2356 /* Maximum number of request credits from XN */
2357 /* ==================================================================== */
2359 typedef union sh_lb_max_req_credit_cnt_u {
2360 mmr_t sh_lb_max_req_credit_cnt_regval;
2363 mmr_t reserved_0 : 59;
2364 } sh_lb_max_req_credit_cnt_s;
2365 } sh_lb_max_req_credit_cnt_u_t;
2367 /* ==================================================================== */
2368 /* Register "SH_PIO_TIME_OUT" */
2369 /* Local Block PIO time out value */
2370 /* ==================================================================== */
2372 typedef union sh_pio_time_out_u {
2373 mmr_t sh_pio_time_out_regval;
2376 mmr_t reserved_0 : 48;
2377 } sh_pio_time_out_s;
2378 } sh_pio_time_out_u_t;
2380 /* ==================================================================== */
2381 /* Register "SH_PIO_NACK_RESET" */
2382 /* Local Block PIO Reset for nack counters */
2383 /* ==================================================================== */
2385 typedef union sh_pio_nack_reset_u {
2386 mmr_t sh_pio_nack_reset_regval;
2389 mmr_t reserved_0 : 63;
2390 } sh_pio_nack_reset_s;
2391 } sh_pio_nack_reset_u_t;
2393 /* ==================================================================== */
2394 /* Register "SH_CONVEYOR_BELT_TIME_OUT" */
2395 /* Local Block conveyor belt time out value */
2396 /* ==================================================================== */
2398 typedef union sh_conveyor_belt_time_out_u {
2399 mmr_t sh_conveyor_belt_time_out_regval;
2402 mmr_t reserved_0 : 52;
2403 } sh_conveyor_belt_time_out_s;
2404 } sh_conveyor_belt_time_out_u_t;
2406 /* ==================================================================== */
2407 /* Register "SH_LB_CREDIT_STATUS" */
2408 /* Credit Counter Status Register */
2409 /* ==================================================================== */
2411 typedef union sh_lb_credit_status_u {
2412 mmr_t sh_lb_credit_status_regval;
2414 mmr_t liq_rq_credit : 5;
2415 mmr_t reserved_0 : 1;
2416 mmr_t liq_rp_credit : 4;
2417 mmr_t reserved_1 : 2;
2418 mmr_t linvv_credit : 6;
2419 mmr_t loq_rq_credit : 5;
2420 mmr_t loq_rp_credit : 5;
2421 mmr_t reserved_2 : 36;
2422 } sh_lb_credit_status_s;
2423 } sh_lb_credit_status_u_t;
2425 /* ==================================================================== */
2426 /* Register "SH_LB_DEBUG_LOCAL_SEL" */
2427 /* LB Debug Port Select */
2428 /* ==================================================================== */
2430 typedef union sh_lb_debug_local_sel_u {
2431 mmr_t sh_lb_debug_local_sel_regval;
2433 mmr_t nibble0_chiplet_sel : 3;
2434 mmr_t reserved_0 : 1;
2435 mmr_t nibble0_nibble_sel : 3;
2436 mmr_t reserved_1 : 1;
2437 mmr_t nibble1_chiplet_sel : 3;
2438 mmr_t reserved_2 : 1;
2439 mmr_t nibble1_nibble_sel : 3;
2440 mmr_t reserved_3 : 1;
2441 mmr_t nibble2_chiplet_sel : 3;
2442 mmr_t reserved_4 : 1;
2443 mmr_t nibble2_nibble_sel : 3;
2444 mmr_t reserved_5 : 1;
2445 mmr_t nibble3_chiplet_sel : 3;
2446 mmr_t reserved_6 : 1;
2447 mmr_t nibble3_nibble_sel : 3;
2448 mmr_t reserved_7 : 1;
2449 mmr_t nibble4_chiplet_sel : 3;
2450 mmr_t reserved_8 : 1;
2451 mmr_t nibble4_nibble_sel : 3;
2452 mmr_t reserved_9 : 1;
2453 mmr_t nibble5_chiplet_sel : 3;
2454 mmr_t reserved_10 : 1;
2455 mmr_t nibble5_nibble_sel : 3;
2456 mmr_t reserved_11 : 1;
2457 mmr_t nibble6_chiplet_sel : 3;
2458 mmr_t reserved_12 : 1;
2459 mmr_t nibble6_nibble_sel : 3;
2460 mmr_t reserved_13 : 1;
2461 mmr_t nibble7_chiplet_sel : 3;
2462 mmr_t reserved_14 : 1;
2463 mmr_t nibble7_nibble_sel : 3;
2464 mmr_t trigger_enable : 1;
2465 } sh_lb_debug_local_sel_s;
2466 } sh_lb_debug_local_sel_u_t;
2468 /* ==================================================================== */
2469 /* Register "SH_LB_DEBUG_PERF_SEL" */
2470 /* LB Debug Port Performance Select */
2471 /* ==================================================================== */
2473 typedef union sh_lb_debug_perf_sel_u {
2474 mmr_t sh_lb_debug_perf_sel_regval;
2476 mmr_t nibble0_chiplet_sel : 3;
2477 mmr_t reserved_0 : 1;
2478 mmr_t nibble0_nibble_sel : 3;
2479 mmr_t reserved_1 : 1;
2480 mmr_t nibble1_chiplet_sel : 3;
2481 mmr_t reserved_2 : 1;
2482 mmr_t nibble1_nibble_sel : 3;
2483 mmr_t reserved_3 : 1;
2484 mmr_t nibble2_chiplet_sel : 3;
2485 mmr_t reserved_4 : 1;
2486 mmr_t nibble2_nibble_sel : 3;
2487 mmr_t reserved_5 : 1;
2488 mmr_t nibble3_chiplet_sel : 3;
2489 mmr_t reserved_6 : 1;
2490 mmr_t nibble3_nibble_sel : 3;
2491 mmr_t reserved_7 : 1;
2492 mmr_t nibble4_chiplet_sel : 3;
2493 mmr_t reserved_8 : 1;
2494 mmr_t nibble4_nibble_sel : 3;
2495 mmr_t reserved_9 : 1;
2496 mmr_t nibble5_chiplet_sel : 3;
2497 mmr_t reserved_10 : 1;
2498 mmr_t nibble5_nibble_sel : 3;
2499 mmr_t reserved_11 : 1;
2500 mmr_t nibble6_chiplet_sel : 3;
2501 mmr_t reserved_12 : 1;
2502 mmr_t nibble6_nibble_sel : 3;
2503 mmr_t reserved_13 : 1;
2504 mmr_t nibble7_chiplet_sel : 3;
2505 mmr_t reserved_14 : 1;
2506 mmr_t nibble7_nibble_sel : 3;
2507 mmr_t reserved_15 : 1;
2508 } sh_lb_debug_perf_sel_s;
2509 } sh_lb_debug_perf_sel_u_t;
2511 /* ==================================================================== */
2512 /* Register "SH_LB_DEBUG_TRIG_SEL" */
2513 /* LB Debug Trigger Select */
2514 /* ==================================================================== */
2516 typedef union sh_lb_debug_trig_sel_u {
2517 mmr_t sh_lb_debug_trig_sel_regval;
2519 mmr_t trigger0_chiplet_sel : 3;
2520 mmr_t reserved_0 : 1;
2521 mmr_t trigger0_nibble_sel : 3;
2522 mmr_t reserved_1 : 1;
2523 mmr_t trigger1_chiplet_sel : 3;
2524 mmr_t reserved_2 : 1;
2525 mmr_t trigger1_nibble_sel : 3;
2526 mmr_t reserved_3 : 1;
2527 mmr_t trigger2_chiplet_sel : 3;
2528 mmr_t reserved_4 : 1;
2529 mmr_t trigger2_nibble_sel : 3;
2530 mmr_t reserved_5 : 1;
2531 mmr_t trigger3_chiplet_sel : 3;
2532 mmr_t reserved_6 : 1;
2533 mmr_t trigger3_nibble_sel : 3;
2534 mmr_t reserved_7 : 1;
2535 mmr_t trigger4_chiplet_sel : 3;
2536 mmr_t reserved_8 : 1;
2537 mmr_t trigger4_nibble_sel : 3;
2538 mmr_t reserved_9 : 1;
2539 mmr_t trigger5_chiplet_sel : 3;
2540 mmr_t reserved_10 : 1;
2541 mmr_t trigger5_nibble_sel : 3;
2542 mmr_t reserved_11 : 1;
2543 mmr_t trigger6_chiplet_sel : 3;
2544 mmr_t reserved_12 : 1;
2545 mmr_t trigger6_nibble_sel : 3;
2546 mmr_t reserved_13 : 1;
2547 mmr_t trigger7_chiplet_sel : 3;
2548 mmr_t reserved_14 : 1;
2549 mmr_t trigger7_nibble_sel : 3;
2550 mmr_t reserved_15 : 1;
2551 } sh_lb_debug_trig_sel_s;
2552 } sh_lb_debug_trig_sel_u_t;
2554 /* ==================================================================== */
2555 /* Register "SH_LB_ERROR_DETAIL_1" */
2556 /* LB Error capture information: HDR1 */
2557 /* ==================================================================== */
2559 typedef union sh_lb_error_detail_1_u {
2560 mmr_t sh_lb_error_detail_1_regval;
2564 mmr_t reserved_0 : 2;
2566 mmr_t reserved_1 : 2;
2568 mmr_t reserved_2 : 5;
2571 mmr_t reserved_3 : 13;
2573 } sh_lb_error_detail_1_s;
2574 } sh_lb_error_detail_1_u_t;
2576 /* ==================================================================== */
2577 /* Register "SH_LB_ERROR_DETAIL_2" */
2579 /* ==================================================================== */
2581 typedef union sh_lb_error_detail_2_u {
2582 mmr_t sh_lb_error_detail_2_regval;
2585 mmr_t reserved_0 : 17;
2586 } sh_lb_error_detail_2_s;
2587 } sh_lb_error_detail_2_u_t;
2589 /* ==================================================================== */
2590 /* Register "SH_LB_ERROR_DETAIL_3" */
2592 /* ==================================================================== */
2594 typedef union sh_lb_error_detail_3_u {
2595 mmr_t sh_lb_error_detail_3_regval;
2598 } sh_lb_error_detail_3_s;
2599 } sh_lb_error_detail_3_u_t;
2601 /* ==================================================================== */
2602 /* Register "SH_LB_ERROR_DETAIL_4" */
2604 /* ==================================================================== */
2606 typedef union sh_lb_error_detail_4_u {
2607 mmr_t sh_lb_error_detail_4_regval;
2610 } sh_lb_error_detail_4_s;
2611 } sh_lb_error_detail_4_u_t;
2613 /* ==================================================================== */
2614 /* Register "SH_LB_ERROR_DETAIL_5" */
2616 /* ==================================================================== */
2618 typedef union sh_lb_error_detail_5_u {
2619 mmr_t sh_lb_error_detail_5_regval;
2621 mmr_t read_retry : 1;
2622 mmr_t ptc1_write : 1;
2623 mmr_t write_retry : 1;
2624 mmr_t count_a_overflow : 1;
2625 mmr_t count_b_overflow : 1;
2626 mmr_t nack_a_timeout : 1;
2627 mmr_t nack_b_timeout : 1;
2628 mmr_t reserved_0 : 57;
2629 } sh_lb_error_detail_5_s;
2630 } sh_lb_error_detail_5_u_t;
2632 /* ==================================================================== */
2633 /* Register "SH_LB_ERROR_MASK" */
2635 /* ==================================================================== */
2637 typedef union sh_lb_error_mask_u {
2638 mmr_t sh_lb_error_mask_regval;
2640 mmr_t rq_bad_cmd : 1;
2641 mmr_t rp_bad_cmd : 1;
2646 mmr_t rq_bad_data : 1;
2647 mmr_t rp_bad_data : 1;
2648 mmr_t rq_bad_addr : 1;
2649 mmr_t rq_time_out : 1;
2650 mmr_t linvv_overflow : 1;
2651 mmr_t unexpected_linv : 1;
2652 mmr_t ptc_1_timeout : 1;
2653 mmr_t junk_bus_err : 1;
2654 mmr_t pio_cb_err : 1;
2655 mmr_t vector_rq_route_error : 1;
2656 mmr_t vector_rp_route_error : 1;
2657 mmr_t gclk_drop : 1;
2658 mmr_t rq_fifo_error : 1;
2659 mmr_t rp_fifo_error : 1;
2660 mmr_t unexp_valid : 1;
2661 mmr_t rq_credit_overflow : 1;
2662 mmr_t rp_credit_overflow : 1;
2663 mmr_t reserved_0 : 41;
2664 } sh_lb_error_mask_s;
2665 } sh_lb_error_mask_u_t;
2667 /* ==================================================================== */
2668 /* Register "SH_LB_ERROR_OVERFLOW" */
2669 /* LB Error Overflow */
2670 /* ==================================================================== */
2672 typedef union sh_lb_error_overflow_u {
2673 mmr_t sh_lb_error_overflow_regval;
2675 mmr_t rq_bad_cmd_ovrfl : 1;
2676 mmr_t rp_bad_cmd_ovrfl : 1;
2677 mmr_t rq_short_ovrfl : 1;
2678 mmr_t rp_short_ovrfl : 1;
2679 mmr_t rq_long_ovrfl : 1;
2680 mmr_t rp_long_ovrfl : 1;
2681 mmr_t rq_bad_data_ovrfl : 1;
2682 mmr_t rp_bad_data_ovrfl : 1;
2683 mmr_t rq_bad_addr_ovrfl : 1;
2684 mmr_t rq_time_out_ovrfl : 1;
2685 mmr_t linvv_overflow_ovrfl : 1;
2686 mmr_t unexpected_linv_ovrfl : 1;
2687 mmr_t ptc_1_timeout_ovrfl : 1;
2688 mmr_t junk_bus_err_ovrfl : 1;
2689 mmr_t pio_cb_err_ovrfl : 1;
2690 mmr_t vector_rq_route_error_ovrfl : 1;
2691 mmr_t vector_rp_route_error_ovrfl : 1;
2692 mmr_t gclk_drop_ovrfl : 1;
2693 mmr_t rq_fifo_error_ovrfl : 1;
2694 mmr_t rp_fifo_error_ovrfl : 1;
2695 mmr_t unexp_valid_ovrfl : 1;
2696 mmr_t rq_credit_overflow_ovrfl : 1;
2697 mmr_t rp_credit_overflow_ovrfl : 1;
2698 mmr_t reserved_0 : 41;
2699 } sh_lb_error_overflow_s;
2700 } sh_lb_error_overflow_u_t;
2702 /* ==================================================================== */
2703 /* Register "SH_LB_ERROR_SUMMARY" */
2705 /* ==================================================================== */
2707 typedef union sh_lb_error_summary_u {
2708 mmr_t sh_lb_error_summary_regval;
2710 mmr_t rq_bad_cmd : 1;
2711 mmr_t rp_bad_cmd : 1;
2716 mmr_t rq_bad_data : 1;
2717 mmr_t rp_bad_data : 1;
2718 mmr_t rq_bad_addr : 1;
2719 mmr_t rq_time_out : 1;
2720 mmr_t linvv_overflow : 1;
2721 mmr_t unexpected_linv : 1;
2722 mmr_t ptc_1_timeout : 1;
2723 mmr_t junk_bus_err : 1;
2724 mmr_t pio_cb_err : 1;
2725 mmr_t vector_rq_route_error : 1;
2726 mmr_t vector_rp_route_error : 1;
2727 mmr_t gclk_drop : 1;
2728 mmr_t rq_fifo_error : 1;
2729 mmr_t rp_fifo_error : 1;
2730 mmr_t unexp_valid : 1;
2731 mmr_t rq_credit_overflow : 1;
2732 mmr_t rp_credit_overflow : 1;
2733 mmr_t reserved_0 : 41;
2734 } sh_lb_error_summary_s;
2735 } sh_lb_error_summary_u_t;
2737 /* ==================================================================== */
2738 /* Register "SH_LB_FIRST_ERROR" */
2739 /* LB First Error */
2740 /* ==================================================================== */
2742 typedef union sh_lb_first_error_u {
2743 mmr_t sh_lb_first_error_regval;
2745 mmr_t rq_bad_cmd : 1;
2746 mmr_t rp_bad_cmd : 1;
2751 mmr_t rq_bad_data : 1;
2752 mmr_t rp_bad_data : 1;
2753 mmr_t rq_bad_addr : 1;
2754 mmr_t rq_time_out : 1;
2755 mmr_t linvv_overflow : 1;
2756 mmr_t unexpected_linv : 1;
2757 mmr_t ptc_1_timeout : 1;
2758 mmr_t junk_bus_err : 1;
2759 mmr_t pio_cb_err : 1;
2760 mmr_t vector_rq_route_error : 1;
2761 mmr_t vector_rp_route_error : 1;
2762 mmr_t gclk_drop : 1;
2763 mmr_t rq_fifo_error : 1;
2764 mmr_t rp_fifo_error : 1;
2765 mmr_t unexp_valid : 1;
2766 mmr_t rq_credit_overflow : 1;
2767 mmr_t rp_credit_overflow : 1;
2768 mmr_t reserved_0 : 41;
2769 } sh_lb_first_error_s;
2770 } sh_lb_first_error_u_t;
2772 /* ==================================================================== */
2773 /* Register "SH_LB_LAST_CREDIT" */
2774 /* Credit counter status register */
2775 /* ==================================================================== */
2777 typedef union sh_lb_last_credit_u {
2778 mmr_t sh_lb_last_credit_regval;
2780 mmr_t liq_rq_credit : 5;
2781 mmr_t reserved_0 : 1;
2782 mmr_t liq_rp_credit : 4;
2783 mmr_t reserved_1 : 2;
2784 mmr_t linvv_credit : 6;
2785 mmr_t loq_rq_credit : 5;
2786 mmr_t loq_rp_credit : 5;
2787 mmr_t reserved_2 : 36;
2788 } sh_lb_last_credit_s;
2789 } sh_lb_last_credit_u_t;
2791 /* ==================================================================== */
2792 /* Register "SH_LB_NACK_STATUS" */
2793 /* Nack Counter Status Register */
2794 /* ==================================================================== */
2796 typedef union sh_lb_nack_status_u {
2797 mmr_t sh_lb_nack_status_regval;
2799 mmr_t pio_nack_a : 12;
2800 mmr_t reserved_0 : 4;
2801 mmr_t pio_nack_b : 12;
2802 mmr_t reserved_1 : 4;
2803 mmr_t junk_nack : 16;
2804 mmr_t cb_timeout_count : 12;
2806 mmr_t reserved_2 : 2;
2807 } sh_lb_nack_status_s;
2808 } sh_lb_nack_status_u_t;
2810 /* ==================================================================== */
2811 /* Register "SH_LB_TRIGGER_COMPARE" */
2812 /* LB Test-point Trigger Compare */
2813 /* ==================================================================== */
2815 typedef union sh_lb_trigger_compare_u {
2816 mmr_t sh_lb_trigger_compare_regval;
2819 mmr_t reserved_0 : 32;
2820 } sh_lb_trigger_compare_s;
2821 } sh_lb_trigger_compare_u_t;
2823 /* ==================================================================== */
2824 /* Register "SH_LB_TRIGGER_DATA" */
2825 /* LB Test-point Trigger Compare Data */
2826 /* ==================================================================== */
2828 typedef union sh_lb_trigger_data_u {
2829 mmr_t sh_lb_trigger_data_regval;
2831 mmr_t compare_pattern : 32;
2832 mmr_t reserved_0 : 32;
2833 } sh_lb_trigger_data_s;
2834 } sh_lb_trigger_data_u_t;
2836 /* ==================================================================== */
2837 /* Register "SH_PI_AEC_CONFIG" */
2838 /* PI Adaptive Error Correction Configuration */
2839 /* ==================================================================== */
2841 typedef union sh_pi_aec_config_u {
2842 mmr_t sh_pi_aec_config_regval;
2845 mmr_t reserved_0 : 61;
2846 } sh_pi_aec_config_s;
2847 } sh_pi_aec_config_u_t;
2849 /* ==================================================================== */
2850 /* Register "SH_PI_AFI_ERROR_MASK" */
2851 /* PI AFI Error Mask */
2852 /* ==================================================================== */
2854 typedef union sh_pi_afi_error_mask_u {
2855 mmr_t sh_pi_afi_error_mask_regval;
2857 mmr_t reserved_0 : 21;
2859 mmr_t rsp_parity : 1;
2860 mmr_t ioq_overrun : 1;
2861 mmr_t req_format : 1;
2862 mmr_t addr_access : 1;
2863 mmr_t req_parity : 1;
2864 mmr_t addr_parity : 1;
2865 mmr_t shub_fsb_dqe : 1;
2866 mmr_t shub_fsb_uce : 1;
2867 mmr_t shub_fsb_ce : 1;
2869 mmr_t bad_snoop : 1;
2870 mmr_t fsb_tbl_miss : 1;
2872 mmr_t reserved_1 : 29;
2873 } sh_pi_afi_error_mask_s;
2874 } sh_pi_afi_error_mask_u_t;
2876 /* ==================================================================== */
2877 /* Register "SH_PI_AFI_TEST_POINT_COMPARE" */
2878 /* PI AFI Test Point Compare */
2879 /* ==================================================================== */
2881 typedef union sh_pi_afi_test_point_compare_u {
2882 mmr_t sh_pi_afi_test_point_compare_regval;
2884 mmr_t compare_mask : 32;
2885 mmr_t compare_pattern : 32;
2886 } sh_pi_afi_test_point_compare_s;
2887 } sh_pi_afi_test_point_compare_u_t;
2889 /* ==================================================================== */
2890 /* Register "SH_PI_AFI_TEST_POINT_SELECT" */
2891 /* PI AFI Test Point Select */
2892 /* ==================================================================== */
2894 typedef union sh_pi_afi_test_point_select_u {
2895 mmr_t sh_pi_afi_test_point_select_regval;
2897 mmr_t nibble0_chiplet_sel : 4;
2898 mmr_t nibble0_nibble_sel : 3;
2899 mmr_t reserved_0 : 1;
2900 mmr_t nibble1_chiplet_sel : 4;
2901 mmr_t nibble1_nibble_sel : 3;
2902 mmr_t reserved_1 : 1;
2903 mmr_t nibble2_chiplet_sel : 4;
2904 mmr_t nibble2_nibble_sel : 3;
2905 mmr_t reserved_2 : 1;
2906 mmr_t nibble3_chiplet_sel : 4;
2907 mmr_t nibble3_nibble_sel : 3;
2908 mmr_t reserved_3 : 1;
2909 mmr_t nibble4_chiplet_sel : 4;
2910 mmr_t nibble4_nibble_sel : 3;
2911 mmr_t reserved_4 : 1;
2912 mmr_t nibble5_chiplet_sel : 4;
2913 mmr_t nibble5_nibble_sel : 3;
2914 mmr_t reserved_5 : 1;
2915 mmr_t nibble6_chiplet_sel : 4;
2916 mmr_t nibble6_nibble_sel : 3;
2917 mmr_t reserved_6 : 1;
2918 mmr_t nibble7_chiplet_sel : 4;
2919 mmr_t nibble7_nibble_sel : 3;
2920 mmr_t trigger_enable : 1;
2921 } sh_pi_afi_test_point_select_s;
2922 } sh_pi_afi_test_point_select_u_t;
2924 /* ==================================================================== */
2925 /* Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT" */
2926 /* PI CRBC Test Point Trigger Select */
2927 /* ==================================================================== */
2929 typedef union sh_pi_afi_test_point_trigger_select_u {
2930 mmr_t sh_pi_afi_test_point_trigger_select_regval;
2932 mmr_t trigger0_chiplet_sel : 4;
2933 mmr_t trigger0_nibble_sel : 3;
2934 mmr_t reserved_0 : 1;
2935 mmr_t trigger1_chiplet_sel : 4;
2936 mmr_t trigger1_nibble_sel : 3;
2937 mmr_t reserved_1 : 1;
2938 mmr_t trigger2_chiplet_sel : 4;
2939 mmr_t trigger2_nibble_sel : 3;
2940 mmr_t reserved_2 : 1;
2941 mmr_t trigger3_chiplet_sel : 4;
2942 mmr_t trigger3_nibble_sel : 3;
2943 mmr_t reserved_3 : 1;
2944 mmr_t trigger4_chiplet_sel : 4;
2945 mmr_t trigger4_nibble_sel : 3;
2946 mmr_t reserved_4 : 1;
2947 mmr_t trigger5_chiplet_sel : 4;
2948 mmr_t trigger5_nibble_sel : 3;
2949 mmr_t reserved_5 : 1;
2950 mmr_t trigger6_chiplet_sel : 4;
2951 mmr_t trigger6_nibble_sel : 3;
2952 mmr_t reserved_6 : 1;
2953 mmr_t trigger7_chiplet_sel : 4;
2954 mmr_t trigger7_nibble_sel : 3;
2955 mmr_t reserved_7 : 1;
2956 } sh_pi_afi_test_point_trigger_select_s;
2957 } sh_pi_afi_test_point_trigger_select_u_t;
2959 /* ==================================================================== */
2960 /* Register "SH_PI_AUTO_REPLY_ENABLE" */
2961 /* PI Auto Reply Enable */
2962 /* ==================================================================== */
2964 typedef union sh_pi_auto_reply_enable_u {
2965 mmr_t sh_pi_auto_reply_enable_regval;
2967 mmr_t auto_reply_enable : 1;
2968 mmr_t reserved_0 : 63;
2969 } sh_pi_auto_reply_enable_s;
2970 } sh_pi_auto_reply_enable_u_t;
2972 /* ==================================================================== */
2973 /* Register "SH_PI_CAM_CONTROL" */
2974 /* CRB CAM MMR Access Control */
2975 /* ==================================================================== */
2977 typedef union sh_pi_cam_control_u {
2978 mmr_t sh_pi_cam_control_regval;
2981 mmr_t reserved_0 : 1;
2982 mmr_t cam_write : 1;
2983 mmr_t rrb_rd_xfer_clear : 1;
2984 mmr_t reserved_1 : 53;
2986 } sh_pi_cam_control_s;
2987 } sh_pi_cam_control_u_t;
2989 /* ==================================================================== */
2990 /* Register "SH_PI_CRBC_TEST_POINT_COMPARE" */
2991 /* PI CRBC Test Point Compare */
2992 /* ==================================================================== */
2994 typedef union sh_pi_crbc_test_point_compare_u {
2995 mmr_t sh_pi_crbc_test_point_compare_regval;
2997 mmr_t compare_mask : 32;
2998 mmr_t compare_pattern : 32;
2999 } sh_pi_crbc_test_point_compare_s;
3000 } sh_pi_crbc_test_point_compare_u_t;
3002 /* ==================================================================== */
3003 /* Register "SH_PI_CRBC_TEST_POINT_SELECT" */
3004 /* PI CRBC Test Point Select */
3005 /* ==================================================================== */
3007 typedef union sh_pi_crbc_test_point_select_u {
3008 mmr_t sh_pi_crbc_test_point_select_regval;
3010 mmr_t nibble0_chiplet_sel : 3;
3011 mmr_t reserved_0 : 1;
3012 mmr_t nibble0_nibble_sel : 3;
3013 mmr_t reserved_1 : 1;
3014 mmr_t nibble1_chiplet_sel : 3;
3015 mmr_t reserved_2 : 1;
3016 mmr_t nibble1_nibble_sel : 3;
3017 mmr_t reserved_3 : 1;
3018 mmr_t nibble2_chiplet_sel : 3;
3019 mmr_t reserved_4 : 1;
3020 mmr_t nibble2_nibble_sel : 3;
3021 mmr_t reserved_5 : 1;
3022 mmr_t nibble3_chiplet_sel : 3;
3023 mmr_t reserved_6 : 1;
3024 mmr_t nibble3_nibble_sel : 3;
3025 mmr_t reserved_7 : 1;
3026 mmr_t nibble4_chiplet_sel : 3;
3027 mmr_t reserved_8 : 1;
3028 mmr_t nibble4_nibble_sel : 3;
3029 mmr_t reserved_9 : 1;
3030 mmr_t nibble5_chiplet_sel : 3;
3031 mmr_t reserved_10 : 1;
3032 mmr_t nibble5_nibble_sel : 3;
3033 mmr_t reserved_11 : 1;
3034 mmr_t nibble6_chiplet_sel : 3;
3035 mmr_t reserved_12 : 1;
3036 mmr_t nibble6_nibble_sel : 3;
3037 mmr_t reserved_13 : 1;
3038 mmr_t nibble7_chiplet_sel : 3;
3039 mmr_t reserved_14 : 1;
3040 mmr_t nibble7_nibble_sel : 3;
3041 mmr_t trigger_enable : 1;
3042 } sh_pi_crbc_test_point_select_s;
3043 } sh_pi_crbc_test_point_select_u_t;
3045 /* ==================================================================== */
3046 /* Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT" */
3047 /* PI CRBC Test Point Trigger Select */
3048 /* ==================================================================== */
3050 typedef union sh_pi_crbc_test_point_trigger_select_u {
3051 mmr_t sh_pi_crbc_test_point_trigger_select_regval;
3053 mmr_t trigger0_chiplet_sel : 3;
3054 mmr_t reserved_0 : 1;
3055 mmr_t trigger0_nibble_sel : 3;
3056 mmr_t reserved_1 : 1;
3057 mmr_t trigger1_chiplet_sel : 3;
3058 mmr_t reserved_2 : 1;
3059 mmr_t trigger1_nibble_sel : 3;
3060 mmr_t reserved_3 : 1;
3061 mmr_t trigger2_chiplet_sel : 3;
3062 mmr_t reserved_4 : 1;
3063 mmr_t trigger2_nibble_sel : 3;
3064 mmr_t reserved_5 : 1;
3065 mmr_t trigger3_chiplet_sel : 3;
3066 mmr_t reserved_6 : 1;
3067 mmr_t trigger3_nibble_sel : 3;
3068 mmr_t reserved_7 : 1;
3069 mmr_t trigger4_chiplet_sel : 3;
3070 mmr_t reserved_8 : 1;
3071 mmr_t trigger4_nibble_sel : 3;
3072 mmr_t reserved_9 : 1;
3073 mmr_t trigger5_chiplet_sel : 3;
3074 mmr_t reserved_10 : 1;
3075 mmr_t trigger5_nibble_sel : 3;
3076 mmr_t reserved_11 : 1;
3077 mmr_t trigger6_chiplet_sel : 3;
3078 mmr_t reserved_12 : 1;
3079 mmr_t trigger6_nibble_sel : 3;
3080 mmr_t reserved_13 : 1;
3081 mmr_t trigger7_chiplet_sel : 3;
3082 mmr_t reserved_14 : 1;
3083 mmr_t trigger7_nibble_sel : 3;
3084 mmr_t reserved_15 : 1;
3085 } sh_pi_crbc_test_point_trigger_select_s;
3086 } sh_pi_crbc_test_point_trigger_select_u_t;
3088 /* ==================================================================== */
3089 /* Register "SH_PI_CRBP_ERROR_MASK" */
3090 /* PI CRBP Error Mask */
3091 /* ==================================================================== */
3093 typedef union sh_pi_crbp_error_mask_u {
3094 mmr_t sh_pi_crbp_error_mask_regval;
3096 mmr_t fsb_proto_err : 1;
3097 mmr_t gfx_rp_err : 1;
3098 mmr_t xb_proto_err : 1;
3099 mmr_t mem_rp_err : 1;
3100 mmr_t pio_rp_err : 1;
3101 mmr_t mem_to_err : 1;
3102 mmr_t pio_to_err : 1;
3103 mmr_t fsb_shub_uce : 1;
3104 mmr_t fsb_shub_ce : 1;
3105 mmr_t msg_color_err : 1;
3106 mmr_t md_rq_q_oflow : 1;
3107 mmr_t md_rp_q_oflow : 1;
3108 mmr_t xn_rq_q_oflow : 1;
3109 mmr_t xn_rp_q_oflow : 1;
3110 mmr_t nack_oflow : 1;
3111 mmr_t gfx_int_0 : 1;
3112 mmr_t gfx_int_1 : 1;
3113 mmr_t md_rq_crd_oflow : 1;
3114 mmr_t md_rp_crd_oflow : 1;
3115 mmr_t xn_rq_crd_oflow : 1;
3116 mmr_t xn_rp_crd_oflow : 1;
3117 mmr_t reserved_0 : 43;
3118 } sh_pi_crbp_error_mask_s;
3119 } sh_pi_crbp_error_mask_u_t;
3121 /* ==================================================================== */
3122 /* Register "SH_PI_CRBP_FSB_PIPE_COMPARE" */
3123 /* CRBP FSB Pipe Compare */
3124 /* ==================================================================== */
3126 typedef union sh_pi_crbp_fsb_pipe_compare_u {
3127 mmr_t sh_pi_crbp_fsb_pipe_compare_regval;
3129 mmr_t compare_address : 47;
3130 mmr_t compare_req : 6;
3131 mmr_t reserved_0 : 11;
3132 } sh_pi_crbp_fsb_pipe_compare_s;
3133 } sh_pi_crbp_fsb_pipe_compare_u_t;
3135 /* ==================================================================== */
3136 /* Register "SH_PI_CRBP_FSB_PIPE_MASK" */
3137 /* CRBP Compare Mask */
3138 /* ==================================================================== */
3140 typedef union sh_pi_crbp_fsb_pipe_mask_u {
3141 mmr_t sh_pi_crbp_fsb_pipe_mask_regval;
3143 mmr_t compare_address_mask : 47;
3144 mmr_t compare_req_mask : 6;
3145 mmr_t reserved_0 : 11;
3146 } sh_pi_crbp_fsb_pipe_mask_s;
3147 } sh_pi_crbp_fsb_pipe_mask_u_t;
3149 /* ==================================================================== */
3150 /* Register "SH_PI_CRBP_TEST_POINT_COMPARE" */
3151 /* PI CRBP Test Point Compare */
3152 /* ==================================================================== */
3154 typedef union sh_pi_crbp_test_point_compare_u {
3155 mmr_t sh_pi_crbp_test_point_compare_regval;
3157 mmr_t compare_mask : 32;
3158 mmr_t compare_pattern : 32;
3159 } sh_pi_crbp_test_point_compare_s;
3160 } sh_pi_crbp_test_point_compare_u_t;
3162 /* ==================================================================== */
3163 /* Register "SH_PI_CRBP_TEST_POINT_SELECT" */
3164 /* PI CRBP Test Point Select */
3165 /* ==================================================================== */
3167 typedef union sh_pi_crbp_test_point_select_u {
3168 mmr_t sh_pi_crbp_test_point_select_regval;
3170 mmr_t nibble0_chiplet_sel : 3;
3171 mmr_t reserved_0 : 1;
3172 mmr_t nibble0_nibble_sel : 3;
3173 mmr_t reserved_1 : 1;
3174 mmr_t nibble1_chiplet_sel : 3;
3175 mmr_t reserved_2 : 1;
3176 mmr_t nibble1_nibble_sel : 3;
3177 mmr_t reserved_3 : 1;
3178 mmr_t nibble2_chiplet_sel : 3;
3179 mmr_t reserved_4 : 1;
3180 mmr_t nibble2_nibble_sel : 3;
3181 mmr_t reserved_5 : 1;
3182 mmr_t nibble3_chiplet_sel : 3;
3183 mmr_t reserved_6 : 1;
3184 mmr_t nibble3_nibble_sel : 3;
3185 mmr_t reserved_7 : 1;
3186 mmr_t nibble4_chiplet_sel : 3;
3187 mmr_t reserved_8 : 1;
3188 mmr_t nibble4_nibble_sel : 3;
3189 mmr_t reserved_9 : 1;
3190 mmr_t nibble5_chiplet_sel : 3;
3191 mmr_t reserved_10 : 1;
3192 mmr_t nibble5_nibble_sel : 3;
3193 mmr_t reserved_11 : 1;
3194 mmr_t nibble6_chiplet_sel : 3;
3195 mmr_t reserved_12 : 1;
3196 mmr_t nibble6_nibble_sel : 3;
3197 mmr_t reserved_13 : 1;
3198 mmr_t nibble7_chiplet_sel : 3;
3199 mmr_t reserved_14 : 1;
3200 mmr_t nibble7_nibble_sel : 3;
3201 mmr_t trigger_enable : 1;
3202 } sh_pi_crbp_test_point_select_s;
3203 } sh_pi_crbp_test_point_select_u_t;
3205 /* ==================================================================== */
3206 /* Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT" */
3207 /* PI CRBP Test Point Trigger Select */
3208 /* ==================================================================== */
3210 typedef union sh_pi_crbp_test_point_trigger_select_u {
3211 mmr_t sh_pi_crbp_test_point_trigger_select_regval;
3213 mmr_t trigger0_chiplet_sel : 3;
3214 mmr_t reserved_0 : 1;
3215 mmr_t trigger0_nibble_sel : 3;
3216 mmr_t reserved_1 : 1;
3217 mmr_t trigger1_chiplet_sel : 3;
3218 mmr_t reserved_2 : 1;
3219 mmr_t trigger1_nibble_sel : 3;
3220 mmr_t reserved_3 : 1;
3221 mmr_t trigger2_chiplet_sel : 3;
3222 mmr_t reserved_4 : 1;
3223 mmr_t trigger2_nibble_sel : 3;
3224 mmr_t reserved_5 : 1;
3225 mmr_t trigger3_chiplet_sel : 3;
3226 mmr_t reserved_6 : 1;
3227 mmr_t trigger3_nibble_sel : 3;
3228 mmr_t reserved_7 : 1;
3229 mmr_t trigger4_chiplet_sel : 3;
3230 mmr_t reserved_8 : 1;
3231 mmr_t trigger4_nibble_sel : 3;
3232 mmr_t reserved_9 : 1;
3233 mmr_t trigger5_chiplet_sel : 3;
3234 mmr_t reserved_10 : 1;
3235 mmr_t trigger5_nibble_sel : 3;
3236 mmr_t reserved_11 : 1;
3237 mmr_t trigger6_chiplet_sel : 3;
3238 mmr_t reserved_12 : 1;
3239 mmr_t trigger6_nibble_sel : 3;
3240 mmr_t reserved_13 : 1;
3241 mmr_t trigger7_chiplet_sel : 3;
3242 mmr_t reserved_14 : 1;
3243 mmr_t trigger7_nibble_sel : 3;
3244 mmr_t reserved_15 : 1;
3245 } sh_pi_crbp_test_point_trigger_select_s;
3246 } sh_pi_crbp_test_point_trigger_select_u_t;
3248 /* ==================================================================== */
3249 /* Register "SH_PI_CRBP_XB_PIPE_COMPARE_0" */
3250 /* CRBP XB Pipe Compare */
3251 /* ==================================================================== */
3253 typedef union sh_pi_crbp_xb_pipe_compare_0_u {
3254 mmr_t sh_pi_crbp_xb_pipe_compare_0_regval;
3256 mmr_t compare_address : 47;
3257 mmr_t compare_command : 8;
3258 mmr_t reserved_0 : 9;
3259 } sh_pi_crbp_xb_pipe_compare_0_s;
3260 } sh_pi_crbp_xb_pipe_compare_0_u_t;
3262 /* ==================================================================== */
3263 /* Register "SH_PI_CRBP_XB_PIPE_COMPARE_1" */
3264 /* CRBP XB Pipe Compare */
3265 /* ==================================================================== */
3267 typedef union sh_pi_crbp_xb_pipe_compare_1_u {
3268 mmr_t sh_pi_crbp_xb_pipe_compare_1_regval;
3270 mmr_t compare_source : 14;
3271 mmr_t reserved_0 : 2;
3272 mmr_t compare_supplemental : 14;
3273 mmr_t reserved_1 : 2;
3274 mmr_t compare_echo : 9;
3275 mmr_t reserved_2 : 23;
3276 } sh_pi_crbp_xb_pipe_compare_1_s;
3277 } sh_pi_crbp_xb_pipe_compare_1_u_t;
3279 /* ==================================================================== */
3280 /* Register "SH_PI_CRBP_XB_PIPE_MASK_0" */
3281 /* CRBP Compare Mask Register 1 */
3282 /* ==================================================================== */
3284 typedef union sh_pi_crbp_xb_pipe_mask_0_u {
3285 mmr_t sh_pi_crbp_xb_pipe_mask_0_regval;
3287 mmr_t compare_address_mask : 47;
3288 mmr_t compare_command_mask : 8;
3289 mmr_t reserved_0 : 9;
3290 } sh_pi_crbp_xb_pipe_mask_0_s;
3291 } sh_pi_crbp_xb_pipe_mask_0_u_t;
3293 /* ==================================================================== */
3294 /* Register "SH_PI_CRBP_XB_PIPE_MASK_1" */
3295 /* CRBP XB Pipe Compare Mask Register 1 */
3296 /* ==================================================================== */
3298 typedef union sh_pi_crbp_xb_pipe_mask_1_u {
3299 mmr_t sh_pi_crbp_xb_pipe_mask_1_regval;
3301 mmr_t compare_source_mask : 14;
3302 mmr_t reserved_0 : 2;
3303 mmr_t compare_supplemental_mask : 14;
3304 mmr_t reserved_1 : 2;
3305 mmr_t compare_echo_mask : 9;
3306 mmr_t reserved_2 : 23;
3307 } sh_pi_crbp_xb_pipe_mask_1_s;
3308 } sh_pi_crbp_xb_pipe_mask_1_u_t;
3310 /* ==================================================================== */
3311 /* Register "SH_PI_DPC_QUEUE_CONFIG" */
3312 /* DPC Queue Configuration */
3313 /* ==================================================================== */
3315 typedef union sh_pi_dpc_queue_config_u {
3316 mmr_t sh_pi_dpc_queue_config_regval;
3318 mmr_t dwcq_ae_level : 5;
3319 mmr_t reserved_0 : 3;
3320 mmr_t dwcq_af_thresh : 5;
3321 mmr_t reserved_1 : 3;
3322 mmr_t fwcq_ae_level : 5;
3323 mmr_t reserved_2 : 3;
3324 mmr_t fwcq_af_thresh : 5;
3325 mmr_t reserved_3 : 35;
3326 } sh_pi_dpc_queue_config_s;
3327 } sh_pi_dpc_queue_config_u_t;
3329 /* ==================================================================== */
3330 /* Register "SH_PI_ERROR_MASK" */
3332 /* ==================================================================== */
3334 typedef union sh_pi_error_mask_u {
3335 mmr_t sh_pi_error_mask_regval;
3337 mmr_t fsb_proto_err : 1;
3338 mmr_t gfx_rp_err : 1;
3339 mmr_t xb_proto_err : 1;
3340 mmr_t mem_rp_err : 1;
3341 mmr_t pio_rp_err : 1;
3342 mmr_t mem_to_err : 1;
3343 mmr_t pio_to_err : 1;
3344 mmr_t fsb_shub_uce : 1;
3345 mmr_t fsb_shub_ce : 1;
3346 mmr_t msg_color_err : 1;
3347 mmr_t md_rq_q_oflow : 1;
3348 mmr_t md_rp_q_oflow : 1;
3349 mmr_t xn_rq_q_oflow : 1;
3350 mmr_t xn_rp_q_oflow : 1;
3351 mmr_t nack_oflow : 1;
3352 mmr_t gfx_int_0 : 1;
3353 mmr_t gfx_int_1 : 1;
3354 mmr_t md_rq_crd_oflow : 1;
3355 mmr_t md_rp_crd_oflow : 1;
3356 mmr_t xn_rq_crd_oflow : 1;
3357 mmr_t xn_rp_crd_oflow : 1;
3359 mmr_t rsp_parity : 1;
3360 mmr_t ioq_overrun : 1;
3361 mmr_t req_format : 1;
3362 mmr_t addr_access : 1;
3363 mmr_t req_parity : 1;
3364 mmr_t addr_parity : 1;
3365 mmr_t shub_fsb_dqe : 1;
3366 mmr_t shub_fsb_uce : 1;
3367 mmr_t shub_fsb_ce : 1;
3369 mmr_t bad_snoop : 1;
3370 mmr_t fsb_tbl_miss : 1;
3371 mmr_t msg_length : 1;
3372 mmr_t reserved_0 : 29;
3373 } sh_pi_error_mask_s;
3374 } sh_pi_error_mask_u_t;
3376 /* ==================================================================== */
3377 /* Register "SH_PI_EXPRESS_REPLY_CONFIG" */
3378 /* PI Express Reply Configuration */
3379 /* ==================================================================== */
3381 typedef union sh_pi_express_reply_config_u {
3382 mmr_t sh_pi_express_reply_config_regval;
3385 mmr_t reserved_0 : 61;
3386 } sh_pi_express_reply_config_s;
3387 } sh_pi_express_reply_config_u_t;
3389 /* ==================================================================== */
3390 /* Register "SH_PI_FSB_COMPARE_VALUE" */
3391 /* FSB Compare Value */
3392 /* ==================================================================== */
3394 typedef union sh_pi_fsb_compare_value_u {
3395 mmr_t sh_pi_fsb_compare_value_regval;
3397 mmr_t compare_value : 64;
3398 } sh_pi_fsb_compare_value_s;
3399 } sh_pi_fsb_compare_value_u_t;
3401 /* ==================================================================== */
3402 /* Register "SH_PI_FSB_COMPARE_MASK" */
3403 /* FSB Compare Mask */
3404 /* ==================================================================== */
3406 typedef union sh_pi_fsb_compare_mask_u {
3407 mmr_t sh_pi_fsb_compare_mask_regval;
3409 mmr_t mask_value : 64;
3410 } sh_pi_fsb_compare_mask_s;
3411 } sh_pi_fsb_compare_mask_u_t;
3413 /* ==================================================================== */
3414 /* Register "SH_PI_FSB_ERROR_INJECTION" */
3415 /* Inject an Error onto the FSB */
3416 /* ==================================================================== */
3418 typedef union sh_pi_fsb_error_injection_u {
3419 mmr_t sh_pi_fsb_error_injection_regval;
3421 mmr_t rp_pe_to_fsb : 1;
3422 mmr_t ap0_pe_to_fsb : 1;
3423 mmr_t ap1_pe_to_fsb : 1;
3424 mmr_t rsp_pe_to_fsb : 1;
3425 mmr_t dw0_ce_to_fsb : 1;
3426 mmr_t dw0_uce_to_fsb : 1;
3427 mmr_t dw1_ce_to_fsb : 1;
3428 mmr_t dw1_uce_to_fsb : 1;
3429 mmr_t ip0_pe_to_fsb : 1;
3430 mmr_t ip1_pe_to_fsb : 1;
3431 mmr_t reserved_0 : 6;
3432 mmr_t rp_pe_from_fsb : 1;
3433 mmr_t ap0_pe_from_fsb : 1;
3434 mmr_t ap1_pe_from_fsb : 1;
3435 mmr_t rsp_pe_from_fsb : 1;
3436 mmr_t dw0_ce_from_fsb : 1;
3437 mmr_t dw0_uce_from_fsb : 1;
3438 mmr_t dw1_ce_from_fsb : 1;
3439 mmr_t dw1_uce_from_fsb : 1;
3440 mmr_t dw2_ce_from_fsb : 1;
3441 mmr_t dw2_uce_from_fsb : 1;
3442 mmr_t dw3_ce_from_fsb : 1;
3443 mmr_t dw3_uce_from_fsb : 1;
3444 mmr_t reserved_1 : 4;
3445 mmr_t ioq_overrun : 1;
3448 mmr_t reserved_2 : 29;
3449 } sh_pi_fsb_error_injection_s;
3450 } sh_pi_fsb_error_injection_u_t;
3452 /* ==================================================================== */
3453 /* Register "SH_PI_MD2PI_REPLY_VC_CONFIG" */
3454 /* MD-to-PI Reply Virtual Channel Configuration */
3455 /* ==================================================================== */
3457 typedef union sh_pi_md2pi_reply_vc_config_u {
3458 mmr_t sh_pi_md2pi_reply_vc_config_regval;
3460 mmr_t hdr_depth : 4;
3461 mmr_t data_depth : 4;
3462 mmr_t max_credits : 6;
3463 mmr_t reserved_0 : 48;
3464 mmr_t force_credit : 1;
3465 mmr_t capture_credit_status : 1;
3466 } sh_pi_md2pi_reply_vc_config_s;
3467 } sh_pi_md2pi_reply_vc_config_u_t;
3469 /* ==================================================================== */
3470 /* Register "SH_PI_MD2PI_REQUEST_VC_CONFIG" */
3471 /* MD-to-PI Request Virtual Channel Configuration */
3472 /* ==================================================================== */
3474 typedef union sh_pi_md2pi_request_vc_config_u {
3475 mmr_t sh_pi_md2pi_request_vc_config_regval;
3477 mmr_t hdr_depth : 4;
3478 mmr_t data_depth : 4;
3479 mmr_t max_credits : 6;
3480 mmr_t reserved_0 : 48;
3481 mmr_t force_credit : 1;
3482 mmr_t capture_credit_status : 1;
3483 } sh_pi_md2pi_request_vc_config_s;
3484 } sh_pi_md2pi_request_vc_config_u_t;
3486 /* ==================================================================== */
3487 /* Register "SH_PI_QUEUE_ERROR_INJECTION" */
3488 /* PI Queue Error Injection */
3489 /* ==================================================================== */
3491 typedef union sh_pi_queue_error_injection_u {
3492 mmr_t sh_pi_queue_error_injection_regval;
3494 mmr_t dat_dfr_q : 1;
3495 mmr_t dxb_wtl_cmnd_q : 1;
3496 mmr_t fsb_wtl_cmnd_q : 1;
3497 mmr_t mdpi_rpy_bfr : 1;
3499 mmr_t rxl_kill_q : 1;
3500 mmr_t rxl_rdy_q : 1;
3501 mmr_t xnpi_rpy_bfr : 1;
3502 mmr_t reserved_0 : 56;
3503 } sh_pi_queue_error_injection_s;
3504 } sh_pi_queue_error_injection_u_t;
3506 /* ==================================================================== */
3507 /* Register "SH_PI_TEST_POINT_COMPARE" */
3508 /* PI Test Point Compare */
3509 /* ==================================================================== */
3511 typedef union sh_pi_test_point_compare_u {
3512 mmr_t sh_pi_test_point_compare_regval;
3514 mmr_t compare_mask : 32;
3515 mmr_t compare_pattern : 32;
3516 } sh_pi_test_point_compare_s;
3517 } sh_pi_test_point_compare_u_t;
3519 /* ==================================================================== */
3520 /* Register "SH_PI_TEST_POINT_SELECT" */
3521 /* PI Test Point Select */
3522 /* ==================================================================== */
3524 typedef union sh_pi_test_point_select_u {
3525 mmr_t sh_pi_test_point_select_regval;
3527 mmr_t nibble0_chiplet_sel : 3;
3528 mmr_t reserved_0 : 1;
3529 mmr_t nibble0_nibble_sel : 3;
3530 mmr_t reserved_1 : 1;
3531 mmr_t nibble1_chiplet_sel : 3;
3532 mmr_t reserved_2 : 1;
3533 mmr_t nibble1_nibble_sel : 3;
3534 mmr_t reserved_3 : 1;
3535 mmr_t nibble2_chiplet_sel : 3;
3536 mmr_t reserved_4 : 1;
3537 mmr_t nibble2_nibble_sel : 3;
3538 mmr_t reserved_5 : 1;
3539 mmr_t nibble3_chiplet_sel : 3;
3540 mmr_t reserved_6 : 1;
3541 mmr_t nibble3_nibble_sel : 3;
3542 mmr_t reserved_7 : 1;
3543 mmr_t nibble4_chiplet_sel : 3;
3544 mmr_t reserved_8 : 1;
3545 mmr_t nibble4_nibble_sel : 3;
3546 mmr_t reserved_9 : 1;
3547 mmr_t nibble5_chiplet_sel : 3;
3548 mmr_t reserved_10 : 1;
3549 mmr_t nibble5_nibble_sel : 3;
3550 mmr_t reserved_11 : 1;
3551 mmr_t nibble6_chiplet_sel : 3;
3552 mmr_t reserved_12 : 1;
3553 mmr_t nibble6_nibble_sel : 3;
3554 mmr_t reserved_13 : 1;
3555 mmr_t nibble7_chiplet_sel : 3;
3556 mmr_t reserved_14 : 1;
3557 mmr_t nibble7_nibble_sel : 3;
3558 mmr_t trigger_enable : 1;
3559 } sh_pi_test_point_select_s;
3560 } sh_pi_test_point_select_u_t;
3562 /* ==================================================================== */
3563 /* Register "SH_PI_TEST_POINT_TRIGGER_SELECT" */
3564 /* PI Test Point Trigger Select */
3565 /* ==================================================================== */
3567 typedef union sh_pi_test_point_trigger_select_u {
3568 mmr_t sh_pi_test_point_trigger_select_regval;
3570 mmr_t trigger0_chiplet_sel : 3;
3571 mmr_t reserved_0 : 1;
3572 mmr_t trigger0_nibble_sel : 3;
3573 mmr_t reserved_1 : 1;
3574 mmr_t trigger1_chiplet_sel : 3;
3575 mmr_t reserved_2 : 1;
3576 mmr_t trigger1_nibble_sel : 3;
3577 mmr_t reserved_3 : 1;
3578 mmr_t trigger2_chiplet_sel : 3;
3579 mmr_t reserved_4 : 1;
3580 mmr_t trigger2_nibble_sel : 3;
3581 mmr_t reserved_5 : 1;
3582 mmr_t trigger3_chiplet_sel : 3;
3583 mmr_t reserved_6 : 1;
3584 mmr_t trigger3_nibble_sel : 3;
3585 mmr_t reserved_7 : 1;
3586 mmr_t trigger4_chiplet_sel : 3;
3587 mmr_t reserved_8 : 1;
3588 mmr_t trigger4_nibble_sel : 3;
3589 mmr_t reserved_9 : 1;
3590 mmr_t trigger5_chiplet_sel : 3;
3591 mmr_t reserved_10 : 1;
3592 mmr_t trigger5_nibble_sel : 3;
3593 mmr_t reserved_11 : 1;
3594 mmr_t trigger6_chiplet_sel : 3;
3595 mmr_t reserved_12 : 1;
3596 mmr_t trigger6_nibble_sel : 3;
3597 mmr_t reserved_13 : 1;
3598 mmr_t trigger7_chiplet_sel : 3;
3599 mmr_t reserved_14 : 1;
3600 mmr_t trigger7_nibble_sel : 3;
3601 mmr_t reserved_15 : 1;
3602 } sh_pi_test_point_trigger_select_s;
3603 } sh_pi_test_point_trigger_select_u_t;
3605 /* ==================================================================== */
3606 /* Register "SH_PI_XN2PI_REPLY_VC_CONFIG" */
3607 /* XN-to-PI Reply Virtual Channel Configuration */
3608 /* ==================================================================== */
3610 typedef union sh_pi_xn2pi_reply_vc_config_u {
3611 mmr_t sh_pi_xn2pi_reply_vc_config_regval;
3613 mmr_t hdr_depth : 4;
3614 mmr_t data_depth : 4;
3615 mmr_t max_credits : 6;
3616 mmr_t reserved_0 : 48;
3617 mmr_t force_credit : 1;
3618 mmr_t capture_credit_status : 1;
3619 } sh_pi_xn2pi_reply_vc_config_s;
3620 } sh_pi_xn2pi_reply_vc_config_u_t;
3622 /* ==================================================================== */
3623 /* Register "SH_PI_XN2PI_REQUEST_VC_CONFIG" */
3624 /* XN-to-PI Request Virtual Channel Configuration */
3625 /* ==================================================================== */
3627 typedef union sh_pi_xn2pi_request_vc_config_u {
3628 mmr_t sh_pi_xn2pi_request_vc_config_regval;
3630 mmr_t hdr_depth : 4;
3631 mmr_t data_depth : 4;
3632 mmr_t max_credits : 6;
3633 mmr_t reserved_0 : 48;
3634 mmr_t force_credit : 1;
3635 mmr_t capture_credit_status : 1;
3636 } sh_pi_xn2pi_request_vc_config_s;
3637 } sh_pi_xn2pi_request_vc_config_u_t;
3639 /* ==================================================================== */
3640 /* Register "SH_PI_AEC_STATUS" */
3641 /* PI Adaptive Error Correction Status */
3642 /* ==================================================================== */
3644 typedef union sh_pi_aec_status_u {
3645 mmr_t sh_pi_aec_status_regval;
3648 mmr_t reserved_0 : 61;
3649 } sh_pi_aec_status_s;
3650 } sh_pi_aec_status_u_t;
3652 /* ==================================================================== */
3653 /* Register "SH_PI_AFI_FIRST_ERROR" */
3654 /* PI AFI First Error */
3655 /* ==================================================================== */
3657 typedef union sh_pi_afi_first_error_u {
3658 mmr_t sh_pi_afi_first_error_regval;
3660 mmr_t reserved_0 : 7;
3661 mmr_t fsb_shub_uce : 1;
3662 mmr_t fsb_shub_ce : 1;
3663 mmr_t reserved_1 : 12;
3665 mmr_t rsp_parity : 1;
3666 mmr_t ioq_overrun : 1;
3667 mmr_t req_format : 1;
3668 mmr_t addr_access : 1;
3669 mmr_t req_parity : 1;
3670 mmr_t addr_parity : 1;
3671 mmr_t shub_fsb_dqe : 1;
3672 mmr_t shub_fsb_uce : 1;
3673 mmr_t shub_fsb_ce : 1;
3675 mmr_t bad_snoop : 1;
3676 mmr_t fsb_tbl_miss : 1;
3678 mmr_t reserved_2 : 29;
3679 } sh_pi_afi_first_error_s;
3680 } sh_pi_afi_first_error_u_t;
3682 /* ==================================================================== */
3683 /* Register "SH_PI_CAM_ADDRESS_READ_DATA" */
3684 /* CRB CAM MMR Address Read Data */
3685 /* ==================================================================== */
3687 typedef union sh_pi_cam_address_read_data_u {
3688 mmr_t sh_pi_cam_address_read_data_regval;
3690 mmr_t cam_addr : 48;
3691 mmr_t reserved_0 : 15;
3692 mmr_t cam_addr_val : 1;
3693 } sh_pi_cam_address_read_data_s;
3694 } sh_pi_cam_address_read_data_u_t;
3696 /* ==================================================================== */
3697 /* Register "SH_PI_CAM_LPRA_READ_DATA" */
3698 /* CRB CAM MMR LPRA Read Data */
3699 /* ==================================================================== */
3701 typedef union sh_pi_cam_lpra_read_data_u {
3702 mmr_t sh_pi_cam_lpra_read_data_regval;
3704 mmr_t cam_lpra : 64;
3705 } sh_pi_cam_lpra_read_data_s;
3706 } sh_pi_cam_lpra_read_data_u_t;
3708 /* ==================================================================== */
3709 /* Register "SH_PI_CAM_STATE_READ_DATA" */
3710 /* CRB CAM MMR State Read Data */
3711 /* ==================================================================== */
3713 typedef union sh_pi_cam_state_read_data_u {
3714 mmr_t sh_pi_cam_state_read_data_regval;
3716 mmr_t cam_state : 4;
3718 mmr_t cam_state_rd_pend : 1;
3719 mmr_t reserved_0 : 26;
3720 mmr_t cam_lpra : 18;
3721 mmr_t reserved_1 : 13;
3722 mmr_t cam_rd_data_val : 1;
3723 } sh_pi_cam_state_read_data_s;
3724 } sh_pi_cam_state_read_data_u_t;
3726 /* ==================================================================== */
3727 /* Register "SH_PI_CORRECTED_DETAIL_1" */
3728 /* PI Corrected Error Detail */
3729 /* ==================================================================== */
3731 typedef union sh_pi_corrected_detail_1_u {
3732 mmr_t sh_pi_corrected_detail_1_regval;
3737 } sh_pi_corrected_detail_1_s;
3738 } sh_pi_corrected_detail_1_u_t;
3740 /* ==================================================================== */
3741 /* Register "SH_PI_CORRECTED_DETAIL_2" */
3742 /* PI Corrected Error Detail 2 */
3743 /* ==================================================================== */
3745 typedef union sh_pi_corrected_detail_2_u {
3746 mmr_t sh_pi_corrected_detail_2_regval;
3749 } sh_pi_corrected_detail_2_s;
3750 } sh_pi_corrected_detail_2_u_t;
3752 /* ==================================================================== */
3753 /* Register "SH_PI_CORRECTED_DETAIL_3" */
3754 /* PI Corrected Error Detail 3 */
3755 /* ==================================================================== */
3757 typedef union sh_pi_corrected_detail_3_u {
3758 mmr_t sh_pi_corrected_detail_3_regval;
3763 } sh_pi_corrected_detail_3_s;
3764 } sh_pi_corrected_detail_3_u_t;
3766 /* ==================================================================== */
3767 /* Register "SH_PI_CORRECTED_DETAIL_4" */
3768 /* PI Corrected Error Detail 4 */
3769 /* ==================================================================== */
3771 typedef union sh_pi_corrected_detail_4_u {
3772 mmr_t sh_pi_corrected_detail_4_regval;
3775 } sh_pi_corrected_detail_4_s;
3776 } sh_pi_corrected_detail_4_u_t;
3778 /* ==================================================================== */
3779 /* Register "SH_PI_CRBP_FIRST_ERROR" */
3780 /* PI CRBP First Error */
3781 /* ==================================================================== */
3783 typedef union sh_pi_crbp_first_error_u {
3784 mmr_t sh_pi_crbp_first_error_regval;
3786 mmr_t fsb_proto_err : 1;
3787 mmr_t gfx_rp_err : 1;
3788 mmr_t xb_proto_err : 1;
3789 mmr_t mem_rp_err : 1;
3790 mmr_t pio_rp_err : 1;
3791 mmr_t mem_to_err : 1;
3792 mmr_t pio_to_err : 1;
3793 mmr_t fsb_shub_uce : 1;
3794 mmr_t fsb_shub_ce : 1;
3795 mmr_t msg_color_err : 1;
3796 mmr_t md_rq_q_oflow : 1;
3797 mmr_t md_rp_q_oflow : 1;
3798 mmr_t xn_rq_q_oflow : 1;
3799 mmr_t xn_rp_q_oflow : 1;
3800 mmr_t nack_oflow : 1;
3801 mmr_t gfx_int_0 : 1;
3802 mmr_t gfx_int_1 : 1;
3803 mmr_t md_rq_crd_oflow : 1;
3804 mmr_t md_rp_crd_oflow : 1;
3805 mmr_t xn_rq_crd_oflow : 1;
3806 mmr_t xn_rp_crd_oflow : 1;
3807 mmr_t reserved_0 : 43;
3808 } sh_pi_crbp_first_error_s;
3809 } sh_pi_crbp_first_error_u_t;
3811 /* ==================================================================== */
3812 /* Register "SH_PI_ERROR_DETAIL_1" */
3813 /* PI Error Detail 1 */
3814 /* ==================================================================== */
3816 typedef union sh_pi_error_detail_1_u {
3817 mmr_t sh_pi_error_detail_1_regval;
3820 } sh_pi_error_detail_1_s;
3821 } sh_pi_error_detail_1_u_t;
3823 /* ==================================================================== */
3824 /* Register "SH_PI_ERROR_DETAIL_2" */
3825 /* PI Error Detail 2 */
3826 /* ==================================================================== */
3828 typedef union sh_pi_error_detail_2_u {
3829 mmr_t sh_pi_error_detail_2_regval;
3832 } sh_pi_error_detail_2_s;
3833 } sh_pi_error_detail_2_u_t;
3835 /* ==================================================================== */
3836 /* Register "SH_PI_ERROR_OVERFLOW" */
3837 /* PI Error Overflow */
3838 /* ==================================================================== */
3840 typedef union sh_pi_error_overflow_u {
3841 mmr_t sh_pi_error_overflow_regval;
3843 mmr_t fsb_proto_err : 1;
3844 mmr_t gfx_rp_err : 1;
3845 mmr_t xb_proto_err : 1;
3846 mmr_t mem_rp_err : 1;
3847 mmr_t pio_rp_err : 1;
3848 mmr_t mem_to_err : 1;
3849 mmr_t pio_to_err : 1;
3850 mmr_t fsb_shub_uce : 1;
3851 mmr_t fsb_shub_ce : 1;
3852 mmr_t msg_color_err : 1;
3853 mmr_t md_rq_q_oflow : 1;
3854 mmr_t md_rp_q_oflow : 1;
3855 mmr_t xn_rq_q_oflow : 1;
3856 mmr_t xn_rp_q_oflow : 1;
3857 mmr_t nack_oflow : 1;
3858 mmr_t gfx_int_0 : 1;
3859 mmr_t gfx_int_1 : 1;
3860 mmr_t md_rq_crd_oflow : 1;
3861 mmr_t md_rp_crd_oflow : 1;
3862 mmr_t xn_rq_crd_oflow : 1;
3863 mmr_t xn_rp_crd_oflow : 1;
3865 mmr_t rsp_parity : 1;
3866 mmr_t ioq_overrun : 1;
3867 mmr_t req_format : 1;
3868 mmr_t addr_access : 1;
3869 mmr_t req_parity : 1;
3870 mmr_t addr_parity : 1;
3871 mmr_t shub_fsb_dqe : 1;
3872 mmr_t shub_fsb_uce : 1;
3873 mmr_t shub_fsb_ce : 1;
3875 mmr_t bad_snoop : 1;
3876 mmr_t fsb_tbl_miss : 1;
3877 mmr_t msg_length : 1;
3878 mmr_t reserved_0 : 29;
3879 } sh_pi_error_overflow_s;
3880 } sh_pi_error_overflow_u_t;
3882 /* ==================================================================== */
3883 /* Register "SH_PI_ERROR_SUMMARY" */
3884 /* PI Error Summary */
3885 /* ==================================================================== */
3887 typedef union sh_pi_error_summary_u {
3888 mmr_t sh_pi_error_summary_regval;
3890 mmr_t fsb_proto_err : 1;
3891 mmr_t gfx_rp_err : 1;
3892 mmr_t xb_proto_err : 1;
3893 mmr_t mem_rp_err : 1;
3894 mmr_t pio_rp_err : 1;
3895 mmr_t mem_to_err : 1;
3896 mmr_t pio_to_err : 1;
3897 mmr_t fsb_shub_uce : 1;
3898 mmr_t fsb_shub_ce : 1;
3899 mmr_t msg_color_err : 1;
3900 mmr_t md_rq_q_oflow : 1;
3901 mmr_t md_rp_q_oflow : 1;
3902 mmr_t xn_rq_q_oflow : 1;
3903 mmr_t xn_rp_q_oflow : 1;
3904 mmr_t nack_oflow : 1;
3905 mmr_t gfx_int_0 : 1;
3906 mmr_t gfx_int_1 : 1;
3907 mmr_t md_rq_crd_oflow : 1;
3908 mmr_t md_rp_crd_oflow : 1;
3909 mmr_t xn_rq_crd_oflow : 1;
3910 mmr_t xn_rp_crd_oflow : 1;
3912 mmr_t rsp_parity : 1;
3913 mmr_t ioq_overrun : 1;
3914 mmr_t req_format : 1;
3915 mmr_t addr_access : 1;
3916 mmr_t req_parity : 1;
3917 mmr_t addr_parity : 1;
3918 mmr_t shub_fsb_dqe : 1;
3919 mmr_t shub_fsb_uce : 1;
3920 mmr_t shub_fsb_ce : 1;
3922 mmr_t bad_snoop : 1;
3923 mmr_t fsb_tbl_miss : 1;
3924 mmr_t msg_length : 1;
3925 mmr_t reserved_0 : 29;
3926 } sh_pi_error_summary_s;
3927 } sh_pi_error_summary_u_t;
3929 /* ==================================================================== */
3930 /* Register "SH_PI_EXPRESS_REPLY_STATUS" */
3931 /* PI Express Reply Status */
3932 /* ==================================================================== */
3934 typedef union sh_pi_express_reply_status_u {
3935 mmr_t sh_pi_express_reply_status_regval;
3938 mmr_t reserved_0 : 61;
3939 } sh_pi_express_reply_status_s;
3940 } sh_pi_express_reply_status_u_t;
3942 /* ==================================================================== */
3943 /* Register "SH_PI_FIRST_ERROR" */
3944 /* PI First Error */
3945 /* ==================================================================== */
3947 typedef union sh_pi_first_error_u {
3948 mmr_t sh_pi_first_error_regval;
3950 mmr_t fsb_proto_err : 1;
3951 mmr_t gfx_rp_err : 1;
3952 mmr_t xb_proto_err : 1;
3953 mmr_t mem_rp_err : 1;
3954 mmr_t pio_rp_err : 1;
3955 mmr_t mem_to_err : 1;
3956 mmr_t pio_to_err : 1;
3957 mmr_t fsb_shub_uce : 1;
3958 mmr_t fsb_shub_ce : 1;
3959 mmr_t msg_color_err : 1;
3960 mmr_t md_rq_q_oflow : 1;
3961 mmr_t md_rp_q_oflow : 1;
3962 mmr_t xn_rq_q_oflow : 1;
3963 mmr_t xn_rp_q_oflow : 1;
3964 mmr_t nack_oflow : 1;
3965 mmr_t gfx_int_0 : 1;
3966 mmr_t gfx_int_1 : 1;
3967 mmr_t md_rq_crd_oflow : 1;
3968 mmr_t md_rp_crd_oflow : 1;
3969 mmr_t xn_rq_crd_oflow : 1;
3970 mmr_t xn_rp_crd_oflow : 1;
3972 mmr_t rsp_parity : 1;
3973 mmr_t ioq_overrun : 1;
3974 mmr_t req_format : 1;
3975 mmr_t addr_access : 1;
3976 mmr_t req_parity : 1;
3977 mmr_t addr_parity : 1;
3978 mmr_t shub_fsb_dqe : 1;
3979 mmr_t shub_fsb_uce : 1;
3980 mmr_t shub_fsb_ce : 1;
3982 mmr_t bad_snoop : 1;
3983 mmr_t fsb_tbl_miss : 1;
3984 mmr_t msg_length : 1;
3985 mmr_t reserved_0 : 29;
3986 } sh_pi_first_error_s;
3987 } sh_pi_first_error_u_t;
3989 /* ==================================================================== */
3990 /* Register "SH_PI_PI2MD_REPLY_VC_STATUS" */
3991 /* PI-to-MD Reply Virtual Channel Status */
3992 /* ==================================================================== */
3994 typedef union sh_pi_pi2md_reply_vc_status_u {
3995 mmr_t sh_pi_pi2md_reply_vc_status_regval;
3997 mmr_t output_crd_stat : 6;
3998 mmr_t reserved_0 : 58;
3999 } sh_pi_pi2md_reply_vc_status_s;
4000 } sh_pi_pi2md_reply_vc_status_u_t;
4002 /* ==================================================================== */
4003 /* Register "SH_PI_PI2MD_REQUEST_VC_STATUS" */
4004 /* PI-to-MD Request Virtual Channel Status */
4005 /* ==================================================================== */
4007 typedef union sh_pi_pi2md_request_vc_status_u {
4008 mmr_t sh_pi_pi2md_request_vc_status_regval;
4010 mmr_t output_crd_stat : 6;
4011 mmr_t reserved_0 : 58;
4012 } sh_pi_pi2md_request_vc_status_s;
4013 } sh_pi_pi2md_request_vc_status_u_t;
4015 /* ==================================================================== */
4016 /* Register "SH_PI_PI2XN_REPLY_VC_STATUS" */
4017 /* PI-to-XN Reply Virtual Channel Status */
4018 /* ==================================================================== */
4020 typedef union sh_pi_pi2xn_reply_vc_status_u {
4021 mmr_t sh_pi_pi2xn_reply_vc_status_regval;
4023 mmr_t output_crd_stat : 6;
4024 mmr_t reserved_0 : 58;
4025 } sh_pi_pi2xn_reply_vc_status_s;
4026 } sh_pi_pi2xn_reply_vc_status_u_t;
4028 /* ==================================================================== */
4029 /* Register "SH_PI_PI2XN_REQUEST_VC_STATUS" */
4030 /* PI-to-XN Request Virtual Channel Status */
4031 /* ==================================================================== */
4033 typedef union sh_pi_pi2xn_request_vc_status_u {
4034 mmr_t sh_pi_pi2xn_request_vc_status_regval;
4036 mmr_t output_crd_stat : 6;
4037 mmr_t reserved_0 : 58;
4038 } sh_pi_pi2xn_request_vc_status_s;
4039 } sh_pi_pi2xn_request_vc_status_u_t;
4041 /* ==================================================================== */
4042 /* Register "SH_PI_UNCORRECTED_DETAIL_1" */
4043 /* PI Uncorrected Error Detail 1 */
4044 /* ==================================================================== */
4046 typedef union sh_pi_uncorrected_detail_1_u {
4047 mmr_t sh_pi_uncorrected_detail_1_regval;
4052 } sh_pi_uncorrected_detail_1_s;
4053 } sh_pi_uncorrected_detail_1_u_t;
4055 /* ==================================================================== */
4056 /* Register "SH_PI_UNCORRECTED_DETAIL_2" */
4057 /* PI Uncorrected Error Detail 2 */
4058 /* ==================================================================== */
4060 typedef union sh_pi_uncorrected_detail_2_u {
4061 mmr_t sh_pi_uncorrected_detail_2_regval;
4064 } sh_pi_uncorrected_detail_2_s;
4065 } sh_pi_uncorrected_detail_2_u_t;
4067 /* ==================================================================== */
4068 /* Register "SH_PI_UNCORRECTED_DETAIL_3" */
4069 /* PI Uncorrected Error Detail 3 */
4070 /* ==================================================================== */
4072 typedef union sh_pi_uncorrected_detail_3_u {
4073 mmr_t sh_pi_uncorrected_detail_3_regval;
4078 } sh_pi_uncorrected_detail_3_s;
4079 } sh_pi_uncorrected_detail_3_u_t;
4081 /* ==================================================================== */
4082 /* Register "SH_PI_UNCORRECTED_DETAIL_4" */
4083 /* PI Uncorrected Error Detail 4 */
4084 /* ==================================================================== */
4086 typedef union sh_pi_uncorrected_detail_4_u {
4087 mmr_t sh_pi_uncorrected_detail_4_regval;
4090 } sh_pi_uncorrected_detail_4_s;
4091 } sh_pi_uncorrected_detail_4_u_t;
4093 /* ==================================================================== */
4094 /* Register "SH_PI_MD2PI_REPLY_VC_STATUS" */
4095 /* MD-to-PI Reply Virtual Channel Status */
4096 /* ==================================================================== */
4098 typedef union sh_pi_md2pi_reply_vc_status_u {
4099 mmr_t sh_pi_md2pi_reply_vc_status_regval;
4101 mmr_t input_hdr_crd_stat : 4;
4102 mmr_t input_dat_crd_stat : 4;
4103 mmr_t input_queue_stat : 4;
4104 mmr_t reserved_0 : 52;
4105 } sh_pi_md2pi_reply_vc_status_s;
4106 } sh_pi_md2pi_reply_vc_status_u_t;
4108 /* ==================================================================== */
4109 /* Register "SH_PI_MD2PI_REQUEST_VC_STATUS" */
4110 /* MD-to-PI Request Virtual Channel Status */
4111 /* ==================================================================== */
4113 typedef union sh_pi_md2pi_request_vc_status_u {
4114 mmr_t sh_pi_md2pi_request_vc_status_regval;
4116 mmr_t input_hdr_crd_stat : 4;
4117 mmr_t input_dat_crd_stat : 4;
4118 mmr_t input_queue_stat : 4;
4119 mmr_t reserved_0 : 52;
4120 } sh_pi_md2pi_request_vc_status_s;
4121 } sh_pi_md2pi_request_vc_status_u_t;
4123 /* ==================================================================== */
4124 /* Register "SH_PI_XN2PI_REPLY_VC_STATUS" */
4125 /* XN-to-PI Reply Virtual Channel Status */
4126 /* ==================================================================== */
4128 typedef union sh_pi_xn2pi_reply_vc_status_u {
4129 mmr_t sh_pi_xn2pi_reply_vc_status_regval;
4131 mmr_t input_hdr_crd_stat : 4;
4132 mmr_t input_dat_crd_stat : 4;
4133 mmr_t input_queue_stat : 4;
4134 mmr_t reserved_0 : 52;
4135 } sh_pi_xn2pi_reply_vc_status_s;
4136 } sh_pi_xn2pi_reply_vc_status_u_t;
4138 /* ==================================================================== */
4139 /* Register "SH_PI_XN2PI_REQUEST_VC_STATUS" */
4140 /* XN-to-PI Request Virtual Channel Status */
4141 /* ==================================================================== */
4143 typedef union sh_pi_xn2pi_request_vc_status_u {
4144 mmr_t sh_pi_xn2pi_request_vc_status_regval;
4146 mmr_t input_hdr_crd_stat : 4;
4147 mmr_t input_dat_crd_stat : 4;
4148 mmr_t input_queue_stat : 4;
4149 mmr_t reserved_0 : 52;
4150 } sh_pi_xn2pi_request_vc_status_s;
4151 } sh_pi_xn2pi_request_vc_status_u_t;
4153 /* ==================================================================== */
4154 /* Register "SH_XNPI_SIC_FLOW" */
4155 /* ==================================================================== */
4157 typedef union sh_xnpi_sic_flow_u {
4158 mmr_t sh_xnpi_sic_flow_regval;
4160 mmr_t debit_vc0_withhold : 5;
4161 mmr_t reserved_0 : 2;
4162 mmr_t debit_vc0_force_cred : 1;
4163 mmr_t debit_vc2_withhold : 5;
4164 mmr_t reserved_1 : 2;
4165 mmr_t debit_vc2_force_cred : 1;
4166 mmr_t credit_vc0_test : 5;
4167 mmr_t reserved_2 : 3;
4168 mmr_t credit_vc0_dyn : 5;
4169 mmr_t reserved_3 : 3;
4170 mmr_t credit_vc0_cap : 5;
4171 mmr_t reserved_4 : 3;
4172 mmr_t credit_vc2_test : 5;
4173 mmr_t reserved_5 : 3;
4174 mmr_t credit_vc2_dyn : 5;
4175 mmr_t reserved_6 : 3;
4176 mmr_t credit_vc2_cap : 5;
4177 mmr_t reserved_7 : 2;
4178 mmr_t disable_bypass_out : 1;
4179 } sh_xnpi_sic_flow_s;
4180 } sh_xnpi_sic_flow_u_t;
4182 /* ==================================================================== */
4183 /* Register "SH_XNPI_TO_NI0_PORT_FLOW" */
4184 /* ==================================================================== */
4186 typedef union sh_xnpi_to_ni0_port_flow_u {
4187 mmr_t sh_xnpi_to_ni0_port_flow_regval;
4189 mmr_t debit_vc0_withhold : 6;
4190 mmr_t reserved_0 : 1;
4191 mmr_t debit_vc0_force_cred : 1;
4192 mmr_t debit_vc2_withhold : 6;
4193 mmr_t reserved_1 : 1;
4194 mmr_t debit_vc2_force_cred : 1;
4195 mmr_t reserved_2 : 8;
4196 mmr_t credit_vc0_dyn : 6;
4197 mmr_t reserved_3 : 2;
4198 mmr_t credit_vc0_cap : 6;
4199 mmr_t reserved_4 : 10;
4200 mmr_t credit_vc2_dyn : 6;
4201 mmr_t reserved_5 : 2;
4202 mmr_t credit_vc2_cap : 6;
4203 mmr_t reserved_6 : 2;
4204 } sh_xnpi_to_ni0_port_flow_s;
4205 } sh_xnpi_to_ni0_port_flow_u_t;
4207 /* ==================================================================== */
4208 /* Register "SH_XNPI_TO_NI1_PORT_FLOW" */
4209 /* ==================================================================== */
4211 typedef union sh_xnpi_to_ni1_port_flow_u {
4212 mmr_t sh_xnpi_to_ni1_port_flow_regval;
4214 mmr_t debit_vc0_withhold : 6;
4215 mmr_t reserved_0 : 1;
4216 mmr_t debit_vc0_force_cred : 1;
4217 mmr_t debit_vc2_withhold : 6;
4218 mmr_t reserved_1 : 1;
4219 mmr_t debit_vc2_force_cred : 1;
4220 mmr_t reserved_2 : 8;
4221 mmr_t credit_vc0_dyn : 6;
4222 mmr_t reserved_3 : 2;
4223 mmr_t credit_vc0_cap : 6;
4224 mmr_t reserved_4 : 10;
4225 mmr_t credit_vc2_dyn : 6;
4226 mmr_t reserved_5 : 2;
4227 mmr_t credit_vc2_cap : 6;
4228 mmr_t reserved_6 : 2;
4229 } sh_xnpi_to_ni1_port_flow_s;
4230 } sh_xnpi_to_ni1_port_flow_u_t;
4232 /* ==================================================================== */
4233 /* Register "SH_XNPI_TO_IILB_PORT_FLOW" */
4234 /* ==================================================================== */
4236 typedef union sh_xnpi_to_iilb_port_flow_u {
4237 mmr_t sh_xnpi_to_iilb_port_flow_regval;
4239 mmr_t debit_vc0_withhold : 6;
4240 mmr_t reserved_0 : 1;
4241 mmr_t debit_vc0_force_cred : 1;
4242 mmr_t debit_vc2_withhold : 6;
4243 mmr_t reserved_1 : 1;
4244 mmr_t debit_vc2_force_cred : 1;
4245 mmr_t reserved_2 : 8;
4246 mmr_t credit_vc0_dyn : 6;
4247 mmr_t reserved_3 : 2;
4248 mmr_t credit_vc0_cap : 6;
4249 mmr_t reserved_4 : 10;
4250 mmr_t credit_vc2_dyn : 6;
4251 mmr_t reserved_5 : 2;
4252 mmr_t credit_vc2_cap : 6;
4253 mmr_t reserved_6 : 2;
4254 } sh_xnpi_to_iilb_port_flow_s;
4255 } sh_xnpi_to_iilb_port_flow_u_t;
4257 /* ==================================================================== */
4258 /* Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO" */
4259 /* ==================================================================== */
4261 typedef union sh_xnpi_fr_ni0_port_flow_fifo_u {
4262 mmr_t sh_xnpi_fr_ni0_port_flow_fifo_regval;
4264 mmr_t entry_vc0_dyn : 6;
4265 mmr_t reserved_0 : 2;
4266 mmr_t entry_vc0_cap : 6;
4267 mmr_t reserved_1 : 2;
4268 mmr_t entry_vc2_dyn : 6;
4269 mmr_t reserved_2 : 2;
4270 mmr_t entry_vc2_cap : 6;
4271 mmr_t reserved_3 : 2;
4272 mmr_t entry_vc0_test : 5;
4273 mmr_t reserved_4 : 3;
4274 mmr_t entry_vc2_test : 5;
4275 mmr_t reserved_5 : 19;
4276 } sh_xnpi_fr_ni0_port_flow_fifo_s;
4277 } sh_xnpi_fr_ni0_port_flow_fifo_u_t;
4279 /* ==================================================================== */
4280 /* Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO" */
4281 /* ==================================================================== */
4283 typedef union sh_xnpi_fr_ni1_port_flow_fifo_u {
4284 mmr_t sh_xnpi_fr_ni1_port_flow_fifo_regval;
4286 mmr_t entry_vc0_dyn : 6;
4287 mmr_t reserved_0 : 2;
4288 mmr_t entry_vc0_cap : 6;
4289 mmr_t reserved_1 : 2;
4290 mmr_t entry_vc2_dyn : 6;
4291 mmr_t reserved_2 : 2;
4292 mmr_t entry_vc2_cap : 6;
4293 mmr_t reserved_3 : 2;
4294 mmr_t entry_vc0_test : 5;
4295 mmr_t reserved_4 : 3;
4296 mmr_t entry_vc2_test : 5;
4297 mmr_t reserved_5 : 19;
4298 } sh_xnpi_fr_ni1_port_flow_fifo_s;
4299 } sh_xnpi_fr_ni1_port_flow_fifo_u_t;
4301 /* ==================================================================== */
4302 /* Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO" */
4303 /* ==================================================================== */
4305 typedef union sh_xnpi_fr_iilb_port_flow_fifo_u {
4306 mmr_t sh_xnpi_fr_iilb_port_flow_fifo_regval;
4308 mmr_t entry_vc0_dyn : 6;
4309 mmr_t reserved_0 : 2;
4310 mmr_t entry_vc0_cap : 6;
4311 mmr_t reserved_1 : 2;
4312 mmr_t entry_vc2_dyn : 6;
4313 mmr_t reserved_2 : 2;
4314 mmr_t entry_vc2_cap : 6;
4315 mmr_t reserved_3 : 2;
4316 mmr_t entry_vc0_test : 5;
4317 mmr_t reserved_4 : 3;
4318 mmr_t entry_vc2_test : 5;
4319 mmr_t reserved_5 : 19;
4320 } sh_xnpi_fr_iilb_port_flow_fifo_s;
4321 } sh_xnpi_fr_iilb_port_flow_fifo_u_t;
4323 /* ==================================================================== */
4324 /* Register "SH_XNMD_SIC_FLOW" */
4325 /* ==================================================================== */
4327 typedef union sh_xnmd_sic_flow_u {
4328 mmr_t sh_xnmd_sic_flow_regval;
4330 mmr_t debit_vc0_withhold : 5;
4331 mmr_t reserved_0 : 2;
4332 mmr_t debit_vc0_force_cred : 1;
4333 mmr_t debit_vc2_withhold : 5;
4334 mmr_t reserved_1 : 2;
4335 mmr_t debit_vc2_force_cred : 1;
4336 mmr_t credit_vc0_test : 5;
4337 mmr_t reserved_2 : 3;
4338 mmr_t credit_vc0_dyn : 5;
4339 mmr_t reserved_3 : 3;
4340 mmr_t credit_vc0_cap : 5;
4341 mmr_t reserved_4 : 3;
4342 mmr_t credit_vc2_test : 5;
4343 mmr_t reserved_5 : 3;
4344 mmr_t credit_vc2_dyn : 5;
4345 mmr_t reserved_6 : 3;
4346 mmr_t credit_vc2_cap : 5;
4347 mmr_t reserved_7 : 2;
4348 mmr_t disable_bypass_out : 1;
4349 } sh_xnmd_sic_flow_s;
4350 } sh_xnmd_sic_flow_u_t;
4352 /* ==================================================================== */
4353 /* Register "SH_XNMD_TO_NI0_PORT_FLOW" */
4354 /* ==================================================================== */
4356 typedef union sh_xnmd_to_ni0_port_flow_u {
4357 mmr_t sh_xnmd_to_ni0_port_flow_regval;
4359 mmr_t debit_vc0_withhold : 6;
4360 mmr_t reserved_0 : 1;
4361 mmr_t debit_vc0_force_cred : 1;
4362 mmr_t debit_vc2_withhold : 6;
4363 mmr_t reserved_1 : 1;
4364 mmr_t debit_vc2_force_cred : 1;
4365 mmr_t reserved_2 : 8;
4366 mmr_t credit_vc0_dyn : 6;
4367 mmr_t reserved_3 : 2;
4368 mmr_t credit_vc0_cap : 6;
4369 mmr_t reserved_4 : 10;
4370 mmr_t credit_vc2_dyn : 6;
4371 mmr_t reserved_5 : 2;
4372 mmr_t credit_vc2_cap : 6;
4373 mmr_t reserved_6 : 2;
4374 } sh_xnmd_to_ni0_port_flow_s;
4375 } sh_xnmd_to_ni0_port_flow_u_t;
4377 /* ==================================================================== */
4378 /* Register "SH_XNMD_TO_NI1_PORT_FLOW" */
4379 /* ==================================================================== */
4381 typedef union sh_xnmd_to_ni1_port_flow_u {
4382 mmr_t sh_xnmd_to_ni1_port_flow_regval;
4384 mmr_t debit_vc0_withhold : 6;
4385 mmr_t reserved_0 : 1;
4386 mmr_t debit_vc0_force_cred : 1;
4387 mmr_t debit_vc2_withhold : 6;
4388 mmr_t reserved_1 : 1;
4389 mmr_t debit_vc2_force_cred : 1;
4390 mmr_t reserved_2 : 8;
4391 mmr_t credit_vc0_dyn : 6;
4392 mmr_t reserved_3 : 2;
4393 mmr_t credit_vc0_cap : 6;
4394 mmr_t reserved_4 : 10;
4395 mmr_t credit_vc2_dyn : 6;
4396 mmr_t reserved_5 : 2;
4397 mmr_t credit_vc2_cap : 6;
4398 mmr_t reserved_6 : 2;
4399 } sh_xnmd_to_ni1_port_flow_s;
4400 } sh_xnmd_to_ni1_port_flow_u_t;
4402 /* ==================================================================== */
4403 /* Register "SH_XNMD_TO_IILB_PORT_FLOW" */
4404 /* ==================================================================== */
4406 typedef union sh_xnmd_to_iilb_port_flow_u {
4407 mmr_t sh_xnmd_to_iilb_port_flow_regval;
4409 mmr_t debit_vc0_withhold : 6;
4410 mmr_t reserved_0 : 1;
4411 mmr_t debit_vc0_force_cred : 1;
4412 mmr_t debit_vc2_withhold : 6;
4413 mmr_t reserved_1 : 1;
4414 mmr_t debit_vc2_force_cred : 1;
4415 mmr_t reserved_2 : 8;
4416 mmr_t credit_vc0_dyn : 6;
4417 mmr_t reserved_3 : 2;
4418 mmr_t credit_vc0_cap : 6;
4419 mmr_t reserved_4 : 10;
4420 mmr_t credit_vc2_dyn : 6;
4421 mmr_t reserved_5 : 2;
4422 mmr_t credit_vc2_cap : 6;
4423 mmr_t reserved_6 : 2;
4424 } sh_xnmd_to_iilb_port_flow_s;
4425 } sh_xnmd_to_iilb_port_flow_u_t;
4427 /* ==================================================================== */
4428 /* Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO" */
4429 /* ==================================================================== */
4431 typedef union sh_xnmd_fr_ni0_port_flow_fifo_u {
4432 mmr_t sh_xnmd_fr_ni0_port_flow_fifo_regval;
4434 mmr_t entry_vc0_dyn : 6;
4435 mmr_t reserved_0 : 2;
4436 mmr_t entry_vc0_cap : 6;
4437 mmr_t reserved_1 : 2;
4438 mmr_t entry_vc2_dyn : 6;
4439 mmr_t reserved_2 : 2;
4440 mmr_t entry_vc2_cap : 6;
4441 mmr_t reserved_3 : 2;
4442 mmr_t entry_vc0_test : 5;
4443 mmr_t reserved_4 : 3;
4444 mmr_t entry_vc2_test : 5;
4445 mmr_t reserved_5 : 19;
4446 } sh_xnmd_fr_ni0_port_flow_fifo_s;
4447 } sh_xnmd_fr_ni0_port_flow_fifo_u_t;
4449 /* ==================================================================== */
4450 /* Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO" */
4451 /* ==================================================================== */
4453 typedef union sh_xnmd_fr_ni1_port_flow_fifo_u {
4454 mmr_t sh_xnmd_fr_ni1_port_flow_fifo_regval;
4456 mmr_t entry_vc0_dyn : 6;
4457 mmr_t reserved_0 : 2;
4458 mmr_t entry_vc0_cap : 6;
4459 mmr_t reserved_1 : 2;
4460 mmr_t entry_vc2_dyn : 6;
4461 mmr_t reserved_2 : 2;
4462 mmr_t entry_vc2_cap : 6;
4463 mmr_t reserved_3 : 2;
4464 mmr_t entry_vc0_test : 5;
4465 mmr_t reserved_4 : 3;
4466 mmr_t entry_vc2_test : 5;
4467 mmr_t reserved_5 : 19;
4468 } sh_xnmd_fr_ni1_port_flow_fifo_s;
4469 } sh_xnmd_fr_ni1_port_flow_fifo_u_t;
4471 /* ==================================================================== */
4472 /* Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO" */
4473 /* ==================================================================== */
4475 typedef union sh_xnmd_fr_iilb_port_flow_fifo_u {
4476 mmr_t sh_xnmd_fr_iilb_port_flow_fifo_regval;
4478 mmr_t entry_vc0_dyn : 6;
4479 mmr_t reserved_0 : 2;
4480 mmr_t entry_vc0_cap : 6;
4481 mmr_t reserved_1 : 2;
4482 mmr_t entry_vc2_dyn : 6;
4483 mmr_t reserved_2 : 2;
4484 mmr_t entry_vc2_cap : 6;
4485 mmr_t reserved_3 : 2;
4486 mmr_t entry_vc0_test : 5;
4487 mmr_t reserved_4 : 3;
4488 mmr_t entry_vc2_test : 5;
4489 mmr_t reserved_5 : 19;
4490 } sh_xnmd_fr_iilb_port_flow_fifo_s;
4491 } sh_xnmd_fr_iilb_port_flow_fifo_u_t;
4493 /* ==================================================================== */
4494 /* Register "SH_XNII_INTRA_FLOW" */
4495 /* ==================================================================== */
4497 typedef union sh_xnii_intra_flow_u {
4498 mmr_t sh_xnii_intra_flow_regval;
4500 mmr_t debit_vc0_withhold : 6;
4501 mmr_t reserved_0 : 1;
4502 mmr_t debit_vc0_force_cred : 1;
4503 mmr_t debit_vc2_withhold : 6;
4504 mmr_t reserved_1 : 1;
4505 mmr_t debit_vc2_force_cred : 1;
4506 mmr_t credit_vc0_test : 7;
4507 mmr_t reserved_2 : 1;
4508 mmr_t credit_vc0_dyn : 7;
4509 mmr_t reserved_3 : 1;
4510 mmr_t credit_vc0_cap : 7;
4511 mmr_t reserved_4 : 1;
4512 mmr_t credit_vc2_test : 7;
4513 mmr_t reserved_5 : 1;
4514 mmr_t credit_vc2_dyn : 7;
4515 mmr_t reserved_6 : 1;
4516 mmr_t credit_vc2_cap : 7;
4517 mmr_t reserved_7 : 1;
4518 } sh_xnii_intra_flow_s;
4519 } sh_xnii_intra_flow_u_t;
4521 /* ==================================================================== */
4522 /* Register "SH_XNLB_INTRA_FLOW" */
4523 /* ==================================================================== */
4525 typedef union sh_xnlb_intra_flow_u {
4526 mmr_t sh_xnlb_intra_flow_regval;
4528 mmr_t debit_vc0_withhold : 6;
4529 mmr_t reserved_0 : 1;
4530 mmr_t debit_vc0_force_cred : 1;
4531 mmr_t debit_vc2_withhold : 6;
4532 mmr_t reserved_1 : 1;
4533 mmr_t debit_vc2_force_cred : 1;
4534 mmr_t credit_vc0_test : 7;
4535 mmr_t reserved_2 : 1;
4536 mmr_t credit_vc0_dyn : 7;
4537 mmr_t reserved_3 : 1;
4538 mmr_t credit_vc0_cap : 7;
4539 mmr_t reserved_4 : 1;
4540 mmr_t credit_vc2_test : 7;
4541 mmr_t reserved_5 : 1;
4542 mmr_t credit_vc2_dyn : 7;
4543 mmr_t reserved_6 : 1;
4544 mmr_t credit_vc2_cap : 7;
4545 mmr_t disable_bypass_in : 1;
4546 } sh_xnlb_intra_flow_s;
4547 } sh_xnlb_intra_flow_u_t;
4549 /* ==================================================================== */
4550 /* Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT" */
4551 /* ==================================================================== */
4553 typedef union sh_xniilb_to_ni0_intra_flow_debit_u {
4554 mmr_t sh_xniilb_to_ni0_intra_flow_debit_regval;
4556 mmr_t vc0_withhold : 6;
4557 mmr_t reserved_0 : 1;
4558 mmr_t vc0_force_cred : 1;
4559 mmr_t vc2_withhold : 6;
4560 mmr_t reserved_1 : 1;
4561 mmr_t vc2_force_cred : 1;
4562 mmr_t reserved_2 : 8;
4564 mmr_t reserved_3 : 1;
4566 mmr_t reserved_4 : 9;
4568 mmr_t reserved_5 : 1;
4570 mmr_t reserved_6 : 1;
4571 } sh_xniilb_to_ni0_intra_flow_debit_s;
4572 } sh_xniilb_to_ni0_intra_flow_debit_u_t;
4574 /* ==================================================================== */
4575 /* Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT" */
4576 /* ==================================================================== */
4578 typedef union sh_xniilb_to_ni1_intra_flow_debit_u {
4579 mmr_t sh_xniilb_to_ni1_intra_flow_debit_regval;
4581 mmr_t vc0_withhold : 6;
4582 mmr_t reserved_0 : 1;
4583 mmr_t vc0_force_cred : 1;
4584 mmr_t vc2_withhold : 6;
4585 mmr_t reserved_1 : 1;
4586 mmr_t vc2_force_cred : 1;
4587 mmr_t reserved_2 : 8;
4589 mmr_t reserved_3 : 1;
4591 mmr_t reserved_4 : 9;
4593 mmr_t reserved_5 : 1;
4595 mmr_t reserved_6 : 1;
4596 } sh_xniilb_to_ni1_intra_flow_debit_s;
4597 } sh_xniilb_to_ni1_intra_flow_debit_u_t;
4599 /* ==================================================================== */
4600 /* Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT" */
4601 /* ==================================================================== */
4603 typedef union sh_xniilb_to_md_intra_flow_debit_u {
4604 mmr_t sh_xniilb_to_md_intra_flow_debit_regval;
4606 mmr_t vc0_withhold : 6;
4607 mmr_t reserved_0 : 1;
4608 mmr_t vc0_force_cred : 1;
4609 mmr_t vc2_withhold : 6;
4610 mmr_t reserved_1 : 1;
4611 mmr_t vc2_force_cred : 1;
4612 mmr_t reserved_2 : 8;
4614 mmr_t reserved_3 : 1;
4616 mmr_t reserved_4 : 9;
4618 mmr_t reserved_5 : 1;
4620 mmr_t reserved_6 : 1;
4621 } sh_xniilb_to_md_intra_flow_debit_s;
4622 } sh_xniilb_to_md_intra_flow_debit_u_t;
4624 /* ==================================================================== */
4625 /* Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT" */
4626 /* ==================================================================== */
4628 typedef union sh_xniilb_to_iilb_intra_flow_debit_u {
4629 mmr_t sh_xniilb_to_iilb_intra_flow_debit_regval;
4631 mmr_t vc0_withhold : 6;
4632 mmr_t reserved_0 : 1;
4633 mmr_t vc0_force_cred : 1;
4634 mmr_t vc2_withhold : 6;
4635 mmr_t reserved_1 : 1;
4636 mmr_t vc2_force_cred : 1;
4637 mmr_t reserved_2 : 8;
4639 mmr_t reserved_3 : 1;
4641 mmr_t reserved_4 : 9;
4643 mmr_t reserved_5 : 1;
4645 mmr_t reserved_6 : 1;
4646 } sh_xniilb_to_iilb_intra_flow_debit_s;
4647 } sh_xniilb_to_iilb_intra_flow_debit_u_t;
4649 /* ==================================================================== */
4650 /* Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT" */
4651 /* ==================================================================== */
4653 typedef union sh_xniilb_to_pi_intra_flow_debit_u {
4654 mmr_t sh_xniilb_to_pi_intra_flow_debit_regval;
4656 mmr_t vc0_withhold : 6;
4657 mmr_t reserved_0 : 1;
4658 mmr_t vc0_force_cred : 1;
4659 mmr_t vc2_withhold : 6;
4660 mmr_t reserved_1 : 1;
4661 mmr_t vc2_force_cred : 1;
4662 mmr_t reserved_2 : 8;
4664 mmr_t reserved_3 : 1;
4666 mmr_t reserved_4 : 9;
4668 mmr_t reserved_5 : 1;
4670 mmr_t reserved_6 : 1;
4671 } sh_xniilb_to_pi_intra_flow_debit_s;
4672 } sh_xniilb_to_pi_intra_flow_debit_u_t;
4674 /* ==================================================================== */
4675 /* Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT" */
4676 /* ==================================================================== */
4678 typedef union sh_xniilb_fr_ni0_intra_flow_credit_u {
4679 mmr_t sh_xniilb_fr_ni0_intra_flow_credit_regval;
4682 mmr_t reserved_0 : 1;
4684 mmr_t reserved_1 : 1;
4686 mmr_t reserved_2 : 1;
4688 mmr_t reserved_3 : 1;
4690 mmr_t reserved_4 : 1;
4692 mmr_t reserved_5 : 17;
4693 } sh_xniilb_fr_ni0_intra_flow_credit_s;
4694 } sh_xniilb_fr_ni0_intra_flow_credit_u_t;
4696 /* ==================================================================== */
4697 /* Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT" */
4698 /* ==================================================================== */
4700 typedef union sh_xniilb_fr_ni1_intra_flow_credit_u {
4701 mmr_t sh_xniilb_fr_ni1_intra_flow_credit_regval;
4704 mmr_t reserved_0 : 1;
4706 mmr_t reserved_1 : 1;
4708 mmr_t reserved_2 : 1;
4710 mmr_t reserved_3 : 1;
4712 mmr_t reserved_4 : 1;
4714 mmr_t reserved_5 : 17;
4715 } sh_xniilb_fr_ni1_intra_flow_credit_s;
4716 } sh_xniilb_fr_ni1_intra_flow_credit_u_t;
4718 /* ==================================================================== */
4719 /* Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT" */
4720 /* ==================================================================== */
4722 typedef union sh_xniilb_fr_md_intra_flow_credit_u {
4723 mmr_t sh_xniilb_fr_md_intra_flow_credit_regval;
4726 mmr_t reserved_0 : 1;
4728 mmr_t reserved_1 : 1;
4730 mmr_t reserved_2 : 1;
4732 mmr_t reserved_3 : 1;
4734 mmr_t reserved_4 : 1;
4736 mmr_t reserved_5 : 17;
4737 } sh_xniilb_fr_md_intra_flow_credit_s;
4738 } sh_xniilb_fr_md_intra_flow_credit_u_t;
4740 /* ==================================================================== */
4741 /* Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT" */
4742 /* ==================================================================== */
4744 typedef union sh_xniilb_fr_iilb_intra_flow_credit_u {
4745 mmr_t sh_xniilb_fr_iilb_intra_flow_credit_regval;
4748 mmr_t reserved_0 : 1;
4750 mmr_t reserved_1 : 1;
4752 mmr_t reserved_2 : 1;
4754 mmr_t reserved_3 : 1;
4756 mmr_t reserved_4 : 1;
4758 mmr_t reserved_5 : 17;
4759 } sh_xniilb_fr_iilb_intra_flow_credit_s;
4760 } sh_xniilb_fr_iilb_intra_flow_credit_u_t;
4762 /* ==================================================================== */
4763 /* Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT" */
4764 /* ==================================================================== */
4766 typedef union sh_xniilb_fr_pi_intra_flow_credit_u {
4767 mmr_t sh_xniilb_fr_pi_intra_flow_credit_regval;
4770 mmr_t reserved_0 : 1;
4772 mmr_t reserved_1 : 1;
4774 mmr_t reserved_2 : 1;
4776 mmr_t reserved_3 : 1;
4778 mmr_t reserved_4 : 1;
4780 mmr_t reserved_5 : 17;
4781 } sh_xniilb_fr_pi_intra_flow_credit_s;
4782 } sh_xniilb_fr_pi_intra_flow_credit_u_t;
4784 /* ==================================================================== */
4785 /* Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT" */
4786 /* ==================================================================== */
4788 typedef union sh_xnni0_to_pi_intra_flow_debit_u {
4789 mmr_t sh_xnni0_to_pi_intra_flow_debit_regval;
4791 mmr_t vc0_withhold : 6;
4792 mmr_t reserved_0 : 1;
4793 mmr_t vc0_force_cred : 1;
4794 mmr_t vc2_withhold : 6;
4795 mmr_t reserved_1 : 1;
4796 mmr_t vc2_force_cred : 1;
4797 mmr_t reserved_2 : 8;
4799 mmr_t reserved_3 : 1;
4801 mmr_t reserved_4 : 9;
4803 mmr_t reserved_5 : 1;
4805 mmr_t reserved_6 : 1;
4806 } sh_xnni0_to_pi_intra_flow_debit_s;
4807 } sh_xnni0_to_pi_intra_flow_debit_u_t;
4809 /* ==================================================================== */
4810 /* Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT" */
4811 /* ==================================================================== */
4813 typedef union sh_xnni0_to_md_intra_flow_debit_u {
4814 mmr_t sh_xnni0_to_md_intra_flow_debit_regval;
4816 mmr_t vc0_withhold : 6;
4817 mmr_t reserved_0 : 1;
4818 mmr_t vc0_force_cred : 1;
4819 mmr_t vc2_withhold : 6;
4820 mmr_t reserved_1 : 1;
4821 mmr_t vc2_force_cred : 1;
4822 mmr_t reserved_2 : 8;
4824 mmr_t reserved_3 : 1;
4826 mmr_t reserved_4 : 9;
4828 mmr_t reserved_5 : 1;
4830 mmr_t reserved_6 : 1;
4831 } sh_xnni0_to_md_intra_flow_debit_s;
4832 } sh_xnni0_to_md_intra_flow_debit_u_t;
4834 /* ==================================================================== */
4835 /* Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT" */
4836 /* ==================================================================== */
4838 typedef union sh_xnni0_to_iilb_intra_flow_debit_u {
4839 mmr_t sh_xnni0_to_iilb_intra_flow_debit_regval;
4841 mmr_t vc0_withhold : 6;
4842 mmr_t reserved_0 : 1;
4843 mmr_t vc0_force_cred : 1;
4844 mmr_t vc2_withhold : 6;
4845 mmr_t reserved_1 : 1;
4846 mmr_t vc2_force_cred : 1;
4847 mmr_t reserved_2 : 8;
4849 mmr_t reserved_3 : 1;
4851 mmr_t reserved_4 : 9;
4853 mmr_t reserved_5 : 1;
4855 mmr_t reserved_6 : 1;
4856 } sh_xnni0_to_iilb_intra_flow_debit_s;
4857 } sh_xnni0_to_iilb_intra_flow_debit_u_t;
4859 /* ==================================================================== */
4860 /* Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT" */
4861 /* ==================================================================== */
4863 typedef union sh_xnni0_fr_pi_intra_flow_credit_u {
4864 mmr_t sh_xnni0_fr_pi_intra_flow_credit_regval;
4867 mmr_t reserved_0 : 1;
4869 mmr_t reserved_1 : 1;
4871 mmr_t reserved_2 : 1;
4873 mmr_t reserved_3 : 1;
4875 mmr_t reserved_4 : 1;
4877 mmr_t reserved_5 : 17;
4878 } sh_xnni0_fr_pi_intra_flow_credit_s;
4879 } sh_xnni0_fr_pi_intra_flow_credit_u_t;
4881 /* ==================================================================== */
4882 /* Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT" */
4883 /* ==================================================================== */
4885 typedef union sh_xnni0_fr_md_intra_flow_credit_u {
4886 mmr_t sh_xnni0_fr_md_intra_flow_credit_regval;
4889 mmr_t reserved_0 : 1;
4891 mmr_t reserved_1 : 1;
4893 mmr_t reserved_2 : 1;
4895 mmr_t reserved_3 : 1;
4897 mmr_t reserved_4 : 1;
4899 mmr_t reserved_5 : 17;
4900 } sh_xnni0_fr_md_intra_flow_credit_s;
4901 } sh_xnni0_fr_md_intra_flow_credit_u_t;
4903 /* ==================================================================== */
4904 /* Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT" */
4905 /* ==================================================================== */
4907 typedef union sh_xnni0_fr_iilb_intra_flow_credit_u {
4908 mmr_t sh_xnni0_fr_iilb_intra_flow_credit_regval;
4911 mmr_t reserved_0 : 1;
4913 mmr_t reserved_1 : 1;
4915 mmr_t reserved_2 : 1;
4917 mmr_t reserved_3 : 1;
4919 mmr_t reserved_4 : 1;
4921 mmr_t reserved_5 : 17;
4922 } sh_xnni0_fr_iilb_intra_flow_credit_s;
4923 } sh_xnni0_fr_iilb_intra_flow_credit_u_t;
4925 /* ==================================================================== */
4926 /* Register "SH_XNNI0_0_INTRANI_FLOW" */
4927 /* ==================================================================== */
4929 typedef union sh_xnni0_0_intrani_flow_u {
4930 mmr_t sh_xnni0_0_intrani_flow_regval;
4932 mmr_t debit_vc0_withhold : 6;
4933 mmr_t reserved_0 : 1;
4934 mmr_t debit_vc0_force_cred : 1;
4935 mmr_t reserved_1 : 56;
4936 } sh_xnni0_0_intrani_flow_s;
4937 } sh_xnni0_0_intrani_flow_u_t;
4939 /* ==================================================================== */
4940 /* Register "SH_XNNI0_1_INTRANI_FLOW" */
4941 /* ==================================================================== */
4943 typedef union sh_xnni0_1_intrani_flow_u {
4944 mmr_t sh_xnni0_1_intrani_flow_regval;
4946 mmr_t debit_vc1_withhold : 6;
4947 mmr_t reserved_0 : 1;
4948 mmr_t debit_vc1_force_cred : 1;
4949 mmr_t reserved_1 : 56;
4950 } sh_xnni0_1_intrani_flow_s;
4951 } sh_xnni0_1_intrani_flow_u_t;
4953 /* ==================================================================== */
4954 /* Register "SH_XNNI0_2_INTRANI_FLOW" */
4955 /* ==================================================================== */
4957 typedef union sh_xnni0_2_intrani_flow_u {
4958 mmr_t sh_xnni0_2_intrani_flow_regval;
4960 mmr_t debit_vc2_withhold : 6;
4961 mmr_t reserved_0 : 1;
4962 mmr_t debit_vc2_force_cred : 1;
4963 mmr_t reserved_1 : 56;
4964 } sh_xnni0_2_intrani_flow_s;
4965 } sh_xnni0_2_intrani_flow_u_t;
4967 /* ==================================================================== */
4968 /* Register "SH_XNNI0_3_INTRANI_FLOW" */
4969 /* ==================================================================== */
4971 typedef union sh_xnni0_3_intrani_flow_u {
4972 mmr_t sh_xnni0_3_intrani_flow_regval;
4974 mmr_t debit_vc3_withhold : 6;
4975 mmr_t reserved_0 : 1;
4976 mmr_t debit_vc3_force_cred : 1;
4977 mmr_t reserved_1 : 56;
4978 } sh_xnni0_3_intrani_flow_s;
4979 } sh_xnni0_3_intrani_flow_u_t;
4981 /* ==================================================================== */
4982 /* Register "SH_XNNI0_VCSWITCH_FLOW" */
4983 /* ==================================================================== */
4985 typedef union sh_xnni0_vcswitch_flow_u {
4986 mmr_t sh_xnni0_vcswitch_flow_regval;
4988 mmr_t ni_vcfifo_dateline_switch : 1;
4989 mmr_t reserved_0 : 7;
4990 mmr_t pi_vcfifo_switch : 1;
4991 mmr_t reserved_1 : 7;
4992 mmr_t md_vcfifo_switch : 1;
4993 mmr_t reserved_2 : 7;
4994 mmr_t iilb_vcfifo_switch : 1;
4995 mmr_t reserved_3 : 7;
4996 mmr_t disable_sync_bypass_in : 1;
4997 mmr_t disable_sync_bypass_out : 1;
4998 mmr_t async_fifoes : 1;
4999 mmr_t reserved_4 : 29;
5000 } sh_xnni0_vcswitch_flow_s;
5001 } sh_xnni0_vcswitch_flow_u_t;
5003 /* ==================================================================== */
5004 /* Register "SH_XNNI0_TIMER_REG" */
5005 /* ==================================================================== */
5007 typedef union sh_xnni0_timer_reg_u {
5008 mmr_t sh_xnni0_timer_reg_regval;
5010 mmr_t timeout_reg : 24;
5011 mmr_t reserved_0 : 8;
5012 mmr_t linkcleanup_reg : 1;
5013 mmr_t reserved_1 : 31;
5014 } sh_xnni0_timer_reg_s;
5015 } sh_xnni0_timer_reg_u_t;
5017 /* ==================================================================== */
5018 /* Register "SH_XNNI0_FIFO02_FLOW" */
5019 /* ==================================================================== */
5021 typedef union sh_xnni0_fifo02_flow_u {
5022 mmr_t sh_xnni0_fifo02_flow_regval;
5024 mmr_t count_vc0_limit : 4;
5025 mmr_t reserved_0 : 4;
5026 mmr_t count_vc0_dyn : 4;
5027 mmr_t reserved_1 : 4;
5028 mmr_t count_vc0_cap : 4;
5029 mmr_t reserved_2 : 4;
5030 mmr_t count_vc2_limit : 4;
5031 mmr_t reserved_3 : 4;
5032 mmr_t count_vc2_dyn : 4;
5033 mmr_t reserved_4 : 4;
5034 mmr_t count_vc2_cap : 4;
5035 mmr_t reserved_5 : 20;
5036 } sh_xnni0_fifo02_flow_s;
5037 } sh_xnni0_fifo02_flow_u_t;
5039 /* ==================================================================== */
5040 /* Register "SH_XNNI0_FIFO13_FLOW" */
5041 /* ==================================================================== */
5043 typedef union sh_xnni0_fifo13_flow_u {
5044 mmr_t sh_xnni0_fifo13_flow_regval;
5046 mmr_t count_vc1_limit : 4;
5047 mmr_t reserved_0 : 4;
5048 mmr_t count_vc1_dyn : 4;
5049 mmr_t reserved_1 : 4;
5050 mmr_t count_vc1_cap : 4;
5051 mmr_t reserved_2 : 4;
5052 mmr_t count_vc3_limit : 4;
5053 mmr_t reserved_3 : 4;
5054 mmr_t count_vc3_dyn : 4;
5055 mmr_t reserved_4 : 4;
5056 mmr_t count_vc3_cap : 4;
5057 mmr_t reserved_5 : 20;
5058 } sh_xnni0_fifo13_flow_s;
5059 } sh_xnni0_fifo13_flow_u_t;
5061 /* ==================================================================== */
5062 /* Register "SH_XNNI0_NI_FLOW" */
5063 /* ==================================================================== */
5065 typedef union sh_xnni0_ni_flow_u {
5066 mmr_t sh_xnni0_ni_flow_regval;
5068 mmr_t vc0_limit : 4;
5069 mmr_t reserved_0 : 4;
5072 mmr_t vc1_limit : 4;
5073 mmr_t reserved_1 : 4;
5076 mmr_t vc2_limit : 4;
5077 mmr_t reserved_2 : 4;
5080 mmr_t vc3_limit : 4;
5081 mmr_t reserved_3 : 4;
5084 } sh_xnni0_ni_flow_s;
5085 } sh_xnni0_ni_flow_u_t;
5087 /* ==================================================================== */
5088 /* Register "SH_XNNI0_DEAD_FLOW" */
5089 /* ==================================================================== */
5091 typedef union sh_xnni0_dead_flow_u {
5092 mmr_t sh_xnni0_dead_flow_regval;
5094 mmr_t vc0_limit : 4;
5095 mmr_t reserved_0 : 4;
5098 mmr_t vc1_limit : 4;
5099 mmr_t reserved_1 : 4;
5102 mmr_t vc2_limit : 4;
5103 mmr_t reserved_2 : 4;
5106 mmr_t vc3_limit : 4;
5107 mmr_t reserved_3 : 4;
5110 } sh_xnni0_dead_flow_s;
5111 } sh_xnni0_dead_flow_u_t;
5113 /* ==================================================================== */
5114 /* Register "SH_XNNI0_INJECT_AGE" */
5115 /* ==================================================================== */
5117 typedef union sh_xnni0_inject_age_u {
5118 mmr_t sh_xnni0_inject_age_regval;
5120 mmr_t request_inject : 8;
5121 mmr_t reply_inject : 8;
5122 mmr_t reserved_0 : 48;
5123 } sh_xnni0_inject_age_s;
5124 } sh_xnni0_inject_age_u_t;
5126 /* ==================================================================== */
5127 /* Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT" */
5128 /* ==================================================================== */
5130 typedef union sh_xnni1_to_pi_intra_flow_debit_u {
5131 mmr_t sh_xnni1_to_pi_intra_flow_debit_regval;
5133 mmr_t vc0_withhold : 6;
5134 mmr_t reserved_0 : 1;
5135 mmr_t vc0_force_cred : 1;
5136 mmr_t vc2_withhold : 6;
5137 mmr_t reserved_1 : 1;
5138 mmr_t vc2_force_cred : 1;
5139 mmr_t reserved_2 : 8;
5141 mmr_t reserved_3 : 1;
5143 mmr_t reserved_4 : 9;
5145 mmr_t reserved_5 : 1;
5147 mmr_t reserved_6 : 1;
5148 } sh_xnni1_to_pi_intra_flow_debit_s;
5149 } sh_xnni1_to_pi_intra_flow_debit_u_t;
5151 /* ==================================================================== */
5152 /* Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT" */
5153 /* ==================================================================== */
5155 typedef union sh_xnni1_to_md_intra_flow_debit_u {
5156 mmr_t sh_xnni1_to_md_intra_flow_debit_regval;
5158 mmr_t vc0_withhold : 6;
5159 mmr_t reserved_0 : 1;
5160 mmr_t vc0_force_cred : 1;
5161 mmr_t vc2_withhold : 6;
5162 mmr_t reserved_1 : 1;
5163 mmr_t vc2_force_cred : 1;
5164 mmr_t reserved_2 : 8;
5166 mmr_t reserved_3 : 1;
5168 mmr_t reserved_4 : 9;
5170 mmr_t reserved_5 : 1;
5172 mmr_t reserved_6 : 1;
5173 } sh_xnni1_to_md_intra_flow_debit_s;
5174 } sh_xnni1_to_md_intra_flow_debit_u_t;
5176 /* ==================================================================== */
5177 /* Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT" */
5178 /* ==================================================================== */
5180 typedef union sh_xnni1_to_iilb_intra_flow_debit_u {
5181 mmr_t sh_xnni1_to_iilb_intra_flow_debit_regval;
5183 mmr_t vc0_withhold : 6;
5184 mmr_t reserved_0 : 1;
5185 mmr_t vc0_force_cred : 1;
5186 mmr_t vc2_withhold : 6;
5187 mmr_t reserved_1 : 1;
5188 mmr_t vc2_force_cred : 1;
5189 mmr_t reserved_2 : 8;
5191 mmr_t reserved_3 : 1;
5193 mmr_t reserved_4 : 9;
5195 mmr_t reserved_5 : 1;
5197 mmr_t reserved_6 : 1;
5198 } sh_xnni1_to_iilb_intra_flow_debit_s;
5199 } sh_xnni1_to_iilb_intra_flow_debit_u_t;
5201 /* ==================================================================== */
5202 /* Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT" */
5203 /* ==================================================================== */
5205 typedef union sh_xnni1_fr_pi_intra_flow_credit_u {
5206 mmr_t sh_xnni1_fr_pi_intra_flow_credit_regval;
5209 mmr_t reserved_0 : 1;
5211 mmr_t reserved_1 : 1;
5213 mmr_t reserved_2 : 1;
5215 mmr_t reserved_3 : 1;
5217 mmr_t reserved_4 : 1;
5219 mmr_t reserved_5 : 17;
5220 } sh_xnni1_fr_pi_intra_flow_credit_s;
5221 } sh_xnni1_fr_pi_intra_flow_credit_u_t;
5223 /* ==================================================================== */
5224 /* Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT" */
5225 /* ==================================================================== */
5227 typedef union sh_xnni1_fr_md_intra_flow_credit_u {
5228 mmr_t sh_xnni1_fr_md_intra_flow_credit_regval;
5231 mmr_t reserved_0 : 1;
5233 mmr_t reserved_1 : 1;
5235 mmr_t reserved_2 : 1;
5237 mmr_t reserved_3 : 1;
5239 mmr_t reserved_4 : 1;
5241 mmr_t reserved_5 : 17;
5242 } sh_xnni1_fr_md_intra_flow_credit_s;
5243 } sh_xnni1_fr_md_intra_flow_credit_u_t;
5245 /* ==================================================================== */
5246 /* Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT" */
5247 /* ==================================================================== */
5249 typedef union sh_xnni1_fr_iilb_intra_flow_credit_u {
5250 mmr_t sh_xnni1_fr_iilb_intra_flow_credit_regval;
5253 mmr_t reserved_0 : 1;
5255 mmr_t reserved_1 : 1;
5257 mmr_t reserved_2 : 1;
5259 mmr_t reserved_3 : 1;
5261 mmr_t reserved_4 : 1;
5263 mmr_t reserved_5 : 17;
5264 } sh_xnni1_fr_iilb_intra_flow_credit_s;
5265 } sh_xnni1_fr_iilb_intra_flow_credit_u_t;
5267 /* ==================================================================== */
5268 /* Register "SH_XNNI1_0_INTRANI_FLOW" */
5269 /* ==================================================================== */
5271 typedef union sh_xnni1_0_intrani_flow_u {
5272 mmr_t sh_xnni1_0_intrani_flow_regval;
5274 mmr_t debit_vc0_withhold : 6;
5275 mmr_t reserved_0 : 1;
5276 mmr_t debit_vc0_force_cred : 1;
5277 mmr_t reserved_1 : 56;
5278 } sh_xnni1_0_intrani_flow_s;
5279 } sh_xnni1_0_intrani_flow_u_t;
5281 /* ==================================================================== */
5282 /* Register "SH_XNNI1_1_INTRANI_FLOW" */
5283 /* ==================================================================== */
5285 typedef union sh_xnni1_1_intrani_flow_u {
5286 mmr_t sh_xnni1_1_intrani_flow_regval;
5288 mmr_t debit_vc1_withhold : 6;
5289 mmr_t reserved_0 : 1;
5290 mmr_t debit_vc1_force_cred : 1;
5291 mmr_t reserved_1 : 56;
5292 } sh_xnni1_1_intrani_flow_s;
5293 } sh_xnni1_1_intrani_flow_u_t;
5295 /* ==================================================================== */
5296 /* Register "SH_XNNI1_2_INTRANI_FLOW" */
5297 /* ==================================================================== */
5299 typedef union sh_xnni1_2_intrani_flow_u {
5300 mmr_t sh_xnni1_2_intrani_flow_regval;
5302 mmr_t debit_vc2_withhold : 6;
5303 mmr_t reserved_0 : 1;
5304 mmr_t debit_vc2_force_cred : 1;
5305 mmr_t reserved_1 : 56;
5306 } sh_xnni1_2_intrani_flow_s;
5307 } sh_xnni1_2_intrani_flow_u_t;
5309 /* ==================================================================== */
5310 /* Register "SH_XNNI1_3_INTRANI_FLOW" */
5311 /* ==================================================================== */
5313 typedef union sh_xnni1_3_intrani_flow_u {
5314 mmr_t sh_xnni1_3_intrani_flow_regval;
5316 mmr_t debit_vc3_withhold : 6;
5317 mmr_t reserved_0 : 1;
5318 mmr_t debit_vc3_force_cred : 1;
5319 mmr_t reserved_1 : 56;
5320 } sh_xnni1_3_intrani_flow_s;
5321 } sh_xnni1_3_intrani_flow_u_t;
5323 /* ==================================================================== */
5324 /* Register "SH_XNNI1_VCSWITCH_FLOW" */
5325 /* ==================================================================== */
5327 typedef union sh_xnni1_vcswitch_flow_u {
5328 mmr_t sh_xnni1_vcswitch_flow_regval;
5330 mmr_t ni_vcfifo_dateline_switch : 1;
5331 mmr_t reserved_0 : 7;
5332 mmr_t pi_vcfifo_switch : 1;
5333 mmr_t reserved_1 : 7;
5334 mmr_t md_vcfifo_switch : 1;
5335 mmr_t reserved_2 : 7;
5336 mmr_t iilb_vcfifo_switch : 1;
5337 mmr_t reserved_3 : 7;
5338 mmr_t disable_sync_bypass_in : 1;
5339 mmr_t disable_sync_bypass_out : 1;
5340 mmr_t async_fifoes : 1;
5341 mmr_t reserved_4 : 29;
5342 } sh_xnni1_vcswitch_flow_s;
5343 } sh_xnni1_vcswitch_flow_u_t;
5345 /* ==================================================================== */
5346 /* Register "SH_XNNI1_TIMER_REG" */
5347 /* ==================================================================== */
5349 typedef union sh_xnni1_timer_reg_u {
5350 mmr_t sh_xnni1_timer_reg_regval;
5352 mmr_t timeout_reg : 24;
5353 mmr_t reserved_0 : 8;
5354 mmr_t linkcleanup_reg : 1;
5355 mmr_t reserved_1 : 31;
5356 } sh_xnni1_timer_reg_s;
5357 } sh_xnni1_timer_reg_u_t;
5359 /* ==================================================================== */
5360 /* Register "SH_XNNI1_FIFO02_FLOW" */
5361 /* ==================================================================== */
5363 typedef union sh_xnni1_fifo02_flow_u {
5364 mmr_t sh_xnni1_fifo02_flow_regval;
5366 mmr_t count_vc0_limit : 4;
5367 mmr_t reserved_0 : 4;
5368 mmr_t count_vc0_dyn : 4;
5369 mmr_t reserved_1 : 4;
5370 mmr_t count_vc0_cap : 4;
5371 mmr_t reserved_2 : 4;
5372 mmr_t count_vc2_limit : 4;
5373 mmr_t reserved_3 : 4;
5374 mmr_t count_vc2_dyn : 4;
5375 mmr_t reserved_4 : 4;
5376 mmr_t count_vc2_cap : 4;
5377 mmr_t reserved_5 : 20;
5378 } sh_xnni1_fifo02_flow_s;
5379 } sh_xnni1_fifo02_flow_u_t;
5381 /* ==================================================================== */
5382 /* Register "SH_XNNI1_FIFO13_FLOW" */
5383 /* ==================================================================== */
5385 typedef union sh_xnni1_fifo13_flow_u {
5386 mmr_t sh_xnni1_fifo13_flow_regval;
5388 mmr_t count_vc1_limit : 4;
5389 mmr_t reserved_0 : 4;
5390 mmr_t count_vc1_dyn : 4;
5391 mmr_t reserved_1 : 4;
5392 mmr_t count_vc1_cap : 4;
5393 mmr_t reserved_2 : 4;
5394 mmr_t count_vc3_limit : 4;
5395 mmr_t reserved_3 : 4;
5396 mmr_t count_vc3_dyn : 4;
5397 mmr_t reserved_4 : 4;
5398 mmr_t count_vc3_cap : 4;
5399 mmr_t reserved_5 : 20;
5400 } sh_xnni1_fifo13_flow_s;
5401 } sh_xnni1_fifo13_flow_u_t;
5403 /* ==================================================================== */
5404 /* Register "SH_XNNI1_NI_FLOW" */
5405 /* ==================================================================== */
5407 typedef union sh_xnni1_ni_flow_u {
5408 mmr_t sh_xnni1_ni_flow_regval;
5410 mmr_t vc0_limit : 4;
5411 mmr_t reserved_0 : 4;
5414 mmr_t vc1_limit : 4;
5415 mmr_t reserved_1 : 4;
5418 mmr_t vc2_limit : 4;
5419 mmr_t reserved_2 : 4;
5422 mmr_t vc3_limit : 4;
5423 mmr_t reserved_3 : 4;
5426 } sh_xnni1_ni_flow_s;
5427 } sh_xnni1_ni_flow_u_t;
5429 /* ==================================================================== */
5430 /* Register "SH_XNNI1_DEAD_FLOW" */
5431 /* ==================================================================== */
5433 typedef union sh_xnni1_dead_flow_u {
5434 mmr_t sh_xnni1_dead_flow_regval;
5436 mmr_t vc0_limit : 4;
5437 mmr_t reserved_0 : 4;
5440 mmr_t vc1_limit : 4;
5441 mmr_t reserved_1 : 4;
5444 mmr_t vc2_limit : 4;
5445 mmr_t reserved_2 : 4;
5448 mmr_t vc3_limit : 4;
5449 mmr_t reserved_3 : 4;
5452 } sh_xnni1_dead_flow_s;
5453 } sh_xnni1_dead_flow_u_t;
5455 /* ==================================================================== */
5456 /* Register "SH_XNNI1_INJECT_AGE" */
5457 /* ==================================================================== */
5459 typedef union sh_xnni1_inject_age_u {
5460 mmr_t sh_xnni1_inject_age_regval;
5462 mmr_t request_inject : 8;
5463 mmr_t reply_inject : 8;
5464 mmr_t reserved_0 : 48;
5465 } sh_xnni1_inject_age_s;
5466 } sh_xnni1_inject_age_u_t;
5468 /* ==================================================================== */
5469 /* Register "SH_XN_DEBUG_SEL" */
5470 /* XN Debug Port Select */
5471 /* ==================================================================== */
5473 typedef union sh_xn_debug_sel_u {
5474 mmr_t sh_xn_debug_sel_regval;
5476 mmr_t nibble0_rlm_sel : 3;
5477 mmr_t reserved_0 : 1;
5478 mmr_t nibble0_nibble_sel : 3;
5479 mmr_t reserved_1 : 1;
5480 mmr_t nibble1_rlm_sel : 3;
5481 mmr_t reserved_2 : 1;
5482 mmr_t nibble1_nibble_sel : 3;
5483 mmr_t reserved_3 : 1;
5484 mmr_t nibble2_rlm_sel : 3;
5485 mmr_t reserved_4 : 1;
5486 mmr_t nibble2_nibble_sel : 3;
5487 mmr_t reserved_5 : 1;
5488 mmr_t nibble3_rlm_sel : 3;
5489 mmr_t reserved_6 : 1;
5490 mmr_t nibble3_nibble_sel : 3;
5491 mmr_t reserved_7 : 1;
5492 mmr_t nibble4_rlm_sel : 3;
5493 mmr_t reserved_8 : 1;
5494 mmr_t nibble4_nibble_sel : 3;
5495 mmr_t reserved_9 : 1;
5496 mmr_t nibble5_rlm_sel : 3;
5497 mmr_t reserved_10 : 1;
5498 mmr_t nibble5_nibble_sel : 3;
5499 mmr_t reserved_11 : 1;
5500 mmr_t nibble6_rlm_sel : 3;
5501 mmr_t reserved_12 : 1;
5502 mmr_t nibble6_nibble_sel : 3;
5503 mmr_t reserved_13 : 1;
5504 mmr_t nibble7_rlm_sel : 3;
5505 mmr_t reserved_14 : 1;
5506 mmr_t nibble7_nibble_sel : 3;
5507 mmr_t trigger_enable : 1;
5508 } sh_xn_debug_sel_s;
5509 } sh_xn_debug_sel_u_t;
5511 /* ==================================================================== */
5512 /* Register "SH_XN_DEBUG_TRIG_SEL" */
5513 /* XN Debug trigger Select */
5514 /* ==================================================================== */
5516 typedef union sh_xn_debug_trig_sel_u {
5517 mmr_t sh_xn_debug_trig_sel_regval;
5519 mmr_t trigger0_rlm_sel : 3;
5520 mmr_t reserved_0 : 1;
5521 mmr_t trigger0_nibble_sel : 3;
5522 mmr_t reserved_1 : 1;
5523 mmr_t trigger1_rlm_sel : 3;
5524 mmr_t reserved_2 : 1;
5525 mmr_t trigger1_nibble_sel : 3;
5526 mmr_t reserved_3 : 1;
5527 mmr_t trigger2_rlm_sel : 3;
5528 mmr_t reserved_4 : 1;
5529 mmr_t trigger2_nibble_sel : 3;
5530 mmr_t reserved_5 : 1;
5531 mmr_t trigger3_rlm_sel : 3;
5532 mmr_t reserved_6 : 1;
5533 mmr_t trigger3_nibble_sel : 3;
5534 mmr_t reserved_7 : 1;
5535 mmr_t trigger4_rlm_sel : 3;
5536 mmr_t reserved_8 : 1;
5537 mmr_t trigger4_nibble_sel : 3;
5538 mmr_t reserved_9 : 1;
5539 mmr_t trigger5_rlm_sel : 3;
5540 mmr_t reserved_10 : 1;
5541 mmr_t trigger5_nibble_sel : 3;
5542 mmr_t reserved_11 : 1;
5543 mmr_t trigger6_rlm_sel : 3;
5544 mmr_t reserved_12 : 1;
5545 mmr_t trigger6_nibble_sel : 3;
5546 mmr_t reserved_13 : 1;
5547 mmr_t trigger7_rlm_sel : 3;
5548 mmr_t reserved_14 : 1;
5549 mmr_t trigger7_nibble_sel : 3;
5550 mmr_t reserved_15 : 1;
5551 } sh_xn_debug_trig_sel_s;
5552 } sh_xn_debug_trig_sel_u_t;
5554 /* ==================================================================== */
5555 /* Register "SH_XN_TRIGGER_COMPARE" */
5556 /* XN Debug Compare */
5557 /* ==================================================================== */
5559 typedef union sh_xn_trigger_compare_u {
5560 mmr_t sh_xn_trigger_compare_regval;
5563 mmr_t reserved_0 : 32;
5564 } sh_xn_trigger_compare_s;
5565 } sh_xn_trigger_compare_u_t;
5567 /* ==================================================================== */
5568 /* Register "SH_XN_TRIGGER_DATA" */
5569 /* XN Debug Compare Data */
5570 /* ==================================================================== */
5572 typedef union sh_xn_trigger_data_u {
5573 mmr_t sh_xn_trigger_data_regval;
5575 mmr_t compare_pattern : 32;
5576 mmr_t reserved_0 : 32;
5577 } sh_xn_trigger_data_s;
5578 } sh_xn_trigger_data_u_t;
5580 /* ==================================================================== */
5581 /* Register "SH_XN_IILB_DEBUG_SEL" */
5582 /* XN IILB Debug Port Select */
5583 /* ==================================================================== */
5585 typedef union sh_xn_iilb_debug_sel_u {
5586 mmr_t sh_xn_iilb_debug_sel_regval;
5588 mmr_t nibble0_input_sel : 3;
5589 mmr_t reserved_0 : 1;
5590 mmr_t nibble0_nibble_sel : 3;
5591 mmr_t reserved_1 : 1;
5592 mmr_t nibble1_input_sel : 3;
5593 mmr_t reserved_2 : 1;
5594 mmr_t nibble1_nibble_sel : 3;
5595 mmr_t reserved_3 : 1;
5596 mmr_t nibble2_input_sel : 3;
5597 mmr_t reserved_4 : 1;
5598 mmr_t nibble2_nibble_sel : 3;
5599 mmr_t reserved_5 : 1;
5600 mmr_t nibble3_input_sel : 3;
5601 mmr_t reserved_6 : 1;
5602 mmr_t nibble3_nibble_sel : 3;
5603 mmr_t reserved_7 : 1;
5604 mmr_t nibble4_input_sel : 3;
5605 mmr_t reserved_8 : 1;
5606 mmr_t nibble4_nibble_sel : 3;
5607 mmr_t reserved_9 : 1;
5608 mmr_t nibble5_input_sel : 3;
5609 mmr_t reserved_10 : 1;
5610 mmr_t nibble5_nibble_sel : 3;
5611 mmr_t reserved_11 : 1;
5612 mmr_t nibble6_input_sel : 3;
5613 mmr_t reserved_12 : 1;
5614 mmr_t nibble6_nibble_sel : 3;
5615 mmr_t reserved_13 : 1;
5616 mmr_t nibble7_input_sel : 3;
5617 mmr_t reserved_14 : 1;
5618 mmr_t nibble7_nibble_sel : 3;
5619 mmr_t reserved_15 : 1;
5620 } sh_xn_iilb_debug_sel_s;
5621 } sh_xn_iilb_debug_sel_u_t;
5623 /* ==================================================================== */
5624 /* Register "SH_XN_PI_DEBUG_SEL" */
5625 /* XN PI Debug Port Select */
5626 /* ==================================================================== */
5628 typedef union sh_xn_pi_debug_sel_u {
5629 mmr_t sh_xn_pi_debug_sel_regval;
5631 mmr_t nibble0_input_sel : 3;
5632 mmr_t reserved_0 : 1;
5633 mmr_t nibble0_nibble_sel : 3;
5634 mmr_t reserved_1 : 1;
5635 mmr_t nibble1_input_sel : 3;
5636 mmr_t reserved_2 : 1;
5637 mmr_t nibble1_nibble_sel : 3;
5638 mmr_t reserved_3 : 1;
5639 mmr_t nibble2_input_sel : 3;
5640 mmr_t reserved_4 : 1;
5641 mmr_t nibble2_nibble_sel : 3;
5642 mmr_t reserved_5 : 1;
5643 mmr_t nibble3_input_sel : 3;
5644 mmr_t reserved_6 : 1;
5645 mmr_t nibble3_nibble_sel : 3;
5646 mmr_t reserved_7 : 1;
5647 mmr_t nibble4_input_sel : 3;
5648 mmr_t reserved_8 : 1;
5649 mmr_t nibble4_nibble_sel : 3;
5650 mmr_t reserved_9 : 1;
5651 mmr_t nibble5_input_sel : 3;
5652 mmr_t reserved_10 : 1;
5653 mmr_t nibble5_nibble_sel : 3;
5654 mmr_t reserved_11 : 1;
5655 mmr_t nibble6_input_sel : 3;
5656 mmr_t reserved_12 : 1;
5657 mmr_t nibble6_nibble_sel : 3;
5658 mmr_t reserved_13 : 1;
5659 mmr_t nibble7_input_sel : 3;
5660 mmr_t reserved_14 : 1;
5661 mmr_t nibble7_nibble_sel : 3;
5662 mmr_t reserved_15 : 1;
5663 } sh_xn_pi_debug_sel_s;
5664 } sh_xn_pi_debug_sel_u_t;
5666 /* ==================================================================== */
5667 /* Register "SH_XN_MD_DEBUG_SEL" */
5668 /* XN MD Debug Port Select */
5669 /* ==================================================================== */
5671 typedef union sh_xn_md_debug_sel_u {
5672 mmr_t sh_xn_md_debug_sel_regval;
5674 mmr_t nibble0_input_sel : 3;
5675 mmr_t reserved_0 : 1;
5676 mmr_t nibble0_nibble_sel : 3;
5677 mmr_t reserved_1 : 1;
5678 mmr_t nibble1_input_sel : 3;
5679 mmr_t reserved_2 : 1;
5680 mmr_t nibble1_nibble_sel : 3;
5681 mmr_t reserved_3 : 1;
5682 mmr_t nibble2_input_sel : 3;
5683 mmr_t reserved_4 : 1;
5684 mmr_t nibble2_nibble_sel : 3;
5685 mmr_t reserved_5 : 1;
5686 mmr_t nibble3_input_sel : 3;
5687 mmr_t reserved_6 : 1;
5688 mmr_t nibble3_nibble_sel : 3;
5689 mmr_t reserved_7 : 1;
5690 mmr_t nibble4_input_sel : 3;
5691 mmr_t reserved_8 : 1;
5692 mmr_t nibble4_nibble_sel : 3;
5693 mmr_t reserved_9 : 1;
5694 mmr_t nibble5_input_sel : 3;
5695 mmr_t reserved_10 : 1;
5696 mmr_t nibble5_nibble_sel : 3;
5697 mmr_t reserved_11 : 1;
5698 mmr_t nibble6_input_sel : 3;
5699 mmr_t reserved_12 : 1;
5700 mmr_t nibble6_nibble_sel : 3;
5701 mmr_t reserved_13 : 1;
5702 mmr_t nibble7_input_sel : 3;
5703 mmr_t reserved_14 : 1;
5704 mmr_t nibble7_nibble_sel : 3;
5705 mmr_t reserved_15 : 1;
5706 } sh_xn_md_debug_sel_s;
5707 } sh_xn_md_debug_sel_u_t;
5709 /* ==================================================================== */
5710 /* Register "SH_XN_NI0_DEBUG_SEL" */
5711 /* XN NI0 Debug Port Select */
5712 /* ==================================================================== */
5714 typedef union sh_xn_ni0_debug_sel_u {
5715 mmr_t sh_xn_ni0_debug_sel_regval;
5717 mmr_t nibble0_input_sel : 3;
5718 mmr_t reserved_0 : 1;
5719 mmr_t nibble0_nibble_sel : 3;
5720 mmr_t reserved_1 : 1;
5721 mmr_t nibble1_input_sel : 3;
5722 mmr_t reserved_2 : 1;
5723 mmr_t nibble1_nibble_sel : 3;
5724 mmr_t reserved_3 : 1;
5725 mmr_t nibble2_input_sel : 3;
5726 mmr_t reserved_4 : 1;
5727 mmr_t nibble2_nibble_sel : 3;
5728 mmr_t reserved_5 : 1;
5729 mmr_t nibble3_input_sel : 3;
5730 mmr_t reserved_6 : 1;
5731 mmr_t nibble3_nibble_sel : 3;
5732 mmr_t reserved_7 : 1;
5733 mmr_t nibble4_input_sel : 3;
5734 mmr_t reserved_8 : 1;
5735 mmr_t nibble4_nibble_sel : 3;
5736 mmr_t reserved_9 : 1;
5737 mmr_t nibble5_input_sel : 3;
5738 mmr_t reserved_10 : 1;
5739 mmr_t nibble5_nibble_sel : 3;
5740 mmr_t reserved_11 : 1;
5741 mmr_t nibble6_input_sel : 3;
5742 mmr_t reserved_12 : 1;
5743 mmr_t nibble6_nibble_sel : 3;
5744 mmr_t reserved_13 : 1;
5745 mmr_t nibble7_input_sel : 3;
5746 mmr_t reserved_14 : 1;
5747 mmr_t nibble7_nibble_sel : 3;
5748 mmr_t reserved_15 : 1;
5749 } sh_xn_ni0_debug_sel_s;
5750 } sh_xn_ni0_debug_sel_u_t;
5752 /* ==================================================================== */
5753 /* Register "SH_XN_NI1_DEBUG_SEL" */
5754 /* XN NI1 Debug Port Select */
5755 /* ==================================================================== */
5757 typedef union sh_xn_ni1_debug_sel_u {
5758 mmr_t sh_xn_ni1_debug_sel_regval;
5760 mmr_t nibble0_input_sel : 3;
5761 mmr_t reserved_0 : 1;
5762 mmr_t nibble0_nibble_sel : 3;
5763 mmr_t reserved_1 : 1;
5764 mmr_t nibble1_input_sel : 3;
5765 mmr_t reserved_2 : 1;
5766 mmr_t nibble1_nibble_sel : 3;
5767 mmr_t reserved_3 : 1;
5768 mmr_t nibble2_input_sel : 3;
5769 mmr_t reserved_4 : 1;
5770 mmr_t nibble2_nibble_sel : 3;
5771 mmr_t reserved_5 : 1;
5772 mmr_t nibble3_input_sel : 3;
5773 mmr_t reserved_6 : 1;
5774 mmr_t nibble3_nibble_sel : 3;
5775 mmr_t reserved_7 : 1;
5776 mmr_t nibble4_input_sel : 3;
5777 mmr_t reserved_8 : 1;
5778 mmr_t nibble4_nibble_sel : 3;
5779 mmr_t reserved_9 : 1;
5780 mmr_t nibble5_input_sel : 3;
5781 mmr_t reserved_10 : 1;
5782 mmr_t nibble5_nibble_sel : 3;
5783 mmr_t reserved_11 : 1;
5784 mmr_t nibble6_input_sel : 3;
5785 mmr_t reserved_12 : 1;
5786 mmr_t nibble6_nibble_sel : 3;
5787 mmr_t reserved_13 : 1;
5788 mmr_t nibble7_input_sel : 3;
5789 mmr_t reserved_14 : 1;
5790 mmr_t nibble7_nibble_sel : 3;
5791 mmr_t reserved_15 : 1;
5792 } sh_xn_ni1_debug_sel_s;
5793 } sh_xn_ni1_debug_sel_u_t;
5795 /* ==================================================================== */
5796 /* Register "SH_XN_IILB_LB_CMP_EXP_DATA0" */
5797 /* IILB compare LB input expected data0 */
5798 /* ==================================================================== */
5800 typedef union sh_xn_iilb_lb_cmp_exp_data0_u {
5801 mmr_t sh_xn_iilb_lb_cmp_exp_data0_regval;
5804 } sh_xn_iilb_lb_cmp_exp_data0_s;
5805 } sh_xn_iilb_lb_cmp_exp_data0_u_t;
5807 /* ==================================================================== */
5808 /* Register "SH_XN_IILB_LB_CMP_EXP_DATA1" */
5809 /* IILB compare LB input expected data1 */
5810 /* ==================================================================== */
5812 typedef union sh_xn_iilb_lb_cmp_exp_data1_u {
5813 mmr_t sh_xn_iilb_lb_cmp_exp_data1_regval;
5816 } sh_xn_iilb_lb_cmp_exp_data1_s;
5817 } sh_xn_iilb_lb_cmp_exp_data1_u_t;
5819 /* ==================================================================== */
5820 /* Register "SH_XN_IILB_LB_CMP_ENABLE0" */
5821 /* IILB compare LB input enable0 */
5822 /* ==================================================================== */
5824 typedef union sh_xn_iilb_lb_cmp_enable0_u {
5825 mmr_t sh_xn_iilb_lb_cmp_enable0_regval;
5828 } sh_xn_iilb_lb_cmp_enable0_s;
5829 } sh_xn_iilb_lb_cmp_enable0_u_t;
5831 /* ==================================================================== */
5832 /* Register "SH_XN_IILB_LB_CMP_ENABLE1" */
5833 /* IILB compare LB input enable1 */
5834 /* ==================================================================== */
5836 typedef union sh_xn_iilb_lb_cmp_enable1_u {
5837 mmr_t sh_xn_iilb_lb_cmp_enable1_regval;
5840 } sh_xn_iilb_lb_cmp_enable1_s;
5841 } sh_xn_iilb_lb_cmp_enable1_u_t;
5843 /* ==================================================================== */
5844 /* Register "SH_XN_IILB_II_CMP_EXP_DATA0" */
5845 /* IILB compare II input expected data0 */
5846 /* ==================================================================== */
5848 typedef union sh_xn_iilb_ii_cmp_exp_data0_u {
5849 mmr_t sh_xn_iilb_ii_cmp_exp_data0_regval;
5852 } sh_xn_iilb_ii_cmp_exp_data0_s;
5853 } sh_xn_iilb_ii_cmp_exp_data0_u_t;
5855 /* ==================================================================== */
5856 /* Register "SH_XN_IILB_II_CMP_EXP_DATA1" */
5857 /* IILB compare II input expected data1 */
5858 /* ==================================================================== */
5860 typedef union sh_xn_iilb_ii_cmp_exp_data1_u {
5861 mmr_t sh_xn_iilb_ii_cmp_exp_data1_regval;
5864 } sh_xn_iilb_ii_cmp_exp_data1_s;
5865 } sh_xn_iilb_ii_cmp_exp_data1_u_t;
5867 /* ==================================================================== */
5868 /* Register "SH_XN_IILB_II_CMP_ENABLE0" */
5869 /* IILB compare II input enable0 */
5870 /* ==================================================================== */
5872 typedef union sh_xn_iilb_ii_cmp_enable0_u {
5873 mmr_t sh_xn_iilb_ii_cmp_enable0_regval;
5876 } sh_xn_iilb_ii_cmp_enable0_s;
5877 } sh_xn_iilb_ii_cmp_enable0_u_t;
5879 /* ==================================================================== */
5880 /* Register "SH_XN_IILB_II_CMP_ENABLE1" */
5881 /* IILB compare II input enable1 */
5882 /* ==================================================================== */
5884 typedef union sh_xn_iilb_ii_cmp_enable1_u {
5885 mmr_t sh_xn_iilb_ii_cmp_enable1_regval;
5888 } sh_xn_iilb_ii_cmp_enable1_s;
5889 } sh_xn_iilb_ii_cmp_enable1_u_t;
5891 /* ==================================================================== */
5892 /* Register "SH_XN_IILB_MD_CMP_EXP_DATA0" */
5893 /* IILB compare MD input expected data0 */
5894 /* ==================================================================== */
5896 typedef union sh_xn_iilb_md_cmp_exp_data0_u {
5897 mmr_t sh_xn_iilb_md_cmp_exp_data0_regval;
5900 } sh_xn_iilb_md_cmp_exp_data0_s;
5901 } sh_xn_iilb_md_cmp_exp_data0_u_t;
5903 /* ==================================================================== */
5904 /* Register "SH_XN_IILB_MD_CMP_EXP_DATA1" */
5905 /* IILB compare MD input expected data1 */
5906 /* ==================================================================== */
5908 typedef union sh_xn_iilb_md_cmp_exp_data1_u {
5909 mmr_t sh_xn_iilb_md_cmp_exp_data1_regval;
5912 } sh_xn_iilb_md_cmp_exp_data1_s;
5913 } sh_xn_iilb_md_cmp_exp_data1_u_t;
5915 /* ==================================================================== */
5916 /* Register "SH_XN_IILB_MD_CMP_ENABLE0" */
5917 /* IILB compare MD input enable0 */
5918 /* ==================================================================== */
5920 typedef union sh_xn_iilb_md_cmp_enable0_u {
5921 mmr_t sh_xn_iilb_md_cmp_enable0_regval;
5924 } sh_xn_iilb_md_cmp_enable0_s;
5925 } sh_xn_iilb_md_cmp_enable0_u_t;
5927 /* ==================================================================== */
5928 /* Register "SH_XN_IILB_MD_CMP_ENABLE1" */
5929 /* IILB compare MD input enable1 */
5930 /* ==================================================================== */
5932 typedef union sh_xn_iilb_md_cmp_enable1_u {
5933 mmr_t sh_xn_iilb_md_cmp_enable1_regval;
5936 } sh_xn_iilb_md_cmp_enable1_s;
5937 } sh_xn_iilb_md_cmp_enable1_u_t;
5939 /* ==================================================================== */
5940 /* Register "SH_XN_IILB_PI_CMP_EXP_DATA0" */
5941 /* IILB compare PI input expected data0 */
5942 /* ==================================================================== */
5944 typedef union sh_xn_iilb_pi_cmp_exp_data0_u {
5945 mmr_t sh_xn_iilb_pi_cmp_exp_data0_regval;
5948 } sh_xn_iilb_pi_cmp_exp_data0_s;
5949 } sh_xn_iilb_pi_cmp_exp_data0_u_t;
5951 /* ==================================================================== */
5952 /* Register "SH_XN_IILB_PI_CMP_EXP_DATA1" */
5953 /* IILB compare PI input expected data1 */
5954 /* ==================================================================== */
5956 typedef union sh_xn_iilb_pi_cmp_exp_data1_u {
5957 mmr_t sh_xn_iilb_pi_cmp_exp_data1_regval;
5960 } sh_xn_iilb_pi_cmp_exp_data1_s;
5961 } sh_xn_iilb_pi_cmp_exp_data1_u_t;
5963 /* ==================================================================== */
5964 /* Register "SH_XN_IILB_PI_CMP_ENABLE0" */
5965 /* IILB compare PI input enable0 */
5966 /* ==================================================================== */
5968 typedef union sh_xn_iilb_pi_cmp_enable0_u {
5969 mmr_t sh_xn_iilb_pi_cmp_enable0_regval;
5972 } sh_xn_iilb_pi_cmp_enable0_s;
5973 } sh_xn_iilb_pi_cmp_enable0_u_t;
5975 /* ==================================================================== */
5976 /* Register "SH_XN_IILB_PI_CMP_ENABLE1" */
5977 /* IILB compare PI input enable1 */
5978 /* ==================================================================== */
5980 typedef union sh_xn_iilb_pi_cmp_enable1_u {
5981 mmr_t sh_xn_iilb_pi_cmp_enable1_regval;
5984 } sh_xn_iilb_pi_cmp_enable1_s;
5985 } sh_xn_iilb_pi_cmp_enable1_u_t;
5987 /* ==================================================================== */
5988 /* Register "SH_XN_IILB_NI0_CMP_EXP_DATA0" */
5989 /* IILB compare NI0 input expected data0 */
5990 /* ==================================================================== */
5992 typedef union sh_xn_iilb_ni0_cmp_exp_data0_u {
5993 mmr_t sh_xn_iilb_ni0_cmp_exp_data0_regval;
5996 } sh_xn_iilb_ni0_cmp_exp_data0_s;
5997 } sh_xn_iilb_ni0_cmp_exp_data0_u_t;
5999 /* ==================================================================== */
6000 /* Register "SH_XN_IILB_NI0_CMP_EXP_DATA1" */
6001 /* IILB compare NI0 input expected data1 */
6002 /* ==================================================================== */
6004 typedef union sh_xn_iilb_ni0_cmp_exp_data1_u {
6005 mmr_t sh_xn_iilb_ni0_cmp_exp_data1_regval;
6008 } sh_xn_iilb_ni0_cmp_exp_data1_s;
6009 } sh_xn_iilb_ni0_cmp_exp_data1_u_t;
6011 /* ==================================================================== */
6012 /* Register "SH_XN_IILB_NI0_CMP_ENABLE0" */
6013 /* IILB compare NI0 input enable0 */
6014 /* ==================================================================== */
6016 typedef union sh_xn_iilb_ni0_cmp_enable0_u {
6017 mmr_t sh_xn_iilb_ni0_cmp_enable0_regval;
6020 } sh_xn_iilb_ni0_cmp_enable0_s;
6021 } sh_xn_iilb_ni0_cmp_enable0_u_t;
6023 /* ==================================================================== */
6024 /* Register "SH_XN_IILB_NI0_CMP_ENABLE1" */
6025 /* IILB compare NI0 input enable1 */
6026 /* ==================================================================== */
6028 typedef union sh_xn_iilb_ni0_cmp_enable1_u {
6029 mmr_t sh_xn_iilb_ni0_cmp_enable1_regval;
6032 } sh_xn_iilb_ni0_cmp_enable1_s;
6033 } sh_xn_iilb_ni0_cmp_enable1_u_t;
6035 /* ==================================================================== */
6036 /* Register "SH_XN_IILB_NI1_CMP_EXP_DATA0" */
6037 /* IILB compare NI1 input expected data0 */
6038 /* ==================================================================== */
6040 typedef union sh_xn_iilb_ni1_cmp_exp_data0_u {
6041 mmr_t sh_xn_iilb_ni1_cmp_exp_data0_regval;
6044 } sh_xn_iilb_ni1_cmp_exp_data0_s;
6045 } sh_xn_iilb_ni1_cmp_exp_data0_u_t;
6047 /* ==================================================================== */
6048 /* Register "SH_XN_IILB_NI1_CMP_EXP_DATA1" */
6049 /* IILB compare NI1 input expected data1 */
6050 /* ==================================================================== */
6052 typedef union sh_xn_iilb_ni1_cmp_exp_data1_u {
6053 mmr_t sh_xn_iilb_ni1_cmp_exp_data1_regval;
6056 } sh_xn_iilb_ni1_cmp_exp_data1_s;
6057 } sh_xn_iilb_ni1_cmp_exp_data1_u_t;
6059 /* ==================================================================== */
6060 /* Register "SH_XN_IILB_NI1_CMP_ENABLE0" */
6061 /* IILB compare NI1 input enable0 */
6062 /* ==================================================================== */
6064 typedef union sh_xn_iilb_ni1_cmp_enable0_u {
6065 mmr_t sh_xn_iilb_ni1_cmp_enable0_regval;
6068 } sh_xn_iilb_ni1_cmp_enable0_s;
6069 } sh_xn_iilb_ni1_cmp_enable0_u_t;
6071 /* ==================================================================== */
6072 /* Register "SH_XN_IILB_NI1_CMP_ENABLE1" */
6073 /* IILB compare NI1 input enable1 */
6074 /* ==================================================================== */
6076 typedef union sh_xn_iilb_ni1_cmp_enable1_u {
6077 mmr_t sh_xn_iilb_ni1_cmp_enable1_regval;
6080 } sh_xn_iilb_ni1_cmp_enable1_s;
6081 } sh_xn_iilb_ni1_cmp_enable1_u_t;
6083 /* ==================================================================== */
6084 /* Register "SH_XN_MD_IILB_CMP_EXP_DATA0" */
6085 /* MD compare IILB input expected data0 */
6086 /* ==================================================================== */
6088 typedef union sh_xn_md_iilb_cmp_exp_data0_u {
6089 mmr_t sh_xn_md_iilb_cmp_exp_data0_regval;
6092 } sh_xn_md_iilb_cmp_exp_data0_s;
6093 } sh_xn_md_iilb_cmp_exp_data0_u_t;
6095 /* ==================================================================== */
6096 /* Register "SH_XN_MD_IILB_CMP_EXP_DATA1" */
6097 /* MD compare IILB input expected data1 */
6098 /* ==================================================================== */
6100 typedef union sh_xn_md_iilb_cmp_exp_data1_u {
6101 mmr_t sh_xn_md_iilb_cmp_exp_data1_regval;
6104 } sh_xn_md_iilb_cmp_exp_data1_s;
6105 } sh_xn_md_iilb_cmp_exp_data1_u_t;
6107 /* ==================================================================== */
6108 /* Register "SH_XN_MD_IILB_CMP_ENABLE0" */
6109 /* MD compare IILB input enable0 */
6110 /* ==================================================================== */
6112 typedef union sh_xn_md_iilb_cmp_enable0_u {
6113 mmr_t sh_xn_md_iilb_cmp_enable0_regval;
6116 } sh_xn_md_iilb_cmp_enable0_s;
6117 } sh_xn_md_iilb_cmp_enable0_u_t;
6119 /* ==================================================================== */
6120 /* Register "SH_XN_MD_IILB_CMP_ENABLE1" */
6121 /* MD compare IILB input enable1 */
6122 /* ==================================================================== */
6124 typedef union sh_xn_md_iilb_cmp_enable1_u {
6125 mmr_t sh_xn_md_iilb_cmp_enable1_regval;
6128 } sh_xn_md_iilb_cmp_enable1_s;
6129 } sh_xn_md_iilb_cmp_enable1_u_t;
6131 /* ==================================================================== */
6132 /* Register "SH_XN_MD_NI0_CMP_EXP_DATA0" */
6133 /* MD compare NI0 input expected data0 */
6134 /* ==================================================================== */
6136 typedef union sh_xn_md_ni0_cmp_exp_data0_u {
6137 mmr_t sh_xn_md_ni0_cmp_exp_data0_regval;
6140 } sh_xn_md_ni0_cmp_exp_data0_s;
6141 } sh_xn_md_ni0_cmp_exp_data0_u_t;
6143 /* ==================================================================== */
6144 /* Register "SH_XN_MD_NI0_CMP_EXP_DATA1" */
6145 /* MD compare NI0 input expected data1 */
6146 /* ==================================================================== */
6148 typedef union sh_xn_md_ni0_cmp_exp_data1_u {
6149 mmr_t sh_xn_md_ni0_cmp_exp_data1_regval;
6152 } sh_xn_md_ni0_cmp_exp_data1_s;
6153 } sh_xn_md_ni0_cmp_exp_data1_u_t;
6155 /* ==================================================================== */
6156 /* Register "SH_XN_MD_NI0_CMP_ENABLE0" */
6157 /* MD compare NI0 input enable0 */
6158 /* ==================================================================== */
6160 typedef union sh_xn_md_ni0_cmp_enable0_u {
6161 mmr_t sh_xn_md_ni0_cmp_enable0_regval;
6164 } sh_xn_md_ni0_cmp_enable0_s;
6165 } sh_xn_md_ni0_cmp_enable0_u_t;
6167 /* ==================================================================== */
6168 /* Register "SH_XN_MD_NI0_CMP_ENABLE1" */
6169 /* MD compare NI0 input enable1 */
6170 /* ==================================================================== */
6172 typedef union sh_xn_md_ni0_cmp_enable1_u {
6173 mmr_t sh_xn_md_ni0_cmp_enable1_regval;
6176 } sh_xn_md_ni0_cmp_enable1_s;
6177 } sh_xn_md_ni0_cmp_enable1_u_t;
6179 /* ==================================================================== */
6180 /* Register "SH_XN_MD_NI1_CMP_EXP_DATA0" */
6181 /* MD compare NI1 input expected data0 */
6182 /* ==================================================================== */
6184 typedef union sh_xn_md_ni1_cmp_exp_data0_u {
6185 mmr_t sh_xn_md_ni1_cmp_exp_data0_regval;
6188 } sh_xn_md_ni1_cmp_exp_data0_s;
6189 } sh_xn_md_ni1_cmp_exp_data0_u_t;
6191 /* ==================================================================== */
6192 /* Register "SH_XN_MD_NI1_CMP_EXP_DATA1" */
6193 /* MD compare NI1 input expected data1 */
6194 /* ==================================================================== */
6196 typedef union sh_xn_md_ni1_cmp_exp_data1_u {
6197 mmr_t sh_xn_md_ni1_cmp_exp_data1_regval;
6200 } sh_xn_md_ni1_cmp_exp_data1_s;
6201 } sh_xn_md_ni1_cmp_exp_data1_u_t;
6203 /* ==================================================================== */
6204 /* Register "SH_XN_MD_NI1_CMP_ENABLE0" */
6205 /* MD compare NI1 input enable0 */
6206 /* ==================================================================== */
6208 typedef union sh_xn_md_ni1_cmp_enable0_u {
6209 mmr_t sh_xn_md_ni1_cmp_enable0_regval;
6212 } sh_xn_md_ni1_cmp_enable0_s;
6213 } sh_xn_md_ni1_cmp_enable0_u_t;
6215 /* ==================================================================== */
6216 /* Register "SH_XN_MD_NI1_CMP_ENABLE1" */
6217 /* MD compare NI1 input enable1 */
6218 /* ==================================================================== */
6220 typedef union sh_xn_md_ni1_cmp_enable1_u {
6221 mmr_t sh_xn_md_ni1_cmp_enable1_regval;
6224 } sh_xn_md_ni1_cmp_enable1_s;
6225 } sh_xn_md_ni1_cmp_enable1_u_t;
6227 /* ==================================================================== */
6228 /* Register "SH_XN_MD_SIC_CMP_EXP_HDR0" */
6229 /* MD compare SIC input expected header0 */
6230 /* ==================================================================== */
6232 typedef union sh_xn_md_sic_cmp_exp_hdr0_u {
6233 mmr_t sh_xn_md_sic_cmp_exp_hdr0_regval;
6236 } sh_xn_md_sic_cmp_exp_hdr0_s;
6237 } sh_xn_md_sic_cmp_exp_hdr0_u_t;
6239 /* ==================================================================== */
6240 /* Register "SH_XN_MD_SIC_CMP_EXP_HDR1" */
6241 /* MD compare SIC input expected header1 */
6242 /* ==================================================================== */
6244 typedef union sh_xn_md_sic_cmp_exp_hdr1_u {
6245 mmr_t sh_xn_md_sic_cmp_exp_hdr1_regval;
6248 mmr_t reserved_0 : 22;
6249 } sh_xn_md_sic_cmp_exp_hdr1_s;
6250 } sh_xn_md_sic_cmp_exp_hdr1_u_t;
6252 /* ==================================================================== */
6253 /* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0" */
6254 /* MD compare SIC header enable0 */
6255 /* ==================================================================== */
6257 typedef union sh_xn_md_sic_cmp_hdr_enable0_u {
6258 mmr_t sh_xn_md_sic_cmp_hdr_enable0_regval;
6261 } sh_xn_md_sic_cmp_hdr_enable0_s;
6262 } sh_xn_md_sic_cmp_hdr_enable0_u_t;
6264 /* ==================================================================== */
6265 /* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1" */
6266 /* MD compare SIC header enable1 */
6267 /* ==================================================================== */
6269 typedef union sh_xn_md_sic_cmp_hdr_enable1_u {
6270 mmr_t sh_xn_md_sic_cmp_hdr_enable1_regval;
6273 mmr_t reserved_0 : 22;
6274 } sh_xn_md_sic_cmp_hdr_enable1_s;
6275 } sh_xn_md_sic_cmp_hdr_enable1_u_t;
6277 /* ==================================================================== */
6278 /* Register "SH_XN_MD_SIC_CMP_DATA0" */
6279 /* MD compare SIC data0 */
6280 /* ==================================================================== */
6282 typedef union sh_xn_md_sic_cmp_data0_u {
6283 mmr_t sh_xn_md_sic_cmp_data0_regval;
6286 } sh_xn_md_sic_cmp_data0_s;
6287 } sh_xn_md_sic_cmp_data0_u_t;
6289 /* ==================================================================== */
6290 /* Register "SH_XN_MD_SIC_CMP_DATA1" */
6291 /* MD compare SIC data1 */
6292 /* ==================================================================== */
6294 typedef union sh_xn_md_sic_cmp_data1_u {
6295 mmr_t sh_xn_md_sic_cmp_data1_regval;
6298 } sh_xn_md_sic_cmp_data1_s;
6299 } sh_xn_md_sic_cmp_data1_u_t;
6301 /* ==================================================================== */
6302 /* Register "SH_XN_MD_SIC_CMP_DATA2" */
6303 /* MD compare SIC data2 */
6304 /* ==================================================================== */
6306 typedef union sh_xn_md_sic_cmp_data2_u {
6307 mmr_t sh_xn_md_sic_cmp_data2_regval;
6310 } sh_xn_md_sic_cmp_data2_s;
6311 } sh_xn_md_sic_cmp_data2_u_t;
6313 /* ==================================================================== */
6314 /* Register "SH_XN_MD_SIC_CMP_DATA3" */
6315 /* MD compare SIC data3 */
6316 /* ==================================================================== */
6318 typedef union sh_xn_md_sic_cmp_data3_u {
6319 mmr_t sh_xn_md_sic_cmp_data3_regval;
6322 } sh_xn_md_sic_cmp_data3_s;
6323 } sh_xn_md_sic_cmp_data3_u_t;
6325 /* ==================================================================== */
6326 /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0" */
6327 /* MD enable compare SIC data0 */
6328 /* ==================================================================== */
6330 typedef union sh_xn_md_sic_cmp_data_enable0_u {
6331 mmr_t sh_xn_md_sic_cmp_data_enable0_regval;
6333 mmr_t data_enable0 : 64;
6334 } sh_xn_md_sic_cmp_data_enable0_s;
6335 } sh_xn_md_sic_cmp_data_enable0_u_t;
6337 /* ==================================================================== */
6338 /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1" */
6339 /* MD enable compare SIC data1 */
6340 /* ==================================================================== */
6342 typedef union sh_xn_md_sic_cmp_data_enable1_u {
6343 mmr_t sh_xn_md_sic_cmp_data_enable1_regval;
6345 mmr_t data_enable1 : 64;
6346 } sh_xn_md_sic_cmp_data_enable1_s;
6347 } sh_xn_md_sic_cmp_data_enable1_u_t;
6349 /* ==================================================================== */
6350 /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2" */
6351 /* MD enable compare SIC data2 */
6352 /* ==================================================================== */
6354 typedef union sh_xn_md_sic_cmp_data_enable2_u {
6355 mmr_t sh_xn_md_sic_cmp_data_enable2_regval;
6357 mmr_t data_enable2 : 64;
6358 } sh_xn_md_sic_cmp_data_enable2_s;
6359 } sh_xn_md_sic_cmp_data_enable2_u_t;
6361 /* ==================================================================== */
6362 /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3" */
6363 /* MD enable compare SIC data3 */
6364 /* ==================================================================== */
6366 typedef union sh_xn_md_sic_cmp_data_enable3_u {
6367 mmr_t sh_xn_md_sic_cmp_data_enable3_regval;
6369 mmr_t data_enable3 : 64;
6370 } sh_xn_md_sic_cmp_data_enable3_s;
6371 } sh_xn_md_sic_cmp_data_enable3_u_t;
6373 /* ==================================================================== */
6374 /* Register "SH_XN_PI_IILB_CMP_EXP_DATA0" */
6375 /* PI compare IILB input expected data0 */
6376 /* ==================================================================== */
6378 typedef union sh_xn_pi_iilb_cmp_exp_data0_u {
6379 mmr_t sh_xn_pi_iilb_cmp_exp_data0_regval;
6382 } sh_xn_pi_iilb_cmp_exp_data0_s;
6383 } sh_xn_pi_iilb_cmp_exp_data0_u_t;
6385 /* ==================================================================== */
6386 /* Register "SH_XN_PI_IILB_CMP_EXP_DATA1" */
6387 /* PI compare IILB input expected data1 */
6388 /* ==================================================================== */
6390 typedef union sh_xn_pi_iilb_cmp_exp_data1_u {
6391 mmr_t sh_xn_pi_iilb_cmp_exp_data1_regval;
6394 } sh_xn_pi_iilb_cmp_exp_data1_s;
6395 } sh_xn_pi_iilb_cmp_exp_data1_u_t;
6397 /* ==================================================================== */
6398 /* Register "SH_XN_PI_IILB_CMP_ENABLE0" */
6399 /* PI compare IILB input enable0 */
6400 /* ==================================================================== */
6402 typedef union sh_xn_pi_iilb_cmp_enable0_u {
6403 mmr_t sh_xn_pi_iilb_cmp_enable0_regval;
6406 } sh_xn_pi_iilb_cmp_enable0_s;
6407 } sh_xn_pi_iilb_cmp_enable0_u_t;
6409 /* ==================================================================== */
6410 /* Register "SH_XN_PI_IILB_CMP_ENABLE1" */
6411 /* PI compare IILB input enable1 */
6412 /* ==================================================================== */
6414 typedef union sh_xn_pi_iilb_cmp_enable1_u {
6415 mmr_t sh_xn_pi_iilb_cmp_enable1_regval;
6418 } sh_xn_pi_iilb_cmp_enable1_s;
6419 } sh_xn_pi_iilb_cmp_enable1_u_t;
6421 /* ==================================================================== */
6422 /* Register "SH_XN_PI_NI0_CMP_EXP_DATA0" */
6423 /* PI compare NI0 input expected data0 */
6424 /* ==================================================================== */
6426 typedef union sh_xn_pi_ni0_cmp_exp_data0_u {
6427 mmr_t sh_xn_pi_ni0_cmp_exp_data0_regval;
6430 } sh_xn_pi_ni0_cmp_exp_data0_s;
6431 } sh_xn_pi_ni0_cmp_exp_data0_u_t;
6433 /* ==================================================================== */
6434 /* Register "SH_XN_PI_NI0_CMP_EXP_DATA1" */
6435 /* PI compare NI0 input expected data1 */
6436 /* ==================================================================== */
6438 typedef union sh_xn_pi_ni0_cmp_exp_data1_u {
6439 mmr_t sh_xn_pi_ni0_cmp_exp_data1_regval;
6442 } sh_xn_pi_ni0_cmp_exp_data1_s;
6443 } sh_xn_pi_ni0_cmp_exp_data1_u_t;
6445 /* ==================================================================== */
6446 /* Register "SH_XN_PI_NI0_CMP_ENABLE0" */
6447 /* PI compare NI0 input enable0 */
6448 /* ==================================================================== */
6450 typedef union sh_xn_pi_ni0_cmp_enable0_u {
6451 mmr_t sh_xn_pi_ni0_cmp_enable0_regval;
6454 } sh_xn_pi_ni0_cmp_enable0_s;
6455 } sh_xn_pi_ni0_cmp_enable0_u_t;
6457 /* ==================================================================== */
6458 /* Register "SH_XN_PI_NI0_CMP_ENABLE1" */
6459 /* PI compare NI0 input enable1 */
6460 /* ==================================================================== */
6462 typedef union sh_xn_pi_ni0_cmp_enable1_u {
6463 mmr_t sh_xn_pi_ni0_cmp_enable1_regval;
6466 } sh_xn_pi_ni0_cmp_enable1_s;
6467 } sh_xn_pi_ni0_cmp_enable1_u_t;
6469 /* ==================================================================== */
6470 /* Register "SH_XN_PI_NI1_CMP_EXP_DATA0" */
6471 /* PI compare NI1 input expected data0 */
6472 /* ==================================================================== */
6474 typedef union sh_xn_pi_ni1_cmp_exp_data0_u {
6475 mmr_t sh_xn_pi_ni1_cmp_exp_data0_regval;
6478 } sh_xn_pi_ni1_cmp_exp_data0_s;
6479 } sh_xn_pi_ni1_cmp_exp_data0_u_t;
6481 /* ==================================================================== */
6482 /* Register "SH_XN_PI_NI1_CMP_EXP_DATA1" */
6483 /* PI compare NI1 input expected data1 */
6484 /* ==================================================================== */
6486 typedef union sh_xn_pi_ni1_cmp_exp_data1_u {
6487 mmr_t sh_xn_pi_ni1_cmp_exp_data1_regval;
6490 } sh_xn_pi_ni1_cmp_exp_data1_s;
6491 } sh_xn_pi_ni1_cmp_exp_data1_u_t;
6493 /* ==================================================================== */
6494 /* Register "SH_XN_PI_NI1_CMP_ENABLE0" */
6495 /* PI compare NI1 input enable0 */
6496 /* ==================================================================== */
6498 typedef union sh_xn_pi_ni1_cmp_enable0_u {
6499 mmr_t sh_xn_pi_ni1_cmp_enable0_regval;
6502 } sh_xn_pi_ni1_cmp_enable0_s;
6503 } sh_xn_pi_ni1_cmp_enable0_u_t;
6505 /* ==================================================================== */
6506 /* Register "SH_XN_PI_NI1_CMP_ENABLE1" */
6507 /* PI compare NI1 input enable1 */
6508 /* ==================================================================== */
6510 typedef union sh_xn_pi_ni1_cmp_enable1_u {
6511 mmr_t sh_xn_pi_ni1_cmp_enable1_regval;
6514 } sh_xn_pi_ni1_cmp_enable1_s;
6515 } sh_xn_pi_ni1_cmp_enable1_u_t;
6517 /* ==================================================================== */
6518 /* Register "SH_XN_PI_SIC_CMP_EXP_HDR0" */
6519 /* PI compare SIC input expected header0 */
6520 /* ==================================================================== */
6522 typedef union sh_xn_pi_sic_cmp_exp_hdr0_u {
6523 mmr_t sh_xn_pi_sic_cmp_exp_hdr0_regval;
6526 } sh_xn_pi_sic_cmp_exp_hdr0_s;
6527 } sh_xn_pi_sic_cmp_exp_hdr0_u_t;
6529 /* ==================================================================== */
6530 /* Register "SH_XN_PI_SIC_CMP_EXP_HDR1" */
6531 /* PI compare SIC input expected header1 */
6532 /* ==================================================================== */
6534 typedef union sh_xn_pi_sic_cmp_exp_hdr1_u {
6535 mmr_t sh_xn_pi_sic_cmp_exp_hdr1_regval;
6538 mmr_t reserved_0 : 22;
6539 } sh_xn_pi_sic_cmp_exp_hdr1_s;
6540 } sh_xn_pi_sic_cmp_exp_hdr1_u_t;
6542 /* ==================================================================== */
6543 /* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0" */
6544 /* PI compare SIC header enable0 */
6545 /* ==================================================================== */
6547 typedef union sh_xn_pi_sic_cmp_hdr_enable0_u {
6548 mmr_t sh_xn_pi_sic_cmp_hdr_enable0_regval;
6551 } sh_xn_pi_sic_cmp_hdr_enable0_s;
6552 } sh_xn_pi_sic_cmp_hdr_enable0_u_t;
6554 /* ==================================================================== */
6555 /* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1" */
6556 /* PI compare SIC header enable1 */
6557 /* ==================================================================== */
6559 typedef union sh_xn_pi_sic_cmp_hdr_enable1_u {
6560 mmr_t sh_xn_pi_sic_cmp_hdr_enable1_regval;
6563 mmr_t reserved_0 : 22;
6564 } sh_xn_pi_sic_cmp_hdr_enable1_s;
6565 } sh_xn_pi_sic_cmp_hdr_enable1_u_t;
6567 /* ==================================================================== */
6568 /* Register "SH_XN_PI_SIC_CMP_DATA0" */
6569 /* PI compare SIC data0 */
6570 /* ==================================================================== */
6572 typedef union sh_xn_pi_sic_cmp_data0_u {
6573 mmr_t sh_xn_pi_sic_cmp_data0_regval;
6576 } sh_xn_pi_sic_cmp_data0_s;
6577 } sh_xn_pi_sic_cmp_data0_u_t;
6579 /* ==================================================================== */
6580 /* Register "SH_XN_PI_SIC_CMP_DATA1" */
6581 /* PI compare SIC data1 */
6582 /* ==================================================================== */
6584 typedef union sh_xn_pi_sic_cmp_data1_u {
6585 mmr_t sh_xn_pi_sic_cmp_data1_regval;
6588 } sh_xn_pi_sic_cmp_data1_s;
6589 } sh_xn_pi_sic_cmp_data1_u_t;
6591 /* ==================================================================== */
6592 /* Register "SH_XN_PI_SIC_CMP_DATA2" */
6593 /* PI compare SIC data2 */
6594 /* ==================================================================== */
6596 typedef union sh_xn_pi_sic_cmp_data2_u {
6597 mmr_t sh_xn_pi_sic_cmp_data2_regval;
6600 } sh_xn_pi_sic_cmp_data2_s;
6601 } sh_xn_pi_sic_cmp_data2_u_t;
6603 /* ==================================================================== */
6604 /* Register "SH_XN_PI_SIC_CMP_DATA3" */
6605 /* PI compare SIC data3 */
6606 /* ==================================================================== */
6608 typedef union sh_xn_pi_sic_cmp_data3_u {
6609 mmr_t sh_xn_pi_sic_cmp_data3_regval;
6612 } sh_xn_pi_sic_cmp_data3_s;
6613 } sh_xn_pi_sic_cmp_data3_u_t;
6615 /* ==================================================================== */
6616 /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0" */
6617 /* PI enable compare SIC data0 */
6618 /* ==================================================================== */
6620 typedef union sh_xn_pi_sic_cmp_data_enable0_u {
6621 mmr_t sh_xn_pi_sic_cmp_data_enable0_regval;
6623 mmr_t data_enable0 : 64;
6624 } sh_xn_pi_sic_cmp_data_enable0_s;
6625 } sh_xn_pi_sic_cmp_data_enable0_u_t;
6627 /* ==================================================================== */
6628 /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1" */
6629 /* PI enable compare SIC data1 */
6630 /* ==================================================================== */
6632 typedef union sh_xn_pi_sic_cmp_data_enable1_u {
6633 mmr_t sh_xn_pi_sic_cmp_data_enable1_regval;
6635 mmr_t data_enable1 : 64;
6636 } sh_xn_pi_sic_cmp_data_enable1_s;
6637 } sh_xn_pi_sic_cmp_data_enable1_u_t;
6639 /* ==================================================================== */
6640 /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2" */
6641 /* PI enable compare SIC data2 */
6642 /* ==================================================================== */
6644 typedef union sh_xn_pi_sic_cmp_data_enable2_u {
6645 mmr_t sh_xn_pi_sic_cmp_data_enable2_regval;
6647 mmr_t data_enable2 : 64;
6648 } sh_xn_pi_sic_cmp_data_enable2_s;
6649 } sh_xn_pi_sic_cmp_data_enable2_u_t;
6651 /* ==================================================================== */
6652 /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3" */
6653 /* PI enable compare SIC data3 */
6654 /* ==================================================================== */
6656 typedef union sh_xn_pi_sic_cmp_data_enable3_u {
6657 mmr_t sh_xn_pi_sic_cmp_data_enable3_regval;
6659 mmr_t data_enable3 : 64;
6660 } sh_xn_pi_sic_cmp_data_enable3_s;
6661 } sh_xn_pi_sic_cmp_data_enable3_u_t;
6663 /* ==================================================================== */
6664 /* Register "SH_XN_NI0_IILB_CMP_EXP_DATA0" */
6665 /* NI0 compare IILB input expected data0 */
6666 /* ==================================================================== */
6668 typedef union sh_xn_ni0_iilb_cmp_exp_data0_u {
6669 mmr_t sh_xn_ni0_iilb_cmp_exp_data0_regval;
6672 } sh_xn_ni0_iilb_cmp_exp_data0_s;
6673 } sh_xn_ni0_iilb_cmp_exp_data0_u_t;
6675 /* ==================================================================== */
6676 /* Register "SH_XN_NI0_IILB_CMP_EXP_DATA1" */
6677 /* NI0 compare IILB input expected data1 */
6678 /* ==================================================================== */
6680 typedef union sh_xn_ni0_iilb_cmp_exp_data1_u {
6681 mmr_t sh_xn_ni0_iilb_cmp_exp_data1_regval;
6684 } sh_xn_ni0_iilb_cmp_exp_data1_s;
6685 } sh_xn_ni0_iilb_cmp_exp_data1_u_t;
6687 /* ==================================================================== */
6688 /* Register "SH_XN_NI0_IILB_CMP_ENABLE0" */
6689 /* NI0 compare IILB input enable0 */
6690 /* ==================================================================== */
6692 typedef union sh_xn_ni0_iilb_cmp_enable0_u {
6693 mmr_t sh_xn_ni0_iilb_cmp_enable0_regval;
6696 } sh_xn_ni0_iilb_cmp_enable0_s;
6697 } sh_xn_ni0_iilb_cmp_enable0_u_t;
6699 /* ==================================================================== */
6700 /* Register "SH_XN_NI0_IILB_CMP_ENABLE1" */
6701 /* NI0 compare IILB input enable1 */
6702 /* ==================================================================== */
6704 typedef union sh_xn_ni0_iilb_cmp_enable1_u {
6705 mmr_t sh_xn_ni0_iilb_cmp_enable1_regval;
6708 } sh_xn_ni0_iilb_cmp_enable1_s;
6709 } sh_xn_ni0_iilb_cmp_enable1_u_t;
6711 /* ==================================================================== */
6712 /* Register "SH_XN_NI0_PI_CMP_EXP_DATA0" */
6713 /* NI0 compare PI input expected data0 */
6714 /* ==================================================================== */
6716 typedef union sh_xn_ni0_pi_cmp_exp_data0_u {
6717 mmr_t sh_xn_ni0_pi_cmp_exp_data0_regval;
6720 } sh_xn_ni0_pi_cmp_exp_data0_s;
6721 } sh_xn_ni0_pi_cmp_exp_data0_u_t;
6723 /* ==================================================================== */
6724 /* Register "SH_XN_NI0_PI_CMP_EXP_DATA1" */
6725 /* NI0 compare PI input expected data1 */
6726 /* ==================================================================== */
6728 typedef union sh_xn_ni0_pi_cmp_exp_data1_u {
6729 mmr_t sh_xn_ni0_pi_cmp_exp_data1_regval;
6732 } sh_xn_ni0_pi_cmp_exp_data1_s;
6733 } sh_xn_ni0_pi_cmp_exp_data1_u_t;
6735 /* ==================================================================== */
6736 /* Register "SH_XN_NI0_PI_CMP_ENABLE0" */
6737 /* NI0 compare PI input enable0 */
6738 /* ==================================================================== */
6740 typedef union sh_xn_ni0_pi_cmp_enable0_u {
6741 mmr_t sh_xn_ni0_pi_cmp_enable0_regval;
6744 } sh_xn_ni0_pi_cmp_enable0_s;
6745 } sh_xn_ni0_pi_cmp_enable0_u_t;
6747 /* ==================================================================== */
6748 /* Register "SH_XN_NI0_PI_CMP_ENABLE1" */
6749 /* NI0 compare PI input enable1 */
6750 /* ==================================================================== */
6752 typedef union sh_xn_ni0_pi_cmp_enable1_u {
6753 mmr_t sh_xn_ni0_pi_cmp_enable1_regval;
6756 } sh_xn_ni0_pi_cmp_enable1_s;
6757 } sh_xn_ni0_pi_cmp_enable1_u_t;
6759 /* ==================================================================== */
6760 /* Register "SH_XN_NI0_MD_CMP_EXP_DATA0" */
6761 /* NI0 compare MD input expected data0 */
6762 /* ==================================================================== */
6764 typedef union sh_xn_ni0_md_cmp_exp_data0_u {
6765 mmr_t sh_xn_ni0_md_cmp_exp_data0_regval;
6768 } sh_xn_ni0_md_cmp_exp_data0_s;
6769 } sh_xn_ni0_md_cmp_exp_data0_u_t;
6771 /* ==================================================================== */
6772 /* Register "SH_XN_NI0_MD_CMP_EXP_DATA1" */
6773 /* NI0 compare MD input expected data1 */
6774 /* ==================================================================== */
6776 typedef union sh_xn_ni0_md_cmp_exp_data1_u {
6777 mmr_t sh_xn_ni0_md_cmp_exp_data1_regval;
6780 } sh_xn_ni0_md_cmp_exp_data1_s;
6781 } sh_xn_ni0_md_cmp_exp_data1_u_t;
6783 /* ==================================================================== */
6784 /* Register "SH_XN_NI0_MD_CMP_ENABLE0" */
6785 /* NI0 compare MD input enable0 */
6786 /* ==================================================================== */
6788 typedef union sh_xn_ni0_md_cmp_enable0_u {
6789 mmr_t sh_xn_ni0_md_cmp_enable0_regval;
6792 } sh_xn_ni0_md_cmp_enable0_s;
6793 } sh_xn_ni0_md_cmp_enable0_u_t;
6795 /* ==================================================================== */
6796 /* Register "SH_XN_NI0_MD_CMP_ENABLE1" */
6797 /* NI0 compare MD input enable1 */
6798 /* ==================================================================== */
6800 typedef union sh_xn_ni0_md_cmp_enable1_u {
6801 mmr_t sh_xn_ni0_md_cmp_enable1_regval;
6804 } sh_xn_ni0_md_cmp_enable1_s;
6805 } sh_xn_ni0_md_cmp_enable1_u_t;
6807 /* ==================================================================== */
6808 /* Register "SH_XN_NI0_NI_CMP_EXP_DATA0" */
6809 /* NI0 compare NI input expected data0 */
6810 /* ==================================================================== */
6812 typedef union sh_xn_ni0_ni_cmp_exp_data0_u {
6813 mmr_t sh_xn_ni0_ni_cmp_exp_data0_regval;
6816 } sh_xn_ni0_ni_cmp_exp_data0_s;
6817 } sh_xn_ni0_ni_cmp_exp_data0_u_t;
6819 /* ==================================================================== */
6820 /* Register "SH_XN_NI0_NI_CMP_EXP_DATA1" */
6821 /* NI0 compare NI input expected data1 */
6822 /* ==================================================================== */
6824 typedef union sh_xn_ni0_ni_cmp_exp_data1_u {
6825 mmr_t sh_xn_ni0_ni_cmp_exp_data1_regval;
6828 } sh_xn_ni0_ni_cmp_exp_data1_s;
6829 } sh_xn_ni0_ni_cmp_exp_data1_u_t;
6831 /* ==================================================================== */
6832 /* Register "SH_XN_NI0_NI_CMP_ENABLE0" */
6833 /* NI0 compare NI input enable0 */
6834 /* ==================================================================== */
6836 typedef union sh_xn_ni0_ni_cmp_enable0_u {
6837 mmr_t sh_xn_ni0_ni_cmp_enable0_regval;
6840 } sh_xn_ni0_ni_cmp_enable0_s;
6841 } sh_xn_ni0_ni_cmp_enable0_u_t;
6843 /* ==================================================================== */
6844 /* Register "SH_XN_NI0_NI_CMP_ENABLE1" */
6845 /* NI0 compare NI input enable1 */
6846 /* ==================================================================== */
6848 typedef union sh_xn_ni0_ni_cmp_enable1_u {
6849 mmr_t sh_xn_ni0_ni_cmp_enable1_regval;
6852 } sh_xn_ni0_ni_cmp_enable1_s;
6853 } sh_xn_ni0_ni_cmp_enable1_u_t;
6855 /* ==================================================================== */
6856 /* Register "SH_XN_NI0_LLP_CMP_EXP_DATA0" */
6857 /* NI0 compare LLP input expected data0 */
6858 /* ==================================================================== */
6860 typedef union sh_xn_ni0_llp_cmp_exp_data0_u {
6861 mmr_t sh_xn_ni0_llp_cmp_exp_data0_regval;
6864 } sh_xn_ni0_llp_cmp_exp_data0_s;
6865 } sh_xn_ni0_llp_cmp_exp_data0_u_t;
6867 /* ==================================================================== */
6868 /* Register "SH_XN_NI0_LLP_CMP_EXP_DATA1" */
6869 /* NI0 compare LLP input expected data1 */
6870 /* ==================================================================== */
6872 typedef union sh_xn_ni0_llp_cmp_exp_data1_u {
6873 mmr_t sh_xn_ni0_llp_cmp_exp_data1_regval;
6876 } sh_xn_ni0_llp_cmp_exp_data1_s;
6877 } sh_xn_ni0_llp_cmp_exp_data1_u_t;
6879 /* ==================================================================== */
6880 /* Register "SH_XN_NI0_LLP_CMP_ENABLE0" */
6881 /* NI0 compare LLP input enable0 */
6882 /* ==================================================================== */
6884 typedef union sh_xn_ni0_llp_cmp_enable0_u {
6885 mmr_t sh_xn_ni0_llp_cmp_enable0_regval;
6888 } sh_xn_ni0_llp_cmp_enable0_s;
6889 } sh_xn_ni0_llp_cmp_enable0_u_t;
6891 /* ==================================================================== */
6892 /* Register "SH_XN_NI0_LLP_CMP_ENABLE1" */
6893 /* NI0 compare LLP input enable1 */
6894 /* ==================================================================== */
6896 typedef union sh_xn_ni0_llp_cmp_enable1_u {
6897 mmr_t sh_xn_ni0_llp_cmp_enable1_regval;
6900 } sh_xn_ni0_llp_cmp_enable1_s;
6901 } sh_xn_ni0_llp_cmp_enable1_u_t;
6903 /* ==================================================================== */
6904 /* Register "SH_XN_NI1_IILB_CMP_EXP_DATA0" */
6905 /* NI1 compare IILB input expected data0 */
6906 /* ==================================================================== */
6908 typedef union sh_xn_ni1_iilb_cmp_exp_data0_u {
6909 mmr_t sh_xn_ni1_iilb_cmp_exp_data0_regval;
6912 } sh_xn_ni1_iilb_cmp_exp_data0_s;
6913 } sh_xn_ni1_iilb_cmp_exp_data0_u_t;
6915 /* ==================================================================== */
6916 /* Register "SH_XN_NI1_IILB_CMP_EXP_DATA1" */
6917 /* NI1 compare IILB input expected data1 */
6918 /* ==================================================================== */
6920 typedef union sh_xn_ni1_iilb_cmp_exp_data1_u {
6921 mmr_t sh_xn_ni1_iilb_cmp_exp_data1_regval;
6924 } sh_xn_ni1_iilb_cmp_exp_data1_s;
6925 } sh_xn_ni1_iilb_cmp_exp_data1_u_t;
6927 /* ==================================================================== */
6928 /* Register "SH_XN_NI1_IILB_CMP_ENABLE0" */
6929 /* NI1 compare IILB input enable0 */
6930 /* ==================================================================== */
6932 typedef union sh_xn_ni1_iilb_cmp_enable0_u {
6933 mmr_t sh_xn_ni1_iilb_cmp_enable0_regval;
6936 } sh_xn_ni1_iilb_cmp_enable0_s;
6937 } sh_xn_ni1_iilb_cmp_enable0_u_t;
6939 /* ==================================================================== */
6940 /* Register "SH_XN_NI1_IILB_CMP_ENABLE1" */
6941 /* NI1 compare IILB input enable1 */
6942 /* ==================================================================== */
6944 typedef union sh_xn_ni1_iilb_cmp_enable1_u {
6945 mmr_t sh_xn_ni1_iilb_cmp_enable1_regval;
6948 } sh_xn_ni1_iilb_cmp_enable1_s;
6949 } sh_xn_ni1_iilb_cmp_enable1_u_t;
6951 /* ==================================================================== */
6952 /* Register "SH_XN_NI1_PI_CMP_EXP_DATA0" */
6953 /* NI1 compare PI input expected data0 */
6954 /* ==================================================================== */
6956 typedef union sh_xn_ni1_pi_cmp_exp_data0_u {
6957 mmr_t sh_xn_ni1_pi_cmp_exp_data0_regval;
6960 } sh_xn_ni1_pi_cmp_exp_data0_s;
6961 } sh_xn_ni1_pi_cmp_exp_data0_u_t;
6963 /* ==================================================================== */
6964 /* Register "SH_XN_NI1_PI_CMP_EXP_DATA1" */
6965 /* NI1 compare PI input expected data1 */
6966 /* ==================================================================== */
6968 typedef union sh_xn_ni1_pi_cmp_exp_data1_u {
6969 mmr_t sh_xn_ni1_pi_cmp_exp_data1_regval;
6972 } sh_xn_ni1_pi_cmp_exp_data1_s;
6973 } sh_xn_ni1_pi_cmp_exp_data1_u_t;
6975 /* ==================================================================== */
6976 /* Register "SH_XN_NI1_PI_CMP_ENABLE0" */
6977 /* NI1 compare PI input enable0 */
6978 /* ==================================================================== */
6980 typedef union sh_xn_ni1_pi_cmp_enable0_u {
6981 mmr_t sh_xn_ni1_pi_cmp_enable0_regval;
6984 } sh_xn_ni1_pi_cmp_enable0_s;
6985 } sh_xn_ni1_pi_cmp_enable0_u_t;
6987 /* ==================================================================== */
6988 /* Register "SH_XN_NI1_PI_CMP_ENABLE1" */
6989 /* NI1 compare PI input enable1 */
6990 /* ==================================================================== */
6992 typedef union sh_xn_ni1_pi_cmp_enable1_u {
6993 mmr_t sh_xn_ni1_pi_cmp_enable1_regval;
6996 } sh_xn_ni1_pi_cmp_enable1_s;
6997 } sh_xn_ni1_pi_cmp_enable1_u_t;
6999 /* ==================================================================== */
7000 /* Register "SH_XN_NI1_MD_CMP_EXP_DATA0" */
7001 /* NI1 compare MD input expected data0 */
7002 /* ==================================================================== */
7004 typedef union sh_xn_ni1_md_cmp_exp_data0_u {
7005 mmr_t sh_xn_ni1_md_cmp_exp_data0_regval;
7008 } sh_xn_ni1_md_cmp_exp_data0_s;
7009 } sh_xn_ni1_md_cmp_exp_data0_u_t;
7011 /* ==================================================================== */
7012 /* Register "SH_XN_NI1_MD_CMP_EXP_DATA1" */
7013 /* NI1 compare MD input expected data1 */
7014 /* ==================================================================== */
7016 typedef union sh_xn_ni1_md_cmp_exp_data1_u {
7017 mmr_t sh_xn_ni1_md_cmp_exp_data1_regval;
7020 } sh_xn_ni1_md_cmp_exp_data1_s;
7021 } sh_xn_ni1_md_cmp_exp_data1_u_t;
7023 /* ==================================================================== */
7024 /* Register "SH_XN_NI1_MD_CMP_ENABLE0" */
7025 /* NI1 compare MD input enable0 */
7026 /* ==================================================================== */
7028 typedef union sh_xn_ni1_md_cmp_enable0_u {
7029 mmr_t sh_xn_ni1_md_cmp_enable0_regval;
7032 } sh_xn_ni1_md_cmp_enable0_s;
7033 } sh_xn_ni1_md_cmp_enable0_u_t;
7035 /* ==================================================================== */
7036 /* Register "SH_XN_NI1_MD_CMP_ENABLE1" */
7037 /* NI1 compare MD input enable1 */
7038 /* ==================================================================== */
7040 typedef union sh_xn_ni1_md_cmp_enable1_u {
7041 mmr_t sh_xn_ni1_md_cmp_enable1_regval;
7044 } sh_xn_ni1_md_cmp_enable1_s;
7045 } sh_xn_ni1_md_cmp_enable1_u_t;
7047 /* ==================================================================== */
7048 /* Register "SH_XN_NI1_NI_CMP_EXP_DATA0" */
7049 /* NI1 compare NI input expected data0 */
7050 /* ==================================================================== */
7052 typedef union sh_xn_ni1_ni_cmp_exp_data0_u {
7053 mmr_t sh_xn_ni1_ni_cmp_exp_data0_regval;
7056 } sh_xn_ni1_ni_cmp_exp_data0_s;
7057 } sh_xn_ni1_ni_cmp_exp_data0_u_t;
7059 /* ==================================================================== */
7060 /* Register "SH_XN_NI1_NI_CMP_EXP_DATA1" */
7061 /* NI1 compare NI input expected data1 */
7062 /* ==================================================================== */
7064 typedef union sh_xn_ni1_ni_cmp_exp_data1_u {
7065 mmr_t sh_xn_ni1_ni_cmp_exp_data1_regval;
7068 } sh_xn_ni1_ni_cmp_exp_data1_s;
7069 } sh_xn_ni1_ni_cmp_exp_data1_u_t;
7071 /* ==================================================================== */
7072 /* Register "SH_XN_NI1_NI_CMP_ENABLE0" */
7073 /* NI1 compare NI input enable0 */
7074 /* ==================================================================== */
7076 typedef union sh_xn_ni1_ni_cmp_enable0_u {
7077 mmr_t sh_xn_ni1_ni_cmp_enable0_regval;
7080 } sh_xn_ni1_ni_cmp_enable0_s;
7081 } sh_xn_ni1_ni_cmp_enable0_u_t;
7083 /* ==================================================================== */
7084 /* Register "SH_XN_NI1_NI_CMP_ENABLE1" */
7085 /* NI1 compare NI input enable1 */
7086 /* ==================================================================== */
7088 typedef union sh_xn_ni1_ni_cmp_enable1_u {
7089 mmr_t sh_xn_ni1_ni_cmp_enable1_regval;
7092 } sh_xn_ni1_ni_cmp_enable1_s;
7093 } sh_xn_ni1_ni_cmp_enable1_u_t;
7095 /* ==================================================================== */
7096 /* Register "SH_XN_NI1_LLP_CMP_EXP_DATA0" */
7097 /* NI1 compare LLP input expected data0 */
7098 /* ==================================================================== */
7100 typedef union sh_xn_ni1_llp_cmp_exp_data0_u {
7101 mmr_t sh_xn_ni1_llp_cmp_exp_data0_regval;
7104 } sh_xn_ni1_llp_cmp_exp_data0_s;
7105 } sh_xn_ni1_llp_cmp_exp_data0_u_t;
7107 /* ==================================================================== */
7108 /* Register "SH_XN_NI1_LLP_CMP_EXP_DATA1" */
7109 /* NI1 compare LLP input expected data1 */
7110 /* ==================================================================== */
7112 typedef union sh_xn_ni1_llp_cmp_exp_data1_u {
7113 mmr_t sh_xn_ni1_llp_cmp_exp_data1_regval;
7116 } sh_xn_ni1_llp_cmp_exp_data1_s;
7117 } sh_xn_ni1_llp_cmp_exp_data1_u_t;
7119 /* ==================================================================== */
7120 /* Register "SH_XN_NI1_LLP_CMP_ENABLE0" */
7121 /* NI1 compare LLP input enable0 */
7122 /* ==================================================================== */
7124 typedef union sh_xn_ni1_llp_cmp_enable0_u {
7125 mmr_t sh_xn_ni1_llp_cmp_enable0_regval;
7128 } sh_xn_ni1_llp_cmp_enable0_s;
7129 } sh_xn_ni1_llp_cmp_enable0_u_t;
7131 /* ==================================================================== */
7132 /* Register "SH_XN_NI1_LLP_CMP_ENABLE1" */
7133 /* NI1 compare LLP input enable1 */
7134 /* ==================================================================== */
7136 typedef union sh_xn_ni1_llp_cmp_enable1_u {
7137 mmr_t sh_xn_ni1_llp_cmp_enable1_regval;
7140 } sh_xn_ni1_llp_cmp_enable1_s;
7141 } sh_xn_ni1_llp_cmp_enable1_u_t;
7143 /* ==================================================================== */
7144 /* Register "SH_XNPI_ECC_INJ_REG" */
7145 /* ==================================================================== */
7147 typedef union sh_xnpi_ecc_inj_reg_u {
7148 mmr_t sh_xnpi_ecc_inj_reg_regval;
7151 mmr_t reserved_0 : 4;
7152 mmr_t data_1shot0 : 1;
7153 mmr_t data_cont0 : 1;
7154 mmr_t data_cb_1shot0 : 1;
7155 mmr_t data_cb_cont0 : 1;
7157 mmr_t reserved_1 : 4;
7158 mmr_t data_1shot1 : 1;
7159 mmr_t data_cont1 : 1;
7160 mmr_t data_cb_1shot1 : 1;
7161 mmr_t data_cb_cont1 : 1;
7163 mmr_t reserved_2 : 4;
7164 mmr_t data_1shot2 : 1;
7165 mmr_t data_cont2 : 1;
7166 mmr_t data_cb_1shot2 : 1;
7167 mmr_t data_cb_cont2 : 1;
7169 mmr_t reserved_3 : 4;
7170 mmr_t data_1shot3 : 1;
7171 mmr_t data_cont3 : 1;
7172 mmr_t data_cb_1shot3 : 1;
7173 mmr_t data_cb_cont3 : 1;
7174 } sh_xnpi_ecc_inj_reg_s;
7175 } sh_xnpi_ecc_inj_reg_u_t;
7177 /* ==================================================================== */
7178 /* Register "SH_XNPI_ECC0_INJ_MASK_REG" */
7179 /* ==================================================================== */
7181 typedef union sh_xnpi_ecc0_inj_mask_reg_u {
7182 mmr_t sh_xnpi_ecc0_inj_mask_reg_regval;
7184 mmr_t mask_ecc0 : 64;
7185 } sh_xnpi_ecc0_inj_mask_reg_s;
7186 } sh_xnpi_ecc0_inj_mask_reg_u_t;
7188 /* ==================================================================== */
7189 /* Register "SH_XNPI_ECC1_INJ_MASK_REG" */
7190 /* ==================================================================== */
7192 typedef union sh_xnpi_ecc1_inj_mask_reg_u {
7193 mmr_t sh_xnpi_ecc1_inj_mask_reg_regval;
7195 mmr_t mask_ecc1 : 64;
7196 } sh_xnpi_ecc1_inj_mask_reg_s;
7197 } sh_xnpi_ecc1_inj_mask_reg_u_t;
7199 /* ==================================================================== */
7200 /* Register "SH_XNPI_ECC2_INJ_MASK_REG" */
7201 /* ==================================================================== */
7203 typedef union sh_xnpi_ecc2_inj_mask_reg_u {
7204 mmr_t sh_xnpi_ecc2_inj_mask_reg_regval;
7206 mmr_t mask_ecc2 : 64;
7207 } sh_xnpi_ecc2_inj_mask_reg_s;
7208 } sh_xnpi_ecc2_inj_mask_reg_u_t;
7210 /* ==================================================================== */
7211 /* Register "SH_XNPI_ECC3_INJ_MASK_REG" */
7212 /* ==================================================================== */
7214 typedef union sh_xnpi_ecc3_inj_mask_reg_u {
7215 mmr_t sh_xnpi_ecc3_inj_mask_reg_regval;
7217 mmr_t mask_ecc3 : 64;
7218 } sh_xnpi_ecc3_inj_mask_reg_s;
7219 } sh_xnpi_ecc3_inj_mask_reg_u_t;
7221 /* ==================================================================== */
7222 /* Register "SH_XNMD_ECC_INJ_REG" */
7223 /* ==================================================================== */
7225 typedef union sh_xnmd_ecc_inj_reg_u {
7226 mmr_t sh_xnmd_ecc_inj_reg_regval;
7229 mmr_t reserved_0 : 4;
7230 mmr_t data_1shot0 : 1;
7231 mmr_t data_cont0 : 1;
7232 mmr_t data_cb_1shot0 : 1;
7233 mmr_t data_cb_cont0 : 1;
7235 mmr_t reserved_1 : 4;
7236 mmr_t data_1shot1 : 1;
7237 mmr_t data_cont1 : 1;
7238 mmr_t data_cb_1shot1 : 1;
7239 mmr_t data_cb_cont1 : 1;
7241 mmr_t reserved_2 : 4;
7242 mmr_t data_1shot2 : 1;
7243 mmr_t data_cont2 : 1;
7244 mmr_t data_cb_1shot2 : 1;
7245 mmr_t data_cb_cont2 : 1;
7247 mmr_t reserved_3 : 4;
7248 mmr_t data_1shot3 : 1;
7249 mmr_t data_cont3 : 1;
7250 mmr_t data_cb_1shot3 : 1;
7251 mmr_t data_cb_cont3 : 1;
7252 } sh_xnmd_ecc_inj_reg_s;
7253 } sh_xnmd_ecc_inj_reg_u_t;
7255 /* ==================================================================== */
7256 /* Register "SH_XNMD_ECC0_INJ_MASK_REG" */
7257 /* ==================================================================== */
7259 typedef union sh_xnmd_ecc0_inj_mask_reg_u {
7260 mmr_t sh_xnmd_ecc0_inj_mask_reg_regval;
7262 mmr_t mask_ecc0 : 64;
7263 } sh_xnmd_ecc0_inj_mask_reg_s;
7264 } sh_xnmd_ecc0_inj_mask_reg_u_t;
7266 /* ==================================================================== */
7267 /* Register "SH_XNMD_ECC1_INJ_MASK_REG" */
7268 /* ==================================================================== */
7270 typedef union sh_xnmd_ecc1_inj_mask_reg_u {
7271 mmr_t sh_xnmd_ecc1_inj_mask_reg_regval;
7273 mmr_t mask_ecc1 : 64;
7274 } sh_xnmd_ecc1_inj_mask_reg_s;
7275 } sh_xnmd_ecc1_inj_mask_reg_u_t;
7277 /* ==================================================================== */
7278 /* Register "SH_XNMD_ECC2_INJ_MASK_REG" */
7279 /* ==================================================================== */
7281 typedef union sh_xnmd_ecc2_inj_mask_reg_u {
7282 mmr_t sh_xnmd_ecc2_inj_mask_reg_regval;
7284 mmr_t mask_ecc2 : 64;
7285 } sh_xnmd_ecc2_inj_mask_reg_s;
7286 } sh_xnmd_ecc2_inj_mask_reg_u_t;
7288 /* ==================================================================== */
7289 /* Register "SH_XNMD_ECC3_INJ_MASK_REG" */
7290 /* ==================================================================== */
7292 typedef union sh_xnmd_ecc3_inj_mask_reg_u {
7293 mmr_t sh_xnmd_ecc3_inj_mask_reg_regval;
7295 mmr_t mask_ecc3 : 64;
7296 } sh_xnmd_ecc3_inj_mask_reg_s;
7297 } sh_xnmd_ecc3_inj_mask_reg_u_t;
7299 /* ==================================================================== */
7300 /* Register "SH_XNMD_ECC_ERR_REPORT" */
7301 /* ==================================================================== */
7303 typedef union sh_xnmd_ecc_err_report_u {
7304 mmr_t sh_xnmd_ecc_err_report_regval;
7306 mmr_t ecc_disable0 : 1;
7307 mmr_t reserved_0 : 15;
7308 mmr_t ecc_disable1 : 1;
7309 mmr_t reserved_1 : 15;
7310 mmr_t ecc_disable2 : 1;
7311 mmr_t reserved_2 : 15;
7312 mmr_t ecc_disable3 : 1;
7313 mmr_t reserved_3 : 15;
7314 } sh_xnmd_ecc_err_report_s;
7315 } sh_xnmd_ecc_err_report_u_t;
7317 /* ==================================================================== */
7318 /* Register "SH_NI0_ERROR_SUMMARY_1" */
7319 /* ni0 Error Summary Bits */
7320 /* ==================================================================== */
7322 typedef union sh_ni0_error_summary_1_u {
7323 mmr_t sh_ni0_error_summary_1_regval;
7325 mmr_t overflow_fifo02_debit0 : 1;
7326 mmr_t overflow_fifo02_debit2 : 1;
7327 mmr_t overflow_fifo13_debit0 : 1;
7328 mmr_t overflow_fifo13_debit2 : 1;
7329 mmr_t overflow_fifo02_vc0_pop : 1;
7330 mmr_t overflow_fifo02_vc2_pop : 1;
7331 mmr_t overflow_fifo13_vc1_pop : 1;
7332 mmr_t overflow_fifo13_vc3_pop : 1;
7333 mmr_t overflow_fifo02_vc0_push : 1;
7334 mmr_t overflow_fifo02_vc2_push : 1;
7335 mmr_t overflow_fifo13_vc1_push : 1;
7336 mmr_t overflow_fifo13_vc3_push : 1;
7337 mmr_t overflow_fifo02_vc0_credit : 1;
7338 mmr_t overflow_fifo02_vc2_credit : 1;
7339 mmr_t overflow_fifo13_vc0_credit : 1;
7340 mmr_t overflow_fifo13_vc2_credit : 1;
7341 mmr_t overflow0_vc0_credit : 1;
7342 mmr_t overflow1_vc0_credit : 1;
7343 mmr_t overflow2_vc0_credit : 1;
7344 mmr_t overflow0_vc2_credit : 1;
7345 mmr_t overflow1_vc2_credit : 1;
7346 mmr_t overflow2_vc2_credit : 1;
7347 mmr_t overflow_pi_fifo_debit0 : 1;
7348 mmr_t overflow_pi_fifo_debit2 : 1;
7349 mmr_t overflow_iilb_fifo_debit0 : 1;
7350 mmr_t overflow_iilb_fifo_debit2 : 1;
7351 mmr_t overflow_md_fifo_debit0 : 1;
7352 mmr_t overflow_md_fifo_debit2 : 1;
7353 mmr_t overflow_ni_fifo_debit0 : 1;
7354 mmr_t overflow_ni_fifo_debit1 : 1;
7355 mmr_t overflow_ni_fifo_debit2 : 1;
7356 mmr_t overflow_ni_fifo_debit3 : 1;
7357 mmr_t overflow_pi_fifo_vc0_pop : 1;
7358 mmr_t overflow_pi_fifo_vc2_pop : 1;
7359 mmr_t overflow_iilb_fifo_vc0_pop : 1;
7360 mmr_t overflow_iilb_fifo_vc2_pop : 1;
7361 mmr_t overflow_md_fifo_vc0_pop : 1;
7362 mmr_t overflow_md_fifo_vc2_pop : 1;
7363 mmr_t overflow_ni_fifo_vc0_pop : 1;
7364 mmr_t overflow_ni_fifo_vc2_pop : 1;
7365 mmr_t overflow_pi_fifo_vc0_push : 1;
7366 mmr_t overflow_pi_fifo_vc2_push : 1;
7367 mmr_t overflow_iilb_fifo_vc0_push : 1;
7368 mmr_t overflow_iilb_fifo_vc2_push : 1;
7369 mmr_t overflow_md_fifo_vc0_push : 1;
7370 mmr_t overflow_md_fifo_vc2_push : 1;
7371 mmr_t overflow_pi_fifo_vc0_credit : 1;
7372 mmr_t overflow_pi_fifo_vc2_credit : 1;
7373 mmr_t overflow_iilb_fifo_vc0_credit : 1;
7374 mmr_t overflow_iilb_fifo_vc2_credit : 1;
7375 mmr_t overflow_md_fifo_vc0_credit : 1;
7376 mmr_t overflow_md_fifo_vc2_credit : 1;
7377 mmr_t overflow_ni_fifo_vc0_credit : 1;
7378 mmr_t overflow_ni_fifo_vc1_credit : 1;
7379 mmr_t overflow_ni_fifo_vc2_credit : 1;
7380 mmr_t overflow_ni_fifo_vc3_credit : 1;
7381 mmr_t tail_timeout_fifo02_vc0 : 1;
7382 mmr_t tail_timeout_fifo02_vc2 : 1;
7383 mmr_t tail_timeout_fifo13_vc1 : 1;
7384 mmr_t tail_timeout_fifo13_vc3 : 1;
7385 mmr_t tail_timeout_ni_vc0 : 1;
7386 mmr_t tail_timeout_ni_vc1 : 1;
7387 mmr_t tail_timeout_ni_vc2 : 1;
7388 mmr_t tail_timeout_ni_vc3 : 1;
7389 } sh_ni0_error_summary_1_s;
7390 } sh_ni0_error_summary_1_u_t;
7392 /* ==================================================================== */
7393 /* Register "SH_NI0_ERROR_SUMMARY_2" */
7394 /* ni0 Error Summary Bits */
7395 /* ==================================================================== */
7397 typedef union sh_ni0_error_summary_2_u {
7398 mmr_t sh_ni0_error_summary_2_regval;
7400 mmr_t illegal_vcni : 1;
7401 mmr_t illegal_vcpi : 1;
7402 mmr_t illegal_vcmd : 1;
7403 mmr_t illegal_vciilb : 1;
7404 mmr_t underflow_fifo02_vc0_pop : 1;
7405 mmr_t underflow_fifo02_vc2_pop : 1;
7406 mmr_t underflow_fifo13_vc1_pop : 1;
7407 mmr_t underflow_fifo13_vc3_pop : 1;
7408 mmr_t underflow_fifo02_vc0_push : 1;
7409 mmr_t underflow_fifo02_vc2_push : 1;
7410 mmr_t underflow_fifo13_vc1_push : 1;
7411 mmr_t underflow_fifo13_vc3_push : 1;
7412 mmr_t underflow_fifo02_vc0_credit : 1;
7413 mmr_t underflow_fifo02_vc2_credit : 1;
7414 mmr_t underflow_fifo13_vc0_credit : 1;
7415 mmr_t underflow_fifo13_vc2_credit : 1;
7416 mmr_t underflow0_vc0_credit : 1;
7417 mmr_t underflow1_vc0_credit : 1;
7418 mmr_t underflow2_vc0_credit : 1;
7419 mmr_t underflow0_vc2_credit : 1;
7420 mmr_t underflow1_vc2_credit : 1;
7421 mmr_t underflow2_vc2_credit : 1;
7422 mmr_t reserved_0 : 10;
7423 mmr_t underflow_pi_fifo_vc0_pop : 1;
7424 mmr_t underflow_pi_fifo_vc2_pop : 1;
7425 mmr_t underflow_iilb_fifo_vc0_pop : 1;
7426 mmr_t underflow_iilb_fifo_vc2_pop : 1;
7427 mmr_t underflow_md_fifo_vc0_pop : 1;
7428 mmr_t underflow_md_fifo_vc2_pop : 1;
7429 mmr_t underflow_ni_fifo_vc0_pop : 1;
7430 mmr_t underflow_ni_fifo_vc2_pop : 1;
7431 mmr_t underflow_pi_fifo_vc0_push : 1;
7432 mmr_t underflow_pi_fifo_vc2_push : 1;
7433 mmr_t underflow_iilb_fifo_vc0_push : 1;
7434 mmr_t underflow_iilb_fifo_vc2_push : 1;
7435 mmr_t underflow_md_fifo_vc0_push : 1;
7436 mmr_t underflow_md_fifo_vc2_push : 1;
7437 mmr_t underflow_pi_fifo_vc0_credit : 1;
7438 mmr_t underflow_pi_fifo_vc2_credit : 1;
7439 mmr_t underflow_iilb_fifo_vc0_credit : 1;
7440 mmr_t underflow_iilb_fifo_vc2_credit : 1;
7441 mmr_t underflow_md_fifo_vc0_credit : 1;
7442 mmr_t underflow_md_fifo_vc2_credit : 1;
7443 mmr_t underflow_ni_fifo_vc0_credit : 1;
7444 mmr_t underflow_ni_fifo_vc1_credit : 1;
7445 mmr_t underflow_ni_fifo_vc2_credit : 1;
7446 mmr_t underflow_ni_fifo_vc3_credit : 1;
7447 mmr_t llp_deadlock_vc0 : 1;
7448 mmr_t llp_deadlock_vc1 : 1;
7449 mmr_t llp_deadlock_vc2 : 1;
7450 mmr_t llp_deadlock_vc3 : 1;
7451 mmr_t chiplet_nomatch : 1;
7452 mmr_t lut_read_error : 1;
7453 mmr_t retry_timeout_error : 1;
7454 mmr_t reserved_1 : 1;
7455 } sh_ni0_error_summary_2_s;
7456 } sh_ni0_error_summary_2_u_t;
7458 /* ==================================================================== */
7459 /* Register "SH_NI0_ERROR_OVERFLOW_1" */
7460 /* ni0 Error Overflow Bits */
7461 /* ==================================================================== */
7463 typedef union sh_ni0_error_overflow_1_u {
7464 mmr_t sh_ni0_error_overflow_1_regval;
7466 mmr_t overflow_fifo02_debit0 : 1;
7467 mmr_t overflow_fifo02_debit2 : 1;
7468 mmr_t overflow_fifo13_debit0 : 1;
7469 mmr_t overflow_fifo13_debit2 : 1;
7470 mmr_t overflow_fifo02_vc0_pop : 1;
7471 mmr_t overflow_fifo02_vc2_pop : 1;
7472 mmr_t overflow_fifo13_vc1_pop : 1;
7473 mmr_t overflow_fifo13_vc3_pop : 1;
7474 mmr_t overflow_fifo02_vc0_push : 1;
7475 mmr_t overflow_fifo02_vc2_push : 1;
7476 mmr_t overflow_fifo13_vc1_push : 1;
7477 mmr_t overflow_fifo13_vc3_push : 1;
7478 mmr_t overflow_fifo02_vc0_credit : 1;
7479 mmr_t overflow_fifo02_vc2_credit : 1;
7480 mmr_t overflow_fifo13_vc0_credit : 1;
7481 mmr_t overflow_fifo13_vc2_credit : 1;
7482 mmr_t overflow0_vc0_credit : 1;
7483 mmr_t overflow1_vc0_credit : 1;
7484 mmr_t overflow2_vc0_credit : 1;
7485 mmr_t overflow0_vc2_credit : 1;
7486 mmr_t overflow1_vc2_credit : 1;
7487 mmr_t overflow2_vc2_credit : 1;
7488 mmr_t overflow_pi_fifo_debit0 : 1;
7489 mmr_t overflow_pi_fifo_debit2 : 1;
7490 mmr_t overflow_iilb_fifo_debit0 : 1;
7491 mmr_t overflow_iilb_fifo_debit2 : 1;
7492 mmr_t overflow_md_fifo_debit0 : 1;
7493 mmr_t overflow_md_fifo_debit2 : 1;
7494 mmr_t overflow_ni_fifo_debit0 : 1;
7495 mmr_t overflow_ni_fifo_debit1 : 1;
7496 mmr_t overflow_ni_fifo_debit2 : 1;
7497 mmr_t overflow_ni_fifo_debit3 : 1;
7498 mmr_t overflow_pi_fifo_vc0_pop : 1;
7499 mmr_t overflow_pi_fifo_vc2_pop : 1;
7500 mmr_t overflow_iilb_fifo_vc0_pop : 1;
7501 mmr_t overflow_iilb_fifo_vc2_pop : 1;
7502 mmr_t overflow_md_fifo_vc0_pop : 1;
7503 mmr_t overflow_md_fifo_vc2_pop : 1;
7504 mmr_t overflow_ni_fifo_vc0_pop : 1;
7505 mmr_t overflow_ni_fifo_vc2_pop : 1;
7506 mmr_t overflow_pi_fifo_vc0_push : 1;
7507 mmr_t overflow_pi_fifo_vc2_push : 1;
7508 mmr_t overflow_iilb_fifo_vc0_push : 1;
7509 mmr_t overflow_iilb_fifo_vc2_push : 1;
7510 mmr_t overflow_md_fifo_vc0_push : 1;
7511 mmr_t overflow_md_fifo_vc2_push : 1;
7512 mmr_t overflow_pi_fifo_vc0_credit : 1;
7513 mmr_t overflow_pi_fifo_vc2_credit : 1;
7514 mmr_t overflow_iilb_fifo_vc0_credit : 1;
7515 mmr_t overflow_iilb_fifo_vc2_credit : 1;
7516 mmr_t overflow_md_fifo_vc0_credit : 1;
7517 mmr_t overflow_md_fifo_vc2_credit : 1;
7518 mmr_t overflow_ni_fifo_vc0_credit : 1;
7519 mmr_t overflow_ni_fifo_vc1_credit : 1;
7520 mmr_t overflow_ni_fifo_vc2_credit : 1;
7521 mmr_t overflow_ni_fifo_vc3_credit : 1;
7522 mmr_t tail_timeout_fifo02_vc0 : 1;
7523 mmr_t tail_timeout_fifo02_vc2 : 1;
7524 mmr_t tail_timeout_fifo13_vc1 : 1;
7525 mmr_t tail_timeout_fifo13_vc3 : 1;
7526 mmr_t tail_timeout_ni_vc0 : 1;
7527 mmr_t tail_timeout_ni_vc1 : 1;
7528 mmr_t tail_timeout_ni_vc2 : 1;
7529 mmr_t tail_timeout_ni_vc3 : 1;
7530 } sh_ni0_error_overflow_1_s;
7531 } sh_ni0_error_overflow_1_u_t;
7533 /* ==================================================================== */
7534 /* Register "SH_NI0_ERROR_OVERFLOW_2" */
7535 /* ni0 Error Overflow Bits */
7536 /* ==================================================================== */
7538 typedef union sh_ni0_error_overflow_2_u {
7539 mmr_t sh_ni0_error_overflow_2_regval;
7541 mmr_t illegal_vcni : 1;
7542 mmr_t illegal_vcpi : 1;
7543 mmr_t illegal_vcmd : 1;
7544 mmr_t illegal_vciilb : 1;
7545 mmr_t underflow_fifo02_vc0_pop : 1;
7546 mmr_t underflow_fifo02_vc2_pop : 1;
7547 mmr_t underflow_fifo13_vc1_pop : 1;
7548 mmr_t underflow_fifo13_vc3_pop : 1;
7549 mmr_t underflow_fifo02_vc0_push : 1;
7550 mmr_t underflow_fifo02_vc2_push : 1;
7551 mmr_t underflow_fifo13_vc1_push : 1;
7552 mmr_t underflow_fifo13_vc3_push : 1;
7553 mmr_t underflow_fifo02_vc0_credit : 1;
7554 mmr_t underflow_fifo02_vc2_credit : 1;
7555 mmr_t underflow_fifo13_vc0_credit : 1;
7556 mmr_t underflow_fifo13_vc2_credit : 1;
7557 mmr_t underflow0_vc0_credit : 1;
7558 mmr_t underflow1_vc0_credit : 1;
7559 mmr_t underflow2_vc0_credit : 1;
7560 mmr_t underflow0_vc2_credit : 1;
7561 mmr_t underflow1_vc2_credit : 1;
7562 mmr_t underflow2_vc2_credit : 1;
7563 mmr_t reserved_0 : 10;
7564 mmr_t underflow_pi_fifo_vc0_pop : 1;
7565 mmr_t underflow_pi_fifo_vc2_pop : 1;
7566 mmr_t underflow_iilb_fifo_vc0_pop : 1;
7567 mmr_t underflow_iilb_fifo_vc2_pop : 1;
7568 mmr_t underflow_md_fifo_vc0_pop : 1;
7569 mmr_t underflow_md_fifo_vc2_pop : 1;
7570 mmr_t underflow_ni_fifo_vc0_pop : 1;
7571 mmr_t underflow_ni_fifo_vc2_pop : 1;
7572 mmr_t underflow_pi_fifo_vc0_push : 1;
7573 mmr_t underflow_pi_fifo_vc2_push : 1;
7574 mmr_t underflow_iilb_fifo_vc0_push : 1;
7575 mmr_t underflow_iilb_fifo_vc2_push : 1;
7576 mmr_t underflow_md_fifo_vc0_push : 1;
7577 mmr_t underflow_md_fifo_vc2_push : 1;
7578 mmr_t underflow_pi_fifo_vc0_credit : 1;
7579 mmr_t underflow_pi_fifo_vc2_credit : 1;
7580 mmr_t underflow_iilb_fifo_vc0_credit : 1;
7581 mmr_t underflow_iilb_fifo_vc2_credit : 1;
7582 mmr_t underflow_md_fifo_vc0_credit : 1;
7583 mmr_t underflow_md_fifo_vc2_credit : 1;
7584 mmr_t underflow_ni_fifo_vc0_credit : 1;
7585 mmr_t underflow_ni_fifo_vc1_credit : 1;
7586 mmr_t underflow_ni_fifo_vc2_credit : 1;
7587 mmr_t underflow_ni_fifo_vc3_credit : 1;
7588 mmr_t llp_deadlock_vc0 : 1;
7589 mmr_t llp_deadlock_vc1 : 1;
7590 mmr_t llp_deadlock_vc2 : 1;
7591 mmr_t llp_deadlock_vc3 : 1;
7592 mmr_t chiplet_nomatch : 1;
7593 mmr_t lut_read_error : 1;
7594 mmr_t retry_timeout_error : 1;
7595 mmr_t reserved_1 : 1;
7596 } sh_ni0_error_overflow_2_s;
7597 } sh_ni0_error_overflow_2_u_t;
7599 /* ==================================================================== */
7600 /* Register "SH_NI0_ERROR_MASK_1" */
7601 /* ni0 Error Mask Bits */
7602 /* ==================================================================== */
7604 typedef union sh_ni0_error_mask_1_u {
7605 mmr_t sh_ni0_error_mask_1_regval;
7607 mmr_t overflow_fifo02_debit0 : 1;
7608 mmr_t overflow_fifo02_debit2 : 1;
7609 mmr_t overflow_fifo13_debit0 : 1;
7610 mmr_t overflow_fifo13_debit2 : 1;
7611 mmr_t overflow_fifo02_vc0_pop : 1;
7612 mmr_t overflow_fifo02_vc2_pop : 1;
7613 mmr_t overflow_fifo13_vc1_pop : 1;
7614 mmr_t overflow_fifo13_vc3_pop : 1;
7615 mmr_t overflow_fifo02_vc0_push : 1;
7616 mmr_t overflow_fifo02_vc2_push : 1;
7617 mmr_t overflow_fifo13_vc1_push : 1;
7618 mmr_t overflow_fifo13_vc3_push : 1;
7619 mmr_t overflow_fifo02_vc0_credit : 1;
7620 mmr_t overflow_fifo02_vc2_credit : 1;
7621 mmr_t overflow_fifo13_vc0_credit : 1;
7622 mmr_t overflow_fifo13_vc2_credit : 1;
7623 mmr_t overflow0_vc0_credit : 1;
7624 mmr_t overflow1_vc0_credit : 1;
7625 mmr_t overflow2_vc0_credit : 1;
7626 mmr_t overflow0_vc2_credit : 1;
7627 mmr_t overflow1_vc2_credit : 1;
7628 mmr_t overflow2_vc2_credit : 1;
7629 mmr_t overflow_pi_fifo_debit0 : 1;
7630 mmr_t overflow_pi_fifo_debit2 : 1;
7631 mmr_t overflow_iilb_fifo_debit0 : 1;
7632 mmr_t overflow_iilb_fifo_debit2 : 1;
7633 mmr_t overflow_md_fifo_debit0 : 1;
7634 mmr_t overflow_md_fifo_debit2 : 1;
7635 mmr_t overflow_ni_fifo_debit0 : 1;
7636 mmr_t overflow_ni_fifo_debit1 : 1;
7637 mmr_t overflow_ni_fifo_debit2 : 1;
7638 mmr_t overflow_ni_fifo_debit3 : 1;
7639 mmr_t overflow_pi_fifo_vc0_pop : 1;
7640 mmr_t overflow_pi_fifo_vc2_pop : 1;
7641 mmr_t overflow_iilb_fifo_vc0_pop : 1;
7642 mmr_t overflow_iilb_fifo_vc2_pop : 1;
7643 mmr_t overflow_md_fifo_vc0_pop : 1;
7644 mmr_t overflow_md_fifo_vc2_pop : 1;
7645 mmr_t overflow_ni_fifo_vc0_pop : 1;
7646 mmr_t overflow_ni_fifo_vc2_pop : 1;
7647 mmr_t overflow_pi_fifo_vc0_push : 1;
7648 mmr_t overflow_pi_fifo_vc2_push : 1;
7649 mmr_t overflow_iilb_fifo_vc0_push : 1;
7650 mmr_t overflow_iilb_fifo_vc2_push : 1;
7651 mmr_t overflow_md_fifo_vc0_push : 1;
7652 mmr_t overflow_md_fifo_vc2_push : 1;
7653 mmr_t overflow_pi_fifo_vc0_credit : 1;
7654 mmr_t overflow_pi_fifo_vc2_credit : 1;
7655 mmr_t overflow_iilb_fifo_vc0_credit : 1;
7656 mmr_t overflow_iilb_fifo_vc2_credit : 1;
7657 mmr_t overflow_md_fifo_vc0_credit : 1;
7658 mmr_t overflow_md_fifo_vc2_credit : 1;
7659 mmr_t overflow_ni_fifo_vc0_credit : 1;
7660 mmr_t overflow_ni_fifo_vc1_credit : 1;
7661 mmr_t overflow_ni_fifo_vc2_credit : 1;
7662 mmr_t overflow_ni_fifo_vc3_credit : 1;
7663 mmr_t tail_timeout_fifo02_vc0 : 1;
7664 mmr_t tail_timeout_fifo02_vc2 : 1;
7665 mmr_t tail_timeout_fifo13_vc1 : 1;
7666 mmr_t tail_timeout_fifo13_vc3 : 1;
7667 mmr_t tail_timeout_ni_vc0 : 1;
7668 mmr_t tail_timeout_ni_vc1 : 1;
7669 mmr_t tail_timeout_ni_vc2 : 1;
7670 mmr_t tail_timeout_ni_vc3 : 1;
7671 } sh_ni0_error_mask_1_s;
7672 } sh_ni0_error_mask_1_u_t;
7674 /* ==================================================================== */
7675 /* Register "SH_NI0_ERROR_MASK_2" */
7676 /* ni0 Error Mask Bits */
7677 /* ==================================================================== */
7679 typedef union sh_ni0_error_mask_2_u {
7680 mmr_t sh_ni0_error_mask_2_regval;
7682 mmr_t illegal_vcni : 1;
7683 mmr_t illegal_vcpi : 1;
7684 mmr_t illegal_vcmd : 1;
7685 mmr_t illegal_vciilb : 1;
7686 mmr_t underflow_fifo02_vc0_pop : 1;
7687 mmr_t underflow_fifo02_vc2_pop : 1;
7688 mmr_t underflow_fifo13_vc1_pop : 1;
7689 mmr_t underflow_fifo13_vc3_pop : 1;
7690 mmr_t underflow_fifo02_vc0_push : 1;
7691 mmr_t underflow_fifo02_vc2_push : 1;
7692 mmr_t underflow_fifo13_vc1_push : 1;
7693 mmr_t underflow_fifo13_vc3_push : 1;
7694 mmr_t underflow_fifo02_vc0_credit : 1;
7695 mmr_t underflow_fifo02_vc2_credit : 1;
7696 mmr_t underflow_fifo13_vc0_credit : 1;
7697 mmr_t underflow_fifo13_vc2_credit : 1;
7698 mmr_t underflow0_vc0_credit : 1;
7699 mmr_t underflow1_vc0_credit : 1;
7700 mmr_t underflow2_vc0_credit : 1;
7701 mmr_t underflow0_vc2_credit : 1;
7702 mmr_t underflow1_vc2_credit : 1;
7703 mmr_t underflow2_vc2_credit : 1;
7704 mmr_t reserved_0 : 10;
7705 mmr_t underflow_pi_fifo_vc0_pop : 1;
7706 mmr_t underflow_pi_fifo_vc2_pop : 1;
7707 mmr_t underflow_iilb_fifo_vc0_pop : 1;
7708 mmr_t underflow_iilb_fifo_vc2_pop : 1;
7709 mmr_t underflow_md_fifo_vc0_pop : 1;
7710 mmr_t underflow_md_fifo_vc2_pop : 1;
7711 mmr_t underflow_ni_fifo_vc0_pop : 1;
7712 mmr_t underflow_ni_fifo_vc2_pop : 1;
7713 mmr_t underflow_pi_fifo_vc0_push : 1;
7714 mmr_t underflow_pi_fifo_vc2_push : 1;
7715 mmr_t underflow_iilb_fifo_vc0_push : 1;
7716 mmr_t underflow_iilb_fifo_vc2_push : 1;
7717 mmr_t underflow_md_fifo_vc0_push : 1;
7718 mmr_t underflow_md_fifo_vc2_push : 1;
7719 mmr_t underflow_pi_fifo_vc0_credit : 1;
7720 mmr_t underflow_pi_fifo_vc2_credit : 1;
7721 mmr_t underflow_iilb_fifo_vc0_credit : 1;
7722 mmr_t underflow_iilb_fifo_vc2_credit : 1;
7723 mmr_t underflow_md_fifo_vc0_credit : 1;
7724 mmr_t underflow_md_fifo_vc2_credit : 1;
7725 mmr_t underflow_ni_fifo_vc0_credit : 1;
7726 mmr_t underflow_ni_fifo_vc1_credit : 1;
7727 mmr_t underflow_ni_fifo_vc2_credit : 1;
7728 mmr_t underflow_ni_fifo_vc3_credit : 1;
7729 mmr_t llp_deadlock_vc0 : 1;
7730 mmr_t llp_deadlock_vc1 : 1;
7731 mmr_t llp_deadlock_vc2 : 1;
7732 mmr_t llp_deadlock_vc3 : 1;
7733 mmr_t chiplet_nomatch : 1;
7734 mmr_t lut_read_error : 1;
7735 mmr_t retry_timeout_error : 1;
7736 mmr_t reserved_1 : 1;
7737 } sh_ni0_error_mask_2_s;
7738 } sh_ni0_error_mask_2_u_t;
7740 /* ==================================================================== */
7741 /* Register "SH_NI0_FIRST_ERROR_1" */
7742 /* ni0 First Error Bits */
7743 /* ==================================================================== */
7745 typedef union sh_ni0_first_error_1_u {
7746 mmr_t sh_ni0_first_error_1_regval;
7748 mmr_t overflow_fifo02_debit0 : 1;
7749 mmr_t overflow_fifo02_debit2 : 1;
7750 mmr_t overflow_fifo13_debit0 : 1;
7751 mmr_t overflow_fifo13_debit2 : 1;
7752 mmr_t overflow_fifo02_vc0_pop : 1;
7753 mmr_t overflow_fifo02_vc2_pop : 1;
7754 mmr_t overflow_fifo13_vc1_pop : 1;
7755 mmr_t overflow_fifo13_vc3_pop : 1;
7756 mmr_t overflow_fifo02_vc0_push : 1;
7757 mmr_t overflow_fifo02_vc2_push : 1;
7758 mmr_t overflow_fifo13_vc1_push : 1;
7759 mmr_t overflow_fifo13_vc3_push : 1;
7760 mmr_t overflow_fifo02_vc0_credit : 1;
7761 mmr_t overflow_fifo02_vc2_credit : 1;
7762 mmr_t overflow_fifo13_vc0_credit : 1;
7763 mmr_t overflow_fifo13_vc2_credit : 1;
7764 mmr_t overflow0_vc0_credit : 1;
7765 mmr_t overflow1_vc0_credit : 1;
7766 mmr_t overflow2_vc0_credit : 1;
7767 mmr_t overflow0_vc2_credit : 1;
7768 mmr_t overflow1_vc2_credit : 1;
7769 mmr_t overflow2_vc2_credit : 1;
7770 mmr_t overflow_pi_fifo_debit0 : 1;
7771 mmr_t overflow_pi_fifo_debit2 : 1;
7772 mmr_t overflow_iilb_fifo_debit0 : 1;
7773 mmr_t overflow_iilb_fifo_debit2 : 1;
7774 mmr_t overflow_md_fifo_debit0 : 1;
7775 mmr_t overflow_md_fifo_debit2 : 1;
7776 mmr_t overflow_ni_fifo_debit0 : 1;
7777 mmr_t overflow_ni_fifo_debit1 : 1;
7778 mmr_t overflow_ni_fifo_debit2 : 1;
7779 mmr_t overflow_ni_fifo_debit3 : 1;
7780 mmr_t overflow_pi_fifo_vc0_pop : 1;
7781 mmr_t overflow_pi_fifo_vc2_pop : 1;
7782 mmr_t overflow_iilb_fifo_vc0_pop : 1;
7783 mmr_t overflow_iilb_fifo_vc2_pop : 1;
7784 mmr_t overflow_md_fifo_vc0_pop : 1;
7785 mmr_t overflow_md_fifo_vc2_pop : 1;
7786 mmr_t overflow_ni_fifo_vc0_pop : 1;
7787 mmr_t overflow_ni_fifo_vc2_pop : 1;
7788 mmr_t overflow_pi_fifo_vc0_push : 1;
7789 mmr_t overflow_pi_fifo_vc2_push : 1;
7790 mmr_t overflow_iilb_fifo_vc0_push : 1;
7791 mmr_t overflow_iilb_fifo_vc2_push : 1;
7792 mmr_t overflow_md_fifo_vc0_push : 1;
7793 mmr_t overflow_md_fifo_vc2_push : 1;
7794 mmr_t overflow_pi_fifo_vc0_credit : 1;
7795 mmr_t overflow_pi_fifo_vc2_credit : 1;
7796 mmr_t overflow_iilb_fifo_vc0_credit : 1;
7797 mmr_t overflow_iilb_fifo_vc2_credit : 1;
7798 mmr_t overflow_md_fifo_vc0_credit : 1;
7799 mmr_t overflow_md_fifo_vc2_credit : 1;
7800 mmr_t overflow_ni_fifo_vc0_credit : 1;
7801 mmr_t overflow_ni_fifo_vc1_credit : 1;
7802 mmr_t overflow_ni_fifo_vc2_credit : 1;
7803 mmr_t overflow_ni_fifo_vc3_credit : 1;
7804 mmr_t tail_timeout_fifo02_vc0 : 1;
7805 mmr_t tail_timeout_fifo02_vc2 : 1;
7806 mmr_t tail_timeout_fifo13_vc1 : 1;
7807 mmr_t tail_timeout_fifo13_vc3 : 1;
7808 mmr_t tail_timeout_ni_vc0 : 1;
7809 mmr_t tail_timeout_ni_vc1 : 1;
7810 mmr_t tail_timeout_ni_vc2 : 1;
7811 mmr_t tail_timeout_ni_vc3 : 1;
7812 } sh_ni0_first_error_1_s;
7813 } sh_ni0_first_error_1_u_t;
7815 /* ==================================================================== */
7816 /* Register "SH_NI0_FIRST_ERROR_2" */
7817 /* ni0 First Error Bits */
7818 /* ==================================================================== */
7820 typedef union sh_ni0_first_error_2_u {
7821 mmr_t sh_ni0_first_error_2_regval;
7823 mmr_t illegal_vcni : 1;
7824 mmr_t illegal_vcpi : 1;
7825 mmr_t illegal_vcmd : 1;
7826 mmr_t illegal_vciilb : 1;
7827 mmr_t underflow_fifo02_vc0_pop : 1;
7828 mmr_t underflow_fifo02_vc2_pop : 1;
7829 mmr_t underflow_fifo13_vc1_pop : 1;
7830 mmr_t underflow_fifo13_vc3_pop : 1;
7831 mmr_t underflow_fifo02_vc0_push : 1;
7832 mmr_t underflow_fifo02_vc2_push : 1;
7833 mmr_t underflow_fifo13_vc1_push : 1;
7834 mmr_t underflow_fifo13_vc3_push : 1;
7835 mmr_t underflow_fifo02_vc0_credit : 1;
7836 mmr_t underflow_fifo02_vc2_credit : 1;
7837 mmr_t underflow_fifo13_vc0_credit : 1;
7838 mmr_t underflow_fifo13_vc2_credit : 1;
7839 mmr_t underflow0_vc0_credit : 1;
7840 mmr_t underflow1_vc0_credit : 1;
7841 mmr_t underflow2_vc0_credit : 1;
7842 mmr_t underflow0_vc2_credit : 1;
7843 mmr_t underflow1_vc2_credit : 1;
7844 mmr_t underflow2_vc2_credit : 1;
7845 mmr_t reserved_0 : 10;
7846 mmr_t underflow_pi_fifo_vc0_pop : 1;
7847 mmr_t underflow_pi_fifo_vc2_pop : 1;
7848 mmr_t underflow_iilb_fifo_vc0_pop : 1;
7849 mmr_t underflow_iilb_fifo_vc2_pop : 1;
7850 mmr_t underflow_md_fifo_vc0_pop : 1;
7851 mmr_t underflow_md_fifo_vc2_pop : 1;
7852 mmr_t underflow_ni_fifo_vc0_pop : 1;
7853 mmr_t underflow_ni_fifo_vc2_pop : 1;
7854 mmr_t underflow_pi_fifo_vc0_push : 1;
7855 mmr_t underflow_pi_fifo_vc2_push : 1;
7856 mmr_t underflow_iilb_fifo_vc0_push : 1;
7857 mmr_t underflow_iilb_fifo_vc2_push : 1;
7858 mmr_t underflow_md_fifo_vc0_push : 1;
7859 mmr_t underflow_md_fifo_vc2_push : 1;
7860 mmr_t underflow_pi_fifo_vc0_credit : 1;
7861 mmr_t underflow_pi_fifo_vc2_credit : 1;
7862 mmr_t underflow_iilb_fifo_vc0_credit : 1;
7863 mmr_t underflow_iilb_fifo_vc2_credit : 1;
7864 mmr_t underflow_md_fifo_vc0_credit : 1;
7865 mmr_t underflow_md_fifo_vc2_credit : 1;
7866 mmr_t underflow_ni_fifo_vc0_credit : 1;
7867 mmr_t underflow_ni_fifo_vc1_credit : 1;
7868 mmr_t underflow_ni_fifo_vc2_credit : 1;
7869 mmr_t underflow_ni_fifo_vc3_credit : 1;
7870 mmr_t llp_deadlock_vc0 : 1;
7871 mmr_t llp_deadlock_vc1 : 1;
7872 mmr_t llp_deadlock_vc2 : 1;
7873 mmr_t llp_deadlock_vc3 : 1;
7874 mmr_t chiplet_nomatch : 1;
7875 mmr_t lut_read_error : 1;
7876 mmr_t retry_timeout_error : 1;
7877 mmr_t reserved_1 : 1;
7878 } sh_ni0_first_error_2_s;
7879 } sh_ni0_first_error_2_u_t;
7881 /* ==================================================================== */
7882 /* Register "SH_NI0_ERROR_DETAIL_1" */
7883 /* ni0 Chiplet no match header bits 63:0 */
7884 /* ==================================================================== */
7886 typedef union sh_ni0_error_detail_1_u {
7887 mmr_t sh_ni0_error_detail_1_regval;
7890 } sh_ni0_error_detail_1_s;
7891 } sh_ni0_error_detail_1_u_t;
7893 /* ==================================================================== */
7894 /* Register "SH_NI0_ERROR_DETAIL_2" */
7895 /* ni0 Chiplet no match header bits 127:64 */
7896 /* ==================================================================== */
7898 typedef union sh_ni0_error_detail_2_u {
7899 mmr_t sh_ni0_error_detail_2_regval;
7902 } sh_ni0_error_detail_2_s;
7903 } sh_ni0_error_detail_2_u_t;
7905 /* ==================================================================== */
7906 /* Register "SH_NI1_ERROR_SUMMARY_1" */
7907 /* ni1 Error Summary Bits */
7908 /* ==================================================================== */
7910 typedef union sh_ni1_error_summary_1_u {
7911 mmr_t sh_ni1_error_summary_1_regval;
7913 mmr_t overflow_fifo02_debit0 : 1;
7914 mmr_t overflow_fifo02_debit2 : 1;
7915 mmr_t overflow_fifo13_debit0 : 1;
7916 mmr_t overflow_fifo13_debit2 : 1;
7917 mmr_t overflow_fifo02_vc0_pop : 1;
7918 mmr_t overflow_fifo02_vc2_pop : 1;
7919 mmr_t overflow_fifo13_vc1_pop : 1;
7920 mmr_t overflow_fifo13_vc3_pop : 1;
7921 mmr_t overflow_fifo02_vc0_push : 1;
7922 mmr_t overflow_fifo02_vc2_push : 1;
7923 mmr_t overflow_fifo13_vc1_push : 1;
7924 mmr_t overflow_fifo13_vc3_push : 1;
7925 mmr_t overflow_fifo02_vc0_credit : 1;
7926 mmr_t overflow_fifo02_vc2_credit : 1;
7927 mmr_t overflow_fifo13_vc0_credit : 1;
7928 mmr_t overflow_fifo13_vc2_credit : 1;
7929 mmr_t overflow0_vc0_credit : 1;
7930 mmr_t overflow1_vc0_credit : 1;
7931 mmr_t overflow2_vc0_credit : 1;
7932 mmr_t overflow0_vc2_credit : 1;
7933 mmr_t overflow1_vc2_credit : 1;
7934 mmr_t overflow2_vc2_credit : 1;
7935 mmr_t overflow_pi_fifo_debit0 : 1;
7936 mmr_t overflow_pi_fifo_debit2 : 1;
7937 mmr_t overflow_iilb_fifo_debit0 : 1;
7938 mmr_t overflow_iilb_fifo_debit2 : 1;
7939 mmr_t overflow_md_fifo_debit0 : 1;
7940 mmr_t overflow_md_fifo_debit2 : 1;
7941 mmr_t overflow_ni_fifo_debit0 : 1;
7942 mmr_t overflow_ni_fifo_debit1 : 1;
7943 mmr_t overflow_ni_fifo_debit2 : 1;
7944 mmr_t overflow_ni_fifo_debit3 : 1;
7945 mmr_t overflow_pi_fifo_vc0_pop : 1;
7946 mmr_t overflow_pi_fifo_vc2_pop : 1;
7947 mmr_t overflow_iilb_fifo_vc0_pop : 1;
7948 mmr_t overflow_iilb_fifo_vc2_pop : 1;
7949 mmr_t overflow_md_fifo_vc0_pop : 1;
7950 mmr_t overflow_md_fifo_vc2_pop : 1;
7951 mmr_t overflow_ni_fifo_vc0_pop : 1;
7952 mmr_t overflow_ni_fifo_vc2_pop : 1;
7953 mmr_t overflow_pi_fifo_vc0_push : 1;
7954 mmr_t overflow_pi_fifo_vc2_push : 1;
7955 mmr_t overflow_iilb_fifo_vc0_push : 1;
7956 mmr_t overflow_iilb_fifo_vc2_push : 1;
7957 mmr_t overflow_md_fifo_vc0_push : 1;
7958 mmr_t overflow_md_fifo_vc2_push : 1;
7959 mmr_t overflow_pi_fifo_vc0_credit : 1;
7960 mmr_t overflow_pi_fifo_vc2_credit : 1;
7961 mmr_t overflow_iilb_fifo_vc0_credit : 1;
7962 mmr_t overflow_iilb_fifo_vc2_credit : 1;
7963 mmr_t overflow_md_fifo_vc0_credit : 1;
7964 mmr_t overflow_md_fifo_vc2_credit : 1;
7965 mmr_t overflow_ni_fifo_vc0_credit : 1;
7966 mmr_t overflow_ni_fifo_vc1_credit : 1;
7967 mmr_t overflow_ni_fifo_vc2_credit : 1;
7968 mmr_t overflow_ni_fifo_vc3_credit : 1;
7969 mmr_t tail_timeout_fifo02_vc0 : 1;
7970 mmr_t tail_timeout_fifo02_vc2 : 1;
7971 mmr_t tail_timeout_fifo13_vc1 : 1;
7972 mmr_t tail_timeout_fifo13_vc3 : 1;
7973 mmr_t tail_timeout_ni_vc0 : 1;
7974 mmr_t tail_timeout_ni_vc1 : 1;
7975 mmr_t tail_timeout_ni_vc2 : 1;
7976 mmr_t tail_timeout_ni_vc3 : 1;
7977 } sh_ni1_error_summary_1_s;
7978 } sh_ni1_error_summary_1_u_t;
7980 /* ==================================================================== */
7981 /* Register "SH_NI1_ERROR_SUMMARY_2" */
7982 /* ni1 Error Summary Bits */
7983 /* ==================================================================== */
7985 typedef union sh_ni1_error_summary_2_u {
7986 mmr_t sh_ni1_error_summary_2_regval;
7988 mmr_t illegal_vcni : 1;
7989 mmr_t illegal_vcpi : 1;
7990 mmr_t illegal_vcmd : 1;
7991 mmr_t illegal_vciilb : 1;
7992 mmr_t underflow_fifo02_vc0_pop : 1;
7993 mmr_t underflow_fifo02_vc2_pop : 1;
7994 mmr_t underflow_fifo13_vc1_pop : 1;
7995 mmr_t underflow_fifo13_vc3_pop : 1;
7996 mmr_t underflow_fifo02_vc0_push : 1;
7997 mmr_t underflow_fifo02_vc2_push : 1;
7998 mmr_t underflow_fifo13_vc1_push : 1;
7999 mmr_t underflow_fifo13_vc3_push : 1;
8000 mmr_t underflow_fifo02_vc0_credit : 1;
8001 mmr_t underflow_fifo02_vc2_credit : 1;
8002 mmr_t underflow_fifo13_vc0_credit : 1;
8003 mmr_t underflow_fifo13_vc2_credit : 1;
8004 mmr_t underflow0_vc0_credit : 1;
8005 mmr_t underflow1_vc0_credit : 1;
8006 mmr_t underflow2_vc0_credit : 1;
8007 mmr_t underflow0_vc2_credit : 1;
8008 mmr_t underflow1_vc2_credit : 1;
8009 mmr_t underflow2_vc2_credit : 1;
8010 mmr_t reserved_0 : 10;
8011 mmr_t underflow_pi_fifo_vc0_pop : 1;
8012 mmr_t underflow_pi_fifo_vc2_pop : 1;
8013 mmr_t underflow_iilb_fifo_vc0_pop : 1;
8014 mmr_t underflow_iilb_fifo_vc2_pop : 1;
8015 mmr_t underflow_md_fifo_vc0_pop : 1;
8016 mmr_t underflow_md_fifo_vc2_pop : 1;
8017 mmr_t underflow_ni_fifo_vc0_pop : 1;
8018 mmr_t underflow_ni_fifo_vc2_pop : 1;
8019 mmr_t underflow_pi_fifo_vc0_push : 1;
8020 mmr_t underflow_pi_fifo_vc2_push : 1;
8021 mmr_t underflow_iilb_fifo_vc0_push : 1;
8022 mmr_t underflow_iilb_fifo_vc2_push : 1;
8023 mmr_t underflow_md_fifo_vc0_push : 1;
8024 mmr_t underflow_md_fifo_vc2_push : 1;
8025 mmr_t underflow_pi_fifo_vc0_credit : 1;
8026 mmr_t underflow_pi_fifo_vc2_credit : 1;
8027 mmr_t underflow_iilb_fifo_vc0_credit : 1;
8028 mmr_t underflow_iilb_fifo_vc2_credit : 1;
8029 mmr_t underflow_md_fifo_vc0_credit : 1;
8030 mmr_t underflow_md_fifo_vc2_credit : 1;
8031 mmr_t underflow_ni_fifo_vc0_credit : 1;
8032 mmr_t underflow_ni_fifo_vc1_credit : 1;
8033 mmr_t underflow_ni_fifo_vc2_credit : 1;
8034 mmr_t underflow_ni_fifo_vc3_credit : 1;
8035 mmr_t llp_deadlock_vc0 : 1;
8036 mmr_t llp_deadlock_vc1 : 1;
8037 mmr_t llp_deadlock_vc2 : 1;
8038 mmr_t llp_deadlock_vc3 : 1;
8039 mmr_t chiplet_nomatch : 1;
8040 mmr_t lut_read_error : 1;
8041 mmr_t retry_timeout_error : 1;
8042 mmr_t reserved_1 : 1;
8043 } sh_ni1_error_summary_2_s;
8044 } sh_ni1_error_summary_2_u_t;
8046 /* ==================================================================== */
8047 /* Register "SH_NI1_ERROR_OVERFLOW_1" */
8048 /* ni1 Error Overflow Bits */
8049 /* ==================================================================== */
8051 typedef union sh_ni1_error_overflow_1_u {
8052 mmr_t sh_ni1_error_overflow_1_regval;
8054 mmr_t overflow_fifo02_debit0 : 1;
8055 mmr_t overflow_fifo02_debit2 : 1;
8056 mmr_t overflow_fifo13_debit0 : 1;
8057 mmr_t overflow_fifo13_debit2 : 1;
8058 mmr_t overflow_fifo02_vc0_pop : 1;
8059 mmr_t overflow_fifo02_vc2_pop : 1;
8060 mmr_t overflow_fifo13_vc1_pop : 1;
8061 mmr_t overflow_fifo13_vc3_pop : 1;
8062 mmr_t overflow_fifo02_vc0_push : 1;
8063 mmr_t overflow_fifo02_vc2_push : 1;
8064 mmr_t overflow_fifo13_vc1_push : 1;
8065 mmr_t overflow_fifo13_vc3_push : 1;
8066 mmr_t overflow_fifo02_vc0_credit : 1;
8067 mmr_t overflow_fifo02_vc2_credit : 1;
8068 mmr_t overflow_fifo13_vc0_credit : 1;
8069 mmr_t overflow_fifo13_vc2_credit : 1;
8070 mmr_t overflow0_vc0_credit : 1;
8071 mmr_t overflow1_vc0_credit : 1;
8072 mmr_t overflow2_vc0_credit : 1;
8073 mmr_t overflow0_vc2_credit : 1;
8074 mmr_t overflow1_vc2_credit : 1;
8075 mmr_t overflow2_vc2_credit : 1;
8076 mmr_t overflow_pi_fifo_debit0 : 1;
8077 mmr_t overflow_pi_fifo_debit2 : 1;
8078 mmr_t overflow_iilb_fifo_debit0 : 1;
8079 mmr_t overflow_iilb_fifo_debit2 : 1;
8080 mmr_t overflow_md_fifo_debit0 : 1;
8081 mmr_t overflow_md_fifo_debit2 : 1;
8082 mmr_t overflow_ni_fifo_debit0 : 1;
8083 mmr_t overflow_ni_fifo_debit1 : 1;
8084 mmr_t overflow_ni_fifo_debit2 : 1;
8085 mmr_t overflow_ni_fifo_debit3 : 1;
8086 mmr_t overflow_pi_fifo_vc0_pop : 1;
8087 mmr_t overflow_pi_fifo_vc2_pop : 1;
8088 mmr_t overflow_iilb_fifo_vc0_pop : 1;
8089 mmr_t overflow_iilb_fifo_vc2_pop : 1;
8090 mmr_t overflow_md_fifo_vc0_pop : 1;
8091 mmr_t overflow_md_fifo_vc2_pop : 1;
8092 mmr_t overflow_ni_fifo_vc0_pop : 1;
8093 mmr_t overflow_ni_fifo_vc2_pop : 1;
8094 mmr_t overflow_pi_fifo_vc0_push : 1;
8095 mmr_t overflow_pi_fifo_vc2_push : 1;
8096 mmr_t overflow_iilb_fifo_vc0_push : 1;
8097 mmr_t overflow_iilb_fifo_vc2_push : 1;
8098 mmr_t overflow_md_fifo_vc0_push : 1;
8099 mmr_t overflow_md_fifo_vc2_push : 1;
8100 mmr_t overflow_pi_fifo_vc0_credit : 1;
8101 mmr_t overflow_pi_fifo_vc2_credit : 1;
8102 mmr_t overflow_iilb_fifo_vc0_credit : 1;
8103 mmr_t overflow_iilb_fifo_vc2_credit : 1;
8104 mmr_t overflow_md_fifo_vc0_credit : 1;
8105 mmr_t overflow_md_fifo_vc2_credit : 1;
8106 mmr_t overflow_ni_fifo_vc0_credit : 1;
8107 mmr_t overflow_ni_fifo_vc1_credit : 1;
8108 mmr_t overflow_ni_fifo_vc2_credit : 1;
8109 mmr_t overflow_ni_fifo_vc3_credit : 1;
8110 mmr_t tail_timeout_fifo02_vc0 : 1;
8111 mmr_t tail_timeout_fifo02_vc2 : 1;
8112 mmr_t tail_timeout_fifo13_vc1 : 1;
8113 mmr_t tail_timeout_fifo13_vc3 : 1;
8114 mmr_t tail_timeout_ni_vc0 : 1;
8115 mmr_t tail_timeout_ni_vc1 : 1;
8116 mmr_t tail_timeout_ni_vc2 : 1;
8117 mmr_t tail_timeout_ni_vc3 : 1;
8118 } sh_ni1_error_overflow_1_s;
8119 } sh_ni1_error_overflow_1_u_t;
8121 /* ==================================================================== */
8122 /* Register "SH_NI1_ERROR_OVERFLOW_2" */
8123 /* ni1 Error Overflow Bits */
8124 /* ==================================================================== */
8126 typedef union sh_ni1_error_overflow_2_u {
8127 mmr_t sh_ni1_error_overflow_2_regval;
8129 mmr_t illegal_vcni : 1;
8130 mmr_t illegal_vcpi : 1;
8131 mmr_t illegal_vcmd : 1;
8132 mmr_t illegal_vciilb : 1;
8133 mmr_t underflow_fifo02_vc0_pop : 1;
8134 mmr_t underflow_fifo02_vc2_pop : 1;
8135 mmr_t underflow_fifo13_vc1_pop : 1;
8136 mmr_t underflow_fifo13_vc3_pop : 1;
8137 mmr_t underflow_fifo02_vc0_push : 1;
8138 mmr_t underflow_fifo02_vc2_push : 1;
8139 mmr_t underflow_fifo13_vc1_push : 1;
8140 mmr_t underflow_fifo13_vc3_push : 1;
8141 mmr_t underflow_fifo02_vc0_credit : 1;
8142 mmr_t underflow_fifo02_vc2_credit : 1;
8143 mmr_t underflow_fifo13_vc0_credit : 1;
8144 mmr_t underflow_fifo13_vc2_credit : 1;
8145 mmr_t underflow0_vc0_credit : 1;
8146 mmr_t underflow1_vc0_credit : 1;
8147 mmr_t underflow2_vc0_credit : 1;
8148 mmr_t underflow0_vc2_credit : 1;
8149 mmr_t underflow1_vc2_credit : 1;
8150 mmr_t underflow2_vc2_credit : 1;
8151 mmr_t reserved_0 : 10;
8152 mmr_t underflow_pi_fifo_vc0_pop : 1;
8153 mmr_t underflow_pi_fifo_vc2_pop : 1;
8154 mmr_t underflow_iilb_fifo_vc0_pop : 1;
8155 mmr_t underflow_iilb_fifo_vc2_pop : 1;
8156 mmr_t underflow_md_fifo_vc0_pop : 1;
8157 mmr_t underflow_md_fifo_vc2_pop : 1;
8158 mmr_t underflow_ni_fifo_vc0_pop : 1;
8159 mmr_t underflow_ni_fifo_vc2_pop : 1;
8160 mmr_t underflow_pi_fifo_vc0_push : 1;
8161 mmr_t underflow_pi_fifo_vc2_push : 1;
8162 mmr_t underflow_iilb_fifo_vc0_push : 1;
8163 mmr_t underflow_iilb_fifo_vc2_push : 1;
8164 mmr_t underflow_md_fifo_vc0_push : 1;
8165 mmr_t underflow_md_fifo_vc2_push : 1;
8166 mmr_t underflow_pi_fifo_vc0_credit : 1;
8167 mmr_t underflow_pi_fifo_vc2_credit : 1;
8168 mmr_t underflow_iilb_fifo_vc0_credit : 1;
8169 mmr_t underflow_iilb_fifo_vc2_credit : 1;
8170 mmr_t underflow_md_fifo_vc0_credit : 1;
8171 mmr_t underflow_md_fifo_vc2_credit : 1;
8172 mmr_t underflow_ni_fifo_vc0_credit : 1;
8173 mmr_t underflow_ni_fifo_vc1_credit : 1;
8174 mmr_t underflow_ni_fifo_vc2_credit : 1;
8175 mmr_t underflow_ni_fifo_vc3_credit : 1;
8176 mmr_t llp_deadlock_vc0 : 1;
8177 mmr_t llp_deadlock_vc1 : 1;
8178 mmr_t llp_deadlock_vc2 : 1;
8179 mmr_t llp_deadlock_vc3 : 1;
8180 mmr_t chiplet_nomatch : 1;
8181 mmr_t lut_read_error : 1;
8182 mmr_t retry_timeout_error : 1;
8183 mmr_t reserved_1 : 1;
8184 } sh_ni1_error_overflow_2_s;
8185 } sh_ni1_error_overflow_2_u_t;
8187 /* ==================================================================== */
8188 /* Register "SH_NI1_ERROR_MASK_1" */
8189 /* ni1 Error Mask Bits */
8190 /* ==================================================================== */
8192 typedef union sh_ni1_error_mask_1_u {
8193 mmr_t sh_ni1_error_mask_1_regval;
8195 mmr_t overflow_fifo02_debit0 : 1;
8196 mmr_t overflow_fifo02_debit2 : 1;
8197 mmr_t overflow_fifo13_debit0 : 1;
8198 mmr_t overflow_fifo13_debit2 : 1;
8199 mmr_t overflow_fifo02_vc0_pop : 1;
8200 mmr_t overflow_fifo02_vc2_pop : 1;
8201 mmr_t overflow_fifo13_vc1_pop : 1;
8202 mmr_t overflow_fifo13_vc3_pop : 1;
8203 mmr_t overflow_fifo02_vc0_push : 1;
8204 mmr_t overflow_fifo02_vc2_push : 1;
8205 mmr_t overflow_fifo13_vc1_push : 1;
8206 mmr_t overflow_fifo13_vc3_push : 1;
8207 mmr_t overflow_fifo02_vc0_credit : 1;
8208 mmr_t overflow_fifo02_vc2_credit : 1;
8209 mmr_t overflow_fifo13_vc0_credit : 1;
8210 mmr_t overflow_fifo13_vc2_credit : 1;
8211 mmr_t overflow0_vc0_credit : 1;
8212 mmr_t overflow1_vc0_credit : 1;
8213 mmr_t overflow2_vc0_credit : 1;
8214 mmr_t overflow0_vc2_credit : 1;
8215 mmr_t overflow1_vc2_credit : 1;
8216 mmr_t overflow2_vc2_credit : 1;
8217 mmr_t overflow_pi_fifo_debit0 : 1;
8218 mmr_t overflow_pi_fifo_debit2 : 1;
8219 mmr_t overflow_iilb_fifo_debit0 : 1;
8220 mmr_t overflow_iilb_fifo_debit2 : 1;
8221 mmr_t overflow_md_fifo_debit0 : 1;
8222 mmr_t overflow_md_fifo_debit2 : 1;
8223 mmr_t overflow_ni_fifo_debit0 : 1;
8224 mmr_t overflow_ni_fifo_debit1 : 1;
8225 mmr_t overflow_ni_fifo_debit2 : 1;
8226 mmr_t overflow_ni_fifo_debit3 : 1;
8227 mmr_t overflow_pi_fifo_vc0_pop : 1;
8228 mmr_t overflow_pi_fifo_vc2_pop : 1;
8229 mmr_t overflow_iilb_fifo_vc0_pop : 1;
8230 mmr_t overflow_iilb_fifo_vc2_pop : 1;
8231 mmr_t overflow_md_fifo_vc0_pop : 1;
8232 mmr_t overflow_md_fifo_vc2_pop : 1;
8233 mmr_t overflow_ni_fifo_vc0_pop : 1;
8234 mmr_t overflow_ni_fifo_vc2_pop : 1;
8235 mmr_t overflow_pi_fifo_vc0_push : 1;
8236 mmr_t overflow_pi_fifo_vc2_push : 1;
8237 mmr_t overflow_iilb_fifo_vc0_push : 1;
8238 mmr_t overflow_iilb_fifo_vc2_push : 1;
8239 mmr_t overflow_md_fifo_vc0_push : 1;
8240 mmr_t overflow_md_fifo_vc2_push : 1;
8241 mmr_t overflow_pi_fifo_vc0_credit : 1;
8242 mmr_t overflow_pi_fifo_vc2_credit : 1;
8243 mmr_t overflow_iilb_fifo_vc0_credit : 1;
8244 mmr_t overflow_iilb_fifo_vc2_credit : 1;
8245 mmr_t overflow_md_fifo_vc0_credit : 1;
8246 mmr_t overflow_md_fifo_vc2_credit : 1;
8247 mmr_t overflow_ni_fifo_vc0_credit : 1;
8248 mmr_t overflow_ni_fifo_vc1_credit : 1;
8249 mmr_t overflow_ni_fifo_vc2_credit : 1;
8250 mmr_t overflow_ni_fifo_vc3_credit : 1;
8251 mmr_t tail_timeout_fifo02_vc0 : 1;
8252 mmr_t tail_timeout_fifo02_vc2 : 1;
8253 mmr_t tail_timeout_fifo13_vc1 : 1;
8254 mmr_t tail_timeout_fifo13_vc3 : 1;
8255 mmr_t tail_timeout_ni_vc0 : 1;
8256 mmr_t tail_timeout_ni_vc1 : 1;
8257 mmr_t tail_timeout_ni_vc2 : 1;
8258 mmr_t tail_timeout_ni_vc3 : 1;
8259 } sh_ni1_error_mask_1_s;
8260 } sh_ni1_error_mask_1_u_t;
8262 /* ==================================================================== */
8263 /* Register "SH_NI1_ERROR_MASK_2" */
8264 /* ni1 Error Mask Bits */
8265 /* ==================================================================== */
8267 typedef union sh_ni1_error_mask_2_u {
8268 mmr_t sh_ni1_error_mask_2_regval;
8270 mmr_t illegal_vcni : 1;
8271 mmr_t illegal_vcpi : 1;
8272 mmr_t illegal_vcmd : 1;
8273 mmr_t illegal_vciilb : 1;
8274 mmr_t underflow_fifo02_vc0_pop : 1;
8275 mmr_t underflow_fifo02_vc2_pop : 1;
8276 mmr_t underflow_fifo13_vc1_pop : 1;
8277 mmr_t underflow_fifo13_vc3_pop : 1;
8278 mmr_t underflow_fifo02_vc0_push : 1;
8279 mmr_t underflow_fifo02_vc2_push : 1;
8280 mmr_t underflow_fifo13_vc1_push : 1;
8281 mmr_t underflow_fifo13_vc3_push : 1;
8282 mmr_t underflow_fifo02_vc0_credit : 1;
8283 mmr_t underflow_fifo02_vc2_credit : 1;
8284 mmr_t underflow_fifo13_vc0_credit : 1;
8285 mmr_t underflow_fifo13_vc2_credit : 1;
8286 mmr_t underflow0_vc0_credit : 1;
8287 mmr_t underflow1_vc0_credit : 1;
8288 mmr_t underflow2_vc0_credit : 1;
8289 mmr_t underflow0_vc2_credit : 1;
8290 mmr_t underflow1_vc2_credit : 1;
8291 mmr_t underflow2_vc2_credit : 1;
8292 mmr_t reserved_0 : 10;
8293 mmr_t underflow_pi_fifo_vc0_pop : 1;
8294 mmr_t underflow_pi_fifo_vc2_pop : 1;
8295 mmr_t underflow_iilb_fifo_vc0_pop : 1;
8296 mmr_t underflow_iilb_fifo_vc2_pop : 1;
8297 mmr_t underflow_md_fifo_vc0_pop : 1;
8298 mmr_t underflow_md_fifo_vc2_pop : 1;
8299 mmr_t underflow_ni_fifo_vc0_pop : 1;
8300 mmr_t underflow_ni_fifo_vc2_pop : 1;
8301 mmr_t underflow_pi_fifo_vc0_push : 1;
8302 mmr_t underflow_pi_fifo_vc2_push : 1;
8303 mmr_t underflow_iilb_fifo_vc0_push : 1;
8304 mmr_t underflow_iilb_fifo_vc2_push : 1;
8305 mmr_t underflow_md_fifo_vc0_push : 1;
8306 mmr_t underflow_md_fifo_vc2_push : 1;
8307 mmr_t underflow_pi_fifo_vc0_credit : 1;
8308 mmr_t underflow_pi_fifo_vc2_credit : 1;
8309 mmr_t underflow_iilb_fifo_vc0_credit : 1;
8310 mmr_t underflow_iilb_fifo_vc2_credit : 1;
8311 mmr_t underflow_md_fifo_vc0_credit : 1;
8312 mmr_t underflow_md_fifo_vc2_credit : 1;
8313 mmr_t underflow_ni_fifo_vc0_credit : 1;
8314 mmr_t underflow_ni_fifo_vc1_credit : 1;
8315 mmr_t underflow_ni_fifo_vc2_credit : 1;
8316 mmr_t underflow_ni_fifo_vc3_credit : 1;
8317 mmr_t llp_deadlock_vc0 : 1;
8318 mmr_t llp_deadlock_vc1 : 1;
8319 mmr_t llp_deadlock_vc2 : 1;
8320 mmr_t llp_deadlock_vc3 : 1;
8321 mmr_t chiplet_nomatch : 1;
8322 mmr_t lut_read_error : 1;
8323 mmr_t retry_timeout_error : 1;
8324 mmr_t reserved_1 : 1;
8325 } sh_ni1_error_mask_2_s;
8326 } sh_ni1_error_mask_2_u_t;
8328 /* ==================================================================== */
8329 /* Register "SH_NI1_FIRST_ERROR_1" */
8330 /* ni1 First Error Bits */
8331 /* ==================================================================== */
8333 typedef union sh_ni1_first_error_1_u {
8334 mmr_t sh_ni1_first_error_1_regval;
8336 mmr_t overflow_fifo02_debit0 : 1;
8337 mmr_t overflow_fifo02_debit2 : 1;
8338 mmr_t overflow_fifo13_debit0 : 1;
8339 mmr_t overflow_fifo13_debit2 : 1;
8340 mmr_t overflow_fifo02_vc0_pop : 1;
8341 mmr_t overflow_fifo02_vc2_pop : 1;
8342 mmr_t overflow_fifo13_vc1_pop : 1;
8343 mmr_t overflow_fifo13_vc3_pop : 1;
8344 mmr_t overflow_fifo02_vc0_push : 1;
8345 mmr_t overflow_fifo02_vc2_push : 1;
8346 mmr_t overflow_fifo13_vc1_push : 1;
8347 mmr_t overflow_fifo13_vc3_push : 1;
8348 mmr_t overflow_fifo02_vc0_credit : 1;
8349 mmr_t overflow_fifo02_vc2_credit : 1;
8350 mmr_t overflow_fifo13_vc0_credit : 1;
8351 mmr_t overflow_fifo13_vc2_credit : 1;
8352 mmr_t overflow0_vc0_credit : 1;
8353 mmr_t overflow1_vc0_credit : 1;
8354 mmr_t overflow2_vc0_credit : 1;
8355 mmr_t overflow0_vc2_credit : 1;
8356 mmr_t overflow1_vc2_credit : 1;
8357 mmr_t overflow2_vc2_credit : 1;
8358 mmr_t overflow_pi_fifo_debit0 : 1;
8359 mmr_t overflow_pi_fifo_debit2 : 1;
8360 mmr_t overflow_iilb_fifo_debit0 : 1;
8361 mmr_t overflow_iilb_fifo_debit2 : 1;
8362 mmr_t overflow_md_fifo_debit0 : 1;
8363 mmr_t overflow_md_fifo_debit2 : 1;
8364 mmr_t overflow_ni_fifo_debit0 : 1;
8365 mmr_t overflow_ni_fifo_debit1 : 1;
8366 mmr_t overflow_ni_fifo_debit2 : 1;
8367 mmr_t overflow_ni_fifo_debit3 : 1;
8368 mmr_t overflow_pi_fifo_vc0_pop : 1;
8369 mmr_t overflow_pi_fifo_vc2_pop : 1;
8370 mmr_t overflow_iilb_fifo_vc0_pop : 1;
8371 mmr_t overflow_iilb_fifo_vc2_pop : 1;
8372 mmr_t overflow_md_fifo_vc0_pop : 1;
8373 mmr_t overflow_md_fifo_vc2_pop : 1;
8374 mmr_t overflow_ni_fifo_vc0_pop : 1;
8375 mmr_t overflow_ni_fifo_vc2_pop : 1;
8376 mmr_t overflow_pi_fifo_vc0_push : 1;
8377 mmr_t overflow_pi_fifo_vc2_push : 1;
8378 mmr_t overflow_iilb_fifo_vc0_push : 1;
8379 mmr_t overflow_iilb_fifo_vc2_push : 1;
8380 mmr_t overflow_md_fifo_vc0_push : 1;
8381 mmr_t overflow_md_fifo_vc2_push : 1;
8382 mmr_t overflow_pi_fifo_vc0_credit : 1;
8383 mmr_t overflow_pi_fifo_vc2_credit : 1;
8384 mmr_t overflow_iilb_fifo_vc0_credit : 1;
8385 mmr_t overflow_iilb_fifo_vc2_credit : 1;
8386 mmr_t overflow_md_fifo_vc0_credit : 1;
8387 mmr_t overflow_md_fifo_vc2_credit : 1;
8388 mmr_t overflow_ni_fifo_vc0_credit : 1;
8389 mmr_t overflow_ni_fifo_vc1_credit : 1;
8390 mmr_t overflow_ni_fifo_vc2_credit : 1;
8391 mmr_t overflow_ni_fifo_vc3_credit : 1;
8392 mmr_t tail_timeout_fifo02_vc0 : 1;
8393 mmr_t tail_timeout_fifo02_vc2 : 1;
8394 mmr_t tail_timeout_fifo13_vc1 : 1;
8395 mmr_t tail_timeout_fifo13_vc3 : 1;
8396 mmr_t tail_timeout_ni_vc0 : 1;
8397 mmr_t tail_timeout_ni_vc1 : 1;
8398 mmr_t tail_timeout_ni_vc2 : 1;
8399 mmr_t tail_timeout_ni_vc3 : 1;
8400 } sh_ni1_first_error_1_s;
8401 } sh_ni1_first_error_1_u_t;
8403 /* ==================================================================== */
8404 /* Register "SH_NI1_FIRST_ERROR_2" */
8405 /* ni1 First Error Bits */
8406 /* ==================================================================== */
8408 typedef union sh_ni1_first_error_2_u {
8409 mmr_t sh_ni1_first_error_2_regval;
8411 mmr_t illegal_vcni : 1;
8412 mmr_t illegal_vcpi : 1;
8413 mmr_t illegal_vcmd : 1;
8414 mmr_t illegal_vciilb : 1;
8415 mmr_t underflow_fifo02_vc0_pop : 1;
8416 mmr_t underflow_fifo02_vc2_pop : 1;
8417 mmr_t underflow_fifo13_vc1_pop : 1;
8418 mmr_t underflow_fifo13_vc3_pop : 1;
8419 mmr_t underflow_fifo02_vc0_push : 1;
8420 mmr_t underflow_fifo02_vc2_push : 1;
8421 mmr_t underflow_fifo13_vc1_push : 1;
8422 mmr_t underflow_fifo13_vc3_push : 1;
8423 mmr_t underflow_fifo02_vc0_credit : 1;
8424 mmr_t underflow_fifo02_vc2_credit : 1;
8425 mmr_t underflow_fifo13_vc0_credit : 1;
8426 mmr_t underflow_fifo13_vc2_credit : 1;
8427 mmr_t underflow0_vc0_credit : 1;
8428 mmr_t underflow1_vc0_credit : 1;
8429 mmr_t underflow2_vc0_credit : 1;
8430 mmr_t underflow0_vc2_credit : 1;
8431 mmr_t underflow1_vc2_credit : 1;
8432 mmr_t underflow2_vc2_credit : 1;
8433 mmr_t reserved_0 : 10;
8434 mmr_t underflow_pi_fifo_vc0_pop : 1;
8435 mmr_t underflow_pi_fifo_vc2_pop : 1;
8436 mmr_t underflow_iilb_fifo_vc0_pop : 1;
8437 mmr_t underflow_iilb_fifo_vc2_pop : 1;
8438 mmr_t underflow_md_fifo_vc0_pop : 1;
8439 mmr_t underflow_md_fifo_vc2_pop : 1;
8440 mmr_t underflow_ni_fifo_vc0_pop : 1;
8441 mmr_t underflow_ni_fifo_vc2_pop : 1;
8442 mmr_t underflow_pi_fifo_vc0_push : 1;
8443 mmr_t underflow_pi_fifo_vc2_push : 1;
8444 mmr_t underflow_iilb_fifo_vc0_push : 1;
8445 mmr_t underflow_iilb_fifo_vc2_push : 1;
8446 mmr_t underflow_md_fifo_vc0_push : 1;
8447 mmr_t underflow_md_fifo_vc2_push : 1;
8448 mmr_t underflow_pi_fifo_vc0_credit : 1;
8449 mmr_t underflow_pi_fifo_vc2_credit : 1;
8450 mmr_t underflow_iilb_fifo_vc0_credit : 1;
8451 mmr_t underflow_iilb_fifo_vc2_credit : 1;
8452 mmr_t underflow_md_fifo_vc0_credit : 1;
8453 mmr_t underflow_md_fifo_vc2_credit : 1;
8454 mmr_t underflow_ni_fifo_vc0_credit : 1;
8455 mmr_t underflow_ni_fifo_vc1_credit : 1;
8456 mmr_t underflow_ni_fifo_vc2_credit : 1;
8457 mmr_t underflow_ni_fifo_vc3_credit : 1;
8458 mmr_t llp_deadlock_vc0 : 1;
8459 mmr_t llp_deadlock_vc1 : 1;
8460 mmr_t llp_deadlock_vc2 : 1;
8461 mmr_t llp_deadlock_vc3 : 1;
8462 mmr_t chiplet_nomatch : 1;
8463 mmr_t lut_read_error : 1;
8464 mmr_t retry_timeout_error : 1;
8465 mmr_t reserved_1 : 1;
8466 } sh_ni1_first_error_2_s;
8467 } sh_ni1_first_error_2_u_t;
8469 /* ==================================================================== */
8470 /* Register "SH_NI1_ERROR_DETAIL_1" */
8471 /* ni1 Chiplet no match header bits 63:0 */
8472 /* ==================================================================== */
8474 typedef union sh_ni1_error_detail_1_u {
8475 mmr_t sh_ni1_error_detail_1_regval;
8478 } sh_ni1_error_detail_1_s;
8479 } sh_ni1_error_detail_1_u_t;
8481 /* ==================================================================== */
8482 /* Register "SH_NI1_ERROR_DETAIL_2" */
8483 /* ni1 Chiplet no match header bits 127:64 */
8484 /* ==================================================================== */
8486 typedef union sh_ni1_error_detail_2_u {
8487 mmr_t sh_ni1_error_detail_2_regval;
8490 } sh_ni1_error_detail_2_s;
8491 } sh_ni1_error_detail_2_u_t;
8493 /* ==================================================================== */
8494 /* Register "SH_XN_CORRECTED_DETAIL_1" */
8495 /* Corrected error details */
8496 /* ==================================================================== */
8498 typedef union sh_xn_corrected_detail_1_u {
8499 mmr_t sh_xn_corrected_detail_1_regval;
8501 mmr_t ecc0_syndrome : 8;
8504 mmr_t reserved_0 : 4;
8505 mmr_t ecc1_syndrome : 8;
8508 mmr_t reserved_1 : 4;
8509 mmr_t ecc2_syndrome : 8;
8512 mmr_t reserved_2 : 4;
8513 mmr_t ecc3_syndrome : 8;
8516 mmr_t reserved_3 : 4;
8517 } sh_xn_corrected_detail_1_s;
8518 } sh_xn_corrected_detail_1_u_t;
8520 /* ==================================================================== */
8521 /* Register "SH_XN_CORRECTED_DETAIL_2" */
8522 /* Corrected error data */
8523 /* ==================================================================== */
8525 typedef union sh_xn_corrected_detail_2_u {
8526 mmr_t sh_xn_corrected_detail_2_regval;
8529 } sh_xn_corrected_detail_2_s;
8530 } sh_xn_corrected_detail_2_u_t;
8532 /* ==================================================================== */
8533 /* Register "SH_XN_CORRECTED_DETAIL_3" */
8534 /* Corrected error header0 */
8535 /* ==================================================================== */
8537 typedef union sh_xn_corrected_detail_3_u {
8538 mmr_t sh_xn_corrected_detail_3_regval;
8541 } sh_xn_corrected_detail_3_s;
8542 } sh_xn_corrected_detail_3_u_t;
8544 /* ==================================================================== */
8545 /* Register "SH_XN_CORRECTED_DETAIL_4" */
8546 /* Corrected error header1 */
8547 /* ==================================================================== */
8549 typedef union sh_xn_corrected_detail_4_u {
8550 mmr_t sh_xn_corrected_detail_4_regval;
8553 mmr_t reserved_0 : 20;
8554 mmr_t err_group : 2;
8555 } sh_xn_corrected_detail_4_s;
8556 } sh_xn_corrected_detail_4_u_t;
8558 /* ==================================================================== */
8559 /* Register "SH_XN_UNCORRECTED_DETAIL_1" */
8560 /* Uncorrected error details */
8561 /* ==================================================================== */
8563 typedef union sh_xn_uncorrected_detail_1_u {
8564 mmr_t sh_xn_uncorrected_detail_1_regval;
8566 mmr_t ecc0_syndrome : 8;
8569 mmr_t reserved_0 : 4;
8570 mmr_t ecc1_syndrome : 8;
8573 mmr_t reserved_1 : 4;
8574 mmr_t ecc2_syndrome : 8;
8577 mmr_t reserved_2 : 4;
8578 mmr_t ecc3_syndrome : 8;
8581 mmr_t reserved_3 : 4;
8582 } sh_xn_uncorrected_detail_1_s;
8583 } sh_xn_uncorrected_detail_1_u_t;
8585 /* ==================================================================== */
8586 /* Register "SH_XN_UNCORRECTED_DETAIL_2" */
8587 /* Uncorrected error data */
8588 /* ==================================================================== */
8590 typedef union sh_xn_uncorrected_detail_2_u {
8591 mmr_t sh_xn_uncorrected_detail_2_regval;
8594 } sh_xn_uncorrected_detail_2_s;
8595 } sh_xn_uncorrected_detail_2_u_t;
8597 /* ==================================================================== */
8598 /* Register "SH_XN_UNCORRECTED_DETAIL_3" */
8599 /* Uncorrected error header0 */
8600 /* ==================================================================== */
8602 typedef union sh_xn_uncorrected_detail_3_u {
8603 mmr_t sh_xn_uncorrected_detail_3_regval;
8606 } sh_xn_uncorrected_detail_3_s;
8607 } sh_xn_uncorrected_detail_3_u_t;
8609 /* ==================================================================== */
8610 /* Register "SH_XN_UNCORRECTED_DETAIL_4" */
8611 /* Uncorrected error header1 */
8612 /* ==================================================================== */
8614 typedef union sh_xn_uncorrected_detail_4_u {
8615 mmr_t sh_xn_uncorrected_detail_4_regval;
8618 mmr_t reserved_0 : 20;
8619 mmr_t err_group : 2;
8620 } sh_xn_uncorrected_detail_4_s;
8621 } sh_xn_uncorrected_detail_4_u_t;
8623 /* ==================================================================== */
8624 /* Register "SH_XNMD_ERROR_DETAIL_1" */
8625 /* Look Up Table Address (md) */
8626 /* ==================================================================== */
8628 typedef union sh_xnmd_error_detail_1_u {
8629 mmr_t sh_xnmd_error_detail_1_regval;
8631 mmr_t lut_addr : 11;
8632 mmr_t reserved_0 : 53;
8633 } sh_xnmd_error_detail_1_s;
8634 } sh_xnmd_error_detail_1_u_t;
8636 /* ==================================================================== */
8637 /* Register "SH_XNPI_ERROR_DETAIL_1" */
8638 /* Look Up Table Address (pi) */
8639 /* ==================================================================== */
8641 typedef union sh_xnpi_error_detail_1_u {
8642 mmr_t sh_xnpi_error_detail_1_regval;
8644 mmr_t lut_addr : 11;
8645 mmr_t reserved_0 : 53;
8646 } sh_xnpi_error_detail_1_s;
8647 } sh_xnpi_error_detail_1_u_t;
8649 /* ==================================================================== */
8650 /* Register "SH_XNIILB_ERROR_DETAIL_1" */
8651 /* Chiplet NoMatch header [63:0] */
8652 /* ==================================================================== */
8654 typedef union sh_xniilb_error_detail_1_u {
8655 mmr_t sh_xniilb_error_detail_1_regval;
8658 } sh_xniilb_error_detail_1_s;
8659 } sh_xniilb_error_detail_1_u_t;
8661 /* ==================================================================== */
8662 /* Register "SH_XNIILB_ERROR_DETAIL_2" */
8663 /* Chiplet NoMatch header [127:64] */
8664 /* ==================================================================== */
8666 typedef union sh_xniilb_error_detail_2_u {
8667 mmr_t sh_xniilb_error_detail_2_regval;
8670 } sh_xniilb_error_detail_2_s;
8671 } sh_xniilb_error_detail_2_u_t;
8673 /* ==================================================================== */
8674 /* Register "SH_XNIILB_ERROR_DETAIL_3" */
8675 /* Look Up Table Address (iilb) */
8676 /* ==================================================================== */
8678 typedef union sh_xniilb_error_detail_3_u {
8679 mmr_t sh_xniilb_error_detail_3_regval;
8681 mmr_t lut_addr : 11;
8682 mmr_t reserved_0 : 53;
8683 } sh_xniilb_error_detail_3_s;
8684 } sh_xniilb_error_detail_3_u_t;
8686 /* ==================================================================== */
8687 /* Register "SH_NI0_ERROR_DETAIL_3" */
8688 /* Look Up Table Address (ni0) */
8689 /* ==================================================================== */
8691 typedef union sh_ni0_error_detail_3_u {
8692 mmr_t sh_ni0_error_detail_3_regval;
8694 mmr_t lut_addr : 11;
8695 mmr_t reserved_0 : 53;
8696 } sh_ni0_error_detail_3_s;
8697 } sh_ni0_error_detail_3_u_t;
8699 /* ==================================================================== */
8700 /* Register "SH_NI1_ERROR_DETAIL_3" */
8701 /* Look Up Table Address (ni1) */
8702 /* ==================================================================== */
8704 typedef union sh_ni1_error_detail_3_u {
8705 mmr_t sh_ni1_error_detail_3_regval;
8707 mmr_t lut_addr : 11;
8708 mmr_t reserved_0 : 53;
8709 } sh_ni1_error_detail_3_s;
8710 } sh_ni1_error_detail_3_u_t;
8712 /* ==================================================================== */
8713 /* Register "SH_XN_ERROR_SUMMARY" */
8714 /* ==================================================================== */
8716 typedef union sh_xn_error_summary_u {
8717 mmr_t sh_xn_error_summary_regval;
8719 mmr_t ni0_pop_overflow : 1;
8720 mmr_t ni0_push_overflow : 1;
8721 mmr_t ni0_credit_overflow : 1;
8722 mmr_t ni0_debit_overflow : 1;
8723 mmr_t ni0_pop_underflow : 1;
8724 mmr_t ni0_push_underflow : 1;
8725 mmr_t ni0_credit_underflow : 1;
8726 mmr_t ni0_llp_error : 1;
8727 mmr_t ni0_pipe_error : 1;
8728 mmr_t ni1_pop_overflow : 1;
8729 mmr_t ni1_push_overflow : 1;
8730 mmr_t ni1_credit_overflow : 1;
8731 mmr_t ni1_debit_overflow : 1;
8732 mmr_t ni1_pop_underflow : 1;
8733 mmr_t ni1_push_underflow : 1;
8734 mmr_t ni1_credit_underflow : 1;
8735 mmr_t ni1_llp_error : 1;
8736 mmr_t ni1_pipe_error : 1;
8737 mmr_t xnmd_credit_overflow : 1;
8738 mmr_t xnmd_debit_overflow : 1;
8739 mmr_t xnmd_data_buff_overflow : 1;
8740 mmr_t xnmd_credit_underflow : 1;
8741 mmr_t xnmd_sbe_error : 1;
8742 mmr_t xnmd_uce_error : 1;
8743 mmr_t xnmd_lut_error : 1;
8744 mmr_t xnpi_credit_overflow : 1;
8745 mmr_t xnpi_debit_overflow : 1;
8746 mmr_t xnpi_data_buff_overflow : 1;
8747 mmr_t xnpi_credit_underflow : 1;
8748 mmr_t xnpi_sbe_error : 1;
8749 mmr_t xnpi_uce_error : 1;
8750 mmr_t xnpi_lut_error : 1;
8751 mmr_t iilb_debit_overflow : 1;
8752 mmr_t iilb_credit_overflow : 1;
8753 mmr_t iilb_fifo_overflow : 1;
8754 mmr_t iilb_credit_underflow : 1;
8755 mmr_t iilb_fifo_underflow : 1;
8756 mmr_t iilb_chiplet_or_lut : 1;
8757 mmr_t reserved_0 : 26;
8758 } sh_xn_error_summary_s;
8759 } sh_xn_error_summary_u_t;
8761 /* ==================================================================== */
8762 /* Register "SH_XN_ERROR_OVERFLOW" */
8763 /* ==================================================================== */
8765 typedef union sh_xn_error_overflow_u {
8766 mmr_t sh_xn_error_overflow_regval;
8768 mmr_t ni0_pop_overflow : 1;
8769 mmr_t ni0_push_overflow : 1;
8770 mmr_t ni0_credit_overflow : 1;
8771 mmr_t ni0_debit_overflow : 1;
8772 mmr_t ni0_pop_underflow : 1;
8773 mmr_t ni0_push_underflow : 1;
8774 mmr_t ni0_credit_underflow : 1;
8775 mmr_t ni0_llp_error : 1;
8776 mmr_t ni0_pipe_error : 1;
8777 mmr_t ni1_pop_overflow : 1;
8778 mmr_t ni1_push_overflow : 1;
8779 mmr_t ni1_credit_overflow : 1;
8780 mmr_t ni1_debit_overflow : 1;
8781 mmr_t ni1_pop_underflow : 1;
8782 mmr_t ni1_push_underflow : 1;
8783 mmr_t ni1_credit_underflow : 1;
8784 mmr_t ni1_llp_error : 1;
8785 mmr_t ni1_pipe_error : 1;
8786 mmr_t xnmd_credit_overflow : 1;
8787 mmr_t xnmd_debit_overflow : 1;
8788 mmr_t xnmd_data_buff_overflow : 1;
8789 mmr_t xnmd_credit_underflow : 1;
8790 mmr_t xnmd_sbe_error : 1;
8791 mmr_t xnmd_uce_error : 1;
8792 mmr_t xnmd_lut_error : 1;
8793 mmr_t xnpi_credit_overflow : 1;
8794 mmr_t xnpi_debit_overflow : 1;
8795 mmr_t xnpi_data_buff_overflow : 1;
8796 mmr_t xnpi_credit_underflow : 1;
8797 mmr_t xnpi_sbe_error : 1;
8798 mmr_t xnpi_uce_error : 1;
8799 mmr_t xnpi_lut_error : 1;
8800 mmr_t iilb_debit_overflow : 1;
8801 mmr_t iilb_credit_overflow : 1;
8802 mmr_t iilb_fifo_overflow : 1;
8803 mmr_t iilb_credit_underflow : 1;
8804 mmr_t iilb_fifo_underflow : 1;
8805 mmr_t iilb_chiplet_or_lut : 1;
8806 mmr_t reserved_0 : 26;
8807 } sh_xn_error_overflow_s;
8808 } sh_xn_error_overflow_u_t;
8810 /* ==================================================================== */
8811 /* Register "SH_XN_ERROR_MASK" */
8812 /* ==================================================================== */
8814 typedef union sh_xn_error_mask_u {
8815 mmr_t sh_xn_error_mask_regval;
8817 mmr_t ni0_pop_overflow : 1;
8818 mmr_t ni0_push_overflow : 1;
8819 mmr_t ni0_credit_overflow : 1;
8820 mmr_t ni0_debit_overflow : 1;
8821 mmr_t ni0_pop_underflow : 1;
8822 mmr_t ni0_push_underflow : 1;
8823 mmr_t ni0_credit_underflow : 1;
8824 mmr_t ni0_llp_error : 1;
8825 mmr_t ni0_pipe_error : 1;
8826 mmr_t ni1_pop_overflow : 1;
8827 mmr_t ni1_push_overflow : 1;
8828 mmr_t ni1_credit_overflow : 1;
8829 mmr_t ni1_debit_overflow : 1;
8830 mmr_t ni1_pop_underflow : 1;
8831 mmr_t ni1_push_underflow : 1;
8832 mmr_t ni1_credit_underflow : 1;
8833 mmr_t ni1_llp_error : 1;
8834 mmr_t ni1_pipe_error : 1;
8835 mmr_t xnmd_credit_overflow : 1;
8836 mmr_t xnmd_debit_overflow : 1;
8837 mmr_t xnmd_data_buff_overflow : 1;
8838 mmr_t xnmd_credit_underflow : 1;
8839 mmr_t xnmd_sbe_error : 1;
8840 mmr_t xnmd_uce_error : 1;
8841 mmr_t xnmd_lut_error : 1;
8842 mmr_t xnpi_credit_overflow : 1;
8843 mmr_t xnpi_debit_overflow : 1;
8844 mmr_t xnpi_data_buff_overflow : 1;
8845 mmr_t xnpi_credit_underflow : 1;
8846 mmr_t xnpi_sbe_error : 1;
8847 mmr_t xnpi_uce_error : 1;
8848 mmr_t xnpi_lut_error : 1;
8849 mmr_t iilb_debit_overflow : 1;
8850 mmr_t iilb_credit_overflow : 1;
8851 mmr_t iilb_fifo_overflow : 1;
8852 mmr_t iilb_credit_underflow : 1;
8853 mmr_t iilb_fifo_underflow : 1;
8854 mmr_t iilb_chiplet_or_lut : 1;
8855 mmr_t reserved_0 : 26;
8856 } sh_xn_error_mask_s;
8857 } sh_xn_error_mask_u_t;
8859 /* ==================================================================== */
8860 /* Register "SH_XN_FIRST_ERROR" */
8861 /* ==================================================================== */
8863 typedef union sh_xn_first_error_u {
8864 mmr_t sh_xn_first_error_regval;
8866 mmr_t ni0_pop_overflow : 1;
8867 mmr_t ni0_push_overflow : 1;
8868 mmr_t ni0_credit_overflow : 1;
8869 mmr_t ni0_debit_overflow : 1;
8870 mmr_t ni0_pop_underflow : 1;
8871 mmr_t ni0_push_underflow : 1;
8872 mmr_t ni0_credit_underflow : 1;
8873 mmr_t ni0_llp_error : 1;
8874 mmr_t ni0_pipe_error : 1;
8875 mmr_t ni1_pop_overflow : 1;
8876 mmr_t ni1_push_overflow : 1;
8877 mmr_t ni1_credit_overflow : 1;
8878 mmr_t ni1_debit_overflow : 1;
8879 mmr_t ni1_pop_underflow : 1;
8880 mmr_t ni1_push_underflow : 1;
8881 mmr_t ni1_credit_underflow : 1;
8882 mmr_t ni1_llp_error : 1;
8883 mmr_t ni1_pipe_error : 1;
8884 mmr_t xnmd_credit_overflow : 1;
8885 mmr_t xnmd_debit_overflow : 1;
8886 mmr_t xnmd_data_buff_overflow : 1;
8887 mmr_t xnmd_credit_underflow : 1;
8888 mmr_t xnmd_sbe_error : 1;
8889 mmr_t xnmd_uce_error : 1;
8890 mmr_t xnmd_lut_error : 1;
8891 mmr_t xnpi_credit_overflow : 1;
8892 mmr_t xnpi_debit_overflow : 1;
8893 mmr_t xnpi_data_buff_overflow : 1;
8894 mmr_t xnpi_credit_underflow : 1;
8895 mmr_t xnpi_sbe_error : 1;
8896 mmr_t xnpi_uce_error : 1;
8897 mmr_t xnpi_lut_error : 1;
8898 mmr_t iilb_debit_overflow : 1;
8899 mmr_t iilb_credit_overflow : 1;
8900 mmr_t iilb_fifo_overflow : 1;
8901 mmr_t iilb_credit_underflow : 1;
8902 mmr_t iilb_fifo_underflow : 1;
8903 mmr_t iilb_chiplet_or_lut : 1;
8904 mmr_t reserved_0 : 26;
8905 } sh_xn_first_error_s;
8906 } sh_xn_first_error_u_t;
8908 /* ==================================================================== */
8909 /* Register "SH_XNIILB_ERROR_SUMMARY" */
8910 /* ==================================================================== */
8912 typedef union sh_xniilb_error_summary_u {
8913 mmr_t sh_xniilb_error_summary_regval;
8915 mmr_t overflow_ii_debit0 : 1;
8916 mmr_t overflow_ii_debit2 : 1;
8917 mmr_t overflow_lb_debit0 : 1;
8918 mmr_t overflow_lb_debit2 : 1;
8919 mmr_t overflow_ii_vc0 : 1;
8920 mmr_t overflow_ii_vc2 : 1;
8921 mmr_t underflow_ii_vc0 : 1;
8922 mmr_t underflow_ii_vc2 : 1;
8923 mmr_t overflow_lb_vc0 : 1;
8924 mmr_t overflow_lb_vc2 : 1;
8925 mmr_t underflow_lb_vc0 : 1;
8926 mmr_t underflow_lb_vc2 : 1;
8927 mmr_t overflow_pi_vc0_credit_in : 1;
8928 mmr_t overflow_iilb_vc0_credit_in : 1;
8929 mmr_t overflow_md_vc0_credit_in : 1;
8930 mmr_t overflow_ni0_vc0_credit_in : 1;
8931 mmr_t overflow_ni1_vc0_credit_in : 1;
8932 mmr_t overflow_pi_vc2_credit_in : 1;
8933 mmr_t overflow_iilb_vc2_credit_in : 1;
8934 mmr_t overflow_md_vc2_credit_in : 1;
8935 mmr_t overflow_ni0_vc2_credit_in : 1;
8936 mmr_t overflow_ni1_vc2_credit_in : 1;
8937 mmr_t underflow_pi_vc0_credit_in : 1;
8938 mmr_t underflow_iilb_vc0_credit_in : 1;
8939 mmr_t underflow_md_vc0_credit_in : 1;
8940 mmr_t underflow_ni0_vc0_credit_in : 1;
8941 mmr_t underflow_ni1_vc0_credit_in : 1;
8942 mmr_t underflow_pi_vc2_credit_in : 1;
8943 mmr_t underflow_iilb_vc2_credit_in : 1;
8944 mmr_t underflow_md_vc2_credit_in : 1;
8945 mmr_t underflow_ni0_vc2_credit_in : 1;
8946 mmr_t underflow_ni1_vc2_credit_in : 1;
8947 mmr_t overflow_pi_debit0 : 1;
8948 mmr_t overflow_pi_debit2 : 1;
8949 mmr_t overflow_iilb_debit0 : 1;
8950 mmr_t overflow_iilb_debit2 : 1;
8951 mmr_t overflow_md_debit0 : 1;
8952 mmr_t overflow_md_debit2 : 1;
8953 mmr_t overflow_ni0_debit0 : 1;
8954 mmr_t overflow_ni0_debit2 : 1;
8955 mmr_t overflow_ni1_debit0 : 1;
8956 mmr_t overflow_ni1_debit2 : 1;
8957 mmr_t overflow_pi_vc0_credit_out : 1;
8958 mmr_t overflow_pi_vc2_credit_out : 1;
8959 mmr_t overflow_md_vc0_credit_out : 1;
8960 mmr_t overflow_md_vc2_credit_out : 1;
8961 mmr_t overflow_iilb_vc0_credit_out : 1;
8962 mmr_t overflow_iilb_vc2_credit_out : 1;
8963 mmr_t overflow_ni0_vc0_credit_out : 1;
8964 mmr_t overflow_ni0_vc2_credit_out : 1;
8965 mmr_t overflow_ni1_vc0_credit_out : 1;
8966 mmr_t overflow_ni1_vc2_credit_out : 1;
8967 mmr_t underflow_pi_vc0_credit_out : 1;
8968 mmr_t underflow_pi_vc2_credit_out : 1;
8969 mmr_t underflow_md_vc0_credit_out : 1;
8970 mmr_t underflow_md_vc2_credit_out : 1;
8971 mmr_t underflow_iilb_vc0_credit_out : 1;
8972 mmr_t underflow_iilb_vc2_credit_out : 1;
8973 mmr_t underflow_ni0_vc0_credit_out : 1;
8974 mmr_t underflow_ni0_vc2_credit_out : 1;
8975 mmr_t underflow_ni1_vc0_credit_out : 1;
8976 mmr_t underflow_ni1_vc2_credit_out : 1;
8977 mmr_t chiplet_nomatch : 1;
8978 mmr_t lut_read_error : 1;
8979 } sh_xniilb_error_summary_s;
8980 } sh_xniilb_error_summary_u_t;
8982 /* ==================================================================== */
8983 /* Register "SH_XNIILB_ERROR_OVERFLOW" */
8984 /* ==================================================================== */
8986 typedef union sh_xniilb_error_overflow_u {
8987 mmr_t sh_xniilb_error_overflow_regval;
8989 mmr_t overflow_ii_debit0 : 1;
8990 mmr_t overflow_ii_debit2 : 1;
8991 mmr_t overflow_lb_debit0 : 1;
8992 mmr_t overflow_lb_debit2 : 1;
8993 mmr_t overflow_ii_vc0 : 1;
8994 mmr_t overflow_ii_vc2 : 1;
8995 mmr_t underflow_ii_vc0 : 1;
8996 mmr_t underflow_ii_vc2 : 1;
8997 mmr_t overflow_lb_vc0 : 1;
8998 mmr_t overflow_lb_vc2 : 1;
8999 mmr_t underflow_lb_vc0 : 1;
9000 mmr_t underflow_lb_vc2 : 1;
9001 mmr_t overflow_pi_vc0_credit_in : 1;
9002 mmr_t overflow_iilb_vc0_credit_in : 1;
9003 mmr_t overflow_md_vc0_credit_in : 1;
9004 mmr_t overflow_ni0_vc0_credit_in : 1;
9005 mmr_t overflow_ni1_vc0_credit_in : 1;
9006 mmr_t overflow_pi_vc2_credit_in : 1;
9007 mmr_t overflow_iilb_vc2_credit_in : 1;
9008 mmr_t overflow_md_vc2_credit_in : 1;
9009 mmr_t overflow_ni0_vc2_credit_in : 1;
9010 mmr_t overflow_ni1_vc2_credit_in : 1;
9011 mmr_t underflow_pi_vc0_credit_in : 1;
9012 mmr_t underflow_iilb_vc0_credit_in : 1;
9013 mmr_t underflow_md_vc0_credit_in : 1;
9014 mmr_t underflow_ni0_vc0_credit_in : 1;
9015 mmr_t underflow_ni1_vc0_credit_in : 1;
9016 mmr_t underflow_pi_vc2_credit_in : 1;
9017 mmr_t underflow_iilb_vc2_credit_in : 1;
9018 mmr_t underflow_md_vc2_credit_in : 1;
9019 mmr_t underflow_ni0_vc2_credit_in : 1;
9020 mmr_t underflow_ni1_vc2_credit_in : 1;
9021 mmr_t overflow_pi_debit0 : 1;
9022 mmr_t overflow_pi_debit2 : 1;
9023 mmr_t overflow_iilb_debit0 : 1;
9024 mmr_t overflow_iilb_debit2 : 1;
9025 mmr_t overflow_md_debit0 : 1;
9026 mmr_t overflow_md_debit2 : 1;
9027 mmr_t overflow_ni0_debit0 : 1;
9028 mmr_t overflow_ni0_debit2 : 1;
9029 mmr_t overflow_ni1_debit0 : 1;
9030 mmr_t overflow_ni1_debit2 : 1;
9031 mmr_t overflow_pi_vc0_credit_out : 1;
9032 mmr_t overflow_pi_vc2_credit_out : 1;
9033 mmr_t overflow_md_vc0_credit_out : 1;
9034 mmr_t overflow_md_vc2_credit_out : 1;
9035 mmr_t overflow_iilb_vc0_credit_out : 1;
9036 mmr_t overflow_iilb_vc2_credit_out : 1;
9037 mmr_t overflow_ni0_vc0_credit_out : 1;
9038 mmr_t overflow_ni0_vc2_credit_out : 1;
9039 mmr_t overflow_ni1_vc0_credit_out : 1;
9040 mmr_t overflow_ni1_vc2_credit_out : 1;
9041 mmr_t underflow_pi_vc0_credit_out : 1;
9042 mmr_t underflow_pi_vc2_credit_out : 1;
9043 mmr_t underflow_md_vc0_credit_out : 1;
9044 mmr_t underflow_md_vc2_credit_out : 1;
9045 mmr_t underflow_iilb_vc0_credit_out : 1;
9046 mmr_t underflow_iilb_vc2_credit_out : 1;
9047 mmr_t underflow_ni0_vc0_credit_out : 1;
9048 mmr_t underflow_ni0_vc2_credit_out : 1;
9049 mmr_t underflow_ni1_vc0_credit_out : 1;
9050 mmr_t underflow_ni1_vc2_credit_out : 1;
9051 mmr_t chiplet_nomatch : 1;
9052 mmr_t lut_read_error : 1;
9053 } sh_xniilb_error_overflow_s;
9054 } sh_xniilb_error_overflow_u_t;
9056 /* ==================================================================== */
9057 /* Register "SH_XNIILB_ERROR_MASK" */
9058 /* ==================================================================== */
9060 typedef union sh_xniilb_error_mask_u {
9061 mmr_t sh_xniilb_error_mask_regval;
9063 mmr_t overflow_ii_debit0 : 1;
9064 mmr_t overflow_ii_debit2 : 1;
9065 mmr_t overflow_lb_debit0 : 1;
9066 mmr_t overflow_lb_debit2 : 1;
9067 mmr_t overflow_ii_vc0 : 1;
9068 mmr_t overflow_ii_vc2 : 1;
9069 mmr_t underflow_ii_vc0 : 1;
9070 mmr_t underflow_ii_vc2 : 1;
9071 mmr_t overflow_lb_vc0 : 1;
9072 mmr_t overflow_lb_vc2 : 1;
9073 mmr_t underflow_lb_vc0 : 1;
9074 mmr_t underflow_lb_vc2 : 1;
9075 mmr_t overflow_pi_vc0_credit_in : 1;
9076 mmr_t overflow_iilb_vc0_credit_in : 1;
9077 mmr_t overflow_md_vc0_credit_in : 1;
9078 mmr_t overflow_ni0_vc0_credit_in : 1;
9079 mmr_t overflow_ni1_vc0_credit_in : 1;
9080 mmr_t overflow_pi_vc2_credit_in : 1;
9081 mmr_t overflow_iilb_vc2_credit_in : 1;
9082 mmr_t overflow_md_vc2_credit_in : 1;
9083 mmr_t overflow_ni0_vc2_credit_in : 1;
9084 mmr_t overflow_ni1_vc2_credit_in : 1;
9085 mmr_t underflow_pi_vc0_credit_in : 1;
9086 mmr_t underflow_iilb_vc0_credit_in : 1;
9087 mmr_t underflow_md_vc0_credit_in : 1;
9088 mmr_t underflow_ni0_vc0_credit_in : 1;
9089 mmr_t underflow_ni1_vc0_credit_in : 1;
9090 mmr_t underflow_pi_vc2_credit_in : 1;
9091 mmr_t underflow_iilb_vc2_credit_in : 1;
9092 mmr_t underflow_md_vc2_credit_in : 1;
9093 mmr_t underflow_ni0_vc2_credit_in : 1;
9094 mmr_t underflow_ni1_vc2_credit_in : 1;
9095 mmr_t overflow_pi_debit0 : 1;
9096 mmr_t overflow_pi_debit2 : 1;
9097 mmr_t overflow_iilb_debit0 : 1;
9098 mmr_t overflow_iilb_debit2 : 1;
9099 mmr_t overflow_md_debit0 : 1;
9100 mmr_t overflow_md_debit2 : 1;
9101 mmr_t overflow_ni0_debit0 : 1;
9102 mmr_t overflow_ni0_debit2 : 1;
9103 mmr_t overflow_ni1_debit0 : 1;
9104 mmr_t overflow_ni1_debit2 : 1;
9105 mmr_t overflow_pi_vc0_credit_out : 1;
9106 mmr_t overflow_pi_vc2_credit_out : 1;
9107 mmr_t overflow_md_vc0_credit_out : 1;
9108 mmr_t overflow_md_vc2_credit_out : 1;
9109 mmr_t overflow_iilb_vc0_credit_out : 1;
9110 mmr_t overflow_iilb_vc2_credit_out : 1;
9111 mmr_t overflow_ni0_vc0_credit_out : 1;
9112 mmr_t overflow_ni0_vc2_credit_out : 1;
9113 mmr_t overflow_ni1_vc0_credit_out : 1;
9114 mmr_t overflow_ni1_vc2_credit_out : 1;
9115 mmr_t underflow_pi_vc0_credit_out : 1;
9116 mmr_t underflow_pi_vc2_credit_out : 1;
9117 mmr_t underflow_md_vc0_credit_out : 1;
9118 mmr_t underflow_md_vc2_credit_out : 1;
9119 mmr_t underflow_iilb_vc0_credit_out : 1;
9120 mmr_t underflow_iilb_vc2_credit_out : 1;
9121 mmr_t underflow_ni0_vc0_credit_out : 1;
9122 mmr_t underflow_ni0_vc2_credit_out : 1;
9123 mmr_t underflow_ni1_vc0_credit_out : 1;
9124 mmr_t underflow_ni1_vc2_credit_out : 1;
9125 mmr_t chiplet_nomatch : 1;
9126 mmr_t lut_read_error : 1;
9127 } sh_xniilb_error_mask_s;
9128 } sh_xniilb_error_mask_u_t;
9130 /* ==================================================================== */
9131 /* Register "SH_XNIILB_FIRST_ERROR" */
9132 /* ==================================================================== */
9134 typedef union sh_xniilb_first_error_u {
9135 mmr_t sh_xniilb_first_error_regval;
9137 mmr_t overflow_ii_debit0 : 1;
9138 mmr_t overflow_ii_debit2 : 1;
9139 mmr_t overflow_lb_debit0 : 1;
9140 mmr_t overflow_lb_debit2 : 1;
9141 mmr_t overflow_ii_vc0 : 1;
9142 mmr_t overflow_ii_vc2 : 1;
9143 mmr_t underflow_ii_vc0 : 1;
9144 mmr_t underflow_ii_vc2 : 1;
9145 mmr_t overflow_lb_vc0 : 1;
9146 mmr_t overflow_lb_vc2 : 1;
9147 mmr_t underflow_lb_vc0 : 1;
9148 mmr_t underflow_lb_vc2 : 1;
9149 mmr_t overflow_pi_vc0_credit_in : 1;
9150 mmr_t overflow_iilb_vc0_credit_in : 1;
9151 mmr_t overflow_md_vc0_credit_in : 1;
9152 mmr_t overflow_ni0_vc0_credit_in : 1;
9153 mmr_t overflow_ni1_vc0_credit_in : 1;
9154 mmr_t overflow_pi_vc2_credit_in : 1;
9155 mmr_t overflow_iilb_vc2_credit_in : 1;
9156 mmr_t overflow_md_vc2_credit_in : 1;
9157 mmr_t overflow_ni0_vc2_credit_in : 1;
9158 mmr_t overflow_ni1_vc2_credit_in : 1;
9159 mmr_t underflow_pi_vc0_credit_in : 1;
9160 mmr_t underflow_iilb_vc0_credit_in : 1;
9161 mmr_t underflow_md_vc0_credit_in : 1;
9162 mmr_t underflow_ni0_vc0_credit_in : 1;
9163 mmr_t underflow_ni1_vc0_credit_in : 1;
9164 mmr_t underflow_pi_vc2_credit_in : 1;
9165 mmr_t underflow_iilb_vc2_credit_in : 1;
9166 mmr_t underflow_md_vc2_credit_in : 1;
9167 mmr_t underflow_ni0_vc2_credit_in : 1;
9168 mmr_t underflow_ni1_vc2_credit_in : 1;
9169 mmr_t overflow_pi_debit0 : 1;
9170 mmr_t overflow_pi_debit2 : 1;
9171 mmr_t overflow_iilb_debit0 : 1;
9172 mmr_t overflow_iilb_debit2 : 1;
9173 mmr_t overflow_md_debit0 : 1;
9174 mmr_t overflow_md_debit2 : 1;
9175 mmr_t overflow_ni0_debit0 : 1;
9176 mmr_t overflow_ni0_debit2 : 1;
9177 mmr_t overflow_ni1_debit0 : 1;
9178 mmr_t overflow_ni1_debit2 : 1;
9179 mmr_t overflow_pi_vc0_credit_out : 1;
9180 mmr_t overflow_pi_vc2_credit_out : 1;
9181 mmr_t overflow_md_vc0_credit_out : 1;
9182 mmr_t overflow_md_vc2_credit_out : 1;
9183 mmr_t overflow_iilb_vc0_credit_out : 1;
9184 mmr_t overflow_iilb_vc2_credit_out : 1;
9185 mmr_t overflow_ni0_vc0_credit_out : 1;
9186 mmr_t overflow_ni0_vc2_credit_out : 1;
9187 mmr_t overflow_ni1_vc0_credit_out : 1;
9188 mmr_t overflow_ni1_vc2_credit_out : 1;
9189 mmr_t underflow_pi_vc0_credit_out : 1;
9190 mmr_t underflow_pi_vc2_credit_out : 1;
9191 mmr_t underflow_md_vc0_credit_out : 1;
9192 mmr_t underflow_md_vc2_credit_out : 1;
9193 mmr_t underflow_iilb_vc0_credit_out : 1;
9194 mmr_t underflow_iilb_vc2_credit_out : 1;
9195 mmr_t underflow_ni0_vc0_credit_out : 1;
9196 mmr_t underflow_ni0_vc2_credit_out : 1;
9197 mmr_t underflow_ni1_vc0_credit_out : 1;
9198 mmr_t underflow_ni1_vc2_credit_out : 1;
9199 mmr_t chiplet_nomatch : 1;
9200 mmr_t lut_read_error : 1;
9201 } sh_xniilb_first_error_s;
9202 } sh_xniilb_first_error_u_t;
9204 /* ==================================================================== */
9205 /* Register "SH_XNPI_ERROR_SUMMARY" */
9206 /* ==================================================================== */
9208 typedef union sh_xnpi_error_summary_u {
9209 mmr_t sh_xnpi_error_summary_regval;
9211 mmr_t underflow_ni0_vc0 : 1;
9212 mmr_t overflow_ni0_vc0 : 1;
9213 mmr_t underflow_ni0_vc2 : 1;
9214 mmr_t overflow_ni0_vc2 : 1;
9215 mmr_t underflow_ni1_vc0 : 1;
9216 mmr_t overflow_ni1_vc0 : 1;
9217 mmr_t underflow_ni1_vc2 : 1;
9218 mmr_t overflow_ni1_vc2 : 1;
9219 mmr_t underflow_iilb_vc0 : 1;
9220 mmr_t overflow_iilb_vc0 : 1;
9221 mmr_t underflow_iilb_vc2 : 1;
9222 mmr_t overflow_iilb_vc2 : 1;
9223 mmr_t underflow_vc0_credit : 1;
9224 mmr_t overflow_vc0_credit : 1;
9225 mmr_t underflow_vc2_credit : 1;
9226 mmr_t overflow_vc2_credit : 1;
9227 mmr_t overflow_databuff_vc0 : 1;
9228 mmr_t overflow_databuff_vc2 : 1;
9229 mmr_t lut_read_error : 1;
9230 mmr_t single_bit_error0 : 1;
9231 mmr_t single_bit_error1 : 1;
9232 mmr_t single_bit_error2 : 1;
9233 mmr_t single_bit_error3 : 1;
9234 mmr_t uncor_error0 : 1;
9235 mmr_t uncor_error1 : 1;
9236 mmr_t uncor_error2 : 1;
9237 mmr_t uncor_error3 : 1;
9238 mmr_t underflow_sic_cntr0 : 1;
9239 mmr_t overflow_sic_cntr0 : 1;
9240 mmr_t underflow_sic_cntr2 : 1;
9241 mmr_t overflow_sic_cntr2 : 1;
9242 mmr_t overflow_ni0_debit0 : 1;
9243 mmr_t overflow_ni0_debit2 : 1;
9244 mmr_t overflow_ni1_debit0 : 1;
9245 mmr_t overflow_ni1_debit2 : 1;
9246 mmr_t overflow_iilb_debit0 : 1;
9247 mmr_t overflow_iilb_debit2 : 1;
9248 mmr_t underflow_ni0_vc0_credit : 1;
9249 mmr_t overflow_ni0_vc0_credit : 1;
9250 mmr_t underflow_ni0_vc2_credit : 1;
9251 mmr_t overflow_ni0_vc2_credit : 1;
9252 mmr_t underflow_ni1_vc0_credit : 1;
9253 mmr_t overflow_ni1_vc0_credit : 1;
9254 mmr_t underflow_ni1_vc2_credit : 1;
9255 mmr_t overflow_ni1_vc2_credit : 1;
9256 mmr_t underflow_iilb_vc0_credit : 1;
9257 mmr_t overflow_iilb_vc0_credit : 1;
9258 mmr_t underflow_iilb_vc2_credit : 1;
9259 mmr_t overflow_iilb_vc2_credit : 1;
9260 mmr_t overflow_header_cancel_fifo : 1;
9261 mmr_t reserved_0 : 14;
9262 } sh_xnpi_error_summary_s;
9263 } sh_xnpi_error_summary_u_t;
9265 /* ==================================================================== */
9266 /* Register "SH_XNPI_ERROR_OVERFLOW" */
9267 /* ==================================================================== */
9269 typedef union sh_xnpi_error_overflow_u {
9270 mmr_t sh_xnpi_error_overflow_regval;
9272 mmr_t underflow_ni0_vc0 : 1;
9273 mmr_t overflow_ni0_vc0 : 1;
9274 mmr_t underflow_ni0_vc2 : 1;
9275 mmr_t overflow_ni0_vc2 : 1;
9276 mmr_t underflow_ni1_vc0 : 1;
9277 mmr_t overflow_ni1_vc0 : 1;
9278 mmr_t underflow_ni1_vc2 : 1;
9279 mmr_t overflow_ni1_vc2 : 1;
9280 mmr_t underflow_iilb_vc0 : 1;
9281 mmr_t overflow_iilb_vc0 : 1;
9282 mmr_t underflow_iilb_vc2 : 1;
9283 mmr_t overflow_iilb_vc2 : 1;
9284 mmr_t underflow_vc0_credit : 1;
9285 mmr_t overflow_vc0_credit : 1;
9286 mmr_t underflow_vc2_credit : 1;
9287 mmr_t overflow_vc2_credit : 1;
9288 mmr_t overflow_databuff_vc0 : 1;
9289 mmr_t overflow_databuff_vc2 : 1;
9290 mmr_t lut_read_error : 1;
9291 mmr_t single_bit_error0 : 1;
9292 mmr_t single_bit_error1 : 1;
9293 mmr_t single_bit_error2 : 1;
9294 mmr_t single_bit_error3 : 1;
9295 mmr_t uncor_error0 : 1;
9296 mmr_t uncor_error1 : 1;
9297 mmr_t uncor_error2 : 1;
9298 mmr_t uncor_error3 : 1;
9299 mmr_t underflow_sic_cntr0 : 1;
9300 mmr_t overflow_sic_cntr0 : 1;
9301 mmr_t underflow_sic_cntr2 : 1;
9302 mmr_t overflow_sic_cntr2 : 1;
9303 mmr_t overflow_ni0_debit0 : 1;
9304 mmr_t overflow_ni0_debit2 : 1;
9305 mmr_t overflow_ni1_debit0 : 1;
9306 mmr_t overflow_ni1_debit2 : 1;
9307 mmr_t overflow_iilb_debit0 : 1;
9308 mmr_t overflow_iilb_debit2 : 1;
9309 mmr_t underflow_ni0_vc0_credit : 1;
9310 mmr_t overflow_ni0_vc0_credit : 1;
9311 mmr_t underflow_ni0_vc2_credit : 1;
9312 mmr_t overflow_ni0_vc2_credit : 1;
9313 mmr_t underflow_ni1_vc0_credit : 1;
9314 mmr_t overflow_ni1_vc0_credit : 1;
9315 mmr_t underflow_ni1_vc2_credit : 1;
9316 mmr_t overflow_ni1_vc2_credit : 1;
9317 mmr_t underflow_iilb_vc0_credit : 1;
9318 mmr_t overflow_iilb_vc0_credit : 1;
9319 mmr_t underflow_iilb_vc2_credit : 1;
9320 mmr_t overflow_iilb_vc2_credit : 1;
9321 mmr_t overflow_header_cancel_fifo : 1;
9322 mmr_t reserved_0 : 14;
9323 } sh_xnpi_error_overflow_s;
9324 } sh_xnpi_error_overflow_u_t;
9326 /* ==================================================================== */
9327 /* Register "SH_XNPI_ERROR_MASK" */
9328 /* ==================================================================== */
9330 typedef union sh_xnpi_error_mask_u {
9331 mmr_t sh_xnpi_error_mask_regval;
9333 mmr_t underflow_ni0_vc0 : 1;
9334 mmr_t overflow_ni0_vc0 : 1;
9335 mmr_t underflow_ni0_vc2 : 1;
9336 mmr_t overflow_ni0_vc2 : 1;
9337 mmr_t underflow_ni1_vc0 : 1;
9338 mmr_t overflow_ni1_vc0 : 1;
9339 mmr_t underflow_ni1_vc2 : 1;
9340 mmr_t overflow_ni1_vc2 : 1;
9341 mmr_t underflow_iilb_vc0 : 1;
9342 mmr_t overflow_iilb_vc0 : 1;
9343 mmr_t underflow_iilb_vc2 : 1;
9344 mmr_t overflow_iilb_vc2 : 1;
9345 mmr_t underflow_vc0_credit : 1;
9346 mmr_t overflow_vc0_credit : 1;
9347 mmr_t underflow_vc2_credit : 1;
9348 mmr_t overflow_vc2_credit : 1;
9349 mmr_t overflow_databuff_vc0 : 1;
9350 mmr_t overflow_databuff_vc2 : 1;
9351 mmr_t lut_read_error : 1;
9352 mmr_t single_bit_error0 : 1;
9353 mmr_t single_bit_error1 : 1;
9354 mmr_t single_bit_error2 : 1;
9355 mmr_t single_bit_error3 : 1;
9356 mmr_t uncor_error0 : 1;
9357 mmr_t uncor_error1 : 1;
9358 mmr_t uncor_error2 : 1;
9359 mmr_t uncor_error3 : 1;
9360 mmr_t underflow_sic_cntr0 : 1;
9361 mmr_t overflow_sic_cntr0 : 1;
9362 mmr_t underflow_sic_cntr2 : 1;
9363 mmr_t overflow_sic_cntr2 : 1;
9364 mmr_t overflow_ni0_debit0 : 1;
9365 mmr_t overflow_ni0_debit2 : 1;
9366 mmr_t overflow_ni1_debit0 : 1;
9367 mmr_t overflow_ni1_debit2 : 1;
9368 mmr_t overflow_iilb_debit0 : 1;
9369 mmr_t overflow_iilb_debit2 : 1;
9370 mmr_t underflow_ni0_vc0_credit : 1;
9371 mmr_t overflow_ni0_vc0_credit : 1;
9372 mmr_t underflow_ni0_vc2_credit : 1;
9373 mmr_t overflow_ni0_vc2_credit : 1;
9374 mmr_t underflow_ni1_vc0_credit : 1;
9375 mmr_t overflow_ni1_vc0_credit : 1;
9376 mmr_t underflow_ni1_vc2_credit : 1;
9377 mmr_t overflow_ni1_vc2_credit : 1;
9378 mmr_t underflow_iilb_vc0_credit : 1;
9379 mmr_t overflow_iilb_vc0_credit : 1;
9380 mmr_t underflow_iilb_vc2_credit : 1;
9381 mmr_t overflow_iilb_vc2_credit : 1;
9382 mmr_t overflow_header_cancel_fifo : 1;
9383 mmr_t reserved_0 : 14;
9384 } sh_xnpi_error_mask_s;
9385 } sh_xnpi_error_mask_u_t;
9387 /* ==================================================================== */
9388 /* Register "SH_XNPI_FIRST_ERROR" */
9389 /* ==================================================================== */
9391 typedef union sh_xnpi_first_error_u {
9392 mmr_t sh_xnpi_first_error_regval;
9394 mmr_t underflow_ni0_vc0 : 1;
9395 mmr_t overflow_ni0_vc0 : 1;
9396 mmr_t underflow_ni0_vc2 : 1;
9397 mmr_t overflow_ni0_vc2 : 1;
9398 mmr_t underflow_ni1_vc0 : 1;
9399 mmr_t overflow_ni1_vc0 : 1;
9400 mmr_t underflow_ni1_vc2 : 1;
9401 mmr_t overflow_ni1_vc2 : 1;
9402 mmr_t underflow_iilb_vc0 : 1;
9403 mmr_t overflow_iilb_vc0 : 1;
9404 mmr_t underflow_iilb_vc2 : 1;
9405 mmr_t overflow_iilb_vc2 : 1;
9406 mmr_t underflow_vc0_credit : 1;
9407 mmr_t overflow_vc0_credit : 1;
9408 mmr_t underflow_vc2_credit : 1;
9409 mmr_t overflow_vc2_credit : 1;
9410 mmr_t overflow_databuff_vc0 : 1;
9411 mmr_t overflow_databuff_vc2 : 1;
9412 mmr_t lut_read_error : 1;
9413 mmr_t single_bit_error0 : 1;
9414 mmr_t single_bit_error1 : 1;
9415 mmr_t single_bit_error2 : 1;
9416 mmr_t single_bit_error3 : 1;
9417 mmr_t uncor_error0 : 1;
9418 mmr_t uncor_error1 : 1;
9419 mmr_t uncor_error2 : 1;
9420 mmr_t uncor_error3 : 1;
9421 mmr_t underflow_sic_cntr0 : 1;
9422 mmr_t overflow_sic_cntr0 : 1;
9423 mmr_t underflow_sic_cntr2 : 1;
9424 mmr_t overflow_sic_cntr2 : 1;
9425 mmr_t overflow_ni0_debit0 : 1;
9426 mmr_t overflow_ni0_debit2 : 1;
9427 mmr_t overflow_ni1_debit0 : 1;
9428 mmr_t overflow_ni1_debit2 : 1;
9429 mmr_t overflow_iilb_debit0 : 1;
9430 mmr_t overflow_iilb_debit2 : 1;
9431 mmr_t underflow_ni0_vc0_credit : 1;
9432 mmr_t overflow_ni0_vc0_credit : 1;
9433 mmr_t underflow_ni0_vc2_credit : 1;
9434 mmr_t overflow_ni0_vc2_credit : 1;
9435 mmr_t underflow_ni1_vc0_credit : 1;
9436 mmr_t overflow_ni1_vc0_credit : 1;
9437 mmr_t underflow_ni1_vc2_credit : 1;
9438 mmr_t overflow_ni1_vc2_credit : 1;
9439 mmr_t underflow_iilb_vc0_credit : 1;
9440 mmr_t overflow_iilb_vc0_credit : 1;
9441 mmr_t underflow_iilb_vc2_credit : 1;
9442 mmr_t overflow_iilb_vc2_credit : 1;
9443 mmr_t overflow_header_cancel_fifo : 1;
9444 mmr_t reserved_0 : 14;
9445 } sh_xnpi_first_error_s;
9446 } sh_xnpi_first_error_u_t;
9448 /* ==================================================================== */
9449 /* Register "SH_XNMD_ERROR_SUMMARY" */
9450 /* ==================================================================== */
9452 typedef union sh_xnmd_error_summary_u {
9453 mmr_t sh_xnmd_error_summary_regval;
9455 mmr_t underflow_ni0_vc0 : 1;
9456 mmr_t overflow_ni0_vc0 : 1;
9457 mmr_t underflow_ni0_vc2 : 1;
9458 mmr_t overflow_ni0_vc2 : 1;
9459 mmr_t underflow_ni1_vc0 : 1;
9460 mmr_t overflow_ni1_vc0 : 1;
9461 mmr_t underflow_ni1_vc2 : 1;
9462 mmr_t overflow_ni1_vc2 : 1;
9463 mmr_t underflow_iilb_vc0 : 1;
9464 mmr_t overflow_iilb_vc0 : 1;
9465 mmr_t underflow_iilb_vc2 : 1;
9466 mmr_t overflow_iilb_vc2 : 1;
9467 mmr_t underflow_vc0_credit : 1;
9468 mmr_t overflow_vc0_credit : 1;
9469 mmr_t underflow_vc2_credit : 1;
9470 mmr_t overflow_vc2_credit : 1;
9471 mmr_t overflow_databuff_vc0 : 1;
9472 mmr_t overflow_databuff_vc2 : 1;
9473 mmr_t lut_read_error : 1;
9474 mmr_t single_bit_error0 : 1;
9475 mmr_t single_bit_error1 : 1;
9476 mmr_t single_bit_error2 : 1;
9477 mmr_t single_bit_error3 : 1;
9478 mmr_t uncor_error0 : 1;
9479 mmr_t uncor_error1 : 1;
9480 mmr_t uncor_error2 : 1;
9481 mmr_t uncor_error3 : 1;
9482 mmr_t underflow_sic_cntr0 : 1;
9483 mmr_t overflow_sic_cntr0 : 1;
9484 mmr_t underflow_sic_cntr2 : 1;
9485 mmr_t overflow_sic_cntr2 : 1;
9486 mmr_t overflow_ni0_debit0 : 1;
9487 mmr_t overflow_ni0_debit2 : 1;
9488 mmr_t overflow_ni1_debit0 : 1;
9489 mmr_t overflow_ni1_debit2 : 1;
9490 mmr_t overflow_iilb_debit0 : 1;
9491 mmr_t overflow_iilb_debit2 : 1;
9492 mmr_t underflow_ni0_vc0_credit : 1;
9493 mmr_t overflow_ni0_vc0_credit : 1;
9494 mmr_t underflow_ni0_vc2_credit : 1;
9495 mmr_t overflow_ni0_vc2_credit : 1;
9496 mmr_t underflow_ni1_vc0_credit : 1;
9497 mmr_t overflow_ni1_vc0_credit : 1;
9498 mmr_t underflow_ni1_vc2_credit : 1;
9499 mmr_t overflow_ni1_vc2_credit : 1;
9500 mmr_t underflow_iilb_vc0_credit : 1;
9501 mmr_t overflow_iilb_vc0_credit : 1;
9502 mmr_t underflow_iilb_vc2_credit : 1;
9503 mmr_t overflow_iilb_vc2_credit : 1;
9504 mmr_t overflow_header_cancel_fifo : 1;
9505 mmr_t reserved_0 : 14;
9506 } sh_xnmd_error_summary_s;
9507 } sh_xnmd_error_summary_u_t;
9509 /* ==================================================================== */
9510 /* Register "SH_XNMD_ERROR_OVERFLOW" */
9511 /* ==================================================================== */
9513 typedef union sh_xnmd_error_overflow_u {
9514 mmr_t sh_xnmd_error_overflow_regval;
9516 mmr_t underflow_ni0_vc0 : 1;
9517 mmr_t overflow_ni0_vc0 : 1;
9518 mmr_t underflow_ni0_vc2 : 1;
9519 mmr_t overflow_ni0_vc2 : 1;
9520 mmr_t underflow_ni1_vc0 : 1;
9521 mmr_t overflow_ni1_vc0 : 1;
9522 mmr_t underflow_ni1_vc2 : 1;
9523 mmr_t overflow_ni1_vc2 : 1;
9524 mmr_t underflow_iilb_vc0 : 1;
9525 mmr_t overflow_iilb_vc0 : 1;
9526 mmr_t underflow_iilb_vc2 : 1;
9527 mmr_t overflow_iilb_vc2 : 1;
9528 mmr_t underflow_vc0_credit : 1;
9529 mmr_t overflow_vc0_credit : 1;
9530 mmr_t underflow_vc2_credit : 1;
9531 mmr_t overflow_vc2_credit : 1;
9532 mmr_t overflow_databuff_vc0 : 1;
9533 mmr_t overflow_databuff_vc2 : 1;
9534 mmr_t lut_read_error : 1;
9535 mmr_t single_bit_error0 : 1;
9536 mmr_t single_bit_error1 : 1;
9537 mmr_t single_bit_error2 : 1;
9538 mmr_t single_bit_error3 : 1;
9539 mmr_t uncor_error0 : 1;
9540 mmr_t uncor_error1 : 1;
9541 mmr_t uncor_error2 : 1;
9542 mmr_t uncor_error3 : 1;
9543 mmr_t underflow_sic_cntr0 : 1;
9544 mmr_t overflow_sic_cntr0 : 1;
9545 mmr_t underflow_sic_cntr2 : 1;
9546 mmr_t overflow_sic_cntr2 : 1;
9547 mmr_t overflow_ni0_debit0 : 1;
9548 mmr_t overflow_ni0_debit2 : 1;
9549 mmr_t overflow_ni1_debit0 : 1;
9550 mmr_t overflow_ni1_debit2 : 1;
9551 mmr_t overflow_iilb_debit0 : 1;
9552 mmr_t overflow_iilb_debit2 : 1;
9553 mmr_t underflow_ni0_vc0_credit : 1;
9554 mmr_t overflow_ni0_vc0_credit : 1;
9555 mmr_t underflow_ni0_vc2_credit : 1;
9556 mmr_t overflow_ni0_vc2_credit : 1;
9557 mmr_t underflow_ni1_vc0_credit : 1;
9558 mmr_t overflow_ni1_vc0_credit : 1;
9559 mmr_t underflow_ni1_vc2_credit : 1;
9560 mmr_t overflow_ni1_vc2_credit : 1;
9561 mmr_t underflow_iilb_vc0_credit : 1;
9562 mmr_t overflow_iilb_vc0_credit : 1;
9563 mmr_t underflow_iilb_vc2_credit : 1;
9564 mmr_t overflow_iilb_vc2_credit : 1;
9565 mmr_t overflow_header_cancel_fifo : 1;
9566 mmr_t reserved_0 : 14;
9567 } sh_xnmd_error_overflow_s;
9568 } sh_xnmd_error_overflow_u_t;
9570 /* ==================================================================== */
9571 /* Register "SH_XNMD_ERROR_MASK" */
9572 /* ==================================================================== */
9574 typedef union sh_xnmd_error_mask_u {
9575 mmr_t sh_xnmd_error_mask_regval;
9577 mmr_t underflow_ni0_vc0 : 1;
9578 mmr_t overflow_ni0_vc0 : 1;
9579 mmr_t underflow_ni0_vc2 : 1;
9580 mmr_t overflow_ni0_vc2 : 1;
9581 mmr_t underflow_ni1_vc0 : 1;
9582 mmr_t overflow_ni1_vc0 : 1;
9583 mmr_t underflow_ni1_vc2 : 1;
9584 mmr_t overflow_ni1_vc2 : 1;
9585 mmr_t underflow_iilb_vc0 : 1;
9586 mmr_t overflow_iilb_vc0 : 1;
9587 mmr_t underflow_iilb_vc2 : 1;
9588 mmr_t overflow_iilb_vc2 : 1;
9589 mmr_t underflow_vc0_credit : 1;
9590 mmr_t overflow_vc0_credit : 1;
9591 mmr_t underflow_vc2_credit : 1;
9592 mmr_t overflow_vc2_credit : 1;
9593 mmr_t overflow_databuff_vc0 : 1;
9594 mmr_t overflow_databuff_vc2 : 1;
9595 mmr_t lut_read_error : 1;
9596 mmr_t single_bit_error0 : 1;
9597 mmr_t single_bit_error1 : 1;
9598 mmr_t single_bit_error2 : 1;
9599 mmr_t single_bit_error3 : 1;
9600 mmr_t uncor_error0 : 1;
9601 mmr_t uncor_error1 : 1;
9602 mmr_t uncor_error2 : 1;
9603 mmr_t uncor_error3 : 1;
9604 mmr_t underflow_sic_cntr0 : 1;
9605 mmr_t overflow_sic_cntr0 : 1;
9606 mmr_t underflow_sic_cntr2 : 1;
9607 mmr_t overflow_sic_cntr2 : 1;
9608 mmr_t overflow_ni0_debit0 : 1;
9609 mmr_t overflow_ni0_debit2 : 1;
9610 mmr_t overflow_ni1_debit0 : 1;
9611 mmr_t overflow_ni1_debit2 : 1;
9612 mmr_t overflow_iilb_debit0 : 1;
9613 mmr_t overflow_iilb_debit2 : 1;
9614 mmr_t underflow_ni0_vc0_credit : 1;
9615 mmr_t overflow_ni0_vc0_credit : 1;
9616 mmr_t underflow_ni0_vc2_credit : 1;
9617 mmr_t overflow_ni0_vc2_credit : 1;
9618 mmr_t underflow_ni1_vc0_credit : 1;
9619 mmr_t overflow_ni1_vc0_credit : 1;
9620 mmr_t underflow_ni1_vc2_credit : 1;
9621 mmr_t overflow_ni1_vc2_credit : 1;
9622 mmr_t underflow_iilb_vc0_credit : 1;
9623 mmr_t overflow_iilb_vc0_credit : 1;
9624 mmr_t underflow_iilb_vc2_credit : 1;
9625 mmr_t overflow_iilb_vc2_credit : 1;
9626 mmr_t overflow_header_cancel_fifo : 1;
9627 mmr_t reserved_0 : 14;
9628 } sh_xnmd_error_mask_s;
9629 } sh_xnmd_error_mask_u_t;
9631 /* ==================================================================== */
9632 /* Register "SH_XNMD_FIRST_ERROR" */
9633 /* ==================================================================== */
9635 typedef union sh_xnmd_first_error_u {
9636 mmr_t sh_xnmd_first_error_regval;
9638 mmr_t underflow_ni0_vc0 : 1;
9639 mmr_t overflow_ni0_vc0 : 1;
9640 mmr_t underflow_ni0_vc2 : 1;
9641 mmr_t overflow_ni0_vc2 : 1;
9642 mmr_t underflow_ni1_vc0 : 1;
9643 mmr_t overflow_ni1_vc0 : 1;
9644 mmr_t underflow_ni1_vc2 : 1;
9645 mmr_t overflow_ni1_vc2 : 1;
9646 mmr_t underflow_iilb_vc0 : 1;
9647 mmr_t overflow_iilb_vc0 : 1;
9648 mmr_t underflow_iilb_vc2 : 1;
9649 mmr_t overflow_iilb_vc2 : 1;
9650 mmr_t underflow_vc0_credit : 1;
9651 mmr_t overflow_vc0_credit : 1;
9652 mmr_t underflow_vc2_credit : 1;
9653 mmr_t overflow_vc2_credit : 1;
9654 mmr_t overflow_databuff_vc0 : 1;
9655 mmr_t overflow_databuff_vc2 : 1;
9656 mmr_t lut_read_error : 1;
9657 mmr_t single_bit_error0 : 1;
9658 mmr_t single_bit_error1 : 1;
9659 mmr_t single_bit_error2 : 1;
9660 mmr_t single_bit_error3 : 1;
9661 mmr_t uncor_error0 : 1;
9662 mmr_t uncor_error1 : 1;
9663 mmr_t uncor_error2 : 1;
9664 mmr_t uncor_error3 : 1;
9665 mmr_t underflow_sic_cntr0 : 1;
9666 mmr_t overflow_sic_cntr0 : 1;
9667 mmr_t underflow_sic_cntr2 : 1;
9668 mmr_t overflow_sic_cntr2 : 1;
9669 mmr_t overflow_ni0_debit0 : 1;
9670 mmr_t overflow_ni0_debit2 : 1;
9671 mmr_t overflow_ni1_debit0 : 1;
9672 mmr_t overflow_ni1_debit2 : 1;
9673 mmr_t overflow_iilb_debit0 : 1;
9674 mmr_t overflow_iilb_debit2 : 1;
9675 mmr_t underflow_ni0_vc0_credit : 1;
9676 mmr_t overflow_ni0_vc0_credit : 1;
9677 mmr_t underflow_ni0_vc2_credit : 1;
9678 mmr_t overflow_ni0_vc2_credit : 1;
9679 mmr_t underflow_ni1_vc0_credit : 1;
9680 mmr_t overflow_ni1_vc0_credit : 1;
9681 mmr_t underflow_ni1_vc2_credit : 1;
9682 mmr_t overflow_ni1_vc2_credit : 1;
9683 mmr_t underflow_iilb_vc0_credit : 1;
9684 mmr_t overflow_iilb_vc0_credit : 1;
9685 mmr_t underflow_iilb_vc2_credit : 1;
9686 mmr_t overflow_iilb_vc2_credit : 1;
9687 mmr_t overflow_header_cancel_fifo : 1;
9688 mmr_t reserved_0 : 14;
9689 } sh_xnmd_first_error_s;
9690 } sh_xnmd_first_error_u_t;
9692 /* ==================================================================== */
9693 /* Register "SH_AUTO_REPLY_ENABLE0" */
9694 /* Automatic Maintenance Reply Enable 0 */
9695 /* ==================================================================== */
9697 typedef union sh_auto_reply_enable0_u {
9698 mmr_t sh_auto_reply_enable0_regval;
9701 } sh_auto_reply_enable0_s;
9702 } sh_auto_reply_enable0_u_t;
9704 /* ==================================================================== */
9705 /* Register "SH_AUTO_REPLY_ENABLE1" */
9706 /* Automatic Maintenance Reply Enable 1 */
9707 /* ==================================================================== */
9709 typedef union sh_auto_reply_enable1_u {
9710 mmr_t sh_auto_reply_enable1_regval;
9713 } sh_auto_reply_enable1_s;
9714 } sh_auto_reply_enable1_u_t;
9716 /* ==================================================================== */
9717 /* Register "SH_AUTO_REPLY_HEADER0" */
9718 /* Automatic Maintenance Reply Header 0 */
9719 /* ==================================================================== */
9721 typedef union sh_auto_reply_header0_u {
9722 mmr_t sh_auto_reply_header0_regval;
9725 } sh_auto_reply_header0_s;
9726 } sh_auto_reply_header0_u_t;
9728 /* ==================================================================== */
9729 /* Register "SH_AUTO_REPLY_HEADER1" */
9730 /* Automatic Maintenance Reply Header 1 */
9731 /* ==================================================================== */
9733 typedef union sh_auto_reply_header1_u {
9734 mmr_t sh_auto_reply_header1_regval;
9737 } sh_auto_reply_header1_s;
9738 } sh_auto_reply_header1_u_t;
9740 /* ==================================================================== */
9741 /* Register "SH_ENABLE_RP_AUTO_REPLY" */
9742 /* Enable Automatic Maintenance Reply From Reply Queue */
9743 /* ==================================================================== */
9745 typedef union sh_enable_rp_auto_reply_u {
9746 mmr_t sh_enable_rp_auto_reply_regval;
9749 mmr_t reserved_0 : 63;
9750 } sh_enable_rp_auto_reply_s;
9751 } sh_enable_rp_auto_reply_u_t;
9753 /* ==================================================================== */
9754 /* Register "SH_ENABLE_RQ_AUTO_REPLY" */
9755 /* Enable Automatic Maintenance Reply From Request Queue */
9756 /* ==================================================================== */
9758 typedef union sh_enable_rq_auto_reply_u {
9759 mmr_t sh_enable_rq_auto_reply_regval;
9762 mmr_t reserved_0 : 63;
9763 } sh_enable_rq_auto_reply_s;
9764 } sh_enable_rq_auto_reply_u_t;
9766 /* ==================================================================== */
9767 /* Register "SH_REDIRECT_INVAL" */
9768 /* Redirect invalidate to LB instead of PI */
9769 /* ==================================================================== */
9771 typedef union sh_redirect_inval_u {
9772 mmr_t sh_redirect_inval_regval;
9775 mmr_t reserved_0 : 63;
9776 } sh_redirect_inval_s;
9777 } sh_redirect_inval_u_t;
9779 /* ==================================================================== */
9780 /* Register "SH_DIAG_MSG_CNTRL" */
9781 /* Diagnostic Message Control Register */
9782 /* ==================================================================== */
9784 typedef union sh_diag_msg_cntrl_u {
9785 mmr_t sh_diag_msg_cntrl_regval;
9787 mmr_t msg_length : 6;
9788 mmr_t error_inject_point : 6;
9789 mmr_t error_inject_enable : 1;
9791 mmr_t reserved_0 : 48;
9794 } sh_diag_msg_cntrl_s;
9795 } sh_diag_msg_cntrl_u_t;
9797 /* ==================================================================== */
9798 /* Register "SH_DIAG_MSG_DATA0L" */
9799 /* Diagnostic Data, lower 64 bits */
9800 /* ==================================================================== */
9802 typedef union sh_diag_msg_data0l_u {
9803 mmr_t sh_diag_msg_data0l_regval;
9805 mmr_t data_lower : 64;
9806 } sh_diag_msg_data0l_s;
9807 } sh_diag_msg_data0l_u_t;
9809 /* ==================================================================== */
9810 /* Register "SH_DIAG_MSG_DATA0U" */
9811 /* Diagnostice Data, upper 64 bits */
9812 /* ==================================================================== */
9814 typedef union sh_diag_msg_data0u_u {
9815 mmr_t sh_diag_msg_data0u_regval;
9817 mmr_t data_upper : 64;
9818 } sh_diag_msg_data0u_s;
9819 } sh_diag_msg_data0u_u_t;
9821 /* ==================================================================== */
9822 /* Register "SH_DIAG_MSG_DATA1L" */
9823 /* Diagnostic Data, lower 64 bits */
9824 /* ==================================================================== */
9826 typedef union sh_diag_msg_data1l_u {
9827 mmr_t sh_diag_msg_data1l_regval;
9829 mmr_t data_lower : 64;
9830 } sh_diag_msg_data1l_s;
9831 } sh_diag_msg_data1l_u_t;
9833 /* ==================================================================== */
9834 /* Register "SH_DIAG_MSG_DATA1U" */
9835 /* Diagnostice Data, upper 64 bits */
9836 /* ==================================================================== */
9838 typedef union sh_diag_msg_data1u_u {
9839 mmr_t sh_diag_msg_data1u_regval;
9841 mmr_t data_upper : 64;
9842 } sh_diag_msg_data1u_s;
9843 } sh_diag_msg_data1u_u_t;
9845 /* ==================================================================== */
9846 /* Register "SH_DIAG_MSG_DATA2L" */
9847 /* Diagnostic Data, lower 64 bits */
9848 /* ==================================================================== */
9850 typedef union sh_diag_msg_data2l_u {
9851 mmr_t sh_diag_msg_data2l_regval;
9853 mmr_t data_lower : 64;
9854 } sh_diag_msg_data2l_s;
9855 } sh_diag_msg_data2l_u_t;
9857 /* ==================================================================== */
9858 /* Register "SH_DIAG_MSG_DATA2U" */
9859 /* Diagnostice Data, upper 64 bits */
9860 /* ==================================================================== */
9862 typedef union sh_diag_msg_data2u_u {
9863 mmr_t sh_diag_msg_data2u_regval;
9865 mmr_t data_upper : 64;
9866 } sh_diag_msg_data2u_s;
9867 } sh_diag_msg_data2u_u_t;
9869 /* ==================================================================== */
9870 /* Register "SH_DIAG_MSG_DATA3L" */
9871 /* Diagnostic Data, lower 64 bits */
9872 /* ==================================================================== */
9874 typedef union sh_diag_msg_data3l_u {
9875 mmr_t sh_diag_msg_data3l_regval;
9877 mmr_t data_lower : 64;
9878 } sh_diag_msg_data3l_s;
9879 } sh_diag_msg_data3l_u_t;
9881 /* ==================================================================== */
9882 /* Register "SH_DIAG_MSG_DATA3U" */
9883 /* Diagnostice Data, upper 64 bits */
9884 /* ==================================================================== */
9886 typedef union sh_diag_msg_data3u_u {
9887 mmr_t sh_diag_msg_data3u_regval;
9889 mmr_t data_upper : 64;
9890 } sh_diag_msg_data3u_s;
9891 } sh_diag_msg_data3u_u_t;
9893 /* ==================================================================== */
9894 /* Register "SH_DIAG_MSG_DATA4L" */
9895 /* Diagnostic Data, lower 64 bits */
9896 /* ==================================================================== */
9898 typedef union sh_diag_msg_data4l_u {
9899 mmr_t sh_diag_msg_data4l_regval;
9901 mmr_t data_lower : 64;
9902 } sh_diag_msg_data4l_s;
9903 } sh_diag_msg_data4l_u_t;
9905 /* ==================================================================== */
9906 /* Register "SH_DIAG_MSG_DATA4U" */
9907 /* Diagnostice Data, upper 64 bits */
9908 /* ==================================================================== */
9910 typedef union sh_diag_msg_data4u_u {
9911 mmr_t sh_diag_msg_data4u_regval;
9913 mmr_t data_upper : 64;
9914 } sh_diag_msg_data4u_s;
9915 } sh_diag_msg_data4u_u_t;
9917 /* ==================================================================== */
9918 /* Register "SH_DIAG_MSG_DATA5L" */
9919 /* Diagnostic Data, lower 64 bits */
9920 /* ==================================================================== */
9922 typedef union sh_diag_msg_data5l_u {
9923 mmr_t sh_diag_msg_data5l_regval;
9925 mmr_t data_lower : 64;
9926 } sh_diag_msg_data5l_s;
9927 } sh_diag_msg_data5l_u_t;
9929 /* ==================================================================== */
9930 /* Register "SH_DIAG_MSG_DATA5U" */
9931 /* Diagnostice Data, upper 64 bits */
9932 /* ==================================================================== */
9934 typedef union sh_diag_msg_data5u_u {
9935 mmr_t sh_diag_msg_data5u_regval;
9937 mmr_t data_upper : 64;
9938 } sh_diag_msg_data5u_s;
9939 } sh_diag_msg_data5u_u_t;
9941 /* ==================================================================== */
9942 /* Register "SH_DIAG_MSG_DATA6L" */
9943 /* Diagnostic Data, lower 64 bits */
9944 /* ==================================================================== */
9946 typedef union sh_diag_msg_data6l_u {
9947 mmr_t sh_diag_msg_data6l_regval;
9949 mmr_t data_lower : 64;
9950 } sh_diag_msg_data6l_s;
9951 } sh_diag_msg_data6l_u_t;
9953 /* ==================================================================== */
9954 /* Register "SH_DIAG_MSG_DATA6U" */
9955 /* Diagnostice Data, upper 64 bits */
9956 /* ==================================================================== */
9958 typedef union sh_diag_msg_data6u_u {
9959 mmr_t sh_diag_msg_data6u_regval;
9961 mmr_t data_upper : 64;
9962 } sh_diag_msg_data6u_s;
9963 } sh_diag_msg_data6u_u_t;
9965 /* ==================================================================== */
9966 /* Register "SH_DIAG_MSG_DATA7L" */
9967 /* Diagnostic Data, lower 64 bits */
9968 /* ==================================================================== */
9970 typedef union sh_diag_msg_data7l_u {
9971 mmr_t sh_diag_msg_data7l_regval;
9973 mmr_t data_lower : 64;
9974 } sh_diag_msg_data7l_s;
9975 } sh_diag_msg_data7l_u_t;
9977 /* ==================================================================== */
9978 /* Register "SH_DIAG_MSG_DATA7U" */
9979 /* Diagnostice Data, upper 64 bits */
9980 /* ==================================================================== */
9982 typedef union sh_diag_msg_data7u_u {
9983 mmr_t sh_diag_msg_data7u_regval;
9985 mmr_t data_upper : 64;
9986 } sh_diag_msg_data7u_s;
9987 } sh_diag_msg_data7u_u_t;
9989 /* ==================================================================== */
9990 /* Register "SH_DIAG_MSG_DATA8L" */
9991 /* Diagnostic Data, lower 64 bits */
9992 /* ==================================================================== */
9994 typedef union sh_diag_msg_data8l_u {
9995 mmr_t sh_diag_msg_data8l_regval;
9997 mmr_t data_lower : 64;
9998 } sh_diag_msg_data8l_s;
9999 } sh_diag_msg_data8l_u_t;
10001 /* ==================================================================== */
10002 /* Register "SH_DIAG_MSG_DATA8U" */
10003 /* Diagnostice Data, upper 64 bits */
10004 /* ==================================================================== */
10006 typedef union sh_diag_msg_data8u_u {
10007 mmr_t sh_diag_msg_data8u_regval;
10009 mmr_t data_upper : 64;
10010 } sh_diag_msg_data8u_s;
10011 } sh_diag_msg_data8u_u_t;
10013 /* ==================================================================== */
10014 /* Register "SH_DIAG_MSG_HDR0" */
10015 /* Diagnostice Data, lower 64 bits of header */
10016 /* ==================================================================== */
10018 typedef union sh_diag_msg_hdr0_u {
10019 mmr_t sh_diag_msg_hdr0_regval;
10021 mmr_t header0 : 64;
10022 } sh_diag_msg_hdr0_s;
10023 } sh_diag_msg_hdr0_u_t;
10025 /* ==================================================================== */
10026 /* Register "SH_DIAG_MSG_HDR1" */
10027 /* Diagnostice Data, upper 64 bits of header */
10028 /* ==================================================================== */
10030 typedef union sh_diag_msg_hdr1_u {
10031 mmr_t sh_diag_msg_hdr1_regval;
10033 mmr_t header1 : 64;
10034 } sh_diag_msg_hdr1_s;
10035 } sh_diag_msg_hdr1_u_t;
10037 /* ==================================================================== */
10038 /* Register "SH_DEBUG_SELECT" */
10039 /* SHub Debug Port Select */
10040 /* ==================================================================== */
10042 typedef union sh_debug_select_u {
10043 mmr_t sh_debug_select_regval;
10045 mmr_t nibble0_nibble_sel : 3;
10046 mmr_t nibble0_chiplet_sel : 3;
10047 mmr_t nibble1_nibble_sel : 3;
10048 mmr_t nibble1_chiplet_sel : 3;
10049 mmr_t nibble2_nibble_sel : 3;
10050 mmr_t nibble2_chiplet_sel : 3;
10051 mmr_t nibble3_nibble_sel : 3;
10052 mmr_t nibble3_chiplet_sel : 3;
10053 mmr_t nibble4_nibble_sel : 3;
10054 mmr_t nibble4_chiplet_sel : 3;
10055 mmr_t nibble5_nibble_sel : 3;
10056 mmr_t nibble5_chiplet_sel : 3;
10057 mmr_t nibble6_nibble_sel : 3;
10058 mmr_t nibble6_chiplet_sel : 3;
10059 mmr_t nibble7_nibble_sel : 3;
10060 mmr_t nibble7_chiplet_sel : 3;
10061 mmr_t debug_ii_sel : 3;
10063 mmr_t reserved_0 : 3;
10064 mmr_t trigger_enable : 1;
10065 } sh_debug_select_s;
10066 } sh_debug_select_u_t;
10068 /* ==================================================================== */
10069 /* Register "SH_TRIGGER_COMPARE_MASK" */
10070 /* SHub Trigger Compare Mask */
10071 /* ==================================================================== */
10073 typedef union sh_trigger_compare_mask_u {
10074 mmr_t sh_trigger_compare_mask_regval;
10077 mmr_t reserved_0 : 32;
10078 } sh_trigger_compare_mask_s;
10079 } sh_trigger_compare_mask_u_t;
10081 /* ==================================================================== */
10082 /* Register "SH_TRIGGER_COMPARE_PATTERN" */
10083 /* SHub Trigger Compare Pattern */
10084 /* ==================================================================== */
10086 typedef union sh_trigger_compare_pattern_u {
10087 mmr_t sh_trigger_compare_pattern_regval;
10090 mmr_t reserved_0 : 32;
10091 } sh_trigger_compare_pattern_s;
10092 } sh_trigger_compare_pattern_u_t;
10094 /* ==================================================================== */
10095 /* Register "SH_TRIGGER_SEL" */
10096 /* Trigger select for SHUB debug port */
10097 /* ==================================================================== */
10099 typedef union sh_trigger_sel_u {
10100 mmr_t sh_trigger_sel_regval;
10102 mmr_t nibble0_input_sel : 3;
10103 mmr_t reserved_0 : 1;
10104 mmr_t nibble0_nibble_sel : 3;
10105 mmr_t reserved_1 : 1;
10106 mmr_t nibble1_input_sel : 3;
10107 mmr_t reserved_2 : 1;
10108 mmr_t nibble1_nibble_sel : 3;
10109 mmr_t reserved_3 : 1;
10110 mmr_t nibble2_input_sel : 3;
10111 mmr_t reserved_4 : 1;
10112 mmr_t nibble2_nibble_sel : 3;
10113 mmr_t reserved_5 : 1;
10114 mmr_t nibble3_input_sel : 3;
10115 mmr_t reserved_6 : 1;
10116 mmr_t nibble3_nibble_sel : 3;
10117 mmr_t reserved_7 : 1;
10118 mmr_t nibble4_input_sel : 3;
10119 mmr_t reserved_8 : 1;
10120 mmr_t nibble4_nibble_sel : 3;
10121 mmr_t reserved_9 : 1;
10122 mmr_t nibble5_input_sel : 3;
10123 mmr_t reserved_10 : 1;
10124 mmr_t nibble5_nibble_sel : 3;
10125 mmr_t reserved_11 : 1;
10126 mmr_t nibble6_input_sel : 3;
10127 mmr_t reserved_12 : 1;
10128 mmr_t nibble6_nibble_sel : 3;
10129 mmr_t reserved_13 : 1;
10130 mmr_t nibble7_input_sel : 3;
10131 mmr_t reserved_14 : 1;
10132 mmr_t nibble7_nibble_sel : 3;
10133 mmr_t reserved_15 : 1;
10134 } sh_trigger_sel_s;
10135 } sh_trigger_sel_u_t;
10137 /* ==================================================================== */
10138 /* Register "SH_STOP_CLK_CONTROL" */
10139 /* Stop Clock Control */
10140 /* ==================================================================== */
10142 typedef union sh_stop_clk_control_u {
10143 mmr_t sh_stop_clk_control_regval;
10145 mmr_t stimulus : 5;
10147 mmr_t polarity : 1;
10149 mmr_t reserved_0 : 56;
10150 } sh_stop_clk_control_s;
10151 } sh_stop_clk_control_u_t;
10153 /* ==================================================================== */
10154 /* Register "SH_STOP_CLK_DELAY_PHASE" */
10155 /* Stop Clock Delay Phase */
10156 /* ==================================================================== */
10158 typedef union sh_stop_clk_delay_phase_u {
10159 mmr_t sh_stop_clk_delay_phase_regval;
10162 mmr_t reserved_0 : 56;
10163 } sh_stop_clk_delay_phase_s;
10164 } sh_stop_clk_delay_phase_u_t;
10166 /* ==================================================================== */
10167 /* Register "SH_TSF_ARM_MASK" */
10168 /* Trigger sequencing facility arm mask */
10169 /* ==================================================================== */
10171 typedef union sh_tsf_arm_mask_u {
10172 mmr_t sh_tsf_arm_mask_regval;
10175 } sh_tsf_arm_mask_s;
10176 } sh_tsf_arm_mask_u_t;
10178 /* ==================================================================== */
10179 /* Register "SH_TSF_COUNTER_PRESETS" */
10180 /* Trigger sequencing facility counter presets */
10181 /* ==================================================================== */
10183 typedef union sh_tsf_counter_presets_u {
10184 mmr_t sh_tsf_counter_presets_regval;
10186 mmr_t count_32 : 32;
10187 mmr_t count_16 : 16;
10188 mmr_t count_8b : 8;
10189 mmr_t count_8a : 8;
10190 } sh_tsf_counter_presets_s;
10191 } sh_tsf_counter_presets_u_t;
10193 /* ==================================================================== */
10194 /* Register "SH_TSF_DECREMENT_CTL" */
10195 /* Trigger sequencing facility counter decrement control */
10196 /* ==================================================================== */
10198 typedef union sh_tsf_decrement_ctl_u {
10199 mmr_t sh_tsf_decrement_ctl_regval;
10202 mmr_t reserved_0 : 48;
10203 } sh_tsf_decrement_ctl_s;
10204 } sh_tsf_decrement_ctl_u_t;
10206 /* ==================================================================== */
10207 /* Register "SH_TSF_DIAG_MSG_CTL" */
10208 /* Trigger sequencing facility diagnostic message control */
10209 /* ==================================================================== */
10211 typedef union sh_tsf_diag_msg_ctl_u {
10212 mmr_t sh_tsf_diag_msg_ctl_regval;
10215 mmr_t reserved_0 : 56;
10216 } sh_tsf_diag_msg_ctl_s;
10217 } sh_tsf_diag_msg_ctl_u_t;
10219 /* ==================================================================== */
10220 /* Register "SH_TSF_DISARM_MASK" */
10221 /* Trigger sequencing facility disarm mask */
10222 /* ==================================================================== */
10224 typedef union sh_tsf_disarm_mask_u {
10225 mmr_t sh_tsf_disarm_mask_regval;
10228 } sh_tsf_disarm_mask_s;
10229 } sh_tsf_disarm_mask_u_t;
10231 /* ==================================================================== */
10232 /* Register "SH_TSF_ENABLE_CTL" */
10233 /* Trigger sequencing facility counter enable control */
10234 /* ==================================================================== */
10236 typedef union sh_tsf_enable_ctl_u {
10237 mmr_t sh_tsf_enable_ctl_regval;
10240 mmr_t reserved_0 : 48;
10241 } sh_tsf_enable_ctl_s;
10242 } sh_tsf_enable_ctl_u_t;
10244 /* ==================================================================== */
10245 /* Register "SH_TSF_SOFTWARE_ARM" */
10246 /* Trigger sequencing facility software arm */
10247 /* ==================================================================== */
10249 typedef union sh_tsf_software_arm_u {
10250 mmr_t sh_tsf_software_arm_regval;
10260 mmr_t reserved_0 : 56;
10261 } sh_tsf_software_arm_s;
10262 } sh_tsf_software_arm_u_t;
10264 /* ==================================================================== */
10265 /* Register "SH_TSF_SOFTWARE_DISARM" */
10266 /* Trigger sequencing facility software disarm */
10267 /* ==================================================================== */
10269 typedef union sh_tsf_software_disarm_u {
10270 mmr_t sh_tsf_software_disarm_regval;
10280 mmr_t reserved_0 : 56;
10281 } sh_tsf_software_disarm_s;
10282 } sh_tsf_software_disarm_u_t;
10284 /* ==================================================================== */
10285 /* Register "SH_TSF_SOFTWARE_TRIGGERED" */
10286 /* Trigger sequencing facility software triggered */
10287 /* ==================================================================== */
10289 typedef union sh_tsf_software_triggered_u {
10290 mmr_t sh_tsf_software_triggered_regval;
10300 mmr_t reserved_0 : 56;
10301 } sh_tsf_software_triggered_s;
10302 } sh_tsf_software_triggered_u_t;
10304 /* ==================================================================== */
10305 /* Register "SH_TSF_TRIGGER_MASK" */
10306 /* Trigger sequencing facility trigger mask */
10307 /* ==================================================================== */
10309 typedef union sh_tsf_trigger_mask_u {
10310 mmr_t sh_tsf_trigger_mask_regval;
10313 } sh_tsf_trigger_mask_s;
10314 } sh_tsf_trigger_mask_u_t;
10316 /* ==================================================================== */
10317 /* Register "SH_VEC_DATA" */
10318 /* Vector Write Request Message Data */
10319 /* ==================================================================== */
10321 typedef union sh_vec_data_u {
10322 mmr_t sh_vec_data_regval;
10328 /* ==================================================================== */
10329 /* Register "SH_VEC_PARMS" */
10330 /* Vector Message Parameters Register */
10331 /* ==================================================================== */
10333 typedef union sh_vec_parms_u {
10334 mmr_t sh_vec_parms_regval;
10338 mmr_t reserved_0 : 1;
10339 mmr_t address : 32;
10341 mmr_t reserved_1 : 16;
10345 } sh_vec_parms_u_t;
10347 /* ==================================================================== */
10348 /* Register "SH_VEC_ROUTE" */
10349 /* Vector Request Message Route */
10350 /* ==================================================================== */
10352 typedef union sh_vec_route_u {
10353 mmr_t sh_vec_route_regval;
10357 } sh_vec_route_u_t;
10359 /* ==================================================================== */
10360 /* Register "SH_CPU_PERM" */
10361 /* CPU MMR Access Permission Bits */
10362 /* ==================================================================== */
10364 typedef union sh_cpu_perm_u {
10365 mmr_t sh_cpu_perm_regval;
10367 mmr_t access_bits : 64;
10371 /* ==================================================================== */
10372 /* Register "SH_CPU_PERM_OVR" */
10373 /* CPU MMR Access Permission Override */
10374 /* ==================================================================== */
10376 typedef union sh_cpu_perm_ovr_u {
10377 mmr_t sh_cpu_perm_ovr_regval;
10379 mmr_t override : 64;
10380 } sh_cpu_perm_ovr_s;
10381 } sh_cpu_perm_ovr_u_t;
10383 /* ==================================================================== */
10384 /* Register "SH_EXT_IO_PERM" */
10385 /* External IO MMR Access Permission Bits */
10386 /* ==================================================================== */
10388 typedef union sh_ext_io_perm_u {
10389 mmr_t sh_ext_io_perm_regval;
10391 mmr_t access_bits : 64;
10392 } sh_ext_io_perm_s;
10393 } sh_ext_io_perm_u_t;
10395 /* ==================================================================== */
10396 /* Register "SH_EXT_IOI_ACCESS" */
10397 /* External IO Interrupt Access Permission Bits */
10398 /* ==================================================================== */
10400 typedef union sh_ext_ioi_access_u {
10401 mmr_t sh_ext_ioi_access_regval;
10403 mmr_t access_bits : 64;
10404 } sh_ext_ioi_access_s;
10405 } sh_ext_ioi_access_u_t;
10407 /* ==================================================================== */
10408 /* Register "SH_GC_FIL_CTRL" */
10409 /* SHub Global Clock Filter Control */
10410 /* ==================================================================== */
10412 typedef union sh_gc_fil_ctrl_u {
10413 mmr_t sh_gc_fil_ctrl_regval;
10416 mmr_t reserved_0 : 3;
10417 mmr_t mask_counter : 12;
10418 mmr_t mask_enable : 1;
10419 mmr_t reserved_1 : 3;
10420 mmr_t dropout_counter : 10;
10421 mmr_t reserved_2 : 2;
10422 mmr_t dropout_thresh : 10;
10423 mmr_t reserved_3 : 2;
10424 mmr_t error_counter : 10;
10425 mmr_t reserved_4 : 6;
10426 } sh_gc_fil_ctrl_s;
10427 } sh_gc_fil_ctrl_u_t;
10429 /* ==================================================================== */
10430 /* Register "SH_GC_SRC_CTRL" */
10431 /* SHub Global Clock Control */
10432 /* ==================================================================== */
10434 typedef union sh_gc_src_ctrl_u {
10435 mmr_t sh_gc_src_ctrl_regval;
10437 mmr_t enable_counter : 1;
10438 mmr_t reserved_0 : 3;
10439 mmr_t max_count : 10;
10440 mmr_t reserved_1 : 2;
10441 mmr_t counter : 10;
10442 mmr_t reserved_2 : 2;
10443 mmr_t toggle_bit : 1;
10444 mmr_t reserved_3 : 3;
10445 mmr_t source_sel : 2;
10446 mmr_t reserved_4 : 30;
10447 } sh_gc_src_ctrl_s;
10448 } sh_gc_src_ctrl_u_t;
10450 /* ==================================================================== */
10451 /* Register "SH_HARD_RESET" */
10452 /* SHub Hard Reset */
10453 /* ==================================================================== */
10455 typedef union sh_hard_reset_u {
10456 mmr_t sh_hard_reset_regval;
10458 mmr_t hard_reset : 1;
10459 mmr_t reserved_0 : 63;
10461 } sh_hard_reset_u_t;
10463 /* ==================================================================== */
10464 /* Register "SH_IO_PERM" */
10465 /* II MMR Access Permission Bits */
10466 /* ==================================================================== */
10468 typedef union sh_io_perm_u {
10469 mmr_t sh_io_perm_regval;
10471 mmr_t access_bits : 64;
10475 /* ==================================================================== */
10476 /* Register "SH_IOI_ACCESS" */
10477 /* II Interrupt Access Permission Bits */
10478 /* ==================================================================== */
10480 typedef union sh_ioi_access_u {
10481 mmr_t sh_ioi_access_regval;
10483 mmr_t access_bits : 64;
10485 } sh_ioi_access_u_t;
10487 /* ==================================================================== */
10488 /* Register "SH_IPI_ACCESS" */
10489 /* CPU interrupt Access Permission Bits */
10490 /* ==================================================================== */
10492 typedef union sh_ipi_access_u {
10493 mmr_t sh_ipi_access_regval;
10495 mmr_t access_bits : 64;
10497 } sh_ipi_access_u_t;
10499 /* ==================================================================== */
10500 /* Register "SH_JTAG_CONFIG" */
10501 /* SHub JTAG configuration */
10502 /* ==================================================================== */
10504 typedef union sh_jtag_config_u {
10505 mmr_t sh_jtag_config_regval;
10507 mmr_t md_clk_sel : 2;
10508 mmr_t ni_clk_sel : 1;
10509 mmr_t ii_clk_sel : 2;
10510 mmr_t wrt90_target : 14;
10511 mmr_t wrt90_overrider : 1;
10512 mmr_t wrt90_override : 1;
10513 mmr_t jtag_mci_reset_delay : 4;
10514 mmr_t jtag_mci_target : 14;
10515 mmr_t jtag_mci_override : 1;
10516 mmr_t fsb_config_ioq_depth : 1;
10517 mmr_t fsb_config_sample_binit : 1;
10518 mmr_t fsb_config_enable_bus_parking : 1;
10519 mmr_t fsb_config_clock_ratio : 5;
10520 mmr_t fsb_config_output_tristate : 4;
10521 mmr_t fsb_config_enable_bist : 1;
10522 mmr_t fsb_config_aux : 2;
10523 mmr_t gtl_config_re : 1;
10524 mmr_t reserved_0 : 8;
10525 } sh_jtag_config_s;
10526 } sh_jtag_config_u_t;
10528 /* ==================================================================== */
10529 /* Register "SH_SHUB_ID" */
10530 /* SHub ID Number */
10531 /* ==================================================================== */
10533 typedef union sh_shub_id_u {
10534 mmr_t sh_shub_id_regval;
10537 mmr_t manufacturer : 11;
10538 mmr_t part_number : 16;
10539 mmr_t revision : 4;
10540 mmr_t node_id : 11;
10541 mmr_t reserved_0 : 1;
10542 mmr_t sharing_mode : 2;
10543 mmr_t reserved_1 : 2;
10544 mmr_t nodes_per_bit : 5;
10545 mmr_t reserved_2 : 3;
10547 mmr_t reserved_3 : 7;
10551 /* ==================================================================== */
10552 /* Register "SH_SHUBS_PRESENT0" */
10553 /* Shubs 0 - 63 Present. Used for invalidate generation */
10554 /* ==================================================================== */
10556 typedef union sh_shubs_present0_u {
10557 mmr_t sh_shubs_present0_regval;
10559 mmr_t shubs_present0 : 64;
10560 } sh_shubs_present0_s;
10561 } sh_shubs_present0_u_t;
10563 /* ==================================================================== */
10564 /* Register "SH_SHUBS_PRESENT1" */
10565 /* Shubs 64 - 127 Present. Used for invalidate generation */
10566 /* ==================================================================== */
10568 typedef union sh_shubs_present1_u {
10569 mmr_t sh_shubs_present1_regval;
10571 mmr_t shubs_present1 : 64;
10572 } sh_shubs_present1_s;
10573 } sh_shubs_present1_u_t;
10575 /* ==================================================================== */
10576 /* Register "SH_SHUBS_PRESENT2" */
10577 /* Shubs 128 - 191 Present. Used for invalidate generation */
10578 /* ==================================================================== */
10580 typedef union sh_shubs_present2_u {
10581 mmr_t sh_shubs_present2_regval;
10583 mmr_t shubs_present2 : 64;
10584 } sh_shubs_present2_s;
10585 } sh_shubs_present2_u_t;
10587 /* ==================================================================== */
10588 /* Register "SH_SHUBS_PRESENT3" */
10589 /* Shubs 192 - 255 Present. Used for invalidate generation */
10590 /* ==================================================================== */
10592 typedef union sh_shubs_present3_u {
10593 mmr_t sh_shubs_present3_regval;
10595 mmr_t shubs_present3 : 64;
10596 } sh_shubs_present3_s;
10597 } sh_shubs_present3_u_t;
10599 /* ==================================================================== */
10600 /* Register "SH_SOFT_RESET" */
10601 /* SHub Soft Reset */
10602 /* ==================================================================== */
10604 typedef union sh_soft_reset_u {
10605 mmr_t sh_soft_reset_regval;
10607 mmr_t soft_reset : 1;
10608 mmr_t reserved_0 : 63;
10610 } sh_soft_reset_u_t;
10612 /* ==================================================================== */
10613 /* Register "SH_FIRST_ERROR" */
10614 /* Shub Global First Error Flags */
10615 /* ==================================================================== */
10617 typedef union sh_first_error_u {
10618 mmr_t sh_first_error_regval;
10620 mmr_t first_error : 19;
10621 mmr_t reserved_0 : 45;
10622 } sh_first_error_s;
10623 } sh_first_error_u_t;
10625 /* ==================================================================== */
10626 /* Register "SH_II_HW_TIME_STAMP" */
10627 /* II hardware error time stamp */
10628 /* ==================================================================== */
10630 typedef union sh_ii_hw_time_stamp_u {
10631 mmr_t sh_ii_hw_time_stamp_regval;
10635 } sh_ii_hw_time_stamp_s;
10636 } sh_ii_hw_time_stamp_u_t;
10638 /* ==================================================================== */
10639 /* Register "SH_LB_HW_TIME_STAMP" */
10640 /* LB hardware error time stamp */
10641 /* ==================================================================== */
10643 typedef union sh_lb_hw_time_stamp_u {
10644 mmr_t sh_lb_hw_time_stamp_regval;
10648 } sh_lb_hw_time_stamp_s;
10649 } sh_lb_hw_time_stamp_u_t;
10651 /* ==================================================================== */
10652 /* Register "SH_MD_COR_TIME_STAMP" */
10653 /* MD correctable error time stamp */
10654 /* ==================================================================== */
10656 typedef union sh_md_cor_time_stamp_u {
10657 mmr_t sh_md_cor_time_stamp_regval;
10661 } sh_md_cor_time_stamp_s;
10662 } sh_md_cor_time_stamp_u_t;
10664 /* ==================================================================== */
10665 /* Register "SH_MD_HW_TIME_STAMP" */
10666 /* MD hardware error time stamp */
10667 /* ==================================================================== */
10669 typedef union sh_md_hw_time_stamp_u {
10670 mmr_t sh_md_hw_time_stamp_regval;
10674 } sh_md_hw_time_stamp_s;
10675 } sh_md_hw_time_stamp_u_t;
10677 /* ==================================================================== */
10678 /* Register "SH_MD_UNCOR_TIME_STAMP" */
10679 /* MD uncorrectable error time stamp */
10680 /* ==================================================================== */
10682 typedef union sh_md_uncor_time_stamp_u {
10683 mmr_t sh_md_uncor_time_stamp_regval;
10687 } sh_md_uncor_time_stamp_s;
10688 } sh_md_uncor_time_stamp_u_t;
10690 /* ==================================================================== */
10691 /* Register "SH_PI_COR_TIME_STAMP" */
10692 /* PI correctable error time stamp */
10693 /* ==================================================================== */
10695 typedef union sh_pi_cor_time_stamp_u {
10696 mmr_t sh_pi_cor_time_stamp_regval;
10700 } sh_pi_cor_time_stamp_s;
10701 } sh_pi_cor_time_stamp_u_t;
10703 /* ==================================================================== */
10704 /* Register "SH_PI_HW_TIME_STAMP" */
10705 /* PI hardware error time stamp */
10706 /* ==================================================================== */
10708 typedef union sh_pi_hw_time_stamp_u {
10709 mmr_t sh_pi_hw_time_stamp_regval;
10713 } sh_pi_hw_time_stamp_s;
10714 } sh_pi_hw_time_stamp_u_t;
10716 /* ==================================================================== */
10717 /* Register "SH_PI_UNCOR_TIME_STAMP" */
10718 /* PI uncorrectable error time stamp */
10719 /* ==================================================================== */
10721 typedef union sh_pi_uncor_time_stamp_u {
10722 mmr_t sh_pi_uncor_time_stamp_regval;
10726 } sh_pi_uncor_time_stamp_s;
10727 } sh_pi_uncor_time_stamp_u_t;
10729 /* ==================================================================== */
10730 /* Register "SH_PROC0_ADV_TIME_STAMP" */
10731 /* Proc 0 advisory time stamp */
10732 /* ==================================================================== */
10734 typedef union sh_proc0_adv_time_stamp_u {
10735 mmr_t sh_proc0_adv_time_stamp_regval;
10739 } sh_proc0_adv_time_stamp_s;
10740 } sh_proc0_adv_time_stamp_u_t;
10742 /* ==================================================================== */
10743 /* Register "SH_PROC0_ERR_TIME_STAMP" */
10744 /* Proc 0 error time stamp */
10745 /* ==================================================================== */
10747 typedef union sh_proc0_err_time_stamp_u {
10748 mmr_t sh_proc0_err_time_stamp_regval;
10752 } sh_proc0_err_time_stamp_s;
10753 } sh_proc0_err_time_stamp_u_t;
10755 /* ==================================================================== */
10756 /* Register "SH_PROC1_ADV_TIME_STAMP" */
10757 /* Proc 1 advisory time stamp */
10758 /* ==================================================================== */
10760 typedef union sh_proc1_adv_time_stamp_u {
10761 mmr_t sh_proc1_adv_time_stamp_regval;
10765 } sh_proc1_adv_time_stamp_s;
10766 } sh_proc1_adv_time_stamp_u_t;
10768 /* ==================================================================== */
10769 /* Register "SH_PROC1_ERR_TIME_STAMP" */
10770 /* Proc 1 error time stamp */
10771 /* ==================================================================== */
10773 typedef union sh_proc1_err_time_stamp_u {
10774 mmr_t sh_proc1_err_time_stamp_regval;
10778 } sh_proc1_err_time_stamp_s;
10779 } sh_proc1_err_time_stamp_u_t;
10781 /* ==================================================================== */
10782 /* Register "SH_PROC2_ADV_TIME_STAMP" */
10783 /* Proc 2 advisory time stamp */
10784 /* ==================================================================== */
10786 typedef union sh_proc2_adv_time_stamp_u {
10787 mmr_t sh_proc2_adv_time_stamp_regval;
10791 } sh_proc2_adv_time_stamp_s;
10792 } sh_proc2_adv_time_stamp_u_t;
10794 /* ==================================================================== */
10795 /* Register "SH_PROC2_ERR_TIME_STAMP" */
10796 /* Proc 2 error time stamp */
10797 /* ==================================================================== */
10799 typedef union sh_proc2_err_time_stamp_u {
10800 mmr_t sh_proc2_err_time_stamp_regval;
10804 } sh_proc2_err_time_stamp_s;
10805 } sh_proc2_err_time_stamp_u_t;
10807 /* ==================================================================== */
10808 /* Register "SH_PROC3_ADV_TIME_STAMP" */
10809 /* Proc 3 advisory time stamp */
10810 /* ==================================================================== */
10812 typedef union sh_proc3_adv_time_stamp_u {
10813 mmr_t sh_proc3_adv_time_stamp_regval;
10817 } sh_proc3_adv_time_stamp_s;
10818 } sh_proc3_adv_time_stamp_u_t;
10820 /* ==================================================================== */
10821 /* Register "SH_PROC3_ERR_TIME_STAMP" */
10822 /* Proc 3 error time stamp */
10823 /* ==================================================================== */
10825 typedef union sh_proc3_err_time_stamp_u {
10826 mmr_t sh_proc3_err_time_stamp_regval;
10830 } sh_proc3_err_time_stamp_s;
10831 } sh_proc3_err_time_stamp_u_t;
10833 /* ==================================================================== */
10834 /* Register "SH_XN_COR_TIME_STAMP" */
10835 /* XN correctable error time stamp */
10836 /* ==================================================================== */
10838 typedef union sh_xn_cor_time_stamp_u {
10839 mmr_t sh_xn_cor_time_stamp_regval;
10843 } sh_xn_cor_time_stamp_s;
10844 } sh_xn_cor_time_stamp_u_t;
10846 /* ==================================================================== */
10847 /* Register "SH_XN_HW_TIME_STAMP" */
10848 /* XN hardware error time stamp */
10849 /* ==================================================================== */
10851 typedef union sh_xn_hw_time_stamp_u {
10852 mmr_t sh_xn_hw_time_stamp_regval;
10856 } sh_xn_hw_time_stamp_s;
10857 } sh_xn_hw_time_stamp_u_t;
10859 /* ==================================================================== */
10860 /* Register "SH_XN_UNCOR_TIME_STAMP" */
10861 /* XN uncorrectable error time stamp */
10862 /* ==================================================================== */
10864 typedef union sh_xn_uncor_time_stamp_u {
10865 mmr_t sh_xn_uncor_time_stamp_regval;
10869 } sh_xn_uncor_time_stamp_s;
10870 } sh_xn_uncor_time_stamp_u_t;
10872 /* ==================================================================== */
10873 /* Register "SH_DEBUG_PORT" */
10874 /* SHub Debug Port */
10875 /* ==================================================================== */
10877 typedef union sh_debug_port_u {
10878 mmr_t sh_debug_port_regval;
10880 mmr_t debug_nibble0 : 4;
10881 mmr_t debug_nibble1 : 4;
10882 mmr_t debug_nibble2 : 4;
10883 mmr_t debug_nibble3 : 4;
10884 mmr_t debug_nibble4 : 4;
10885 mmr_t debug_nibble5 : 4;
10886 mmr_t debug_nibble6 : 4;
10887 mmr_t debug_nibble7 : 4;
10888 mmr_t reserved_0 : 32;
10890 } sh_debug_port_u_t;
10892 /* ==================================================================== */
10893 /* Register "SH_II_DEBUG_DATA" */
10894 /* II Debug Data */
10895 /* ==================================================================== */
10897 typedef union sh_ii_debug_data_u {
10898 mmr_t sh_ii_debug_data_regval;
10900 mmr_t ii_data : 32;
10901 mmr_t reserved_0 : 32;
10902 } sh_ii_debug_data_s;
10903 } sh_ii_debug_data_u_t;
10905 /* ==================================================================== */
10906 /* Register "SH_II_WRAP_DEBUG_DATA" */
10907 /* SHub II Wrapper Debug Data */
10908 /* ==================================================================== */
10910 typedef union sh_ii_wrap_debug_data_u {
10911 mmr_t sh_ii_wrap_debug_data_regval;
10913 mmr_t ii_wrap_data : 32;
10914 mmr_t reserved_0 : 32;
10915 } sh_ii_wrap_debug_data_s;
10916 } sh_ii_wrap_debug_data_u_t;
10918 /* ==================================================================== */
10919 /* Register "SH_LB_DEBUG_DATA" */
10920 /* SHub LB Debug Data */
10921 /* ==================================================================== */
10923 typedef union sh_lb_debug_data_u {
10924 mmr_t sh_lb_debug_data_regval;
10926 mmr_t lb_data : 32;
10927 mmr_t reserved_0 : 32;
10928 } sh_lb_debug_data_s;
10929 } sh_lb_debug_data_u_t;
10931 /* ==================================================================== */
10932 /* Register "SH_MD_DEBUG_DATA" */
10933 /* SHub MD Debug Data */
10934 /* ==================================================================== */
10936 typedef union sh_md_debug_data_u {
10937 mmr_t sh_md_debug_data_regval;
10939 mmr_t md_data : 32;
10940 mmr_t reserved_0 : 32;
10941 } sh_md_debug_data_s;
10942 } sh_md_debug_data_u_t;
10944 /* ==================================================================== */
10945 /* Register "SH_PI_DEBUG_DATA" */
10946 /* SHub PI Debug Data */
10947 /* ==================================================================== */
10949 typedef union sh_pi_debug_data_u {
10950 mmr_t sh_pi_debug_data_regval;
10952 mmr_t pi_data : 32;
10953 mmr_t reserved_0 : 32;
10954 } sh_pi_debug_data_s;
10955 } sh_pi_debug_data_u_t;
10957 /* ==================================================================== */
10958 /* Register "SH_XN_DEBUG_DATA" */
10959 /* SHub XN Debug Data */
10960 /* ==================================================================== */
10962 typedef union sh_xn_debug_data_u {
10963 mmr_t sh_xn_debug_data_regval;
10965 mmr_t xn_data : 32;
10966 mmr_t reserved_0 : 32;
10967 } sh_xn_debug_data_s;
10968 } sh_xn_debug_data_u_t;
10970 /* ==================================================================== */
10971 /* Register "SH_TSF_ARMED_STATE" */
10972 /* Trigger sequencing facility arm state */
10973 /* ==================================================================== */
10975 typedef union sh_tsf_armed_state_u {
10976 mmr_t sh_tsf_armed_state_regval;
10979 mmr_t reserved_0 : 56;
10980 } sh_tsf_armed_state_s;
10981 } sh_tsf_armed_state_u_t;
10983 /* ==================================================================== */
10984 /* Register "SH_TSF_COUNTER_VALUE" */
10985 /* Trigger sequencing facility counter value */
10986 /* ==================================================================== */
10988 typedef union sh_tsf_counter_value_u {
10989 mmr_t sh_tsf_counter_value_regval;
10991 mmr_t count_32 : 32;
10992 mmr_t count_16 : 16;
10993 mmr_t count_8b : 8;
10994 mmr_t count_8a : 8;
10995 } sh_tsf_counter_value_s;
10996 } sh_tsf_counter_value_u_t;
10998 /* ==================================================================== */
10999 /* Register "SH_TSF_TRIGGERED_STATE" */
11000 /* Trigger sequencing facility triggered state */
11001 /* ==================================================================== */
11003 typedef union sh_tsf_triggered_state_u {
11004 mmr_t sh_tsf_triggered_state_regval;
11007 mmr_t reserved_0 : 56;
11008 } sh_tsf_triggered_state_s;
11009 } sh_tsf_triggered_state_u_t;
11011 /* ==================================================================== */
11012 /* Register "SH_VEC_RDDATA" */
11013 /* Vector Reply Message Data */
11014 /* ==================================================================== */
11016 typedef union sh_vec_rddata_u {
11017 mmr_t sh_vec_rddata_regval;
11021 } sh_vec_rddata_u_t;
11023 /* ==================================================================== */
11024 /* Register "SH_VEC_RETURN" */
11025 /* Vector Reply Message Return Route */
11026 /* ==================================================================== */
11028 typedef union sh_vec_return_u {
11029 mmr_t sh_vec_return_regval;
11033 } sh_vec_return_u_t;
11035 /* ==================================================================== */
11036 /* Register "SH_VEC_STATUS" */
11037 /* Vector Reply Message Status */
11038 /* ==================================================================== */
11040 typedef union sh_vec_status_u {
11041 mmr_t sh_vec_status_regval;
11044 mmr_t address : 32;
11047 mmr_t reserved_0 : 2;
11049 mmr_t status_valid : 1;
11051 } sh_vec_status_u_t;
11053 /* ==================================================================== */
11054 /* Register "SH_PERFORMANCE_COUNT0_CONTROL" */
11055 /* Performance Counter 0 Control */
11056 /* ==================================================================== */
11058 typedef union sh_performance_count0_control_u {
11059 mmr_t sh_performance_count0_control_regval;
11061 mmr_t up_stimulus : 5;
11062 mmr_t up_event : 1;
11063 mmr_t up_polarity : 1;
11065 mmr_t dn_stimulus : 5;
11066 mmr_t dn_event : 1;
11067 mmr_t dn_polarity : 1;
11069 mmr_t inc_enable : 1;
11070 mmr_t dec_enable : 1;
11071 mmr_t peak_det_enable : 1;
11072 mmr_t reserved_0 : 45;
11073 } sh_performance_count0_control_s;
11074 } sh_performance_count0_control_u_t;
11076 /* ==================================================================== */
11077 /* Register "SH_PERFORMANCE_COUNT1_CONTROL" */
11078 /* Performance Counter 1 Control */
11079 /* ==================================================================== */
11081 typedef union sh_performance_count1_control_u {
11082 mmr_t sh_performance_count1_control_regval;
11084 mmr_t up_stimulus : 5;
11085 mmr_t up_event : 1;
11086 mmr_t up_polarity : 1;
11088 mmr_t dn_stimulus : 5;
11089 mmr_t dn_event : 1;
11090 mmr_t dn_polarity : 1;
11092 mmr_t inc_enable : 1;
11093 mmr_t dec_enable : 1;
11094 mmr_t peak_det_enable : 1;
11095 mmr_t reserved_0 : 45;
11096 } sh_performance_count1_control_s;
11097 } sh_performance_count1_control_u_t;
11099 /* ==================================================================== */
11100 /* Register "SH_PERFORMANCE_COUNT2_CONTROL" */
11101 /* Performance Counter 2 Control */
11102 /* ==================================================================== */
11104 typedef union sh_performance_count2_control_u {
11105 mmr_t sh_performance_count2_control_regval;
11107 mmr_t up_stimulus : 5;
11108 mmr_t up_event : 1;
11109 mmr_t up_polarity : 1;
11111 mmr_t dn_stimulus : 5;
11112 mmr_t dn_event : 1;
11113 mmr_t dn_polarity : 1;
11115 mmr_t inc_enable : 1;
11116 mmr_t dec_enable : 1;
11117 mmr_t peak_det_enable : 1;
11118 mmr_t reserved_0 : 45;
11119 } sh_performance_count2_control_s;
11120 } sh_performance_count2_control_u_t;
11122 /* ==================================================================== */
11123 /* Register "SH_PERFORMANCE_COUNT3_CONTROL" */
11124 /* Performance Counter 3 Control */
11125 /* ==================================================================== */
11127 typedef union sh_performance_count3_control_u {
11128 mmr_t sh_performance_count3_control_regval;
11130 mmr_t up_stimulus : 5;
11131 mmr_t up_event : 1;
11132 mmr_t up_polarity : 1;
11134 mmr_t dn_stimulus : 5;
11135 mmr_t dn_event : 1;
11136 mmr_t dn_polarity : 1;
11138 mmr_t inc_enable : 1;
11139 mmr_t dec_enable : 1;
11140 mmr_t peak_det_enable : 1;
11141 mmr_t reserved_0 : 45;
11142 } sh_performance_count3_control_s;
11143 } sh_performance_count3_control_u_t;
11145 /* ==================================================================== */
11146 /* Register "SH_PERFORMANCE_COUNT4_CONTROL" */
11147 /* Performance Counter 4 Control */
11148 /* ==================================================================== */
11150 typedef union sh_performance_count4_control_u {
11151 mmr_t sh_performance_count4_control_regval;
11153 mmr_t up_stimulus : 5;
11154 mmr_t up_event : 1;
11155 mmr_t up_polarity : 1;
11157 mmr_t dn_stimulus : 5;
11158 mmr_t dn_event : 1;
11159 mmr_t dn_polarity : 1;
11161 mmr_t inc_enable : 1;
11162 mmr_t dec_enable : 1;
11163 mmr_t peak_det_enable : 1;
11164 mmr_t reserved_0 : 45;
11165 } sh_performance_count4_control_s;
11166 } sh_performance_count4_control_u_t;
11168 /* ==================================================================== */
11169 /* Register "SH_PERFORMANCE_COUNT5_CONTROL" */
11170 /* Performance Counter 5 Control */
11171 /* ==================================================================== */
11173 typedef union sh_performance_count5_control_u {
11174 mmr_t sh_performance_count5_control_regval;
11176 mmr_t up_stimulus : 5;
11177 mmr_t up_event : 1;
11178 mmr_t up_polarity : 1;
11180 mmr_t dn_stimulus : 5;
11181 mmr_t dn_event : 1;
11182 mmr_t dn_polarity : 1;
11184 mmr_t inc_enable : 1;
11185 mmr_t dec_enable : 1;
11186 mmr_t peak_det_enable : 1;
11187 mmr_t reserved_0 : 45;
11188 } sh_performance_count5_control_s;
11189 } sh_performance_count5_control_u_t;
11191 /* ==================================================================== */
11192 /* Register "SH_PERFORMANCE_COUNT6_CONTROL" */
11193 /* Performance Counter 6 Control */
11194 /* ==================================================================== */
11196 typedef union sh_performance_count6_control_u {
11197 mmr_t sh_performance_count6_control_regval;
11199 mmr_t up_stimulus : 5;
11200 mmr_t up_event : 1;
11201 mmr_t up_polarity : 1;
11203 mmr_t dn_stimulus : 5;
11204 mmr_t dn_event : 1;
11205 mmr_t dn_polarity : 1;
11207 mmr_t inc_enable : 1;
11208 mmr_t dec_enable : 1;
11209 mmr_t peak_det_enable : 1;
11210 mmr_t reserved_0 : 45;
11211 } sh_performance_count6_control_s;
11212 } sh_performance_count6_control_u_t;
11214 /* ==================================================================== */
11215 /* Register "SH_PERFORMANCE_COUNT7_CONTROL" */
11216 /* Performance Counter 7 Control */
11217 /* ==================================================================== */
11219 typedef union sh_performance_count7_control_u {
11220 mmr_t sh_performance_count7_control_regval;
11222 mmr_t up_stimulus : 5;
11223 mmr_t up_event : 1;
11224 mmr_t up_polarity : 1;
11226 mmr_t dn_stimulus : 5;
11227 mmr_t dn_event : 1;
11228 mmr_t dn_polarity : 1;
11230 mmr_t inc_enable : 1;
11231 mmr_t dec_enable : 1;
11232 mmr_t peak_det_enable : 1;
11233 mmr_t reserved_0 : 45;
11234 } sh_performance_count7_control_s;
11235 } sh_performance_count7_control_u_t;
11237 /* ==================================================================== */
11238 /* Register "SH_PROFILE_DN_CONTROL" */
11239 /* Profile Counter Down Control */
11240 /* ==================================================================== */
11242 typedef union sh_profile_dn_control_u {
11243 mmr_t sh_profile_dn_control_regval;
11245 mmr_t stimulus : 5;
11247 mmr_t polarity : 1;
11249 mmr_t reserved_0 : 56;
11250 } sh_profile_dn_control_s;
11251 } sh_profile_dn_control_u_t;
11253 /* ==================================================================== */
11254 /* Register "SH_PROFILE_PEAK_CONTROL" */
11255 /* Profile Counter Peak Control */
11256 /* ==================================================================== */
11258 typedef union sh_profile_peak_control_u {
11259 mmr_t sh_profile_peak_control_regval;
11261 mmr_t reserved_0 : 3;
11262 mmr_t stimulus : 1;
11263 mmr_t reserved_1 : 1;
11265 mmr_t polarity : 1;
11266 mmr_t reserved_2 : 57;
11267 } sh_profile_peak_control_s;
11268 } sh_profile_peak_control_u_t;
11270 /* ==================================================================== */
11271 /* Register "SH_PROFILE_RANGE" */
11272 /* Profile Counter Range */
11273 /* ==================================================================== */
11275 typedef union sh_profile_range_u {
11276 mmr_t sh_profile_range_regval;
11286 } sh_profile_range_s;
11287 } sh_profile_range_u_t;
11289 /* ==================================================================== */
11290 /* Register "SH_PROFILE_UP_CONTROL" */
11291 /* Profile Counter Up Control */
11292 /* ==================================================================== */
11294 typedef union sh_profile_up_control_u {
11295 mmr_t sh_profile_up_control_regval;
11297 mmr_t stimulus : 5;
11299 mmr_t polarity : 1;
11301 mmr_t reserved_0 : 56;
11302 } sh_profile_up_control_s;
11303 } sh_profile_up_control_u_t;
11305 /* ==================================================================== */
11306 /* Register "SH_PERFORMANCE_COUNTER0" */
11307 /* Performance Counter 0 */
11308 /* ==================================================================== */
11310 typedef union sh_performance_counter0_u {
11311 mmr_t sh_performance_counter0_regval;
11314 mmr_t reserved_0 : 32;
11315 } sh_performance_counter0_s;
11316 } sh_performance_counter0_u_t;
11318 /* ==================================================================== */
11319 /* Register "SH_PERFORMANCE_COUNTER1" */
11320 /* Performance Counter 1 */
11321 /* ==================================================================== */
11323 typedef union sh_performance_counter1_u {
11324 mmr_t sh_performance_counter1_regval;
11327 mmr_t reserved_0 : 32;
11328 } sh_performance_counter1_s;
11329 } sh_performance_counter1_u_t;
11331 /* ==================================================================== */
11332 /* Register "SH_PERFORMANCE_COUNTER2" */
11333 /* Performance Counter 2 */
11334 /* ==================================================================== */
11336 typedef union sh_performance_counter2_u {
11337 mmr_t sh_performance_counter2_regval;
11340 mmr_t reserved_0 : 32;
11341 } sh_performance_counter2_s;
11342 } sh_performance_counter2_u_t;
11344 /* ==================================================================== */
11345 /* Register "SH_PERFORMANCE_COUNTER3" */
11346 /* Performance Counter 3 */
11347 /* ==================================================================== */
11349 typedef union sh_performance_counter3_u {
11350 mmr_t sh_performance_counter3_regval;
11353 mmr_t reserved_0 : 32;
11354 } sh_performance_counter3_s;
11355 } sh_performance_counter3_u_t;
11357 /* ==================================================================== */
11358 /* Register "SH_PERFORMANCE_COUNTER4" */
11359 /* Performance Counter 4 */
11360 /* ==================================================================== */
11362 typedef union sh_performance_counter4_u {
11363 mmr_t sh_performance_counter4_regval;
11366 mmr_t reserved_0 : 32;
11367 } sh_performance_counter4_s;
11368 } sh_performance_counter4_u_t;
11370 /* ==================================================================== */
11371 /* Register "SH_PERFORMANCE_COUNTER5" */
11372 /* Performance Counter 5 */
11373 /* ==================================================================== */
11375 typedef union sh_performance_counter5_u {
11376 mmr_t sh_performance_counter5_regval;
11379 mmr_t reserved_0 : 32;
11380 } sh_performance_counter5_s;
11381 } sh_performance_counter5_u_t;
11383 /* ==================================================================== */
11384 /* Register "SH_PERFORMANCE_COUNTER6" */
11385 /* Performance Counter 6 */
11386 /* ==================================================================== */
11388 typedef union sh_performance_counter6_u {
11389 mmr_t sh_performance_counter6_regval;
11392 mmr_t reserved_0 : 32;
11393 } sh_performance_counter6_s;
11394 } sh_performance_counter6_u_t;
11396 /* ==================================================================== */
11397 /* Register "SH_PERFORMANCE_COUNTER7" */
11398 /* Performance Counter 7 */
11399 /* ==================================================================== */
11401 typedef union sh_performance_counter7_u {
11402 mmr_t sh_performance_counter7_regval;
11405 mmr_t reserved_0 : 32;
11406 } sh_performance_counter7_s;
11407 } sh_performance_counter7_u_t;
11409 /* ==================================================================== */
11410 /* Register "SH_PROFILE_COUNTER" */
11411 /* Profile Counter */
11412 /* ==================================================================== */
11414 typedef union sh_profile_counter_u {
11415 mmr_t sh_profile_counter_regval;
11418 mmr_t reserved_0 : 56;
11419 } sh_profile_counter_s;
11420 } sh_profile_counter_u_t;
11422 /* ==================================================================== */
11423 /* Register "SH_PROFILE_PEAK" */
11424 /* Profile Peak Counter */
11425 /* ==================================================================== */
11427 typedef union sh_profile_peak_u {
11428 mmr_t sh_profile_peak_regval;
11431 mmr_t reserved_0 : 56;
11432 } sh_profile_peak_s;
11433 } sh_profile_peak_u_t;
11435 /* ==================================================================== */
11436 /* Register "SH_PTC_0" */
11437 /* Puge Translation Cache Message Configuration Information */
11438 /* ==================================================================== */
11440 typedef union sh_ptc_0_u {
11441 mmr_t sh_ptc_0_regval;
11444 mmr_t reserved_0 : 1;
11447 mmr_t reserved_1 : 31;
11452 /* ==================================================================== */
11453 /* Register "SH_PTC_1" */
11454 /* Puge Translation Cache Message Configuration Information */
11455 /* ==================================================================== */
11457 typedef union sh_ptc_1_u {
11458 mmr_t sh_ptc_1_regval;
11460 mmr_t reserved_0 : 12;
11462 mmr_t reserved_1 : 2;
11467 /* ==================================================================== */
11468 /* Register "SH_PTC_PARMS" */
11469 /* PTC Time-out parmaeters */
11470 /* ==================================================================== */
11472 typedef union sh_ptc_parms_u {
11473 mmr_t sh_ptc_parms_regval;
11475 mmr_t ptc_to_wrap : 24;
11476 mmr_t ptc_to_val : 12;
11477 mmr_t reserved_0 : 28;
11479 } sh_ptc_parms_u_t;
11481 /* ==================================================================== */
11482 /* Register "SH_INT_CMPA" */
11483 /* RTC Compare Value for Processor A */
11484 /* ==================================================================== */
11486 typedef union sh_int_cmpa_u {
11487 mmr_t sh_int_cmpa_regval;
11489 mmr_t real_time_cmpa : 55;
11490 mmr_t reserved_0 : 9;
11494 /* ==================================================================== */
11495 /* Register "SH_INT_CMPB" */
11496 /* RTC Compare Value for Processor B */
11497 /* ==================================================================== */
11499 typedef union sh_int_cmpb_u {
11500 mmr_t sh_int_cmpb_regval;
11502 mmr_t real_time_cmpb : 55;
11503 mmr_t reserved_0 : 9;
11507 /* ==================================================================== */
11508 /* Register "SH_INT_CMPC" */
11509 /* RTC Compare Value for Processor C */
11510 /* ==================================================================== */
11512 typedef union sh_int_cmpc_u {
11513 mmr_t sh_int_cmpc_regval;
11515 mmr_t real_time_cmpc : 55;
11516 mmr_t reserved_0 : 9;
11520 /* ==================================================================== */
11521 /* Register "SH_INT_CMPD" */
11522 /* RTC Compare Value for Processor D */
11523 /* ==================================================================== */
11525 typedef union sh_int_cmpd_u {
11526 mmr_t sh_int_cmpd_regval;
11528 mmr_t real_time_cmpd : 55;
11529 mmr_t reserved_0 : 9;
11533 /* ==================================================================== */
11534 /* Register "SH_INT_PROF" */
11535 /* Profile Compare Registers */
11536 /* ==================================================================== */
11538 typedef union sh_int_prof_u {
11539 mmr_t sh_int_prof_regval;
11541 mmr_t profile_compare : 32;
11542 mmr_t reserved_0 : 32;
11546 /* ==================================================================== */
11547 /* Register "SH_RTC" */
11548 /* Real-time Clock */
11549 /* ==================================================================== */
11551 typedef union sh_rtc_u {
11552 mmr_t sh_rtc_regval;
11554 mmr_t real_time_clock : 55;
11555 mmr_t reserved_0 : 9;
11559 /* ==================================================================== */
11560 /* Register "SH_SCRATCH0" */
11561 /* Scratch Register 0 */
11562 /* ==================================================================== */
11564 typedef union sh_scratch0_u {
11565 mmr_t sh_scratch0_regval;
11567 mmr_t scratch0 : 64;
11571 /* ==================================================================== */
11572 /* Register "SH_SCRATCH1" */
11573 /* Scratch Register 1 */
11574 /* ==================================================================== */
11576 typedef union sh_scratch1_u {
11577 mmr_t sh_scratch1_regval;
11579 mmr_t scratch1 : 64;
11583 /* ==================================================================== */
11584 /* Register "SH_SCRATCH2" */
11585 /* Scratch Register 2 */
11586 /* ==================================================================== */
11588 typedef union sh_scratch2_u {
11589 mmr_t sh_scratch2_regval;
11591 mmr_t scratch2 : 64;
11595 /* ==================================================================== */
11596 /* Register "SH_SCRATCH3" */
11597 /* Scratch Register 3 */
11598 /* ==================================================================== */
11600 typedef union sh_scratch3_u {
11601 mmr_t sh_scratch3_regval;
11603 mmr_t scratch3 : 1;
11604 mmr_t reserved_0 : 63;
11608 /* ==================================================================== */
11609 /* Register "SH_SCRATCH4" */
11610 /* Scratch Register 4 */
11611 /* ==================================================================== */
11613 typedef union sh_scratch4_u {
11614 mmr_t sh_scratch4_regval;
11616 mmr_t scratch4 : 1;
11617 mmr_t reserved_0 : 63;
11621 /* ==================================================================== */
11622 /* Register "SH_CRB_MESSAGE_CONTROL" */
11623 /* Coherent Request Buffer Message Control */
11624 /* ==================================================================== */
11626 typedef union sh_crb_message_control_u {
11627 mmr_t sh_crb_message_control_regval;
11629 mmr_t system_coherence_enable : 1;
11630 mmr_t local_speculative_message_enable : 1;
11631 mmr_t remote_speculative_message_enable : 1;
11632 mmr_t message_color : 1;
11633 mmr_t message_color_enable : 1;
11634 mmr_t rrb_attribute_mismatch_fsb_enable : 1;
11635 mmr_t wrb_attribute_mismatch_fsb_enable : 1;
11636 mmr_t irb_attribute_mismatch_fsb_enable : 1;
11637 mmr_t rrb_attribute_mismatch_xb_enable : 1;
11638 mmr_t wrb_attribute_mismatch_xb_enable : 1;
11639 mmr_t suppress_bogus_writes : 1;
11640 mmr_t enable_ivack_consolidation : 1;
11641 mmr_t reserved_0 : 20;
11642 mmr_t ivack_stall_count : 16;
11643 mmr_t ivack_throttle_control : 16;
11644 } sh_crb_message_control_s;
11645 } sh_crb_message_control_u_t;
11647 /* ==================================================================== */
11648 /* Register "SH_CRB_NACK_LIMIT" */
11649 /* CRB Nack Limit */
11650 /* ==================================================================== */
11652 typedef union sh_crb_nack_limit_u {
11653 mmr_t sh_crb_nack_limit_regval;
11656 mmr_t pri_freq : 4;
11657 mmr_t reserved_0 : 47;
11659 } sh_crb_nack_limit_s;
11660 } sh_crb_nack_limit_u_t;
11662 /* ==================================================================== */
11663 /* Register "SH_CRB_TIMEOUT_PRESCALE" */
11664 /* Coherent Request Buffer Timeout Prescale */
11665 /* ==================================================================== */
11667 typedef union sh_crb_timeout_prescale_u {
11668 mmr_t sh_crb_timeout_prescale_regval;
11670 mmr_t scaling_factor : 32;
11671 mmr_t reserved_0 : 32;
11672 } sh_crb_timeout_prescale_s;
11673 } sh_crb_timeout_prescale_u_t;
11675 /* ==================================================================== */
11676 /* Register "SH_CRB_TIMEOUT_SKID" */
11677 /* Coherent Request Buffer Timeout Skid Limit */
11678 /* ==================================================================== */
11680 typedef union sh_crb_timeout_skid_u {
11681 mmr_t sh_crb_timeout_skid_regval;
11684 mmr_t reserved_0 : 57;
11685 mmr_t reset_skid_count : 1;
11686 } sh_crb_timeout_skid_s;
11687 } sh_crb_timeout_skid_u_t;
11689 /* ==================================================================== */
11690 /* Register "SH_MEMORY_WRITE_STATUS_0" */
11691 /* Memory Write Status for CPU 0 */
11692 /* ==================================================================== */
11694 typedef union sh_memory_write_status_0_u {
11695 mmr_t sh_memory_write_status_0_regval;
11697 mmr_t pending_write_count : 6;
11698 mmr_t reserved_0 : 58;
11699 } sh_memory_write_status_0_s;
11700 } sh_memory_write_status_0_u_t;
11702 /* ==================================================================== */
11703 /* Register "SH_MEMORY_WRITE_STATUS_1" */
11704 /* Memory Write Status for CPU 1 */
11705 /* ==================================================================== */
11707 typedef union sh_memory_write_status_1_u {
11708 mmr_t sh_memory_write_status_1_regval;
11710 mmr_t pending_write_count : 6;
11711 mmr_t reserved_0 : 58;
11712 } sh_memory_write_status_1_s;
11713 } sh_memory_write_status_1_u_t;
11715 /* ==================================================================== */
11716 /* Register "SH_PIO_WRITE_STATUS_0" */
11717 /* PIO Write Status for CPU 0 */
11718 /* ==================================================================== */
11720 typedef union sh_pio_write_status_0_u {
11721 mmr_t sh_pio_write_status_0_regval;
11723 mmr_t multi_write_error : 1;
11724 mmr_t write_deadlock : 1;
11725 mmr_t write_error : 1;
11726 mmr_t write_error_address : 47;
11727 mmr_t reserved_0 : 6;
11728 mmr_t pending_write_count : 6;
11729 mmr_t reserved_1 : 1;
11730 mmr_t writes_ok : 1;
11731 } sh_pio_write_status_0_s;
11732 } sh_pio_write_status_0_u_t;
11734 /* ==================================================================== */
11735 /* Register "SH_PIO_WRITE_STATUS_1" */
11736 /* PIO Write Status for CPU 1 */
11737 /* ==================================================================== */
11739 typedef union sh_pio_write_status_1_u {
11740 mmr_t sh_pio_write_status_1_regval;
11742 mmr_t multi_write_error : 1;
11743 mmr_t write_deadlock : 1;
11744 mmr_t write_error : 1;
11745 mmr_t write_error_address : 47;
11746 mmr_t reserved_0 : 6;
11747 mmr_t pending_write_count : 6;
11748 mmr_t reserved_1 : 1;
11749 mmr_t writes_ok : 1;
11750 } sh_pio_write_status_1_s;
11751 } sh_pio_write_status_1_u_t;
11753 /* ==================================================================== */
11754 /* Register "SH_MEMORY_WRITE_STATUS_NON_USER_0" */
11755 /* Memory Write Status for CPU 0. OS access only */
11756 /* ==================================================================== */
11758 typedef union sh_memory_write_status_non_user_0_u {
11759 mmr_t sh_memory_write_status_non_user_0_regval;
11761 mmr_t pending_write_count : 6;
11762 mmr_t reserved_0 : 57;
11764 } sh_memory_write_status_non_user_0_s;
11765 } sh_memory_write_status_non_user_0_u_t;
11767 /* ==================================================================== */
11768 /* Register "SH_MEMORY_WRITE_STATUS_NON_USER_1" */
11769 /* Memory Write Status for CPU 1. OS access only */
11770 /* ==================================================================== */
11772 typedef union sh_memory_write_status_non_user_1_u {
11773 mmr_t sh_memory_write_status_non_user_1_regval;
11775 mmr_t pending_write_count : 6;
11776 mmr_t reserved_0 : 57;
11778 } sh_memory_write_status_non_user_1_s;
11779 } sh_memory_write_status_non_user_1_u_t;
11781 /* ==================================================================== */
11782 /* Register "SH_MMRBIST_ERR" */
11783 /* Error capture for bist read errors */
11784 /* ==================================================================== */
11786 typedef union sh_mmrbist_err_u {
11787 mmr_t sh_mmrbist_err_regval;
11790 mmr_t reserved_0 : 3;
11791 mmr_t detected : 1;
11792 mmr_t multiple_detected : 1;
11793 mmr_t cancelled : 1;
11794 mmr_t reserved_1 : 25;
11795 } sh_mmrbist_err_s;
11796 } sh_mmrbist_err_u_t;
11798 /* ==================================================================== */
11799 /* Register "SH_MISC_ERR_HDR_LOWER" */
11800 /* Header capture register */
11801 /* ==================================================================== */
11803 typedef union sh_misc_err_hdr_lower_u {
11804 mmr_t sh_misc_err_hdr_lower_regval;
11806 mmr_t reserved_0 : 3;
11810 mmr_t reserved_1 : 2;
11812 mmr_t reserved_2 : 2;
11814 } sh_misc_err_hdr_lower_s;
11815 } sh_misc_err_hdr_lower_u_t;
11817 /* ==================================================================== */
11818 /* Register "SH_MISC_ERR_HDR_UPPER" */
11819 /* Error header capture packet and protocol errors */
11820 /* ==================================================================== */
11822 typedef union sh_misc_err_hdr_upper_u {
11823 mmr_t sh_misc_err_hdr_upper_regval;
11825 mmr_t dir_protocol : 1;
11826 mmr_t illegal_cmd : 1;
11827 mmr_t nonexist_addr : 1;
11831 mmr_t pi_pkt_size : 1;
11832 mmr_t xn_pkt_size : 1;
11833 mmr_t reserved_0 : 12;
11835 mmr_t reserved_1 : 35;
11836 } sh_misc_err_hdr_upper_s;
11837 } sh_misc_err_hdr_upper_u_t;
11839 /* ==================================================================== */
11840 /* Register "SH_DIR_UC_ERR_HDR_LOWER" */
11841 /* Header capture register */
11842 /* ==================================================================== */
11844 typedef union sh_dir_uc_err_hdr_lower_u {
11845 mmr_t sh_dir_uc_err_hdr_lower_regval;
11847 mmr_t reserved_0 : 3;
11851 mmr_t reserved_1 : 2;
11853 mmr_t reserved_2 : 2;
11855 } sh_dir_uc_err_hdr_lower_s;
11856 } sh_dir_uc_err_hdr_lower_u_t;
11858 /* ==================================================================== */
11859 /* Register "SH_DIR_UC_ERR_HDR_UPPER" */
11860 /* Error header capture packet and protocol errors */
11861 /* ==================================================================== */
11863 typedef union sh_dir_uc_err_hdr_upper_u {
11864 mmr_t sh_dir_uc_err_hdr_upper_regval;
11866 mmr_t reserved_0 : 3;
11868 mmr_t reserved_1 : 16;
11870 mmr_t reserved_2 : 35;
11871 } sh_dir_uc_err_hdr_upper_s;
11872 } sh_dir_uc_err_hdr_upper_u_t;
11874 /* ==================================================================== */
11875 /* Register "SH_DIR_COR_ERR_HDR_LOWER" */
11876 /* Header capture register */
11877 /* ==================================================================== */
11879 typedef union sh_dir_cor_err_hdr_lower_u {
11880 mmr_t sh_dir_cor_err_hdr_lower_regval;
11882 mmr_t reserved_0 : 3;
11886 mmr_t reserved_1 : 2;
11888 mmr_t reserved_2 : 2;
11890 } sh_dir_cor_err_hdr_lower_s;
11891 } sh_dir_cor_err_hdr_lower_u_t;
11893 /* ==================================================================== */
11894 /* Register "SH_DIR_COR_ERR_HDR_UPPER" */
11895 /* Error header capture packet and protocol errors */
11896 /* ==================================================================== */
11898 typedef union sh_dir_cor_err_hdr_upper_u {
11899 mmr_t sh_dir_cor_err_hdr_upper_regval;
11901 mmr_t reserved_0 : 8;
11903 mmr_t reserved_1 : 11;
11905 mmr_t reserved_2 : 35;
11906 } sh_dir_cor_err_hdr_upper_s;
11907 } sh_dir_cor_err_hdr_upper_u_t;
11909 /* ==================================================================== */
11910 /* Register "SH_MEM_ERROR_SUMMARY" */
11911 /* Memory error flags */
11912 /* ==================================================================== */
11914 typedef union sh_mem_error_summary_u {
11915 mmr_t sh_mem_error_summary_regval;
11917 mmr_t illegal_cmd : 1;
11918 mmr_t nonexist_addr : 1;
11919 mmr_t dqlp_dir_perr : 1;
11920 mmr_t dqrp_dir_perr : 1;
11921 mmr_t dqlp_dir_uc : 1;
11922 mmr_t dqlp_dir_cor : 1;
11923 mmr_t dqrp_dir_uc : 1;
11924 mmr_t dqrp_dir_cor : 1;
11925 mmr_t acx_int_hw : 1;
11926 mmr_t acy_int_hw : 1;
11928 mmr_t reserved_0 : 1;
11929 mmr_t dqlp_int_uc : 1;
11930 mmr_t dqlp_int_cor : 1;
11931 mmr_t dqlp_int_hw : 1;
11932 mmr_t reserved_1 : 1;
11933 mmr_t dqls_int_uc : 1;
11934 mmr_t dqls_int_cor : 1;
11935 mmr_t dqls_int_hw : 1;
11936 mmr_t reserved_2 : 1;
11937 mmr_t dqrp_int_uc : 1;
11938 mmr_t dqrp_int_cor : 1;
11939 mmr_t dqrp_int_hw : 1;
11940 mmr_t reserved_3 : 1;
11941 mmr_t dqrs_int_uc : 1;
11942 mmr_t dqrs_int_cor : 1;
11943 mmr_t dqrs_int_hw : 1;
11944 mmr_t reserved_4 : 1;
11945 mmr_t pi_reply_overflow : 1;
11946 mmr_t xn_reply_overflow : 1;
11947 mmr_t pi_request_overflow : 1;
11948 mmr_t xn_request_overflow : 1;
11949 mmr_t red_black_err_timeout : 1;
11950 mmr_t pi_pkt_size : 1;
11951 mmr_t xn_pkt_size : 1;
11952 mmr_t reserved_5 : 29;
11953 } sh_mem_error_summary_s;
11954 } sh_mem_error_summary_u_t;
11956 /* ==================================================================== */
11957 /* Register "SH_MEM_ERROR_OVERFLOW" */
11958 /* Memory error flags */
11959 /* ==================================================================== */
11961 typedef union sh_mem_error_overflow_u {
11962 mmr_t sh_mem_error_overflow_regval;
11964 mmr_t illegal_cmd : 1;
11965 mmr_t nonexist_addr : 1;
11966 mmr_t dqlp_dir_perr : 1;
11967 mmr_t dqrp_dir_perr : 1;
11968 mmr_t dqlp_dir_uc : 1;
11969 mmr_t dqlp_dir_cor : 1;
11970 mmr_t dqrp_dir_uc : 1;
11971 mmr_t dqrp_dir_cor : 1;
11972 mmr_t acx_int_hw : 1;
11973 mmr_t acy_int_hw : 1;
11975 mmr_t reserved_0 : 1;
11976 mmr_t dqlp_int_uc : 1;
11977 mmr_t dqlp_int_cor : 1;
11978 mmr_t dqlp_int_hw : 1;
11979 mmr_t reserved_1 : 1;
11980 mmr_t dqls_int_uc : 1;
11981 mmr_t dqls_int_cor : 1;
11982 mmr_t dqls_int_hw : 1;
11983 mmr_t reserved_2 : 1;
11984 mmr_t dqrp_int_uc : 1;
11985 mmr_t dqrp_int_cor : 1;
11986 mmr_t dqrp_int_hw : 1;
11987 mmr_t reserved_3 : 1;
11988 mmr_t dqrs_int_uc : 1;
11989 mmr_t dqrs_int_cor : 1;
11990 mmr_t dqrs_int_hw : 1;
11991 mmr_t reserved_4 : 1;
11992 mmr_t pi_reply_overflow : 1;
11993 mmr_t xn_reply_overflow : 1;
11994 mmr_t pi_request_overflow : 1;
11995 mmr_t xn_request_overflow : 1;
11996 mmr_t red_black_err_timeout : 1;
11997 mmr_t pi_pkt_size : 1;
11998 mmr_t xn_pkt_size : 1;
11999 mmr_t reserved_5 : 29;
12000 } sh_mem_error_overflow_s;
12001 } sh_mem_error_overflow_u_t;
12003 /* ==================================================================== */
12004 /* Register "SH_MEM_ERROR_MASK" */
12005 /* Memory error flags */
12006 /* ==================================================================== */
12008 typedef union sh_mem_error_mask_u {
12009 mmr_t sh_mem_error_mask_regval;
12011 mmr_t illegal_cmd : 1;
12012 mmr_t nonexist_addr : 1;
12013 mmr_t dqlp_dir_perr : 1;
12014 mmr_t dqrp_dir_perr : 1;
12015 mmr_t dqlp_dir_uc : 1;
12016 mmr_t dqlp_dir_cor : 1;
12017 mmr_t dqrp_dir_uc : 1;
12018 mmr_t dqrp_dir_cor : 1;
12019 mmr_t acx_int_hw : 1;
12020 mmr_t acy_int_hw : 1;
12022 mmr_t reserved_0 : 1;
12023 mmr_t dqlp_int_uc : 1;
12024 mmr_t dqlp_int_cor : 1;
12025 mmr_t dqlp_int_hw : 1;
12026 mmr_t reserved_1 : 1;
12027 mmr_t dqls_int_uc : 1;
12028 mmr_t dqls_int_cor : 1;
12029 mmr_t dqls_int_hw : 1;
12030 mmr_t reserved_2 : 1;
12031 mmr_t dqrp_int_uc : 1;
12032 mmr_t dqrp_int_cor : 1;
12033 mmr_t dqrp_int_hw : 1;
12034 mmr_t reserved_3 : 1;
12035 mmr_t dqrs_int_uc : 1;
12036 mmr_t dqrs_int_cor : 1;
12037 mmr_t dqrs_int_hw : 1;
12038 mmr_t reserved_4 : 1;
12039 mmr_t pi_reply_overflow : 1;
12040 mmr_t xn_reply_overflow : 1;
12041 mmr_t pi_request_overflow : 1;
12042 mmr_t xn_request_overflow : 1;
12043 mmr_t red_black_err_timeout : 1;
12044 mmr_t pi_pkt_size : 1;
12045 mmr_t xn_pkt_size : 1;
12046 mmr_t reserved_5 : 29;
12047 } sh_mem_error_mask_s;
12048 } sh_mem_error_mask_u_t;
12050 /* ==================================================================== */
12051 /* Register "SH_X_DIMM_CFG" */
12052 /* AC Mem Config Registers */
12053 /* ==================================================================== */
12055 typedef union sh_x_dimm_cfg_u {
12056 mmr_t sh_x_dimm_cfg_regval;
12058 mmr_t dimm0_size : 3;
12059 mmr_t dimm0_2bk : 1;
12060 mmr_t dimm0_rev : 1;
12061 mmr_t dimm0_cs : 2;
12062 mmr_t reserved_0 : 1;
12063 mmr_t dimm1_size : 3;
12064 mmr_t dimm1_2bk : 1;
12065 mmr_t dimm1_rev : 1;
12066 mmr_t dimm1_cs : 2;
12067 mmr_t reserved_1 : 1;
12068 mmr_t dimm2_size : 3;
12069 mmr_t dimm2_2bk : 1;
12070 mmr_t dimm2_rev : 1;
12071 mmr_t dimm2_cs : 2;
12072 mmr_t reserved_2 : 1;
12073 mmr_t dimm3_size : 3;
12074 mmr_t dimm3_2bk : 1;
12075 mmr_t dimm3_rev : 1;
12076 mmr_t dimm3_cs : 2;
12077 mmr_t reserved_3 : 1;
12079 mmr_t reserved_4 : 28;
12081 } sh_x_dimm_cfg_u_t;
12083 /* ==================================================================== */
12084 /* Register "SH_Y_DIMM_CFG" */
12085 /* AC Mem Config Registers */
12086 /* ==================================================================== */
12088 typedef union sh_y_dimm_cfg_u {
12089 mmr_t sh_y_dimm_cfg_regval;
12091 mmr_t dimm0_size : 3;
12092 mmr_t dimm0_2bk : 1;
12093 mmr_t dimm0_rev : 1;
12094 mmr_t dimm0_cs : 2;
12095 mmr_t reserved_0 : 1;
12096 mmr_t dimm1_size : 3;
12097 mmr_t dimm1_2bk : 1;
12098 mmr_t dimm1_rev : 1;
12099 mmr_t dimm1_cs : 2;
12100 mmr_t reserved_1 : 1;
12101 mmr_t dimm2_size : 3;
12102 mmr_t dimm2_2bk : 1;
12103 mmr_t dimm2_rev : 1;
12104 mmr_t dimm2_cs : 2;
12105 mmr_t reserved_2 : 1;
12106 mmr_t dimm3_size : 3;
12107 mmr_t dimm3_2bk : 1;
12108 mmr_t dimm3_rev : 1;
12109 mmr_t dimm3_cs : 2;
12110 mmr_t reserved_3 : 1;
12112 mmr_t reserved_4 : 28;
12114 } sh_y_dimm_cfg_u_t;
12116 /* ==================================================================== */
12117 /* Register "SH_JNR_DIMM_CFG" */
12118 /* AC Mem Config Registers */
12119 /* ==================================================================== */
12121 typedef union sh_jnr_dimm_cfg_u {
12122 mmr_t sh_jnr_dimm_cfg_regval;
12124 mmr_t dimm0_size : 3;
12125 mmr_t dimm0_2bk : 1;
12126 mmr_t dimm0_rev : 1;
12127 mmr_t dimm0_cs : 2;
12128 mmr_t reserved_0 : 1;
12129 mmr_t dimm1_size : 3;
12130 mmr_t dimm1_2bk : 1;
12131 mmr_t dimm1_rev : 1;
12132 mmr_t dimm1_cs : 2;
12133 mmr_t reserved_1 : 1;
12134 mmr_t dimm2_size : 3;
12135 mmr_t dimm2_2bk : 1;
12136 mmr_t dimm2_rev : 1;
12137 mmr_t dimm2_cs : 2;
12138 mmr_t reserved_2 : 1;
12139 mmr_t dimm3_size : 3;
12140 mmr_t dimm3_2bk : 1;
12141 mmr_t dimm3_rev : 1;
12142 mmr_t dimm3_cs : 2;
12143 mmr_t reserved_3 : 1;
12145 mmr_t reserved_4 : 28;
12146 } sh_jnr_dimm_cfg_s;
12147 } sh_jnr_dimm_cfg_u_t;
12149 /* ==================================================================== */
12150 /* Register "SH_X_PHASE_CFG" */
12151 /* AC Phase Config Registers */
12152 /* ==================================================================== */
12154 typedef union sh_x_phase_cfg_u {
12155 mmr_t sh_x_phase_cfg_regval;
12162 mmr_t hold_req : 5;
12164 mmr_t bubble_en : 5;
12165 mmr_t pha_bubble : 3;
12166 mmr_t phb_bubble : 3;
12167 mmr_t phc_bubble : 3;
12168 mmr_t phd_bubble : 3;
12169 mmr_t phe_bubble : 3;
12171 mmr_t dq_sel_a : 4;
12172 mmr_t reserved_0 : 1;
12173 } sh_x_phase_cfg_s;
12174 } sh_x_phase_cfg_u_t;
12176 /* ==================================================================== */
12177 /* Register "SH_X_CFG" */
12178 /* AC Config Registers */
12179 /* ==================================================================== */
12181 typedef union sh_x_cfg_u {
12182 mmr_t sh_x_cfg_regval;
12184 mmr_t mode_serial : 1;
12185 mmr_t dirc_random_replacement : 1;
12186 mmr_t dir_counter_init : 6;
12187 mmr_t ta_dlys : 32;
12188 mmr_t da_bb_clr : 4;
12189 mmr_t dc_bb_clr : 4;
12190 mmr_t wt_bb_clr : 4;
12191 mmr_t sso_wt_en : 1;
12192 mmr_t trcd2_en : 1;
12193 mmr_t trcd4_en : 1;
12194 mmr_t req_cntr_dis : 1;
12195 mmr_t req_cntr_val : 6;
12196 mmr_t inv_cas_addr : 1;
12197 mmr_t clr_dir_cache : 1;
12201 /* ==================================================================== */
12202 /* Register "SH_X_DQCT_CFG" */
12203 /* AC Config Registers */
12204 /* ==================================================================== */
12206 typedef union sh_x_dqct_cfg_u {
12207 mmr_t sh_x_dqct_cfg_regval;
12211 mmr_t dta_rd_sel : 4;
12212 mmr_t dta_wt_sel : 4;
12213 mmr_t dir_rd_sel : 4;
12214 mmr_t mdir_rd_sel : 4;
12215 mmr_t reserved_0 : 40;
12217 } sh_x_dqct_cfg_u_t;
12219 /* ==================================================================== */
12220 /* Register "SH_X_REFRESH_CONTROL" */
12221 /* Refresh Control Register */
12222 /* ==================================================================== */
12224 typedef union sh_x_refresh_control_u {
12225 mmr_t sh_x_refresh_control_regval;
12228 mmr_t interval : 9;
12230 mmr_t interleave : 1;
12231 mmr_t half_rate : 4;
12232 mmr_t reserved_0 : 36;
12233 } sh_x_refresh_control_s;
12234 } sh_x_refresh_control_u_t;
12236 /* ==================================================================== */
12237 /* Register "SH_Y_PHASE_CFG" */
12238 /* AC Phase Config Registers */
12239 /* ==================================================================== */
12241 typedef union sh_y_phase_cfg_u {
12242 mmr_t sh_y_phase_cfg_regval;
12249 mmr_t hold_req : 5;
12251 mmr_t bubble_en : 5;
12252 mmr_t pha_bubble : 3;
12253 mmr_t phb_bubble : 3;
12254 mmr_t phc_bubble : 3;
12255 mmr_t phd_bubble : 3;
12256 mmr_t phe_bubble : 3;
12258 mmr_t dq_sel_a : 4;
12259 mmr_t reserved_0 : 1;
12260 } sh_y_phase_cfg_s;
12261 } sh_y_phase_cfg_u_t;
12263 /* ==================================================================== */
12264 /* Register "SH_Y_CFG" */
12265 /* AC Config Registers */
12266 /* ==================================================================== */
12268 typedef union sh_y_cfg_u {
12269 mmr_t sh_y_cfg_regval;
12271 mmr_t mode_serial : 1;
12272 mmr_t dirc_random_replacement : 1;
12273 mmr_t dir_counter_init : 6;
12274 mmr_t ta_dlys : 32;
12275 mmr_t da_bb_clr : 4;
12276 mmr_t dc_bb_clr : 4;
12277 mmr_t wt_bb_clr : 4;
12278 mmr_t sso_wt_en : 1;
12279 mmr_t trcd2_en : 1;
12280 mmr_t trcd4_en : 1;
12281 mmr_t req_cntr_dis : 1;
12282 mmr_t req_cntr_val : 6;
12283 mmr_t inv_cas_addr : 1;
12284 mmr_t clr_dir_cache : 1;
12288 /* ==================================================================== */
12289 /* Register "SH_Y_DQCT_CFG" */
12290 /* AC Config Registers */
12291 /* ==================================================================== */
12293 typedef union sh_y_dqct_cfg_u {
12294 mmr_t sh_y_dqct_cfg_regval;
12298 mmr_t dta_rd_sel : 4;
12299 mmr_t dta_wt_sel : 4;
12300 mmr_t dir_rd_sel : 4;
12301 mmr_t mdir_rd_sel : 4;
12302 mmr_t reserved_0 : 40;
12304 } sh_y_dqct_cfg_u_t;
12306 /* ==================================================================== */
12307 /* Register "SH_Y_REFRESH_CONTROL" */
12308 /* Refresh Control Register */
12309 /* ==================================================================== */
12311 typedef union sh_y_refresh_control_u {
12312 mmr_t sh_y_refresh_control_regval;
12315 mmr_t interval : 9;
12317 mmr_t interleave : 1;
12318 mmr_t half_rate : 4;
12319 mmr_t reserved_0 : 36;
12320 } sh_y_refresh_control_s;
12321 } sh_y_refresh_control_u_t;
12323 /* ==================================================================== */
12324 /* Register "SH_MEM_RED_BLACK" */
12325 /* MD fairness watchdog timers */
12326 /* ==================================================================== */
12328 typedef union sh_mem_red_black_u {
12329 mmr_t sh_mem_red_black_regval;
12332 mmr_t err_time : 36;
12333 mmr_t reserved_0 : 12;
12334 } sh_mem_red_black_s;
12335 } sh_mem_red_black_u_t;
12337 /* ==================================================================== */
12338 /* Register "SH_MISC_MEM_CFG" */
12339 /* ==================================================================== */
12341 typedef union sh_misc_mem_cfg_u {
12342 mmr_t sh_misc_mem_cfg_regval;
12344 mmr_t express_header_enable : 1;
12345 mmr_t spec_header_enable : 1;
12346 mmr_t jnr_bypass_enable : 1;
12347 mmr_t xn_rd_same_as_pi : 1;
12348 mmr_t low_write_buffer_threshold : 6;
12349 mmr_t reserved_0 : 2;
12350 mmr_t low_victim_buffer_threshold : 6;
12351 mmr_t reserved_1 : 2;
12352 mmr_t throttle_cnt : 8;
12353 mmr_t disabled_read_tnums : 5;
12354 mmr_t reserved_2 : 3;
12355 mmr_t disabled_write_tnums : 5;
12356 mmr_t reserved_3 : 3;
12357 mmr_t disabled_victims : 6;
12358 mmr_t reserved_4 : 2;
12359 mmr_t alternate_xn_rp_plane : 1;
12360 mmr_t reserved_5 : 11;
12361 } sh_misc_mem_cfg_s;
12362 } sh_misc_mem_cfg_u_t;
12364 /* ==================================================================== */
12365 /* Register "SH_PIO_RQ_CRD_CTL" */
12366 /* pio_rq Credit Circulation Control */
12367 /* ==================================================================== */
12369 typedef union sh_pio_rq_crd_ctl_u {
12370 mmr_t sh_pio_rq_crd_ctl_regval;
12373 mmr_t reserved_0 : 58;
12374 } sh_pio_rq_crd_ctl_s;
12375 } sh_pio_rq_crd_ctl_u_t;
12377 /* ==================================================================== */
12378 /* Register "SH_PI_MD_RQ_CRD_CTL" */
12379 /* pi_md_rq Credit Circulation Control */
12380 /* ==================================================================== */
12382 typedef union sh_pi_md_rq_crd_ctl_u {
12383 mmr_t sh_pi_md_rq_crd_ctl_regval;
12386 mmr_t reserved_0 : 58;
12387 } sh_pi_md_rq_crd_ctl_s;
12388 } sh_pi_md_rq_crd_ctl_u_t;
12390 /* ==================================================================== */
12391 /* Register "SH_PI_MD_RP_CRD_CTL" */
12392 /* pi_md_rp Credit Circulation Control */
12393 /* ==================================================================== */
12395 typedef union sh_pi_md_rp_crd_ctl_u {
12396 mmr_t sh_pi_md_rp_crd_ctl_regval;
12399 mmr_t reserved_0 : 58;
12400 } sh_pi_md_rp_crd_ctl_s;
12401 } sh_pi_md_rp_crd_ctl_u_t;
12403 /* ==================================================================== */
12404 /* Register "SH_XN_MD_RQ_CRD_CTL" */
12405 /* xn_md_rq Credit Circulation Control */
12406 /* ==================================================================== */
12408 typedef union sh_xn_md_rq_crd_ctl_u {
12409 mmr_t sh_xn_md_rq_crd_ctl_regval;
12412 mmr_t reserved_0 : 58;
12413 } sh_xn_md_rq_crd_ctl_s;
12414 } sh_xn_md_rq_crd_ctl_u_t;
12416 /* ==================================================================== */
12417 /* Register "SH_XN_MD_RP_CRD_CTL" */
12418 /* xn_md_rp Credit Circulation Control */
12419 /* ==================================================================== */
12421 typedef union sh_xn_md_rp_crd_ctl_u {
12422 mmr_t sh_xn_md_rp_crd_ctl_regval;
12425 mmr_t reserved_0 : 58;
12426 } sh_xn_md_rp_crd_ctl_s;
12427 } sh_xn_md_rp_crd_ctl_u_t;
12429 /* ==================================================================== */
12430 /* Register "SH_X_TAG0" */
12431 /* AC tag Registers */
12432 /* ==================================================================== */
12434 typedef union sh_x_tag0_u {
12435 mmr_t sh_x_tag0_regval;
12438 mmr_t reserved_0 : 44;
12442 /* ==================================================================== */
12443 /* Register "SH_X_TAG1" */
12444 /* AC tag Registers */
12445 /* ==================================================================== */
12447 typedef union sh_x_tag1_u {
12448 mmr_t sh_x_tag1_regval;
12451 mmr_t reserved_0 : 44;
12455 /* ==================================================================== */
12456 /* Register "SH_X_TAG2" */
12457 /* AC tag Registers */
12458 /* ==================================================================== */
12460 typedef union sh_x_tag2_u {
12461 mmr_t sh_x_tag2_regval;
12464 mmr_t reserved_0 : 44;
12468 /* ==================================================================== */
12469 /* Register "SH_X_TAG3" */
12470 /* AC tag Registers */
12471 /* ==================================================================== */
12473 typedef union sh_x_tag3_u {
12474 mmr_t sh_x_tag3_regval;
12477 mmr_t reserved_0 : 44;
12481 /* ==================================================================== */
12482 /* Register "SH_X_TAG4" */
12483 /* AC tag Registers */
12484 /* ==================================================================== */
12486 typedef union sh_x_tag4_u {
12487 mmr_t sh_x_tag4_regval;
12490 mmr_t reserved_0 : 44;
12494 /* ==================================================================== */
12495 /* Register "SH_X_TAG5" */
12496 /* AC tag Registers */
12497 /* ==================================================================== */
12499 typedef union sh_x_tag5_u {
12500 mmr_t sh_x_tag5_regval;
12503 mmr_t reserved_0 : 44;
12507 /* ==================================================================== */
12508 /* Register "SH_X_TAG6" */
12509 /* AC tag Registers */
12510 /* ==================================================================== */
12512 typedef union sh_x_tag6_u {
12513 mmr_t sh_x_tag6_regval;
12516 mmr_t reserved_0 : 44;
12520 /* ==================================================================== */
12521 /* Register "SH_X_TAG7" */
12522 /* AC tag Registers */
12523 /* ==================================================================== */
12525 typedef union sh_x_tag7_u {
12526 mmr_t sh_x_tag7_regval;
12529 mmr_t reserved_0 : 44;
12533 /* ==================================================================== */
12534 /* Register "SH_Y_TAG0" */
12535 /* AC tag Registers */
12536 /* ==================================================================== */
12538 typedef union sh_y_tag0_u {
12539 mmr_t sh_y_tag0_regval;
12542 mmr_t reserved_0 : 44;
12546 /* ==================================================================== */
12547 /* Register "SH_Y_TAG1" */
12548 /* AC tag Registers */
12549 /* ==================================================================== */
12551 typedef union sh_y_tag1_u {
12552 mmr_t sh_y_tag1_regval;
12555 mmr_t reserved_0 : 44;
12559 /* ==================================================================== */
12560 /* Register "SH_Y_TAG2" */
12561 /* AC tag Registers */
12562 /* ==================================================================== */
12564 typedef union sh_y_tag2_u {
12565 mmr_t sh_y_tag2_regval;
12568 mmr_t reserved_0 : 44;
12572 /* ==================================================================== */
12573 /* Register "SH_Y_TAG3" */
12574 /* AC tag Registers */
12575 /* ==================================================================== */
12577 typedef union sh_y_tag3_u {
12578 mmr_t sh_y_tag3_regval;
12581 mmr_t reserved_0 : 44;
12585 /* ==================================================================== */
12586 /* Register "SH_Y_TAG4" */
12587 /* AC tag Registers */
12588 /* ==================================================================== */
12590 typedef union sh_y_tag4_u {
12591 mmr_t sh_y_tag4_regval;
12594 mmr_t reserved_0 : 44;
12598 /* ==================================================================== */
12599 /* Register "SH_Y_TAG5" */
12600 /* AC tag Registers */
12601 /* ==================================================================== */
12603 typedef union sh_y_tag5_u {
12604 mmr_t sh_y_tag5_regval;
12607 mmr_t reserved_0 : 44;
12611 /* ==================================================================== */
12612 /* Register "SH_Y_TAG6" */
12613 /* AC tag Registers */
12614 /* ==================================================================== */
12616 typedef union sh_y_tag6_u {
12617 mmr_t sh_y_tag6_regval;
12620 mmr_t reserved_0 : 44;
12624 /* ==================================================================== */
12625 /* Register "SH_Y_TAG7" */
12626 /* AC tag Registers */
12627 /* ==================================================================== */
12629 typedef union sh_y_tag7_u {
12630 mmr_t sh_y_tag7_regval;
12633 mmr_t reserved_0 : 44;
12637 /* ==================================================================== */
12638 /* Register "SH_MMRBIST_BASE" */
12639 /* mmr/bist base address */
12640 /* ==================================================================== */
12642 typedef union sh_mmrbist_base_u {
12643 mmr_t sh_mmrbist_base_regval;
12645 mmr_t reserved_0 : 3;
12646 mmr_t dword_addr : 47;
12647 mmr_t reserved_1 : 14;
12648 } sh_mmrbist_base_s;
12649 } sh_mmrbist_base_u_t;
12651 /* ==================================================================== */
12652 /* Register "SH_MMRBIST_CTL" */
12653 /* Bist base address */
12654 /* ==================================================================== */
12656 typedef union sh_mmrbist_ctl_u {
12657 mmr_t sh_mmrbist_ctl_regval;
12659 mmr_t block_length : 31;
12660 mmr_t reserved_0 : 1;
12662 mmr_t reserved_1 : 1;
12663 mmr_t in_progress : 1;
12665 mmr_t mem_idle : 1;
12666 mmr_t reserved_2 : 1;
12667 mmr_t reset_state : 1;
12668 mmr_t reserved_3 : 19;
12669 } sh_mmrbist_ctl_s;
12670 } sh_mmrbist_ctl_u_t;
12672 /* ==================================================================== */
12673 /* Register "SH_MD_DBUG_DATA_CFG" */
12674 /* configuration for md debug data muxes */
12675 /* ==================================================================== */
12677 typedef union sh_md_dbug_data_cfg_u {
12678 mmr_t sh_md_dbug_data_cfg_regval;
12680 mmr_t nibble0_chiplet : 3;
12681 mmr_t reserved_0 : 1;
12682 mmr_t nibble0_nibble : 3;
12683 mmr_t reserved_1 : 1;
12684 mmr_t nibble1_chiplet : 3;
12685 mmr_t reserved_2 : 1;
12686 mmr_t nibble1_nibble : 3;
12687 mmr_t reserved_3 : 1;
12688 mmr_t nibble2_chiplet : 3;
12689 mmr_t reserved_4 : 1;
12690 mmr_t nibble2_nibble : 3;
12691 mmr_t reserved_5 : 1;
12692 mmr_t nibble3_chiplet : 3;
12693 mmr_t reserved_6 : 1;
12694 mmr_t nibble3_nibble : 3;
12695 mmr_t reserved_7 : 1;
12696 mmr_t nibble4_chiplet : 3;
12697 mmr_t reserved_8 : 1;
12698 mmr_t nibble4_nibble : 3;
12699 mmr_t reserved_9 : 1;
12700 mmr_t nibble5_chiplet : 3;
12701 mmr_t reserved_10 : 1;
12702 mmr_t nibble5_nibble : 3;
12703 mmr_t reserved_11 : 1;
12704 mmr_t nibble6_chiplet : 3;
12705 mmr_t reserved_12 : 1;
12706 mmr_t nibble6_nibble : 3;
12707 mmr_t reserved_13 : 1;
12708 mmr_t nibble7_chiplet : 3;
12709 mmr_t reserved_14 : 1;
12710 mmr_t nibble7_nibble : 3;
12711 mmr_t reserved_15 : 1;
12712 } sh_md_dbug_data_cfg_s;
12713 } sh_md_dbug_data_cfg_u_t;
12715 /* ==================================================================== */
12716 /* Register "SH_MD_DBUG_TRIGGER_CFG" */
12717 /* configuration for md debug triggers */
12718 /* ==================================================================== */
12720 typedef union sh_md_dbug_trigger_cfg_u {
12721 mmr_t sh_md_dbug_trigger_cfg_regval;
12723 mmr_t nibble0_chiplet : 3;
12724 mmr_t reserved_0 : 1;
12725 mmr_t nibble0_nibble : 3;
12726 mmr_t reserved_1 : 1;
12727 mmr_t nibble1_chiplet : 3;
12728 mmr_t reserved_2 : 1;
12729 mmr_t nibble1_nibble : 3;
12730 mmr_t reserved_3 : 1;
12731 mmr_t nibble2_chiplet : 3;
12732 mmr_t reserved_4 : 1;
12733 mmr_t nibble2_nibble : 3;
12734 mmr_t reserved_5 : 1;
12735 mmr_t nibble3_chiplet : 3;
12736 mmr_t reserved_6 : 1;
12737 mmr_t nibble3_nibble : 3;
12738 mmr_t reserved_7 : 1;
12739 mmr_t nibble4_chiplet : 3;
12740 mmr_t reserved_8 : 1;
12741 mmr_t nibble4_nibble : 3;
12742 mmr_t reserved_9 : 1;
12743 mmr_t nibble5_chiplet : 3;
12744 mmr_t reserved_10 : 1;
12745 mmr_t nibble5_nibble : 3;
12746 mmr_t reserved_11 : 1;
12747 mmr_t nibble6_chiplet : 3;
12748 mmr_t reserved_12 : 1;
12749 mmr_t nibble6_nibble : 3;
12750 mmr_t reserved_13 : 1;
12751 mmr_t nibble7_chiplet : 3;
12752 mmr_t reserved_14 : 1;
12753 mmr_t nibble7_nibble : 3;
12755 } sh_md_dbug_trigger_cfg_s;
12756 } sh_md_dbug_trigger_cfg_u_t;
12758 /* ==================================================================== */
12759 /* Register "SH_MD_DBUG_COMPARE" */
12760 /* md debug compare pattern and mask */
12761 /* ==================================================================== */
12763 typedef union sh_md_dbug_compare_u {
12764 mmr_t sh_md_dbug_compare_regval;
12766 mmr_t pattern : 32;
12768 } sh_md_dbug_compare_s;
12769 } sh_md_dbug_compare_u_t;
12771 /* ==================================================================== */
12772 /* Register "SH_X_MOD_DBUG_SEL" */
12773 /* MD acx debug select */
12774 /* ==================================================================== */
12776 typedef union sh_x_mod_dbug_sel_u {
12777 mmr_t sh_x_mod_dbug_sel_regval;
12782 mmr_t atl_sel : 11;
12783 mmr_t atr_sel : 11;
12786 mmr_t reserved_0 : 6;
12787 } sh_x_mod_dbug_sel_s;
12788 } sh_x_mod_dbug_sel_u_t;
12790 /* ==================================================================== */
12791 /* Register "SH_X_DBUG_SEL" */
12792 /* MD acx debug select */
12793 /* ==================================================================== */
12795 typedef union sh_x_dbug_sel_u {
12796 mmr_t sh_x_dbug_sel_regval;
12798 mmr_t dbg_sel : 24;
12799 mmr_t reserved_0 : 40;
12801 } sh_x_dbug_sel_u_t;
12803 /* ==================================================================== */
12804 /* Register "SH_X_LADDR_CMP" */
12805 /* MD acx address compare */
12806 /* ==================================================================== */
12808 typedef union sh_x_laddr_cmp_u {
12809 mmr_t sh_x_laddr_cmp_regval;
12811 mmr_t cmp_val : 28;
12812 mmr_t reserved_0 : 4;
12813 mmr_t mask_val : 28;
12814 mmr_t reserved_1 : 4;
12815 } sh_x_laddr_cmp_s;
12816 } sh_x_laddr_cmp_u_t;
12818 /* ==================================================================== */
12819 /* Register "SH_X_RADDR_CMP" */
12820 /* MD acx address compare */
12821 /* ==================================================================== */
12823 typedef union sh_x_raddr_cmp_u {
12824 mmr_t sh_x_raddr_cmp_regval;
12826 mmr_t cmp_val : 28;
12827 mmr_t reserved_0 : 4;
12828 mmr_t mask_val : 28;
12829 mmr_t reserved_1 : 4;
12830 } sh_x_raddr_cmp_s;
12831 } sh_x_raddr_cmp_u_t;
12833 /* ==================================================================== */
12834 /* Register "SH_X_TAG_CMP" */
12835 /* MD acx tagmgr compare */
12836 /* ==================================================================== */
12838 typedef union sh_x_tag_cmp_u {
12839 mmr_t sh_x_tag_cmp_regval;
12844 mmr_t reserved_0 : 9;
12846 } sh_x_tag_cmp_u_t;
12848 /* ==================================================================== */
12849 /* Register "SH_X_TAG_MASK" */
12850 /* MD acx tagmgr mask */
12851 /* ==================================================================== */
12853 typedef union sh_x_tag_mask_u {
12854 mmr_t sh_x_tag_mask_regval;
12859 mmr_t reserved_0 : 9;
12861 } sh_x_tag_mask_u_t;
12863 /* ==================================================================== */
12864 /* Register "SH_Y_MOD_DBUG_SEL" */
12865 /* MD acy debug select */
12866 /* ==================================================================== */
12868 typedef union sh_y_mod_dbug_sel_u {
12869 mmr_t sh_y_mod_dbug_sel_regval;
12874 mmr_t atl_sel : 11;
12875 mmr_t atr_sel : 11;
12878 mmr_t reserved_0 : 6;
12879 } sh_y_mod_dbug_sel_s;
12880 } sh_y_mod_dbug_sel_u_t;
12882 /* ==================================================================== */
12883 /* Register "SH_Y_DBUG_SEL" */
12884 /* MD acy debug select */
12885 /* ==================================================================== */
12887 typedef union sh_y_dbug_sel_u {
12888 mmr_t sh_y_dbug_sel_regval;
12890 mmr_t dbg_sel : 24;
12891 mmr_t reserved_0 : 40;
12893 } sh_y_dbug_sel_u_t;
12895 /* ==================================================================== */
12896 /* Register "SH_Y_LADDR_CMP" */
12897 /* MD acy address compare */
12898 /* ==================================================================== */
12900 typedef union sh_y_laddr_cmp_u {
12901 mmr_t sh_y_laddr_cmp_regval;
12903 mmr_t cmp_val : 28;
12904 mmr_t reserved_0 : 4;
12905 mmr_t mask_val : 28;
12906 mmr_t reserved_1 : 4;
12907 } sh_y_laddr_cmp_s;
12908 } sh_y_laddr_cmp_u_t;
12910 /* ==================================================================== */
12911 /* Register "SH_Y_RADDR_CMP" */
12912 /* MD acy address compare */
12913 /* ==================================================================== */
12915 typedef union sh_y_raddr_cmp_u {
12916 mmr_t sh_y_raddr_cmp_regval;
12918 mmr_t cmp_val : 28;
12919 mmr_t reserved_0 : 4;
12920 mmr_t mask_val : 28;
12921 mmr_t reserved_1 : 4;
12922 } sh_y_raddr_cmp_s;
12923 } sh_y_raddr_cmp_u_t;
12925 /* ==================================================================== */
12926 /* Register "SH_Y_TAG_CMP" */
12927 /* MD acy tagmgr compare */
12928 /* ==================================================================== */
12930 typedef union sh_y_tag_cmp_u {
12931 mmr_t sh_y_tag_cmp_regval;
12936 mmr_t reserved_0 : 9;
12938 } sh_y_tag_cmp_u_t;
12940 /* ==================================================================== */
12941 /* Register "SH_Y_TAG_MASK" */
12942 /* MD acy tagmgr mask */
12943 /* ==================================================================== */
12945 typedef union sh_y_tag_mask_u {
12946 mmr_t sh_y_tag_mask_regval;
12951 mmr_t reserved_0 : 9;
12953 } sh_y_tag_mask_u_t;
12955 /* ==================================================================== */
12956 /* Register "SH_MD_JNR_DBUG_DATA_CFG" */
12957 /* configuration for md jnr debug data muxes */
12958 /* ==================================================================== */
12960 typedef union sh_md_jnr_dbug_data_cfg_u {
12961 mmr_t sh_md_jnr_dbug_data_cfg_regval;
12963 mmr_t nibble0_sel : 3;
12964 mmr_t reserved_0 : 1;
12965 mmr_t nibble1_sel : 3;
12966 mmr_t reserved_1 : 1;
12967 mmr_t nibble2_sel : 3;
12968 mmr_t reserved_2 : 1;
12969 mmr_t nibble3_sel : 3;
12970 mmr_t reserved_3 : 1;
12971 mmr_t nibble4_sel : 3;
12972 mmr_t reserved_4 : 1;
12973 mmr_t nibble5_sel : 3;
12974 mmr_t reserved_5 : 1;
12975 mmr_t nibble6_sel : 3;
12976 mmr_t reserved_6 : 1;
12977 mmr_t nibble7_sel : 3;
12978 mmr_t reserved_7 : 33;
12979 } sh_md_jnr_dbug_data_cfg_s;
12980 } sh_md_jnr_dbug_data_cfg_u_t;
12982 /* ==================================================================== */
12983 /* Register "SH_MD_LAST_CREDIT" */
12984 /* captures last credit values on reset */
12985 /* ==================================================================== */
12987 typedef union sh_md_last_credit_u {
12988 mmr_t sh_md_last_credit_regval;
12990 mmr_t rq_to_pi : 6;
12991 mmr_t reserved_0 : 2;
12992 mmr_t rp_to_pi : 6;
12993 mmr_t reserved_1 : 2;
12994 mmr_t rq_to_xn : 6;
12995 mmr_t reserved_2 : 2;
12996 mmr_t rp_to_xn : 6;
12997 mmr_t reserved_3 : 2;
12999 mmr_t reserved_4 : 26;
13000 } sh_md_last_credit_s;
13001 } sh_md_last_credit_u_t;
13003 /* ==================================================================== */
13004 /* Register "SH_MEM_CAPTURE_ADDR" */
13005 /* Address capture address register */
13006 /* ==================================================================== */
13008 typedef union sh_mem_capture_addr_u {
13009 mmr_t sh_mem_capture_addr_regval;
13011 mmr_t reserved_0 : 3;
13014 mmr_t reserved_1 : 20;
13015 } sh_mem_capture_addr_s;
13016 } sh_mem_capture_addr_u_t;
13018 /* ==================================================================== */
13019 /* Register "SH_MEM_CAPTURE_MASK" */
13020 /* Address capture mask register */
13021 /* ==================================================================== */
13023 typedef union sh_mem_capture_mask_u {
13024 mmr_t sh_mem_capture_mask_regval;
13026 mmr_t reserved_0 : 3;
13029 mmr_t enable_local : 1;
13030 mmr_t enable_remote : 1;
13031 mmr_t reserved_1 : 18;
13032 } sh_mem_capture_mask_s;
13033 } sh_mem_capture_mask_u_t;
13035 /* ==================================================================== */
13036 /* Register "SH_MEM_CAPTURE_HDR" */
13037 /* Address capture header register */
13038 /* ==================================================================== */
13040 typedef union sh_mem_capture_hdr_u {
13041 mmr_t sh_mem_capture_hdr_regval;
13043 mmr_t reserved_0 : 3;
13048 } sh_mem_capture_hdr_s;
13049 } sh_mem_capture_hdr_u_t;
13051 /* ==================================================================== */
13052 /* Register "SH_MD_DQLP_MMR_DIR_CONFIG" */
13053 /* DQ directory config register */
13054 /* ==================================================================== */
13056 typedef union sh_md_dqlp_mmr_dir_config_u {
13057 mmr_t sh_md_dqlp_mmr_dir_config_regval;
13059 mmr_t sys_size : 3;
13060 mmr_t en_direcc : 1;
13061 mmr_t en_dirpois : 1;
13062 mmr_t reserved_0 : 59;
13063 } sh_md_dqlp_mmr_dir_config_s;
13064 } sh_md_dqlp_mmr_dir_config_u_t;
13066 /* ==================================================================== */
13067 /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC0" */
13068 /* node [63:0] presence bits */
13069 /* ==================================================================== */
13071 typedef union sh_md_dqlp_mmr_dir_presvec0_u {
13072 mmr_t sh_md_dqlp_mmr_dir_presvec0_regval;
13075 } sh_md_dqlp_mmr_dir_presvec0_s;
13076 } sh_md_dqlp_mmr_dir_presvec0_u_t;
13078 /* ==================================================================== */
13079 /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC1" */
13080 /* node [127:64] presence bits */
13081 /* ==================================================================== */
13083 typedef union sh_md_dqlp_mmr_dir_presvec1_u {
13084 mmr_t sh_md_dqlp_mmr_dir_presvec1_regval;
13087 } sh_md_dqlp_mmr_dir_presvec1_s;
13088 } sh_md_dqlp_mmr_dir_presvec1_u_t;
13090 /* ==================================================================== */
13091 /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC2" */
13092 /* node [191:128] presence bits */
13093 /* ==================================================================== */
13095 typedef union sh_md_dqlp_mmr_dir_presvec2_u {
13096 mmr_t sh_md_dqlp_mmr_dir_presvec2_regval;
13099 } sh_md_dqlp_mmr_dir_presvec2_s;
13100 } sh_md_dqlp_mmr_dir_presvec2_u_t;
13102 /* ==================================================================== */
13103 /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC3" */
13104 /* node [255:192] presence bits */
13105 /* ==================================================================== */
13107 typedef union sh_md_dqlp_mmr_dir_presvec3_u {
13108 mmr_t sh_md_dqlp_mmr_dir_presvec3_regval;
13111 } sh_md_dqlp_mmr_dir_presvec3_s;
13112 } sh_md_dqlp_mmr_dir_presvec3_u_t;
13114 /* ==================================================================== */
13115 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC0" */
13116 /* local vector for acc=0 */
13117 /* ==================================================================== */
13119 typedef union sh_md_dqlp_mmr_dir_locvec0_u {
13120 mmr_t sh_md_dqlp_mmr_dir_locvec0_regval;
13123 } sh_md_dqlp_mmr_dir_locvec0_s;
13124 } sh_md_dqlp_mmr_dir_locvec0_u_t;
13126 /* ==================================================================== */
13127 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC1" */
13128 /* local vector for acc=1 */
13129 /* ==================================================================== */
13131 typedef union sh_md_dqlp_mmr_dir_locvec1_u {
13132 mmr_t sh_md_dqlp_mmr_dir_locvec1_regval;
13135 } sh_md_dqlp_mmr_dir_locvec1_s;
13136 } sh_md_dqlp_mmr_dir_locvec1_u_t;
13138 /* ==================================================================== */
13139 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC2" */
13140 /* local vector for acc=2 */
13141 /* ==================================================================== */
13143 typedef union sh_md_dqlp_mmr_dir_locvec2_u {
13144 mmr_t sh_md_dqlp_mmr_dir_locvec2_regval;
13147 } sh_md_dqlp_mmr_dir_locvec2_s;
13148 } sh_md_dqlp_mmr_dir_locvec2_u_t;
13150 /* ==================================================================== */
13151 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC3" */
13152 /* local vector for acc=3 */
13153 /* ==================================================================== */
13155 typedef union sh_md_dqlp_mmr_dir_locvec3_u {
13156 mmr_t sh_md_dqlp_mmr_dir_locvec3_regval;
13159 } sh_md_dqlp_mmr_dir_locvec3_s;
13160 } sh_md_dqlp_mmr_dir_locvec3_u_t;
13162 /* ==================================================================== */
13163 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC4" */
13164 /* local vector for acc=4 */
13165 /* ==================================================================== */
13167 typedef union sh_md_dqlp_mmr_dir_locvec4_u {
13168 mmr_t sh_md_dqlp_mmr_dir_locvec4_regval;
13171 } sh_md_dqlp_mmr_dir_locvec4_s;
13172 } sh_md_dqlp_mmr_dir_locvec4_u_t;
13174 /* ==================================================================== */
13175 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC5" */
13176 /* local vector for acc=5 */
13177 /* ==================================================================== */
13179 typedef union sh_md_dqlp_mmr_dir_locvec5_u {
13180 mmr_t sh_md_dqlp_mmr_dir_locvec5_regval;
13183 } sh_md_dqlp_mmr_dir_locvec5_s;
13184 } sh_md_dqlp_mmr_dir_locvec5_u_t;
13186 /* ==================================================================== */
13187 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC6" */
13188 /* local vector for acc=6 */
13189 /* ==================================================================== */
13191 typedef union sh_md_dqlp_mmr_dir_locvec6_u {
13192 mmr_t sh_md_dqlp_mmr_dir_locvec6_regval;
13195 } sh_md_dqlp_mmr_dir_locvec6_s;
13196 } sh_md_dqlp_mmr_dir_locvec6_u_t;
13198 /* ==================================================================== */
13199 /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC7" */
13200 /* local vector for acc=7 */
13201 /* ==================================================================== */
13203 typedef union sh_md_dqlp_mmr_dir_locvec7_u {
13204 mmr_t sh_md_dqlp_mmr_dir_locvec7_regval;
13207 } sh_md_dqlp_mmr_dir_locvec7_s;
13208 } sh_md_dqlp_mmr_dir_locvec7_u_t;
13210 /* ==================================================================== */
13211 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
13212 /* privilege vector for acc=0 */
13213 /* ==================================================================== */
13215 typedef union sh_md_dqlp_mmr_dir_privec0_u {
13216 mmr_t sh_md_dqlp_mmr_dir_privec0_regval;
13220 mmr_t reserved_0 : 36;
13221 } sh_md_dqlp_mmr_dir_privec0_s;
13222 } sh_md_dqlp_mmr_dir_privec0_u_t;
13224 /* ==================================================================== */
13225 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC1" */
13226 /* privilege vector for acc=1 */
13227 /* ==================================================================== */
13229 typedef union sh_md_dqlp_mmr_dir_privec1_u {
13230 mmr_t sh_md_dqlp_mmr_dir_privec1_regval;
13234 mmr_t reserved_0 : 36;
13235 } sh_md_dqlp_mmr_dir_privec1_s;
13236 } sh_md_dqlp_mmr_dir_privec1_u_t;
13238 /* ==================================================================== */
13239 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC2" */
13240 /* privilege vector for acc=2 */
13241 /* ==================================================================== */
13243 typedef union sh_md_dqlp_mmr_dir_privec2_u {
13244 mmr_t sh_md_dqlp_mmr_dir_privec2_regval;
13248 mmr_t reserved_0 : 36;
13249 } sh_md_dqlp_mmr_dir_privec2_s;
13250 } sh_md_dqlp_mmr_dir_privec2_u_t;
13252 /* ==================================================================== */
13253 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC3" */
13254 /* privilege vector for acc=3 */
13255 /* ==================================================================== */
13257 typedef union sh_md_dqlp_mmr_dir_privec3_u {
13258 mmr_t sh_md_dqlp_mmr_dir_privec3_regval;
13262 mmr_t reserved_0 : 36;
13263 } sh_md_dqlp_mmr_dir_privec3_s;
13264 } sh_md_dqlp_mmr_dir_privec3_u_t;
13266 /* ==================================================================== */
13267 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC4" */
13268 /* privilege vector for acc=4 */
13269 /* ==================================================================== */
13271 typedef union sh_md_dqlp_mmr_dir_privec4_u {
13272 mmr_t sh_md_dqlp_mmr_dir_privec4_regval;
13276 mmr_t reserved_0 : 36;
13277 } sh_md_dqlp_mmr_dir_privec4_s;
13278 } sh_md_dqlp_mmr_dir_privec4_u_t;
13280 /* ==================================================================== */
13281 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC5" */
13282 /* privilege vector for acc=5 */
13283 /* ==================================================================== */
13285 typedef union sh_md_dqlp_mmr_dir_privec5_u {
13286 mmr_t sh_md_dqlp_mmr_dir_privec5_regval;
13290 mmr_t reserved_0 : 36;
13291 } sh_md_dqlp_mmr_dir_privec5_s;
13292 } sh_md_dqlp_mmr_dir_privec5_u_t;
13294 /* ==================================================================== */
13295 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC6" */
13296 /* privilege vector for acc=6 */
13297 /* ==================================================================== */
13299 typedef union sh_md_dqlp_mmr_dir_privec6_u {
13300 mmr_t sh_md_dqlp_mmr_dir_privec6_regval;
13304 mmr_t reserved_0 : 36;
13305 } sh_md_dqlp_mmr_dir_privec6_s;
13306 } sh_md_dqlp_mmr_dir_privec6_u_t;
13308 /* ==================================================================== */
13309 /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC7" */
13310 /* privilege vector for acc=7 */
13311 /* ==================================================================== */
13313 typedef union sh_md_dqlp_mmr_dir_privec7_u {
13314 mmr_t sh_md_dqlp_mmr_dir_privec7_regval;
13318 mmr_t reserved_0 : 36;
13319 } sh_md_dqlp_mmr_dir_privec7_s;
13320 } sh_md_dqlp_mmr_dir_privec7_u_t;
13322 /* ==================================================================== */
13323 /* Register "SH_MD_DQLP_MMR_DIR_TIMER" */
13324 /* MD SXRO timer */
13325 /* ==================================================================== */
13327 typedef union sh_md_dqlp_mmr_dir_timer_u {
13328 mmr_t sh_md_dqlp_mmr_dir_timer_regval;
13330 mmr_t timer_div : 12;
13331 mmr_t timer_en : 1;
13332 mmr_t timer_cur : 9;
13333 mmr_t reserved_0 : 42;
13334 } sh_md_dqlp_mmr_dir_timer_s;
13335 } sh_md_dqlp_mmr_dir_timer_u_t;
13337 /* ==================================================================== */
13338 /* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY" */
13339 /* directory pio write data */
13340 /* ==================================================================== */
13342 typedef union sh_md_dqlp_mmr_piowd_dir_entry_u {
13343 mmr_t sh_md_dqlp_mmr_piowd_dir_entry_regval;
13349 mmr_t reserved_0 : 6;
13350 } sh_md_dqlp_mmr_piowd_dir_entry_s;
13351 } sh_md_dqlp_mmr_piowd_dir_entry_u_t;
13353 /* ==================================================================== */
13354 /* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC" */
13355 /* directory ecc register */
13356 /* ==================================================================== */
13358 typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u {
13359 mmr_t sh_md_dqlp_mmr_piowd_dir_ecc_regval;
13363 mmr_t reserved_0 : 50;
13364 } sh_md_dqlp_mmr_piowd_dir_ecc_s;
13365 } sh_md_dqlp_mmr_piowd_dir_ecc_u_t;
13367 /* ==================================================================== */
13368 /* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY" */
13369 /* x directory pio read data */
13370 /* ==================================================================== */
13372 typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u {
13373 mmr_t sh_md_dqlp_mmr_xpiord_xdir_entry_regval;
13381 mmr_t reserved_0 : 4;
13382 } sh_md_dqlp_mmr_xpiord_xdir_entry_s;
13383 } sh_md_dqlp_mmr_xpiord_xdir_entry_u_t;
13385 /* ==================================================================== */
13386 /* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC" */
13387 /* x directory ecc */
13388 /* ==================================================================== */
13390 typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u {
13391 mmr_t sh_md_dqlp_mmr_xpiord_xdir_ecc_regval;
13395 mmr_t reserved_0 : 50;
13396 } sh_md_dqlp_mmr_xpiord_xdir_ecc_s;
13397 } sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t;
13399 /* ==================================================================== */
13400 /* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY" */
13401 /* y directory pio read data */
13402 /* ==================================================================== */
13404 typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u {
13405 mmr_t sh_md_dqlp_mmr_ypiord_ydir_entry_regval;
13413 mmr_t reserved_0 : 4;
13414 } sh_md_dqlp_mmr_ypiord_ydir_entry_s;
13415 } sh_md_dqlp_mmr_ypiord_ydir_entry_u_t;
13417 /* ==================================================================== */
13418 /* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC" */
13419 /* y directory ecc */
13420 /* ==================================================================== */
13422 typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u {
13423 mmr_t sh_md_dqlp_mmr_ypiord_ydir_ecc_regval;
13427 mmr_t reserved_0 : 50;
13428 } sh_md_dqlp_mmr_ypiord_ydir_ecc_s;
13429 } sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t;
13431 /* ==================================================================== */
13432 /* Register "SH_MD_DQLP_MMR_XCERR1" */
13433 /* correctable dir ecc group 1 error register */
13434 /* ==================================================================== */
13436 typedef union sh_md_dqlp_mmr_xcerr1_u {
13437 mmr_t sh_md_dqlp_mmr_xcerr1_regval;
13443 mmr_t reserved_0 : 25;
13444 } sh_md_dqlp_mmr_xcerr1_s;
13445 } sh_md_dqlp_mmr_xcerr1_u_t;
13447 /* ==================================================================== */
13448 /* Register "SH_MD_DQLP_MMR_XCERR2" */
13449 /* correctable dir ecc group 2 error register */
13450 /* ==================================================================== */
13452 typedef union sh_md_dqlp_mmr_xcerr2_u {
13453 mmr_t sh_md_dqlp_mmr_xcerr2_regval;
13458 mmr_t reserved_0 : 26;
13459 } sh_md_dqlp_mmr_xcerr2_s;
13460 } sh_md_dqlp_mmr_xcerr2_u_t;
13462 /* ==================================================================== */
13463 /* Register "SH_MD_DQLP_MMR_XUERR1" */
13464 /* uncorrectable dir ecc group 1 error register */
13465 /* ==================================================================== */
13467 typedef union sh_md_dqlp_mmr_xuerr1_u {
13468 mmr_t sh_md_dqlp_mmr_xuerr1_regval;
13474 mmr_t reserved_0 : 25;
13475 } sh_md_dqlp_mmr_xuerr1_s;
13476 } sh_md_dqlp_mmr_xuerr1_u_t;
13478 /* ==================================================================== */
13479 /* Register "SH_MD_DQLP_MMR_XUERR2" */
13480 /* uncorrectable dir ecc group 2 error register */
13481 /* ==================================================================== */
13483 typedef union sh_md_dqlp_mmr_xuerr2_u {
13484 mmr_t sh_md_dqlp_mmr_xuerr2_regval;
13489 mmr_t reserved_0 : 26;
13490 } sh_md_dqlp_mmr_xuerr2_s;
13491 } sh_md_dqlp_mmr_xuerr2_u_t;
13493 /* ==================================================================== */
13494 /* Register "SH_MD_DQLP_MMR_XPERR" */
13495 /* protocol error register */
13496 /* ==================================================================== */
13498 typedef union sh_md_dqlp_mmr_xperr_u {
13499 mmr_t sh_md_dqlp_mmr_xperr_regval;
13512 mmr_t reserved_0 : 1;
13513 } sh_md_dqlp_mmr_xperr_s;
13514 } sh_md_dqlp_mmr_xperr_u_t;
13516 /* ==================================================================== */
13517 /* Register "SH_MD_DQLP_MMR_YCERR1" */
13518 /* correctable dir ecc group 1 error register */
13519 /* ==================================================================== */
13521 typedef union sh_md_dqlp_mmr_ycerr1_u {
13522 mmr_t sh_md_dqlp_mmr_ycerr1_regval;
13528 mmr_t reserved_0 : 25;
13529 } sh_md_dqlp_mmr_ycerr1_s;
13530 } sh_md_dqlp_mmr_ycerr1_u_t;
13532 /* ==================================================================== */
13533 /* Register "SH_MD_DQLP_MMR_YCERR2" */
13534 /* correctable dir ecc group 2 error register */
13535 /* ==================================================================== */
13537 typedef union sh_md_dqlp_mmr_ycerr2_u {
13538 mmr_t sh_md_dqlp_mmr_ycerr2_regval;
13543 mmr_t reserved_0 : 26;
13544 } sh_md_dqlp_mmr_ycerr2_s;
13545 } sh_md_dqlp_mmr_ycerr2_u_t;
13547 /* ==================================================================== */
13548 /* Register "SH_MD_DQLP_MMR_YUERR1" */
13549 /* uncorrectable dir ecc group 1 error register */
13550 /* ==================================================================== */
13552 typedef union sh_md_dqlp_mmr_yuerr1_u {
13553 mmr_t sh_md_dqlp_mmr_yuerr1_regval;
13559 mmr_t reserved_0 : 25;
13560 } sh_md_dqlp_mmr_yuerr1_s;
13561 } sh_md_dqlp_mmr_yuerr1_u_t;
13563 /* ==================================================================== */
13564 /* Register "SH_MD_DQLP_MMR_YUERR2" */
13565 /* uncorrectable dir ecc group 2 error register */
13566 /* ==================================================================== */
13568 typedef union sh_md_dqlp_mmr_yuerr2_u {
13569 mmr_t sh_md_dqlp_mmr_yuerr2_regval;
13574 mmr_t reserved_0 : 26;
13575 } sh_md_dqlp_mmr_yuerr2_s;
13576 } sh_md_dqlp_mmr_yuerr2_u_t;
13578 /* ==================================================================== */
13579 /* Register "SH_MD_DQLP_MMR_YPERR" */
13580 /* protocol error register */
13581 /* ==================================================================== */
13583 typedef union sh_md_dqlp_mmr_yperr_u {
13584 mmr_t sh_md_dqlp_mmr_yperr_regval;
13597 mmr_t reserved_0 : 1;
13598 } sh_md_dqlp_mmr_yperr_s;
13599 } sh_md_dqlp_mmr_yperr_u_t;
13601 /* ==================================================================== */
13602 /* Register "SH_MD_DQLP_MMR_DIR_CMDTRIG" */
13604 /* ==================================================================== */
13606 typedef union sh_md_dqlp_mmr_dir_cmdtrig_u {
13607 mmr_t sh_md_dqlp_mmr_dir_cmdtrig_regval;
13613 mmr_t reserved_0 : 32;
13614 } sh_md_dqlp_mmr_dir_cmdtrig_s;
13615 } sh_md_dqlp_mmr_dir_cmdtrig_u_t;
13617 /* ==================================================================== */
13618 /* Register "SH_MD_DQLP_MMR_DIR_TBLTRIG" */
13619 /* dir table trigger */
13620 /* ==================================================================== */
13622 typedef union sh_md_dqlp_mmr_dir_tbltrig_u {
13623 mmr_t sh_md_dqlp_mmr_dir_tbltrig_regval;
13631 mmr_t reserved_0 : 22;
13632 } sh_md_dqlp_mmr_dir_tbltrig_s;
13633 } sh_md_dqlp_mmr_dir_tbltrig_u_t;
13635 /* ==================================================================== */
13636 /* Register "SH_MD_DQLP_MMR_DIR_TBLMASK" */
13637 /* dir table trigger mask */
13638 /* ==================================================================== */
13640 typedef union sh_md_dqlp_mmr_dir_tblmask_u {
13641 mmr_t sh_md_dqlp_mmr_dir_tblmask_regval;
13649 mmr_t reserved_0 : 22;
13650 } sh_md_dqlp_mmr_dir_tblmask_s;
13651 } sh_md_dqlp_mmr_dir_tblmask_u_t;
13653 /* ==================================================================== */
13654 /* Register "SH_MD_DQLP_MMR_XBIST_H" */
13655 /* rising edge bist/fill pattern */
13656 /* ==================================================================== */
13658 typedef union sh_md_dqlp_mmr_xbist_h_u {
13659 mmr_t sh_md_dqlp_mmr_xbist_h_regval;
13662 mmr_t reserved_0 : 8;
13666 mmr_t reserved_1 : 21;
13667 } sh_md_dqlp_mmr_xbist_h_s;
13668 } sh_md_dqlp_mmr_xbist_h_u_t;
13670 /* ==================================================================== */
13671 /* Register "SH_MD_DQLP_MMR_XBIST_L" */
13672 /* falling edge bist/fill pattern */
13673 /* ==================================================================== */
13675 typedef union sh_md_dqlp_mmr_xbist_l_u {
13676 mmr_t sh_md_dqlp_mmr_xbist_l_regval;
13679 mmr_t reserved_0 : 8;
13682 mmr_t reserved_1 : 22;
13683 } sh_md_dqlp_mmr_xbist_l_s;
13684 } sh_md_dqlp_mmr_xbist_l_u_t;
13686 /* ==================================================================== */
13687 /* Register "SH_MD_DQLP_MMR_XBIST_ERR_H" */
13688 /* rising edge bist error pattern */
13689 /* ==================================================================== */
13691 typedef union sh_md_dqlp_mmr_xbist_err_h_u {
13692 mmr_t sh_md_dqlp_mmr_xbist_err_h_regval;
13695 mmr_t reserved_0 : 8;
13698 mmr_t reserved_1 : 22;
13699 } sh_md_dqlp_mmr_xbist_err_h_s;
13700 } sh_md_dqlp_mmr_xbist_err_h_u_t;
13702 /* ==================================================================== */
13703 /* Register "SH_MD_DQLP_MMR_XBIST_ERR_L" */
13704 /* falling edge bist error pattern */
13705 /* ==================================================================== */
13707 typedef union sh_md_dqlp_mmr_xbist_err_l_u {
13708 mmr_t sh_md_dqlp_mmr_xbist_err_l_regval;
13711 mmr_t reserved_0 : 8;
13714 mmr_t reserved_1 : 22;
13715 } sh_md_dqlp_mmr_xbist_err_l_s;
13716 } sh_md_dqlp_mmr_xbist_err_l_u_t;
13718 /* ==================================================================== */
13719 /* Register "SH_MD_DQLP_MMR_YBIST_H" */
13720 /* rising edge bist/fill pattern */
13721 /* ==================================================================== */
13723 typedef union sh_md_dqlp_mmr_ybist_h_u {
13724 mmr_t sh_md_dqlp_mmr_ybist_h_regval;
13727 mmr_t reserved_0 : 8;
13731 mmr_t reserved_1 : 21;
13732 } sh_md_dqlp_mmr_ybist_h_s;
13733 } sh_md_dqlp_mmr_ybist_h_u_t;
13735 /* ==================================================================== */
13736 /* Register "SH_MD_DQLP_MMR_YBIST_L" */
13737 /* falling edge bist/fill pattern */
13738 /* ==================================================================== */
13740 typedef union sh_md_dqlp_mmr_ybist_l_u {
13741 mmr_t sh_md_dqlp_mmr_ybist_l_regval;
13744 mmr_t reserved_0 : 8;
13747 mmr_t reserved_1 : 22;
13748 } sh_md_dqlp_mmr_ybist_l_s;
13749 } sh_md_dqlp_mmr_ybist_l_u_t;
13751 /* ==================================================================== */
13752 /* Register "SH_MD_DQLP_MMR_YBIST_ERR_H" */
13753 /* rising edge bist error pattern */
13754 /* ==================================================================== */
13756 typedef union sh_md_dqlp_mmr_ybist_err_h_u {
13757 mmr_t sh_md_dqlp_mmr_ybist_err_h_regval;
13760 mmr_t reserved_0 : 8;
13763 mmr_t reserved_1 : 22;
13764 } sh_md_dqlp_mmr_ybist_err_h_s;
13765 } sh_md_dqlp_mmr_ybist_err_h_u_t;
13767 /* ==================================================================== */
13768 /* Register "SH_MD_DQLP_MMR_YBIST_ERR_L" */
13769 /* falling edge bist error pattern */
13770 /* ==================================================================== */
13772 typedef union sh_md_dqlp_mmr_ybist_err_l_u {
13773 mmr_t sh_md_dqlp_mmr_ybist_err_l_regval;
13776 mmr_t reserved_0 : 8;
13779 mmr_t reserved_1 : 22;
13780 } sh_md_dqlp_mmr_ybist_err_l_s;
13781 } sh_md_dqlp_mmr_ybist_err_l_u_t;
13783 /* ==================================================================== */
13784 /* Register "SH_MD_DQLS_MMR_XBIST_H" */
13785 /* rising edge bist/fill pattern */
13786 /* ==================================================================== */
13788 typedef union sh_md_dqls_mmr_xbist_h_u {
13789 mmr_t sh_md_dqls_mmr_xbist_h_regval;
13795 mmr_t reserved_0 : 21;
13796 } sh_md_dqls_mmr_xbist_h_s;
13797 } sh_md_dqls_mmr_xbist_h_u_t;
13799 /* ==================================================================== */
13800 /* Register "SH_MD_DQLS_MMR_XBIST_L" */
13801 /* falling edge bist/fill pattern */
13802 /* ==================================================================== */
13804 typedef union sh_md_dqls_mmr_xbist_l_u {
13805 mmr_t sh_md_dqls_mmr_xbist_l_regval;
13810 mmr_t reserved_0 : 22;
13811 } sh_md_dqls_mmr_xbist_l_s;
13812 } sh_md_dqls_mmr_xbist_l_u_t;
13814 /* ==================================================================== */
13815 /* Register "SH_MD_DQLS_MMR_XBIST_ERR_H" */
13816 /* rising edge bist error pattern */
13817 /* ==================================================================== */
13819 typedef union sh_md_dqls_mmr_xbist_err_h_u {
13820 mmr_t sh_md_dqls_mmr_xbist_err_h_regval;
13825 mmr_t reserved_0 : 22;
13826 } sh_md_dqls_mmr_xbist_err_h_s;
13827 } sh_md_dqls_mmr_xbist_err_h_u_t;
13829 /* ==================================================================== */
13830 /* Register "SH_MD_DQLS_MMR_XBIST_ERR_L" */
13831 /* falling edge bist error pattern */
13832 /* ==================================================================== */
13834 typedef union sh_md_dqls_mmr_xbist_err_l_u {
13835 mmr_t sh_md_dqls_mmr_xbist_err_l_regval;
13840 mmr_t reserved_0 : 22;
13841 } sh_md_dqls_mmr_xbist_err_l_s;
13842 } sh_md_dqls_mmr_xbist_err_l_u_t;
13844 /* ==================================================================== */
13845 /* Register "SH_MD_DQLS_MMR_YBIST_H" */
13846 /* rising edge bist/fill pattern */
13847 /* ==================================================================== */
13849 typedef union sh_md_dqls_mmr_ybist_h_u {
13850 mmr_t sh_md_dqls_mmr_ybist_h_regval;
13856 mmr_t reserved_0 : 21;
13857 } sh_md_dqls_mmr_ybist_h_s;
13858 } sh_md_dqls_mmr_ybist_h_u_t;
13860 /* ==================================================================== */
13861 /* Register "SH_MD_DQLS_MMR_YBIST_L" */
13862 /* falling edge bist/fill pattern */
13863 /* ==================================================================== */
13865 typedef union sh_md_dqls_mmr_ybist_l_u {
13866 mmr_t sh_md_dqls_mmr_ybist_l_regval;
13871 mmr_t reserved_0 : 22;
13872 } sh_md_dqls_mmr_ybist_l_s;
13873 } sh_md_dqls_mmr_ybist_l_u_t;
13875 /* ==================================================================== */
13876 /* Register "SH_MD_DQLS_MMR_YBIST_ERR_H" */
13877 /* rising edge bist error pattern */
13878 /* ==================================================================== */
13880 typedef union sh_md_dqls_mmr_ybist_err_h_u {
13881 mmr_t sh_md_dqls_mmr_ybist_err_h_regval;
13886 mmr_t reserved_0 : 22;
13887 } sh_md_dqls_mmr_ybist_err_h_s;
13888 } sh_md_dqls_mmr_ybist_err_h_u_t;
13890 /* ==================================================================== */
13891 /* Register "SH_MD_DQLS_MMR_YBIST_ERR_L" */
13892 /* falling edge bist error pattern */
13893 /* ==================================================================== */
13895 typedef union sh_md_dqls_mmr_ybist_err_l_u {
13896 mmr_t sh_md_dqls_mmr_ybist_err_l_regval;
13901 mmr_t reserved_0 : 22;
13902 } sh_md_dqls_mmr_ybist_err_l_s;
13903 } sh_md_dqls_mmr_ybist_err_l_u_t;
13905 /* ==================================================================== */
13906 /* Register "SH_MD_DQLS_MMR_JNR_DEBUG" */
13907 /* joiner/fct debug configuration */
13908 /* ==================================================================== */
13910 typedef union sh_md_dqls_mmr_jnr_debug_u {
13911 mmr_t sh_md_dqls_mmr_jnr_debug_regval;
13915 mmr_t reserved_0 : 62;
13916 } sh_md_dqls_mmr_jnr_debug_s;
13917 } sh_md_dqls_mmr_jnr_debug_u_t;
13919 /* ==================================================================== */
13920 /* Register "SH_MD_DQLS_MMR_XAMOPW_ERR" */
13921 /* amo/partial rmw ecc error register */
13922 /* ==================================================================== */
13924 typedef union sh_md_dqls_mmr_xamopw_err_u {
13925 mmr_t sh_md_dqls_mmr_xamopw_err_regval;
13930 mmr_t reserved_0 : 6;
13934 mmr_t reserved_1 : 6;
13936 mmr_t reserved_2 : 31;
13937 } sh_md_dqls_mmr_xamopw_err_s;
13938 } sh_md_dqls_mmr_xamopw_err_u_t;
13940 /* ==================================================================== */
13941 /* Register "SH_MD_DQRP_MMR_DIR_CONFIG" */
13942 /* DQ directory config register */
13943 /* ==================================================================== */
13945 typedef union sh_md_dqrp_mmr_dir_config_u {
13946 mmr_t sh_md_dqrp_mmr_dir_config_regval;
13948 mmr_t sys_size : 3;
13949 mmr_t en_direcc : 1;
13950 mmr_t en_dirpois : 1;
13951 mmr_t reserved_0 : 59;
13952 } sh_md_dqrp_mmr_dir_config_s;
13953 } sh_md_dqrp_mmr_dir_config_u_t;
13955 /* ==================================================================== */
13956 /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC0" */
13957 /* node [63:0] presence bits */
13958 /* ==================================================================== */
13960 typedef union sh_md_dqrp_mmr_dir_presvec0_u {
13961 mmr_t sh_md_dqrp_mmr_dir_presvec0_regval;
13964 } sh_md_dqrp_mmr_dir_presvec0_s;
13965 } sh_md_dqrp_mmr_dir_presvec0_u_t;
13967 /* ==================================================================== */
13968 /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC1" */
13969 /* node [127:64] presence bits */
13970 /* ==================================================================== */
13972 typedef union sh_md_dqrp_mmr_dir_presvec1_u {
13973 mmr_t sh_md_dqrp_mmr_dir_presvec1_regval;
13976 } sh_md_dqrp_mmr_dir_presvec1_s;
13977 } sh_md_dqrp_mmr_dir_presvec1_u_t;
13979 /* ==================================================================== */
13980 /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC2" */
13981 /* node [191:128] presence bits */
13982 /* ==================================================================== */
13984 typedef union sh_md_dqrp_mmr_dir_presvec2_u {
13985 mmr_t sh_md_dqrp_mmr_dir_presvec2_regval;
13988 } sh_md_dqrp_mmr_dir_presvec2_s;
13989 } sh_md_dqrp_mmr_dir_presvec2_u_t;
13991 /* ==================================================================== */
13992 /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC3" */
13993 /* node [255:192] presence bits */
13994 /* ==================================================================== */
13996 typedef union sh_md_dqrp_mmr_dir_presvec3_u {
13997 mmr_t sh_md_dqrp_mmr_dir_presvec3_regval;
14000 } sh_md_dqrp_mmr_dir_presvec3_s;
14001 } sh_md_dqrp_mmr_dir_presvec3_u_t;
14003 /* ==================================================================== */
14004 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC0" */
14005 /* local vector for acc=0 */
14006 /* ==================================================================== */
14008 typedef union sh_md_dqrp_mmr_dir_locvec0_u {
14009 mmr_t sh_md_dqrp_mmr_dir_locvec0_regval;
14012 } sh_md_dqrp_mmr_dir_locvec0_s;
14013 } sh_md_dqrp_mmr_dir_locvec0_u_t;
14015 /* ==================================================================== */
14016 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC1" */
14017 /* local vector for acc=1 */
14018 /* ==================================================================== */
14020 typedef union sh_md_dqrp_mmr_dir_locvec1_u {
14021 mmr_t sh_md_dqrp_mmr_dir_locvec1_regval;
14024 } sh_md_dqrp_mmr_dir_locvec1_s;
14025 } sh_md_dqrp_mmr_dir_locvec1_u_t;
14027 /* ==================================================================== */
14028 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC2" */
14029 /* local vector for acc=2 */
14030 /* ==================================================================== */
14032 typedef union sh_md_dqrp_mmr_dir_locvec2_u {
14033 mmr_t sh_md_dqrp_mmr_dir_locvec2_regval;
14036 } sh_md_dqrp_mmr_dir_locvec2_s;
14037 } sh_md_dqrp_mmr_dir_locvec2_u_t;
14039 /* ==================================================================== */
14040 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC3" */
14041 /* local vector for acc=3 */
14042 /* ==================================================================== */
14044 typedef union sh_md_dqrp_mmr_dir_locvec3_u {
14045 mmr_t sh_md_dqrp_mmr_dir_locvec3_regval;
14048 } sh_md_dqrp_mmr_dir_locvec3_s;
14049 } sh_md_dqrp_mmr_dir_locvec3_u_t;
14051 /* ==================================================================== */
14052 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC4" */
14053 /* local vector for acc=4 */
14054 /* ==================================================================== */
14056 typedef union sh_md_dqrp_mmr_dir_locvec4_u {
14057 mmr_t sh_md_dqrp_mmr_dir_locvec4_regval;
14060 } sh_md_dqrp_mmr_dir_locvec4_s;
14061 } sh_md_dqrp_mmr_dir_locvec4_u_t;
14063 /* ==================================================================== */
14064 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC5" */
14065 /* local vector for acc=5 */
14066 /* ==================================================================== */
14068 typedef union sh_md_dqrp_mmr_dir_locvec5_u {
14069 mmr_t sh_md_dqrp_mmr_dir_locvec5_regval;
14072 } sh_md_dqrp_mmr_dir_locvec5_s;
14073 } sh_md_dqrp_mmr_dir_locvec5_u_t;
14075 /* ==================================================================== */
14076 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC6" */
14077 /* local vector for acc=6 */
14078 /* ==================================================================== */
14080 typedef union sh_md_dqrp_mmr_dir_locvec6_u {
14081 mmr_t sh_md_dqrp_mmr_dir_locvec6_regval;
14084 } sh_md_dqrp_mmr_dir_locvec6_s;
14085 } sh_md_dqrp_mmr_dir_locvec6_u_t;
14087 /* ==================================================================== */
14088 /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC7" */
14089 /* local vector for acc=7 */
14090 /* ==================================================================== */
14092 typedef union sh_md_dqrp_mmr_dir_locvec7_u {
14093 mmr_t sh_md_dqrp_mmr_dir_locvec7_regval;
14096 } sh_md_dqrp_mmr_dir_locvec7_s;
14097 } sh_md_dqrp_mmr_dir_locvec7_u_t;
14099 /* ==================================================================== */
14100 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
14101 /* privilege vector for acc=0 */
14102 /* ==================================================================== */
14104 typedef union sh_md_dqrp_mmr_dir_privec0_u {
14105 mmr_t sh_md_dqrp_mmr_dir_privec0_regval;
14109 mmr_t reserved_0 : 36;
14110 } sh_md_dqrp_mmr_dir_privec0_s;
14111 } sh_md_dqrp_mmr_dir_privec0_u_t;
14113 /* ==================================================================== */
14114 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC1" */
14115 /* privilege vector for acc=1 */
14116 /* ==================================================================== */
14118 typedef union sh_md_dqrp_mmr_dir_privec1_u {
14119 mmr_t sh_md_dqrp_mmr_dir_privec1_regval;
14123 mmr_t reserved_0 : 36;
14124 } sh_md_dqrp_mmr_dir_privec1_s;
14125 } sh_md_dqrp_mmr_dir_privec1_u_t;
14127 /* ==================================================================== */
14128 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC2" */
14129 /* privilege vector for acc=2 */
14130 /* ==================================================================== */
14132 typedef union sh_md_dqrp_mmr_dir_privec2_u {
14133 mmr_t sh_md_dqrp_mmr_dir_privec2_regval;
14137 mmr_t reserved_0 : 36;
14138 } sh_md_dqrp_mmr_dir_privec2_s;
14139 } sh_md_dqrp_mmr_dir_privec2_u_t;
14141 /* ==================================================================== */
14142 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC3" */
14143 /* privilege vector for acc=3 */
14144 /* ==================================================================== */
14146 typedef union sh_md_dqrp_mmr_dir_privec3_u {
14147 mmr_t sh_md_dqrp_mmr_dir_privec3_regval;
14151 mmr_t reserved_0 : 36;
14152 } sh_md_dqrp_mmr_dir_privec3_s;
14153 } sh_md_dqrp_mmr_dir_privec3_u_t;
14155 /* ==================================================================== */
14156 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC4" */
14157 /* privilege vector for acc=4 */
14158 /* ==================================================================== */
14160 typedef union sh_md_dqrp_mmr_dir_privec4_u {
14161 mmr_t sh_md_dqrp_mmr_dir_privec4_regval;
14165 mmr_t reserved_0 : 36;
14166 } sh_md_dqrp_mmr_dir_privec4_s;
14167 } sh_md_dqrp_mmr_dir_privec4_u_t;
14169 /* ==================================================================== */
14170 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC5" */
14171 /* privilege vector for acc=5 */
14172 /* ==================================================================== */
14174 typedef union sh_md_dqrp_mmr_dir_privec5_u {
14175 mmr_t sh_md_dqrp_mmr_dir_privec5_regval;
14179 mmr_t reserved_0 : 36;
14180 } sh_md_dqrp_mmr_dir_privec5_s;
14181 } sh_md_dqrp_mmr_dir_privec5_u_t;
14183 /* ==================================================================== */
14184 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC6" */
14185 /* privilege vector for acc=6 */
14186 /* ==================================================================== */
14188 typedef union sh_md_dqrp_mmr_dir_privec6_u {
14189 mmr_t sh_md_dqrp_mmr_dir_privec6_regval;
14193 mmr_t reserved_0 : 36;
14194 } sh_md_dqrp_mmr_dir_privec6_s;
14195 } sh_md_dqrp_mmr_dir_privec6_u_t;
14197 /* ==================================================================== */
14198 /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC7" */
14199 /* privilege vector for acc=7 */
14200 /* ==================================================================== */
14202 typedef union sh_md_dqrp_mmr_dir_privec7_u {
14203 mmr_t sh_md_dqrp_mmr_dir_privec7_regval;
14207 mmr_t reserved_0 : 36;
14208 } sh_md_dqrp_mmr_dir_privec7_s;
14209 } sh_md_dqrp_mmr_dir_privec7_u_t;
14211 /* ==================================================================== */
14212 /* Register "SH_MD_DQRP_MMR_DIR_TIMER" */
14213 /* MD SXRO timer */
14214 /* ==================================================================== */
14216 typedef union sh_md_dqrp_mmr_dir_timer_u {
14217 mmr_t sh_md_dqrp_mmr_dir_timer_regval;
14219 mmr_t timer_div : 12;
14220 mmr_t timer_en : 1;
14221 mmr_t timer_cur : 9;
14222 mmr_t reserved_0 : 42;
14223 } sh_md_dqrp_mmr_dir_timer_s;
14224 } sh_md_dqrp_mmr_dir_timer_u_t;
14226 /* ==================================================================== */
14227 /* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY" */
14228 /* directory pio write data */
14229 /* ==================================================================== */
14231 typedef union sh_md_dqrp_mmr_piowd_dir_entry_u {
14232 mmr_t sh_md_dqrp_mmr_piowd_dir_entry_regval;
14238 mmr_t reserved_0 : 6;
14239 } sh_md_dqrp_mmr_piowd_dir_entry_s;
14240 } sh_md_dqrp_mmr_piowd_dir_entry_u_t;
14242 /* ==================================================================== */
14243 /* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC" */
14244 /* directory ecc register */
14245 /* ==================================================================== */
14247 typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u {
14248 mmr_t sh_md_dqrp_mmr_piowd_dir_ecc_regval;
14252 mmr_t reserved_0 : 50;
14253 } sh_md_dqrp_mmr_piowd_dir_ecc_s;
14254 } sh_md_dqrp_mmr_piowd_dir_ecc_u_t;
14256 /* ==================================================================== */
14257 /* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY" */
14258 /* x directory pio read data */
14259 /* ==================================================================== */
14261 typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u {
14262 mmr_t sh_md_dqrp_mmr_xpiord_xdir_entry_regval;
14270 mmr_t reserved_0 : 4;
14271 } sh_md_dqrp_mmr_xpiord_xdir_entry_s;
14272 } sh_md_dqrp_mmr_xpiord_xdir_entry_u_t;
14274 /* ==================================================================== */
14275 /* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC" */
14276 /* x directory ecc */
14277 /* ==================================================================== */
14279 typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u {
14280 mmr_t sh_md_dqrp_mmr_xpiord_xdir_ecc_regval;
14284 mmr_t reserved_0 : 50;
14285 } sh_md_dqrp_mmr_xpiord_xdir_ecc_s;
14286 } sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t;
14288 /* ==================================================================== */
14289 /* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY" */
14290 /* y directory pio read data */
14291 /* ==================================================================== */
14293 typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u {
14294 mmr_t sh_md_dqrp_mmr_ypiord_ydir_entry_regval;
14302 mmr_t reserved_0 : 4;
14303 } sh_md_dqrp_mmr_ypiord_ydir_entry_s;
14304 } sh_md_dqrp_mmr_ypiord_ydir_entry_u_t;
14306 /* ==================================================================== */
14307 /* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC" */
14308 /* y directory ecc */
14309 /* ==================================================================== */
14311 typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u {
14312 mmr_t sh_md_dqrp_mmr_ypiord_ydir_ecc_regval;
14316 mmr_t reserved_0 : 50;
14317 } sh_md_dqrp_mmr_ypiord_ydir_ecc_s;
14318 } sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t;
14320 /* ==================================================================== */
14321 /* Register "SH_MD_DQRP_MMR_XCERR1" */
14322 /* correctable dir ecc group 1 error register */
14323 /* ==================================================================== */
14325 typedef union sh_md_dqrp_mmr_xcerr1_u {
14326 mmr_t sh_md_dqrp_mmr_xcerr1_regval;
14332 mmr_t reserved_0 : 25;
14333 } sh_md_dqrp_mmr_xcerr1_s;
14334 } sh_md_dqrp_mmr_xcerr1_u_t;
14336 /* ==================================================================== */
14337 /* Register "SH_MD_DQRP_MMR_XCERR2" */
14338 /* correctable dir ecc group 2 error register */
14339 /* ==================================================================== */
14341 typedef union sh_md_dqrp_mmr_xcerr2_u {
14342 mmr_t sh_md_dqrp_mmr_xcerr2_regval;
14347 mmr_t reserved_0 : 26;
14348 } sh_md_dqrp_mmr_xcerr2_s;
14349 } sh_md_dqrp_mmr_xcerr2_u_t;
14351 /* ==================================================================== */
14352 /* Register "SH_MD_DQRP_MMR_XUERR1" */
14353 /* uncorrectable dir ecc group 1 error register */
14354 /* ==================================================================== */
14356 typedef union sh_md_dqrp_mmr_xuerr1_u {
14357 mmr_t sh_md_dqrp_mmr_xuerr1_regval;
14363 mmr_t reserved_0 : 25;
14364 } sh_md_dqrp_mmr_xuerr1_s;
14365 } sh_md_dqrp_mmr_xuerr1_u_t;
14367 /* ==================================================================== */
14368 /* Register "SH_MD_DQRP_MMR_XUERR2" */
14369 /* uncorrectable dir ecc group 2 error register */
14370 /* ==================================================================== */
14372 typedef union sh_md_dqrp_mmr_xuerr2_u {
14373 mmr_t sh_md_dqrp_mmr_xuerr2_regval;
14378 mmr_t reserved_0 : 26;
14379 } sh_md_dqrp_mmr_xuerr2_s;
14380 } sh_md_dqrp_mmr_xuerr2_u_t;
14382 /* ==================================================================== */
14383 /* Register "SH_MD_DQRP_MMR_XPERR" */
14384 /* protocol error register */
14385 /* ==================================================================== */
14387 typedef union sh_md_dqrp_mmr_xperr_u {
14388 mmr_t sh_md_dqrp_mmr_xperr_regval;
14401 mmr_t reserved_0 : 1;
14402 } sh_md_dqrp_mmr_xperr_s;
14403 } sh_md_dqrp_mmr_xperr_u_t;
14405 /* ==================================================================== */
14406 /* Register "SH_MD_DQRP_MMR_YCERR1" */
14407 /* correctable dir ecc group 1 error register */
14408 /* ==================================================================== */
14410 typedef union sh_md_dqrp_mmr_ycerr1_u {
14411 mmr_t sh_md_dqrp_mmr_ycerr1_regval;
14417 mmr_t reserved_0 : 25;
14418 } sh_md_dqrp_mmr_ycerr1_s;
14419 } sh_md_dqrp_mmr_ycerr1_u_t;
14421 /* ==================================================================== */
14422 /* Register "SH_MD_DQRP_MMR_YCERR2" */
14423 /* correctable dir ecc group 2 error register */
14424 /* ==================================================================== */
14426 typedef union sh_md_dqrp_mmr_ycerr2_u {
14427 mmr_t sh_md_dqrp_mmr_ycerr2_regval;
14432 mmr_t reserved_0 : 26;
14433 } sh_md_dqrp_mmr_ycerr2_s;
14434 } sh_md_dqrp_mmr_ycerr2_u_t;
14436 /* ==================================================================== */
14437 /* Register "SH_MD_DQRP_MMR_YUERR1" */
14438 /* uncorrectable dir ecc group 1 error register */
14439 /* ==================================================================== */
14441 typedef union sh_md_dqrp_mmr_yuerr1_u {
14442 mmr_t sh_md_dqrp_mmr_yuerr1_regval;
14448 mmr_t reserved_0 : 25;
14449 } sh_md_dqrp_mmr_yuerr1_s;
14450 } sh_md_dqrp_mmr_yuerr1_u_t;
14452 /* ==================================================================== */
14453 /* Register "SH_MD_DQRP_MMR_YUERR2" */
14454 /* uncorrectable dir ecc group 2 error register */
14455 /* ==================================================================== */
14457 typedef union sh_md_dqrp_mmr_yuerr2_u {
14458 mmr_t sh_md_dqrp_mmr_yuerr2_regval;
14463 mmr_t reserved_0 : 26;
14464 } sh_md_dqrp_mmr_yuerr2_s;
14465 } sh_md_dqrp_mmr_yuerr2_u_t;
14467 /* ==================================================================== */
14468 /* Register "SH_MD_DQRP_MMR_YPERR" */
14469 /* protocol error register */
14470 /* ==================================================================== */
14472 typedef union sh_md_dqrp_mmr_yperr_u {
14473 mmr_t sh_md_dqrp_mmr_yperr_regval;
14486 mmr_t reserved_0 : 1;
14487 } sh_md_dqrp_mmr_yperr_s;
14488 } sh_md_dqrp_mmr_yperr_u_t;
14490 /* ==================================================================== */
14491 /* Register "SH_MD_DQRP_MMR_DIR_CMDTRIG" */
14493 /* ==================================================================== */
14495 typedef union sh_md_dqrp_mmr_dir_cmdtrig_u {
14496 mmr_t sh_md_dqrp_mmr_dir_cmdtrig_regval;
14502 mmr_t reserved_0 : 32;
14503 } sh_md_dqrp_mmr_dir_cmdtrig_s;
14504 } sh_md_dqrp_mmr_dir_cmdtrig_u_t;
14506 /* ==================================================================== */
14507 /* Register "SH_MD_DQRP_MMR_DIR_TBLTRIG" */
14508 /* dir table trigger */
14509 /* ==================================================================== */
14511 typedef union sh_md_dqrp_mmr_dir_tbltrig_u {
14512 mmr_t sh_md_dqrp_mmr_dir_tbltrig_regval;
14520 mmr_t reserved_0 : 22;
14521 } sh_md_dqrp_mmr_dir_tbltrig_s;
14522 } sh_md_dqrp_mmr_dir_tbltrig_u_t;
14524 /* ==================================================================== */
14525 /* Register "SH_MD_DQRP_MMR_DIR_TBLMASK" */
14526 /* dir table trigger mask */
14527 /* ==================================================================== */
14529 typedef union sh_md_dqrp_mmr_dir_tblmask_u {
14530 mmr_t sh_md_dqrp_mmr_dir_tblmask_regval;
14538 mmr_t reserved_0 : 22;
14539 } sh_md_dqrp_mmr_dir_tblmask_s;
14540 } sh_md_dqrp_mmr_dir_tblmask_u_t;
14542 /* ==================================================================== */
14543 /* Register "SH_MD_DQRP_MMR_XBIST_H" */
14544 /* rising edge bist/fill pattern */
14545 /* ==================================================================== */
14547 typedef union sh_md_dqrp_mmr_xbist_h_u {
14548 mmr_t sh_md_dqrp_mmr_xbist_h_regval;
14551 mmr_t reserved_0 : 8;
14555 mmr_t reserved_1 : 21;
14556 } sh_md_dqrp_mmr_xbist_h_s;
14557 } sh_md_dqrp_mmr_xbist_h_u_t;
14559 /* ==================================================================== */
14560 /* Register "SH_MD_DQRP_MMR_XBIST_L" */
14561 /* falling edge bist/fill pattern */
14562 /* ==================================================================== */
14564 typedef union sh_md_dqrp_mmr_xbist_l_u {
14565 mmr_t sh_md_dqrp_mmr_xbist_l_regval;
14568 mmr_t reserved_0 : 8;
14571 mmr_t reserved_1 : 22;
14572 } sh_md_dqrp_mmr_xbist_l_s;
14573 } sh_md_dqrp_mmr_xbist_l_u_t;
14575 /* ==================================================================== */
14576 /* Register "SH_MD_DQRP_MMR_XBIST_ERR_H" */
14577 /* rising edge bist error pattern */
14578 /* ==================================================================== */
14580 typedef union sh_md_dqrp_mmr_xbist_err_h_u {
14581 mmr_t sh_md_dqrp_mmr_xbist_err_h_regval;
14584 mmr_t reserved_0 : 8;
14587 mmr_t reserved_1 : 22;
14588 } sh_md_dqrp_mmr_xbist_err_h_s;
14589 } sh_md_dqrp_mmr_xbist_err_h_u_t;
14591 /* ==================================================================== */
14592 /* Register "SH_MD_DQRP_MMR_XBIST_ERR_L" */
14593 /* falling edge bist error pattern */
14594 /* ==================================================================== */
14596 typedef union sh_md_dqrp_mmr_xbist_err_l_u {
14597 mmr_t sh_md_dqrp_mmr_xbist_err_l_regval;
14600 mmr_t reserved_0 : 8;
14603 mmr_t reserved_1 : 22;
14604 } sh_md_dqrp_mmr_xbist_err_l_s;
14605 } sh_md_dqrp_mmr_xbist_err_l_u_t;
14607 /* ==================================================================== */
14608 /* Register "SH_MD_DQRP_MMR_YBIST_H" */
14609 /* rising edge bist/fill pattern */
14610 /* ==================================================================== */
14612 typedef union sh_md_dqrp_mmr_ybist_h_u {
14613 mmr_t sh_md_dqrp_mmr_ybist_h_regval;
14616 mmr_t reserved_0 : 8;
14620 mmr_t reserved_1 : 21;
14621 } sh_md_dqrp_mmr_ybist_h_s;
14622 } sh_md_dqrp_mmr_ybist_h_u_t;
14624 /* ==================================================================== */
14625 /* Register "SH_MD_DQRP_MMR_YBIST_L" */
14626 /* falling edge bist/fill pattern */
14627 /* ==================================================================== */
14629 typedef union sh_md_dqrp_mmr_ybist_l_u {
14630 mmr_t sh_md_dqrp_mmr_ybist_l_regval;
14633 mmr_t reserved_0 : 8;
14636 mmr_t reserved_1 : 22;
14637 } sh_md_dqrp_mmr_ybist_l_s;
14638 } sh_md_dqrp_mmr_ybist_l_u_t;
14640 /* ==================================================================== */
14641 /* Register "SH_MD_DQRP_MMR_YBIST_ERR_H" */
14642 /* rising edge bist error pattern */
14643 /* ==================================================================== */
14645 typedef union sh_md_dqrp_mmr_ybist_err_h_u {
14646 mmr_t sh_md_dqrp_mmr_ybist_err_h_regval;
14649 mmr_t reserved_0 : 8;
14652 mmr_t reserved_1 : 22;
14653 } sh_md_dqrp_mmr_ybist_err_h_s;
14654 } sh_md_dqrp_mmr_ybist_err_h_u_t;
14656 /* ==================================================================== */
14657 /* Register "SH_MD_DQRP_MMR_YBIST_ERR_L" */
14658 /* falling edge bist error pattern */
14659 /* ==================================================================== */
14661 typedef union sh_md_dqrp_mmr_ybist_err_l_u {
14662 mmr_t sh_md_dqrp_mmr_ybist_err_l_regval;
14665 mmr_t reserved_0 : 8;
14668 mmr_t reserved_1 : 22;
14669 } sh_md_dqrp_mmr_ybist_err_l_s;
14670 } sh_md_dqrp_mmr_ybist_err_l_u_t;
14672 /* ==================================================================== */
14673 /* Register "SH_MD_DQRS_MMR_XBIST_H" */
14674 /* rising edge bist/fill pattern */
14675 /* ==================================================================== */
14677 typedef union sh_md_dqrs_mmr_xbist_h_u {
14678 mmr_t sh_md_dqrs_mmr_xbist_h_regval;
14684 mmr_t reserved_0 : 21;
14685 } sh_md_dqrs_mmr_xbist_h_s;
14686 } sh_md_dqrs_mmr_xbist_h_u_t;
14688 /* ==================================================================== */
14689 /* Register "SH_MD_DQRS_MMR_XBIST_L" */
14690 /* falling edge bist/fill pattern */
14691 /* ==================================================================== */
14693 typedef union sh_md_dqrs_mmr_xbist_l_u {
14694 mmr_t sh_md_dqrs_mmr_xbist_l_regval;
14699 mmr_t reserved_0 : 22;
14700 } sh_md_dqrs_mmr_xbist_l_s;
14701 } sh_md_dqrs_mmr_xbist_l_u_t;
14703 /* ==================================================================== */
14704 /* Register "SH_MD_DQRS_MMR_XBIST_ERR_H" */
14705 /* rising edge bist error pattern */
14706 /* ==================================================================== */
14708 typedef union sh_md_dqrs_mmr_xbist_err_h_u {
14709 mmr_t sh_md_dqrs_mmr_xbist_err_h_regval;
14714 mmr_t reserved_0 : 22;
14715 } sh_md_dqrs_mmr_xbist_err_h_s;
14716 } sh_md_dqrs_mmr_xbist_err_h_u_t;
14718 /* ==================================================================== */
14719 /* Register "SH_MD_DQRS_MMR_XBIST_ERR_L" */
14720 /* falling edge bist error pattern */
14721 /* ==================================================================== */
14723 typedef union sh_md_dqrs_mmr_xbist_err_l_u {
14724 mmr_t sh_md_dqrs_mmr_xbist_err_l_regval;
14729 mmr_t reserved_0 : 22;
14730 } sh_md_dqrs_mmr_xbist_err_l_s;
14731 } sh_md_dqrs_mmr_xbist_err_l_u_t;
14733 /* ==================================================================== */
14734 /* Register "SH_MD_DQRS_MMR_YBIST_H" */
14735 /* rising edge bist/fill pattern */
14736 /* ==================================================================== */
14738 typedef union sh_md_dqrs_mmr_ybist_h_u {
14739 mmr_t sh_md_dqrs_mmr_ybist_h_regval;
14745 mmr_t reserved_0 : 21;
14746 } sh_md_dqrs_mmr_ybist_h_s;
14747 } sh_md_dqrs_mmr_ybist_h_u_t;
14749 /* ==================================================================== */
14750 /* Register "SH_MD_DQRS_MMR_YBIST_L" */
14751 /* falling edge bist/fill pattern */
14752 /* ==================================================================== */
14754 typedef union sh_md_dqrs_mmr_ybist_l_u {
14755 mmr_t sh_md_dqrs_mmr_ybist_l_regval;
14760 mmr_t reserved_0 : 22;
14761 } sh_md_dqrs_mmr_ybist_l_s;
14762 } sh_md_dqrs_mmr_ybist_l_u_t;
14764 /* ==================================================================== */
14765 /* Register "SH_MD_DQRS_MMR_YBIST_ERR_H" */
14766 /* rising edge bist error pattern */
14767 /* ==================================================================== */
14769 typedef union sh_md_dqrs_mmr_ybist_err_h_u {
14770 mmr_t sh_md_dqrs_mmr_ybist_err_h_regval;
14775 mmr_t reserved_0 : 22;
14776 } sh_md_dqrs_mmr_ybist_err_h_s;
14777 } sh_md_dqrs_mmr_ybist_err_h_u_t;
14779 /* ==================================================================== */
14780 /* Register "SH_MD_DQRS_MMR_YBIST_ERR_L" */
14781 /* falling edge bist error pattern */
14782 /* ==================================================================== */
14784 typedef union sh_md_dqrs_mmr_ybist_err_l_u {
14785 mmr_t sh_md_dqrs_mmr_ybist_err_l_regval;
14790 mmr_t reserved_0 : 22;
14791 } sh_md_dqrs_mmr_ybist_err_l_s;
14792 } sh_md_dqrs_mmr_ybist_err_l_u_t;
14794 /* ==================================================================== */
14795 /* Register "SH_MD_DQRS_MMR_JNR_DEBUG" */
14796 /* joiner/fct debug configuration */
14797 /* ==================================================================== */
14799 typedef union sh_md_dqrs_mmr_jnr_debug_u {
14800 mmr_t sh_md_dqrs_mmr_jnr_debug_regval;
14804 mmr_t reserved_0 : 62;
14805 } sh_md_dqrs_mmr_jnr_debug_s;
14806 } sh_md_dqrs_mmr_jnr_debug_u_t;
14808 /* ==================================================================== */
14809 /* Register "SH_MD_DQRS_MMR_YAMOPW_ERR" */
14810 /* amo/partial rmw ecc error register */
14811 /* ==================================================================== */
14813 typedef union sh_md_dqrs_mmr_yamopw_err_u {
14814 mmr_t sh_md_dqrs_mmr_yamopw_err_regval;
14819 mmr_t reserved_0 : 6;
14823 mmr_t reserved_1 : 6;
14825 mmr_t reserved_2 : 31;
14826 } sh_md_dqrs_mmr_yamopw_err_s;
14827 } sh_md_dqrs_mmr_yamopw_err_u_t;
14829 #endif /* _ASM_IA64_SN_SN2_SHUB_MMR_T_H */