2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_IA64_SN_SN2_SHUBIO_H
10 #define _ASM_IA64_SN_SN2_SHUBIO_H
12 #include <asm/sn/arch.h>
14 #define HUB_WIDGET_ID_MAX 0xf
15 #define IIO_NUM_ITTES 7
16 #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
18 #define IIO_WID 0x00400000 /* Crosstalk Widget Identification */
19 /* This register is also accessible from
20 * Crosstalk at address 0x0. */
21 #define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */
22 #define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */
23 #define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */
24 #define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */
25 #define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */
26 #define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */
27 #define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */
28 #define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */
29 #define IIO_ILLR 0x00400130 /* IO LLP Log Register */
30 #define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */
32 #define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */
33 #define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */
35 #define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */
36 #define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */
38 #define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */
39 #define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */
40 #define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */
41 #define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */
42 #define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */
43 #define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */
44 #define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */
46 #define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */
47 #define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */
48 #define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */
49 #define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */
50 #define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */
51 #define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */
52 #define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */
53 #define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */
54 #define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */
56 #define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */
57 #define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */
58 #define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */
59 #define IIO_IECLR 0x004001F8 /* IO Error Clear Register */
60 #define IIO_IBCR 0x00400200 /* IO BTE Control Register */
62 #define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */
63 #define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */
65 #define IIO_ILCT 0x00400218 /* IO LLP Channel Test */
67 #define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */
68 #define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */
71 #define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */
72 #define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */
74 #define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */
75 #define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */
76 #define IIO_IWC 0x00400250 /* IO Wrapper Control Register */
77 #define IIO_IWS 0x00400258 /* IO Wrapper Status Register */
78 #define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */
80 #define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */
82 #define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */
83 #define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */
84 #define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */
85 #define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */
86 #define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */
87 #define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */
88 #define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */
89 #define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */
91 #define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */
92 #define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */
93 #define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */
94 #define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */
95 #define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */
96 #define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */
97 #define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */
98 #define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */
100 #define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */
101 #define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */
102 #define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */
103 #define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */
104 #define IIO_ICMR 0x004003A8 /* IO CRB Management Register */
105 #define IIO_ICCR 0x004003B0 /* IO CRB Control Register */
106 #define IIO_ICTO 0x004003B8 /* IO CRB Timeout */
107 #define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */
109 #define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */
110 #define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */
111 #define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */
112 #define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */
113 #define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */
115 #define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */
116 #define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */
117 #define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */
118 #define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */
119 #define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */
121 #define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */
122 #define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */
123 #define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */
124 #define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */
125 #define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */
127 #define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */
128 #define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */
129 #define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */
130 #define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */
131 #define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */
133 #define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */
134 #define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */
135 #define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */
136 #define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */
137 #define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */
139 #define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */
140 #define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */
141 #define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */
142 #define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */
143 #define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */
145 #define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */
146 #define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */
147 #define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */
148 #define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */
149 #define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */
151 #define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */
152 #define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */
153 #define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */
154 #define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */
155 #define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */
157 #define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */
158 #define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */
159 #define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */
160 #define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */
161 #define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */
163 #define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */
164 #define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */
165 #define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */
166 #define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */
167 #define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */
169 #define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */
170 #define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */
171 #define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */
172 #define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */
173 #define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */
175 #define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */
176 #define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */
177 #define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */
178 #define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */
179 #define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */
181 #define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */
182 #define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */
183 #define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */
184 #define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */
185 #define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */
187 #define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */
188 #define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */
189 #define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */
190 #define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */
191 #define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */
193 #define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */
194 #define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */
195 #define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */
196 #define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */
197 #define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */
199 #define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */
200 #define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */
201 #define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */
203 #define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */
205 #define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */
206 #define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */
207 #define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */
208 #define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */
209 #define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */
210 #define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */
211 #define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */
212 #define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */
213 #define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */
214 #define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */
215 #define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */
216 #define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */
218 #define IIO_IPCR 0x00430000 /* IO Performance Control */
219 #define IIO_IPPR 0x00430008 /* IO Performance Profiling */
222 /************************************************************************
224 * Description: This register echoes some information from the *
225 * LB_REV_ID register. It is available through Crosstalk as described *
226 * above. The REV_NUM and MFG_NUM fields receive their values from *
227 * the REVISION and MANUFACTURER fields in the LB_REV_ID register. *
228 * The PART_NUM field's value is the Crosstalk device ID number that *
229 * Steve Miller assigned to the SHub chip. *
231 ************************************************************************/
233 typedef union ii_wid_u {
234 shubreg_t ii_wid_regval;
236 shubreg_t w_rsvd_1 : 1;
237 shubreg_t w_mfg_num : 11;
238 shubreg_t w_part_num : 16;
239 shubreg_t w_rev_num : 4;
240 shubreg_t w_rsvd : 32;
245 /************************************************************************
247 * The fields in this register are set upon detection of an error *
248 * and cleared by various mechanisms, as explained in the *
251 ************************************************************************/
253 typedef union ii_wstat_u {
254 shubreg_t ii_wstat_regval;
256 shubreg_t w_pending : 4;
257 shubreg_t w_xt_crd_to : 1;
258 shubreg_t w_xt_tail_to : 1;
259 shubreg_t w_rsvd_3 : 3;
260 shubreg_t w_tx_mx_rty : 1;
261 shubreg_t w_rsvd_2 : 6;
262 shubreg_t w_llp_tx_cnt : 8;
263 shubreg_t w_rsvd_1 : 8;
264 shubreg_t w_crazy : 1;
265 shubreg_t w_rsvd : 31;
270 /************************************************************************
272 * Description: This is a read-write enabled register. It controls *
273 * various aspects of the Crosstalk flow control. *
275 ************************************************************************/
277 typedef union ii_wcr_u {
278 shubreg_t ii_wcr_regval;
282 shubreg_t w_rsvd_1 : 8;
283 shubreg_t w_dst_crd : 3;
284 shubreg_t w_f_bad_pkt : 1;
285 shubreg_t w_dir_con : 1;
286 shubreg_t w_e_thresh : 5;
287 shubreg_t w_rsvd : 41;
292 /************************************************************************
294 * Description: This register's value is a bit vector that guards *
295 * access to local registers within the II as well as to external *
296 * Crosstalk widgets. Each bit in the register corresponds to a *
297 * particular region in the system; a region consists of one, two or *
298 * four nodes (depending on the value of the REGION_SIZE field in the *
299 * LB_REV_ID register, which is documented in Section 8.3.1.1). The *
300 * protection provided by this register applies to PIO read *
301 * operations as well as PIO write operations. The II will perform a *
302 * PIO read or write request only if the bit for the requestor's *
303 * region is set; otherwise, the II will not perform the requested *
304 * operation and will return an error response. When a PIO read or *
305 * write request targets an external Crosstalk widget, then not only *
306 * must the bit for the requestor's region be set in the ILAPR, but *
307 * also the target widget's bit in the IOWA register must be set in *
308 * order for the II to perform the requested operation; otherwise, *
309 * the II will return an error response. Hence, the protection *
310 * provided by the IOWA register supplements the protection provided *
311 * by the ILAPR for requests that target external Crosstalk widgets. *
312 * This register itself can be accessed only by the nodes whose *
313 * region ID bits are enabled in this same register. It can also be *
314 * accessed through the IAlias space by the local processors. *
315 * The reset value of this register allows access by all nodes. *
317 ************************************************************************/
319 typedef union ii_ilapr_u {
320 shubreg_t ii_ilapr_regval;
322 shubreg_t i_region : 64;
329 /************************************************************************
331 * Description: A write to this register of the 64-bit value *
332 * "SGIrules" in ASCII, will cause the bit in the ILAPR register *
333 * corresponding to the region of the requestor to be set (allow *
334 * access). A write of any other value will be ignored. Access *
335 * protection for this register is "SGIrules". *
336 * This register can also be accessed through the IAlias space. *
337 * However, this access will not change the access permissions in the *
340 ************************************************************************/
342 typedef union ii_ilapo_u {
343 shubreg_t ii_ilapo_regval;
345 shubreg_t i_io_ovrride : 64;
351 /************************************************************************
353 * This register qualifies all the PIO and Graphics writes launched *
354 * from the SHUB towards a widget. *
356 ************************************************************************/
358 typedef union ii_iowa_u {
359 shubreg_t ii_iowa_regval;
361 shubreg_t i_w0_oac : 1;
362 shubreg_t i_rsvd_1 : 7;
363 shubreg_t i_wx_oac : 8;
364 shubreg_t i_rsvd : 48;
369 /************************************************************************
371 * Description: This register qualifies all the requests launched *
372 * from a widget towards the Shub. This register is intended to be *
373 * used by software in case of misbehaving widgets. *
376 ************************************************************************/
378 typedef union ii_iiwa_u {
379 shubreg_t ii_iiwa_regval;
381 shubreg_t i_w0_iac : 1;
382 shubreg_t i_rsvd_1 : 7;
383 shubreg_t i_wx_iac : 8;
384 shubreg_t i_rsvd : 48;
390 /************************************************************************
392 * Description: This register qualifies all the operations launched *
393 * from a widget towards the SHub. It allows individual access *
394 * control for up to 8 devices per widget. A device refers to *
395 * individual DMA master hosted by a widget. *
396 * The bits in each field of this register are cleared by the Shub *
397 * upon detection of an error which requires the device to be *
398 * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric *
399 * Crosstalk). Whether or not a device has access rights to this *
400 * Shub is determined by an AND of the device enable bit in the *
401 * appropriate field of this register and the corresponding bit in *
402 * the Wx_IAC field (for the widget which this device belongs to). *
403 * The bits in this field are set by writing a 1 to them. Incoming *
404 * replies from Crosstalk are not subject to this access control *
407 ************************************************************************/
409 typedef union ii_iidem_u {
410 shubreg_t ii_iidem_regval;
412 shubreg_t i_w8_dxs : 8;
413 shubreg_t i_w9_dxs : 8;
414 shubreg_t i_wa_dxs : 8;
415 shubreg_t i_wb_dxs : 8;
416 shubreg_t i_wc_dxs : 8;
417 shubreg_t i_wd_dxs : 8;
418 shubreg_t i_we_dxs : 8;
419 shubreg_t i_wf_dxs : 8;
424 /************************************************************************
426 * This register contains the various programmable fields necessary *
427 * for controlling and observing the LLP signals. *
429 ************************************************************************/
431 typedef union ii_ilcsr_u {
432 shubreg_t ii_ilcsr_regval;
434 shubreg_t i_nullto : 6;
435 shubreg_t i_rsvd_4 : 2;
436 shubreg_t i_wrmrst : 1;
437 shubreg_t i_rsvd_3 : 1;
438 shubreg_t i_llp_en : 1;
440 shubreg_t i_llp_stat : 2;
441 shubreg_t i_remote_power : 1;
442 shubreg_t i_rsvd_2 : 1;
443 shubreg_t i_maxrtry : 10;
444 shubreg_t i_d_avail_sel : 2;
445 shubreg_t i_rsvd_1 : 4;
446 shubreg_t i_maxbrst : 10;
447 shubreg_t i_rsvd : 22;
453 /************************************************************************
455 * This is simply a status registers that monitors the LLP error *
458 ************************************************************************/
460 typedef union ii_illr_u {
461 shubreg_t ii_illr_regval;
463 shubreg_t i_sn_cnt : 16;
464 shubreg_t i_cb_cnt : 16;
465 shubreg_t i_rsvd : 32;
470 /************************************************************************
472 * Description: All II-detected non-BTE error interrupts are *
473 * specified via this register. *
474 * NOTE: The PI interrupt register address is hardcoded in the II. If *
475 * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI *
476 * packet) to address offset 0x0180_0090 within the local register *
477 * address space of PI0 on the node specified by the NODE field. If *
478 * PI_ID==1, then the II sends the interrupt request to address *
479 * offset 0x01A0_0090 within the local register address space of PI1 *
480 * on the node specified by the NODE field. *
482 ************************************************************************/
484 typedef union ii_iidsr_u {
485 shubreg_t ii_iidsr_regval;
487 shubreg_t i_level : 8;
488 shubreg_t i_pi_id : 1;
489 shubreg_t i_node : 11;
490 shubreg_t i_rsvd_3 : 4;
491 shubreg_t i_enable : 1;
492 shubreg_t i_rsvd_2 : 3;
493 shubreg_t i_int_sent : 2;
494 shubreg_t i_rsvd_1 : 2;
495 shubreg_t i_pi0_forward_int : 1;
496 shubreg_t i_pi1_forward_int : 1;
497 shubreg_t i_rsvd : 30;
503 /************************************************************************
505 * There are two instances of this register. This register is used *
506 * for matching up the incoming responses from the graphics widget to *
507 * the processor that initiated the graphics operation. The *
508 * write-responses are converted to graphics credits and returned to *
509 * the processor so that the processor interface can manage the flow *
512 ************************************************************************/
514 typedef union ii_igfx0_u {
515 shubreg_t ii_igfx0_regval;
517 shubreg_t i_w_num : 4;
518 shubreg_t i_pi_id : 1;
519 shubreg_t i_n_num : 12;
520 shubreg_t i_p_num : 1;
521 shubreg_t i_rsvd : 46;
526 /************************************************************************
528 * There are two instances of this register. This register is used *
529 * for matching up the incoming responses from the graphics widget to *
530 * the processor that initiated the graphics operation. The *
531 * write-responses are converted to graphics credits and returned to *
532 * the processor so that the processor interface can manage the flow *
535 ************************************************************************/
537 typedef union ii_igfx1_u {
538 shubreg_t ii_igfx1_regval;
540 shubreg_t i_w_num : 4;
541 shubreg_t i_pi_id : 1;
542 shubreg_t i_n_num : 12;
543 shubreg_t i_p_num : 1;
544 shubreg_t i_rsvd : 46;
549 /************************************************************************
551 * There are two instances of this registers. These registers are *
552 * used as scratch registers for software use. *
554 ************************************************************************/
556 typedef union ii_iscr0_u {
557 shubreg_t ii_iscr0_regval;
559 shubreg_t i_scratch : 64;
565 /************************************************************************
567 * There are two instances of this registers. These registers are *
568 * used as scratch registers for software use. *
570 ************************************************************************/
572 typedef union ii_iscr1_u {
573 shubreg_t ii_iscr1_regval;
575 shubreg_t i_scratch : 64;
580 /************************************************************************
582 * Description: There are seven instances of translation table entry *
583 * registers. Each register maps a Shub Big Window to a 48-bit *
584 * address on Crosstalk. *
585 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
586 * number) are used to select one of these 7 registers. The Widget *
587 * number field is then derived from the W_NUM field for synthesizing *
588 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
589 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
590 * are padded with zeros. Although the maximum Crosstalk space *
591 * addressable by the SHub is thus the lower 16 GBytes per widget *
592 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
593 * space can be accessed. *
594 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
595 * Window number) are used to select one of these 7 registers. The *
596 * Widget number field is then derived from the W_NUM field for *
597 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
598 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
599 * field is used as Crosstalk[47], and remainder of the Crosstalk *
600 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
601 * Crosstalk space addressable by the Shub is thus the lower *
602 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
603 * of this space can be accessed. *
605 ************************************************************************/
607 typedef union ii_itte1_u {
608 shubreg_t ii_itte1_regval;
610 shubreg_t i_offset : 5;
611 shubreg_t i_rsvd_1 : 3;
612 shubreg_t i_w_num : 4;
613 shubreg_t i_iosp : 1;
614 shubreg_t i_rsvd : 51;
619 /************************************************************************
621 * Description: There are seven instances of translation table entry *
622 * registers. Each register maps a Shub Big Window to a 48-bit *
623 * address on Crosstalk. *
624 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
625 * number) are used to select one of these 7 registers. The Widget *
626 * number field is then derived from the W_NUM field for synthesizing *
627 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
628 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
629 * are padded with zeros. Although the maximum Crosstalk space *
630 * addressable by the Shub is thus the lower 16 GBytes per widget *
631 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
632 * space can be accessed. *
633 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
634 * Window number) are used to select one of these 7 registers. The *
635 * Widget number field is then derived from the W_NUM field for *
636 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
637 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
638 * field is used as Crosstalk[47], and remainder of the Crosstalk *
639 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
640 * Crosstalk space addressable by the Shub is thus the lower *
641 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
642 * of this space can be accessed. *
644 ************************************************************************/
646 typedef union ii_itte2_u {
647 shubreg_t ii_itte2_regval;
649 shubreg_t i_offset : 5;
650 shubreg_t i_rsvd_1 : 3;
651 shubreg_t i_w_num : 4;
652 shubreg_t i_iosp : 1;
653 shubreg_t i_rsvd : 51;
658 /************************************************************************
660 * Description: There are seven instances of translation table entry *
661 * registers. Each register maps a Shub Big Window to a 48-bit *
662 * address on Crosstalk. *
663 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
664 * number) are used to select one of these 7 registers. The Widget *
665 * number field is then derived from the W_NUM field for synthesizing *
666 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
667 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
668 * are padded with zeros. Although the maximum Crosstalk space *
669 * addressable by the Shub is thus the lower 16 GBytes per widget *
670 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
671 * space can be accessed. *
672 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
673 * Window number) are used to select one of these 7 registers. The *
674 * Widget number field is then derived from the W_NUM field for *
675 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
676 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
677 * field is used as Crosstalk[47], and remainder of the Crosstalk *
678 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
679 * Crosstalk space addressable by the SHub is thus the lower *
680 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
681 * of this space can be accessed. *
683 ************************************************************************/
685 typedef union ii_itte3_u {
686 shubreg_t ii_itte3_regval;
688 shubreg_t i_offset : 5;
689 shubreg_t i_rsvd_1 : 3;
690 shubreg_t i_w_num : 4;
691 shubreg_t i_iosp : 1;
692 shubreg_t i_rsvd : 51;
697 /************************************************************************
699 * Description: There are seven instances of translation table entry *
700 * registers. Each register maps a SHub Big Window to a 48-bit *
701 * address on Crosstalk. *
702 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
703 * number) are used to select one of these 7 registers. The Widget *
704 * number field is then derived from the W_NUM field for synthesizing *
705 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
706 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
707 * are padded with zeros. Although the maximum Crosstalk space *
708 * addressable by the SHub is thus the lower 16 GBytes per widget *
709 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
710 * space can be accessed. *
711 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
712 * Window number) are used to select one of these 7 registers. The *
713 * Widget number field is then derived from the W_NUM field for *
714 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
715 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
716 * field is used as Crosstalk[47], and remainder of the Crosstalk *
717 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
718 * Crosstalk space addressable by the SHub is thus the lower *
719 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
720 * of this space can be accessed. *
722 ************************************************************************/
724 typedef union ii_itte4_u {
725 shubreg_t ii_itte4_regval;
727 shubreg_t i_offset : 5;
728 shubreg_t i_rsvd_1 : 3;
729 shubreg_t i_w_num : 4;
730 shubreg_t i_iosp : 1;
731 shubreg_t i_rsvd : 51;
736 /************************************************************************
738 * Description: There are seven instances of translation table entry *
739 * registers. Each register maps a SHub Big Window to a 48-bit *
740 * address on Crosstalk. *
741 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
742 * number) are used to select one of these 7 registers. The Widget *
743 * number field is then derived from the W_NUM field for synthesizing *
744 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
745 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
746 * are padded with zeros. Although the maximum Crosstalk space *
747 * addressable by the Shub is thus the lower 16 GBytes per widget *
748 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
749 * space can be accessed. *
750 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
751 * Window number) are used to select one of these 7 registers. The *
752 * Widget number field is then derived from the W_NUM field for *
753 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
754 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
755 * field is used as Crosstalk[47], and remainder of the Crosstalk *
756 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
757 * Crosstalk space addressable by the Shub is thus the lower *
758 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
759 * of this space can be accessed. *
761 ************************************************************************/
763 typedef union ii_itte5_u {
764 shubreg_t ii_itte5_regval;
766 shubreg_t i_offset : 5;
767 shubreg_t i_rsvd_1 : 3;
768 shubreg_t i_w_num : 4;
769 shubreg_t i_iosp : 1;
770 shubreg_t i_rsvd : 51;
775 /************************************************************************
777 * Description: There are seven instances of translation table entry *
778 * registers. Each register maps a Shub Big Window to a 48-bit *
779 * address on Crosstalk. *
780 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
781 * number) are used to select one of these 7 registers. The Widget *
782 * number field is then derived from the W_NUM field for synthesizing *
783 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
784 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
785 * are padded with zeros. Although the maximum Crosstalk space *
786 * addressable by the Shub is thus the lower 16 GBytes per widget *
787 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
788 * space can be accessed. *
789 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
790 * Window number) are used to select one of these 7 registers. The *
791 * Widget number field is then derived from the W_NUM field for *
792 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
793 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
794 * field is used as Crosstalk[47], and remainder of the Crosstalk *
795 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
796 * Crosstalk space addressable by the Shub is thus the lower *
797 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
798 * of this space can be accessed. *
800 ************************************************************************/
802 typedef union ii_itte6_u {
803 shubreg_t ii_itte6_regval;
805 shubreg_t i_offset : 5;
806 shubreg_t i_rsvd_1 : 3;
807 shubreg_t i_w_num : 4;
808 shubreg_t i_iosp : 1;
809 shubreg_t i_rsvd : 51;
814 /************************************************************************
816 * Description: There are seven instances of translation table entry *
817 * registers. Each register maps a Shub Big Window to a 48-bit *
818 * address on Crosstalk. *
819 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
820 * number) are used to select one of these 7 registers. The Widget *
821 * number field is then derived from the W_NUM field for synthesizing *
822 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
823 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
824 * are padded with zeros. Although the maximum Crosstalk space *
825 * addressable by the Shub is thus the lower 16 GBytes per widget *
826 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
827 * space can be accessed. *
828 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
829 * Window number) are used to select one of these 7 registers. The *
830 * Widget number field is then derived from the W_NUM field for *
831 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
832 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
833 * field is used as Crosstalk[47], and remainder of the Crosstalk *
834 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
835 * Crosstalk space addressable by the SHub is thus the lower *
836 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
837 * of this space can be accessed. *
839 ************************************************************************/
841 typedef union ii_itte7_u {
842 shubreg_t ii_itte7_regval;
844 shubreg_t i_offset : 5;
845 shubreg_t i_rsvd_1 : 3;
846 shubreg_t i_w_num : 4;
847 shubreg_t i_iosp : 1;
848 shubreg_t i_rsvd : 51;
853 /************************************************************************
855 * Description: There are 9 instances of this register, one per *
856 * actual widget in this implementation of SHub and Crossbow. *
857 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
858 * refers to Crossbow's internal space. *
859 * This register contains the state elements per widget that are *
860 * necessary to manage the PIO flow control on Crosstalk and on the *
861 * Router Network. See the PIO Flow Control chapter for a complete *
862 * description of this register *
863 * The SPUR_WR bit requires some explanation. When this register is *
864 * written, the new value of the C field is captured in an internal *
865 * register so the hardware can remember what the programmer wrote *
866 * into the credit counter. The SPUR_WR bit sets whenever the C field *
867 * increments above this stored value, which indicates that there *
868 * have been more responses received than requests sent. The SPUR_WR *
869 * bit cannot be cleared until a value is written to the IPRBx *
870 * register; the write will correct the C field and capture its new *
871 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
872 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
875 ************************************************************************/
877 typedef union ii_iprb0_u {
878 shubreg_t ii_iprb0_regval;
882 shubreg_t i_rsvd_2 : 2;
884 shubreg_t i_rsvd_1 : 2;
887 shubreg_t i_of_cnt : 5;
888 shubreg_t i_error : 1;
889 shubreg_t i_rd_to : 1;
890 shubreg_t i_spur_wr : 1;
891 shubreg_t i_spur_rd : 1;
892 shubreg_t i_rsvd : 11;
893 shubreg_t i_mult_err : 1;
898 /************************************************************************
900 * Description: There are 9 instances of this register, one per *
901 * actual widget in this implementation of SHub and Crossbow. *
902 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
903 * refers to Crossbow's internal space. *
904 * This register contains the state elements per widget that are *
905 * necessary to manage the PIO flow control on Crosstalk and on the *
906 * Router Network. See the PIO Flow Control chapter for a complete *
907 * description of this register *
908 * The SPUR_WR bit requires some explanation. When this register is *
909 * written, the new value of the C field is captured in an internal *
910 * register so the hardware can remember what the programmer wrote *
911 * into the credit counter. The SPUR_WR bit sets whenever the C field *
912 * increments above this stored value, which indicates that there *
913 * have been more responses received than requests sent. The SPUR_WR *
914 * bit cannot be cleared until a value is written to the IPRBx *
915 * register; the write will correct the C field and capture its new *
916 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
917 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
920 ************************************************************************/
922 typedef union ii_iprb8_u {
923 shubreg_t ii_iprb8_regval;
927 shubreg_t i_rsvd_2 : 2;
929 shubreg_t i_rsvd_1 : 2;
932 shubreg_t i_of_cnt : 5;
933 shubreg_t i_error : 1;
934 shubreg_t i_rd_to : 1;
935 shubreg_t i_spur_wr : 1;
936 shubreg_t i_spur_rd : 1;
937 shubreg_t i_rsvd : 11;
938 shubreg_t i_mult_err : 1;
943 /************************************************************************
945 * Description: There are 9 instances of this register, one per *
946 * actual widget in this implementation of SHub and Crossbow. *
947 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
948 * refers to Crossbow's internal space. *
949 * This register contains the state elements per widget that are *
950 * necessary to manage the PIO flow control on Crosstalk and on the *
951 * Router Network. See the PIO Flow Control chapter for a complete *
952 * description of this register *
953 * The SPUR_WR bit requires some explanation. When this register is *
954 * written, the new value of the C field is captured in an internal *
955 * register so the hardware can remember what the programmer wrote *
956 * into the credit counter. The SPUR_WR bit sets whenever the C field *
957 * increments above this stored value, which indicates that there *
958 * have been more responses received than requests sent. The SPUR_WR *
959 * bit cannot be cleared until a value is written to the IPRBx *
960 * register; the write will correct the C field and capture its new *
961 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
962 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
965 ************************************************************************/
967 typedef union ii_iprb9_u {
968 shubreg_t ii_iprb9_regval;
972 shubreg_t i_rsvd_2 : 2;
974 shubreg_t i_rsvd_1 : 2;
977 shubreg_t i_of_cnt : 5;
978 shubreg_t i_error : 1;
979 shubreg_t i_rd_to : 1;
980 shubreg_t i_spur_wr : 1;
981 shubreg_t i_spur_rd : 1;
982 shubreg_t i_rsvd : 11;
983 shubreg_t i_mult_err : 1;
988 /************************************************************************
990 * Description: There are 9 instances of this register, one per *
991 * actual widget in this implementation of SHub and Crossbow. *
992 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
993 * refers to Crossbow's internal space. *
994 * This register contains the state elements per widget that are *
995 * necessary to manage the PIO flow control on Crosstalk and on the *
996 * Router Network. See the PIO Flow Control chapter for a complete *
997 * description of this register *
998 * The SPUR_WR bit requires some explanation. When this register is *
999 * written, the new value of the C field is captured in an internal *
1000 * register so the hardware can remember what the programmer wrote *
1001 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1002 * increments above this stored value, which indicates that there *
1003 * have been more responses received than requests sent. The SPUR_WR *
1004 * bit cannot be cleared until a value is written to the IPRBx *
1005 * register; the write will correct the C field and capture its new *
1006 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1007 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1010 ************************************************************************/
1012 typedef union ii_iprba_u {
1013 shubreg_t ii_iprba_regval;
1016 shubreg_t i_na : 14;
1017 shubreg_t i_rsvd_2 : 2;
1018 shubreg_t i_nb : 14;
1019 shubreg_t i_rsvd_1 : 2;
1022 shubreg_t i_of_cnt : 5;
1023 shubreg_t i_error : 1;
1024 shubreg_t i_rd_to : 1;
1025 shubreg_t i_spur_wr : 1;
1026 shubreg_t i_spur_rd : 1;
1027 shubreg_t i_rsvd : 11;
1028 shubreg_t i_mult_err : 1;
1033 /************************************************************************
1035 * Description: There are 9 instances of this register, one per *
1036 * actual widget in this implementation of SHub and Crossbow. *
1037 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1038 * refers to Crossbow's internal space. *
1039 * This register contains the state elements per widget that are *
1040 * necessary to manage the PIO flow control on Crosstalk and on the *
1041 * Router Network. See the PIO Flow Control chapter for a complete *
1042 * description of this register *
1043 * The SPUR_WR bit requires some explanation. When this register is *
1044 * written, the new value of the C field is captured in an internal *
1045 * register so the hardware can remember what the programmer wrote *
1046 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1047 * increments above this stored value, which indicates that there *
1048 * have been more responses received than requests sent. The SPUR_WR *
1049 * bit cannot be cleared until a value is written to the IPRBx *
1050 * register; the write will correct the C field and capture its new *
1051 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1052 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1055 ************************************************************************/
1057 typedef union ii_iprbb_u {
1058 shubreg_t ii_iprbb_regval;
1061 shubreg_t i_na : 14;
1062 shubreg_t i_rsvd_2 : 2;
1063 shubreg_t i_nb : 14;
1064 shubreg_t i_rsvd_1 : 2;
1067 shubreg_t i_of_cnt : 5;
1068 shubreg_t i_error : 1;
1069 shubreg_t i_rd_to : 1;
1070 shubreg_t i_spur_wr : 1;
1071 shubreg_t i_spur_rd : 1;
1072 shubreg_t i_rsvd : 11;
1073 shubreg_t i_mult_err : 1;
1078 /************************************************************************
1080 * Description: There are 9 instances of this register, one per *
1081 * actual widget in this implementation of SHub and Crossbow. *
1082 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1083 * refers to Crossbow's internal space. *
1084 * This register contains the state elements per widget that are *
1085 * necessary to manage the PIO flow control on Crosstalk and on the *
1086 * Router Network. See the PIO Flow Control chapter for a complete *
1087 * description of this register *
1088 * The SPUR_WR bit requires some explanation. When this register is *
1089 * written, the new value of the C field is captured in an internal *
1090 * register so the hardware can remember what the programmer wrote *
1091 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1092 * increments above this stored value, which indicates that there *
1093 * have been more responses received than requests sent. The SPUR_WR *
1094 * bit cannot be cleared until a value is written to the IPRBx *
1095 * register; the write will correct the C field and capture its new *
1096 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1097 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1100 ************************************************************************/
1102 typedef union ii_iprbc_u {
1103 shubreg_t ii_iprbc_regval;
1106 shubreg_t i_na : 14;
1107 shubreg_t i_rsvd_2 : 2;
1108 shubreg_t i_nb : 14;
1109 shubreg_t i_rsvd_1 : 2;
1112 shubreg_t i_of_cnt : 5;
1113 shubreg_t i_error : 1;
1114 shubreg_t i_rd_to : 1;
1115 shubreg_t i_spur_wr : 1;
1116 shubreg_t i_spur_rd : 1;
1117 shubreg_t i_rsvd : 11;
1118 shubreg_t i_mult_err : 1;
1123 /************************************************************************
1125 * Description: There are 9 instances of this register, one per *
1126 * actual widget in this implementation of SHub and Crossbow. *
1127 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1128 * refers to Crossbow's internal space. *
1129 * This register contains the state elements per widget that are *
1130 * necessary to manage the PIO flow control on Crosstalk and on the *
1131 * Router Network. See the PIO Flow Control chapter for a complete *
1132 * description of this register *
1133 * The SPUR_WR bit requires some explanation. When this register is *
1134 * written, the new value of the C field is captured in an internal *
1135 * register so the hardware can remember what the programmer wrote *
1136 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1137 * increments above this stored value, which indicates that there *
1138 * have been more responses received than requests sent. The SPUR_WR *
1139 * bit cannot be cleared until a value is written to the IPRBx *
1140 * register; the write will correct the C field and capture its new *
1141 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1142 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1145 ************************************************************************/
1147 typedef union ii_iprbd_u {
1148 shubreg_t ii_iprbd_regval;
1151 shubreg_t i_na : 14;
1152 shubreg_t i_rsvd_2 : 2;
1153 shubreg_t i_nb : 14;
1154 shubreg_t i_rsvd_1 : 2;
1157 shubreg_t i_of_cnt : 5;
1158 shubreg_t i_error : 1;
1159 shubreg_t i_rd_to : 1;
1160 shubreg_t i_spur_wr : 1;
1161 shubreg_t i_spur_rd : 1;
1162 shubreg_t i_rsvd : 11;
1163 shubreg_t i_mult_err : 1;
1168 /************************************************************************
1170 * Description: There are 9 instances of this register, one per *
1171 * actual widget in this implementation of SHub and Crossbow. *
1172 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1173 * refers to Crossbow's internal space. *
1174 * This register contains the state elements per widget that are *
1175 * necessary to manage the PIO flow control on Crosstalk and on the *
1176 * Router Network. See the PIO Flow Control chapter for a complete *
1177 * description of this register *
1178 * The SPUR_WR bit requires some explanation. When this register is *
1179 * written, the new value of the C field is captured in an internal *
1180 * register so the hardware can remember what the programmer wrote *
1181 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1182 * increments above this stored value, which indicates that there *
1183 * have been more responses received than requests sent. The SPUR_WR *
1184 * bit cannot be cleared until a value is written to the IPRBx *
1185 * register; the write will correct the C field and capture its new *
1186 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1187 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1190 ************************************************************************/
1192 typedef union ii_iprbe_u {
1193 shubreg_t ii_iprbe_regval;
1196 shubreg_t i_na : 14;
1197 shubreg_t i_rsvd_2 : 2;
1198 shubreg_t i_nb : 14;
1199 shubreg_t i_rsvd_1 : 2;
1202 shubreg_t i_of_cnt : 5;
1203 shubreg_t i_error : 1;
1204 shubreg_t i_rd_to : 1;
1205 shubreg_t i_spur_wr : 1;
1206 shubreg_t i_spur_rd : 1;
1207 shubreg_t i_rsvd : 11;
1208 shubreg_t i_mult_err : 1;
1213 /************************************************************************
1215 * Description: There are 9 instances of this register, one per *
1216 * actual widget in this implementation of Shub and Crossbow. *
1217 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1218 * refers to Crossbow's internal space. *
1219 * This register contains the state elements per widget that are *
1220 * necessary to manage the PIO flow control on Crosstalk and on the *
1221 * Router Network. See the PIO Flow Control chapter for a complete *
1222 * description of this register *
1223 * The SPUR_WR bit requires some explanation. When this register is *
1224 * written, the new value of the C field is captured in an internal *
1225 * register so the hardware can remember what the programmer wrote *
1226 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1227 * increments above this stored value, which indicates that there *
1228 * have been more responses received than requests sent. The SPUR_WR *
1229 * bit cannot be cleared until a value is written to the IPRBx *
1230 * register; the write will correct the C field and capture its new *
1231 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1232 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1235 ************************************************************************/
1237 typedef union ii_iprbf_u {
1238 shubreg_t ii_iprbf_regval;
1241 shubreg_t i_na : 14;
1242 shubreg_t i_rsvd_2 : 2;
1243 shubreg_t i_nb : 14;
1244 shubreg_t i_rsvd_1 : 2;
1247 shubreg_t i_of_cnt : 5;
1248 shubreg_t i_error : 1;
1249 shubreg_t i_rd_to : 1;
1250 shubreg_t i_spur_wr : 1;
1251 shubreg_t i_spur_rd : 1;
1252 shubreg_t i_rsvd : 11;
1253 shubreg_t i_mult_err : 1;
1258 /************************************************************************
1260 * This register specifies the timeout value to use for monitoring *
1261 * Crosstalk credits which are used outbound to Crosstalk. An *
1262 * internal counter called the Crosstalk Credit Timeout Counter *
1263 * increments every 128 II clocks. The counter starts counting *
1264 * anytime the credit count drops below a threshold, and resets to *
1265 * zero (stops counting) anytime the credit count is at or above the *
1266 * threshold. The threshold is 1 credit in direct connect mode and 2 *
1267 * in Crossbow connect mode. When the internal Crosstalk Credit *
1268 * Timeout Counter reaches the value programmed in this register, a *
1269 * Crosstalk Credit Timeout has occurred. The internal counter is not *
1270 * readable from software, and stops counting at its maximum value, *
1271 * so it cannot cause more than one interrupt. *
1273 ************************************************************************/
1275 typedef union ii_ixcc_u {
1276 shubreg_t ii_ixcc_regval;
1278 shubreg_t i_time_out : 26;
1279 shubreg_t i_rsvd : 38;
1284 /************************************************************************
1286 * Description: This register qualifies all the PIO and DMA *
1287 * operations launched from widget 0 towards the SHub. In *
1288 * addition, it also qualifies accesses by the BTE streams. *
1289 * The bits in each field of this register are cleared by the SHub *
1290 * upon detection of an error which requires widget 0 or the BTE *
1291 * streams to be terminated. Whether or not widget x has access *
1292 * rights to this SHub is determined by an AND of the device *
1293 * enable bit in the appropriate field of this register and bit 0 in *
1294 * the Wx_IAC field. The bits in this field are set by writing a 1 to *
1295 * them. Incoming replies from Crosstalk are not subject to this *
1296 * access control mechanism. *
1298 ************************************************************************/
1300 typedef union ii_imem_u {
1301 shubreg_t ii_imem_regval;
1303 shubreg_t i_w0_esd : 1;
1304 shubreg_t i_rsvd_3 : 3;
1305 shubreg_t i_b0_esd : 1;
1306 shubreg_t i_rsvd_2 : 3;
1307 shubreg_t i_b1_esd : 1;
1308 shubreg_t i_rsvd_1 : 3;
1309 shubreg_t i_clr_precise : 1;
1310 shubreg_t i_rsvd : 51;
1316 /************************************************************************
1318 * Description: This register specifies the timeout value to use for *
1319 * monitoring Crosstalk tail flits coming into the Shub in the *
1320 * TAIL_TO field. An internal counter associated with this register *
1321 * is incremented every 128 II internal clocks (7 bits). The counter *
1322 * starts counting anytime a header micropacket is received and stops *
1323 * counting (and resets to zero) any time a micropacket with a Tail *
1324 * bit is received. Once the counter reaches the threshold value *
1325 * programmed in this register, it generates an interrupt to the *
1326 * processor that is programmed into the IIDSR. The counter saturates *
1327 * (does not roll over) at its maximum value, so it cannot cause *
1328 * another interrupt until after it is cleared. *
1329 * The register also contains the Read Response Timeout values. The *
1330 * Prescalar is 23 bits, and counts II clocks. An internal counter *
1331 * increments on every II clock and when it reaches the value in the *
1332 * Prescalar field, all IPRTE registers with their valid bits set *
1333 * have their Read Response timers bumped. Whenever any of them match *
1334 * the value in the RRSP_TO field, a Read Response Timeout has *
1335 * occurred, and error handling occurs as described in the Error *
1336 * Handling section of this document. *
1338 ************************************************************************/
1340 typedef union ii_ixtt_u {
1341 shubreg_t ii_ixtt_regval;
1343 shubreg_t i_tail_to : 26;
1344 shubreg_t i_rsvd_1 : 6;
1345 shubreg_t i_rrsp_ps : 23;
1346 shubreg_t i_rrsp_to : 5;
1347 shubreg_t i_rsvd : 4;
1352 /************************************************************************
1354 * Writing a 1 to the fields of this register clears the appropriate *
1355 * error bits in other areas of SHub. Note that when the *
1356 * E_PRB_x bits are used to clear error bits in PRB registers, *
1357 * SPUR_RD and SPUR_WR may persist, because they require additional *
1358 * action to clear them. See the IPRBx and IXSS Register *
1361 ************************************************************************/
1363 typedef union ii_ieclr_u {
1364 shubreg_t ii_ieclr_regval;
1366 shubreg_t i_e_prb_0 : 1;
1367 shubreg_t i_rsvd : 7;
1368 shubreg_t i_e_prb_8 : 1;
1369 shubreg_t i_e_prb_9 : 1;
1370 shubreg_t i_e_prb_a : 1;
1371 shubreg_t i_e_prb_b : 1;
1372 shubreg_t i_e_prb_c : 1;
1373 shubreg_t i_e_prb_d : 1;
1374 shubreg_t i_e_prb_e : 1;
1375 shubreg_t i_e_prb_f : 1;
1376 shubreg_t i_e_crazy : 1;
1377 shubreg_t i_e_bte_0 : 1;
1378 shubreg_t i_e_bte_1 : 1;
1379 shubreg_t i_reserved_1 : 10;
1380 shubreg_t i_spur_rd_hdr : 1;
1381 shubreg_t i_cam_intr_to : 1;
1382 shubreg_t i_cam_overflow : 1;
1383 shubreg_t i_cam_read_miss : 1;
1384 shubreg_t i_ioq_rep_underflow : 1;
1385 shubreg_t i_ioq_req_underflow : 1;
1386 shubreg_t i_ioq_rep_overflow : 1;
1387 shubreg_t i_ioq_req_overflow : 1;
1388 shubreg_t i_iiq_rep_overflow : 1;
1389 shubreg_t i_iiq_req_overflow : 1;
1390 shubreg_t i_ii_xn_rep_cred_overflow : 1;
1391 shubreg_t i_ii_xn_req_cred_overflow : 1;
1392 shubreg_t i_ii_xn_invalid_cmd : 1;
1393 shubreg_t i_xn_ii_invalid_cmd : 1;
1394 shubreg_t i_reserved_2 : 21;
1399 /************************************************************************
1401 * This register controls both BTEs. SOFT_RESET is intended for *
1402 * recovery after an error. COUNT controls the total number of CRBs *
1403 * that both BTEs (combined) can use, which affects total BTE *
1406 ************************************************************************/
1408 typedef union ii_ibcr_u {
1409 shubreg_t ii_ibcr_regval;
1411 shubreg_t i_count : 4;
1412 shubreg_t i_rsvd_1 : 4;
1413 shubreg_t i_soft_reset : 1;
1414 shubreg_t i_rsvd : 55;
1419 /************************************************************************
1421 * This register contains the header of a spurious read response *
1422 * received from Crosstalk. A spurious read response is defined as a *
1423 * read response received by II from a widget for which (1) the SIDN *
1424 * has a value between 1 and 7, inclusive (II never sends requests to *
1425 * these widgets (2) there is no valid IPRTE register which *
1426 * corresponds to the TNUM, or (3) the widget indicated in SIDN is *
1427 * not the same as the widget recorded in the IPRTE register *
1428 * referenced by the TNUM. If this condition is true, and if the *
1429 * IXSS[VALID] bit is clear, then the header of the spurious read *
1430 * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The *
1431 * errant header is thereby captured, and no further spurious read *
1432 * respones are captured until IXSS[VALID] is cleared by setting the *
1433 * appropriate bit in IECLR.Everytime a spurious read response is *
1434 * detected, the SPUR_RD bit of the PRB corresponding to the incoming *
1435 * message's SIDN field is set. This always happens, regarless of *
1436 * whether a header is captured. The programmer should check *
1437 * IXSM[SIDN] to determine which widget sent the spurious response, *
1438 * because there may be more than one SPUR_RD bit set in the PRB *
1439 * registers. The widget indicated by IXSM[SIDN] was the first *
1440 * spurious read response to be received since the last time *
1441 * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB *
1442 * will be set. Any SPUR_RD bits in any other PRB registers indicate *
1443 * spurious messages from other widets which were detected after the *
1444 * header was captured.. *
1446 ************************************************************************/
1448 typedef union ii_ixsm_u {
1449 shubreg_t ii_ixsm_regval;
1451 shubreg_t i_byte_en : 32;
1452 shubreg_t i_reserved : 1;
1453 shubreg_t i_tag : 3;
1454 shubreg_t i_alt_pactyp : 4;
1456 shubreg_t i_error : 1;
1457 shubreg_t i_vbpm : 1;
1458 shubreg_t i_gbr : 1;
1461 shubreg_t i_tnum : 5;
1462 shubreg_t i_pactyp : 4;
1463 shubreg_t i_sidn : 4;
1464 shubreg_t i_didn : 4;
1469 /************************************************************************
1471 * This register contains the sideband bits of a spurious read *
1472 * response received from Crosstalk. *
1474 ************************************************************************/
1476 typedef union ii_ixss_u {
1477 shubreg_t ii_ixss_regval;
1479 shubreg_t i_sideband : 8;
1480 shubreg_t i_rsvd : 55;
1481 shubreg_t i_valid : 1;
1486 /************************************************************************
1488 * This register enables software to access the II LLP's test port. *
1489 * Refer to the LLP 2.5 documentation for an explanation of the test *
1490 * port. Software can write to this register to program the values *
1491 * for the control fields (TestErrCapture, TestClear, TestFlit, *
1492 * TestMask and TestSeed). Similarly, software can read from this *
1493 * register to obtain the values of the test port's status outputs *
1494 * (TestCBerr, TestValid and TestData). *
1496 ************************************************************************/
1498 typedef union ii_ilct_u {
1499 shubreg_t ii_ilct_regval;
1501 shubreg_t i_test_seed : 20;
1502 shubreg_t i_test_mask : 8;
1503 shubreg_t i_test_data : 20;
1504 shubreg_t i_test_valid : 1;
1505 shubreg_t i_test_cberr : 1;
1506 shubreg_t i_test_flit : 3;
1507 shubreg_t i_test_clear : 1;
1508 shubreg_t i_test_err_capture : 1;
1509 shubreg_t i_rsvd : 9;
1514 /************************************************************************
1516 * If the II detects an illegal incoming Duplonet packet (request or *
1517 * reply) when VALID==0 in the IIEPH1 register, then it saves the *
1518 * contents of the packet's header flit in the IIEPH1 and IIEPH2 *
1519 * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, *
1520 * and assigns a value to the ERR_TYPE field which indicates the *
1521 * specific nature of the error. The II recognizes four different *
1522 * types of errors: short request packets (ERR_TYPE==2), short reply *
1523 * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long *
1524 * reply packets (ERR_TYPE==5). The encodings for these types of *
1525 * errors were chosen to be consistent with the same types of errors *
1526 * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in *
1527 * the LB unit). If the II detects an illegal incoming Duplonet *
1528 * packet when VALID==1 in the IIEPH1 register, then it merely sets *
1529 * the OVERRUN bit to indicate that a subsequent error has happened, *
1530 * and does nothing further. *
1532 ************************************************************************/
1534 typedef union ii_iieph1_u {
1535 shubreg_t ii_iieph1_regval;
1537 shubreg_t i_command : 7;
1538 shubreg_t i_rsvd_5 : 1;
1539 shubreg_t i_suppl : 14;
1540 shubreg_t i_rsvd_4 : 1;
1541 shubreg_t i_source : 14;
1542 shubreg_t i_rsvd_3 : 1;
1543 shubreg_t i_err_type : 4;
1544 shubreg_t i_rsvd_2 : 4;
1545 shubreg_t i_overrun : 1;
1546 shubreg_t i_rsvd_1 : 3;
1547 shubreg_t i_valid : 1;
1548 shubreg_t i_rsvd : 13;
1553 /************************************************************************
1555 * This register holds the Address field from the header flit of an *
1556 * incoming erroneous Duplonet packet, along with the tail bit which *
1557 * accompanied this header flit. This register is essentially an *
1558 * extension of IIEPH1. Two registers were necessary because the 64 *
1559 * bits available in only a single register were insufficient to *
1560 * capture the entire header flit of an erroneous packet. *
1562 ************************************************************************/
1564 typedef union ii_iieph2_u {
1565 shubreg_t ii_iieph2_regval;
1567 shubreg_t i_rsvd_0 : 3;
1568 shubreg_t i_address : 47;
1569 shubreg_t i_rsvd_1 : 10;
1570 shubreg_t i_tail : 1;
1571 shubreg_t i_rsvd : 3;
1576 /******************************/
1580 /************************************************************************
1582 * This register's value is a bit vector that guards access from SXBs *
1583 * to local registers within the II as well as to external Crosstalk *
1586 ************************************************************************/
1588 typedef union ii_islapr_u {
1589 shubreg_t ii_islapr_regval;
1591 shubreg_t i_region : 64;
1596 /************************************************************************
1598 * A write to this register of the 56-bit value "Pup+Bun" will cause *
1599 * the bit in the ISLAPR register corresponding to the region of the *
1600 * requestor to be set (access allowed). (
1602 ************************************************************************/
1604 typedef union ii_islapo_u {
1605 shubreg_t ii_islapo_regval;
1607 shubreg_t i_io_sbx_ovrride : 56;
1608 shubreg_t i_rsvd : 8;
1612 /************************************************************************
1614 * Determines how long the wrapper will wait aftr an interrupt is *
1615 * initially issued from the II before it times out the outstanding *
1616 * interrupt and drops it from the interrupt queue. *
1618 ************************************************************************/
1620 typedef union ii_iwi_u {
1621 shubreg_t ii_iwi_regval;
1623 shubreg_t i_prescale : 24;
1624 shubreg_t i_rsvd : 8;
1625 shubreg_t i_timeout : 8;
1626 shubreg_t i_rsvd1 : 8;
1627 shubreg_t i_intrpt_retry_period : 8;
1628 shubreg_t i_rsvd2 : 8;
1632 /************************************************************************
1634 * Log errors which have occurred in the II wrapper. The errors are *
1635 * cleared by writing to the IECLR register. *
1637 ************************************************************************/
1639 typedef union ii_iwel_u {
1640 shubreg_t ii_iwel_regval;
1642 shubreg_t i_intr_timed_out : 1;
1643 shubreg_t i_rsvd : 7;
1644 shubreg_t i_cam_overflow : 1;
1645 shubreg_t i_cam_read_miss : 1;
1646 shubreg_t i_rsvd1 : 2;
1647 shubreg_t i_ioq_rep_underflow : 1;
1648 shubreg_t i_ioq_req_underflow : 1;
1649 shubreg_t i_ioq_rep_overflow : 1;
1650 shubreg_t i_ioq_req_overflow : 1;
1651 shubreg_t i_iiq_rep_overflow : 1;
1652 shubreg_t i_iiq_req_overflow : 1;
1653 shubreg_t i_rsvd2 : 6;
1654 shubreg_t i_ii_xn_rep_cred_over_under: 1;
1655 shubreg_t i_ii_xn_req_cred_over_under: 1;
1656 shubreg_t i_rsvd3 : 6;
1657 shubreg_t i_ii_xn_invalid_cmd : 1;
1658 shubreg_t i_xn_ii_invalid_cmd : 1;
1659 shubreg_t i_rsvd4 : 30;
1663 /************************************************************************
1665 * Controls the II wrapper. *
1667 ************************************************************************/
1669 typedef union ii_iwc_u {
1670 shubreg_t ii_iwc_regval;
1672 shubreg_t i_dma_byte_swap : 1;
1673 shubreg_t i_rsvd : 3;
1674 shubreg_t i_cam_read_lines_reset : 1;
1675 shubreg_t i_rsvd1 : 3;
1676 shubreg_t i_ii_xn_cred_over_under_log: 1;
1677 shubreg_t i_rsvd2 : 19;
1678 shubreg_t i_xn_rep_iq_depth : 5;
1679 shubreg_t i_rsvd3 : 3;
1680 shubreg_t i_xn_req_iq_depth : 5;
1681 shubreg_t i_rsvd4 : 3;
1682 shubreg_t i_iiq_depth : 6;
1683 shubreg_t i_rsvd5 : 12;
1684 shubreg_t i_force_rep_cred : 1;
1685 shubreg_t i_force_req_cred : 1;
1689 /************************************************************************
1691 * Status in the II wrapper. *
1693 ************************************************************************/
1695 typedef union ii_iws_u {
1696 shubreg_t ii_iws_regval;
1698 shubreg_t i_xn_rep_iq_credits : 5;
1699 shubreg_t i_rsvd : 3;
1700 shubreg_t i_xn_req_iq_credits : 5;
1701 shubreg_t i_rsvd1 : 51;
1705 /************************************************************************
1707 * Masks errors in the IWEL register. *
1709 ************************************************************************/
1711 typedef union ii_iweim_u {
1712 shubreg_t ii_iweim_regval;
1714 shubreg_t i_intr_timed_out : 1;
1715 shubreg_t i_rsvd : 7;
1716 shubreg_t i_cam_overflow : 1;
1717 shubreg_t i_cam_read_miss : 1;
1718 shubreg_t i_rsvd1 : 2;
1719 shubreg_t i_ioq_rep_underflow : 1;
1720 shubreg_t i_ioq_req_underflow : 1;
1721 shubreg_t i_ioq_rep_overflow : 1;
1722 shubreg_t i_ioq_req_overflow : 1;
1723 shubreg_t i_iiq_rep_overflow : 1;
1724 shubreg_t i_iiq_req_overflow : 1;
1725 shubreg_t i_rsvd2 : 6;
1726 shubreg_t i_ii_xn_rep_cred_overflow : 1;
1727 shubreg_t i_ii_xn_req_cred_overflow : 1;
1728 shubreg_t i_rsvd3 : 6;
1729 shubreg_t i_ii_xn_invalid_cmd : 1;
1730 shubreg_t i_xn_ii_invalid_cmd : 1;
1731 shubreg_t i_rsvd4 : 30;
1736 /************************************************************************
1738 * A write to this register causes a particular field in the *
1739 * corresponding widget's PRB entry to be adjusted up or down by 1. *
1740 * This counter should be used when recovering from error and reset *
1741 * conditions. Note that software would be capable of causing *
1742 * inadvertent overflow or underflow of these counters. *
1744 ************************************************************************/
1746 typedef union ii_ipca_u {
1747 shubreg_t ii_ipca_regval;
1749 shubreg_t i_wid : 4;
1750 shubreg_t i_adjust : 1;
1751 shubreg_t i_rsvd_1 : 3;
1752 shubreg_t i_field : 2;
1753 shubreg_t i_rsvd : 54;
1758 /************************************************************************
1760 * There are 8 instances of this register. This register contains *
1761 * the information that the II has to remember once it has launched a *
1762 * PIO Read operation. The contents are used to form the correct *
1763 * Router Network packet and direct the Crosstalk reply to the *
1764 * appropriate processor. *
1766 ************************************************************************/
1769 typedef union ii_iprte0a_u {
1770 shubreg_t ii_iprte0a_regval;
1772 shubreg_t i_rsvd_1 : 54;
1773 shubreg_t i_widget : 4;
1774 shubreg_t i_to_cnt : 5;
1775 shubreg_t i_vld : 1;
1780 /************************************************************************
1782 * There are 8 instances of this register. This register contains *
1783 * the information that the II has to remember once it has launched a *
1784 * PIO Read operation. The contents are used to form the correct *
1785 * Router Network packet and direct the Crosstalk reply to the *
1786 * appropriate processor. *
1788 ************************************************************************/
1790 typedef union ii_iprte1a_u {
1791 shubreg_t ii_iprte1a_regval;
1793 shubreg_t i_rsvd_1 : 54;
1794 shubreg_t i_widget : 4;
1795 shubreg_t i_to_cnt : 5;
1796 shubreg_t i_vld : 1;
1801 /************************************************************************
1803 * There are 8 instances of this register. This register contains *
1804 * the information that the II has to remember once it has launched a *
1805 * PIO Read operation. The contents are used to form the correct *
1806 * Router Network packet and direct the Crosstalk reply to the *
1807 * appropriate processor. *
1809 ************************************************************************/
1811 typedef union ii_iprte2a_u {
1812 shubreg_t ii_iprte2a_regval;
1814 shubreg_t i_rsvd_1 : 54;
1815 shubreg_t i_widget : 4;
1816 shubreg_t i_to_cnt : 5;
1817 shubreg_t i_vld : 1;
1822 /************************************************************************
1824 * There are 8 instances of this register. This register contains *
1825 * the information that the II has to remember once it has launched a *
1826 * PIO Read operation. The contents are used to form the correct *
1827 * Router Network packet and direct the Crosstalk reply to the *
1828 * appropriate processor. *
1830 ************************************************************************/
1832 typedef union ii_iprte3a_u {
1833 shubreg_t ii_iprte3a_regval;
1835 shubreg_t i_rsvd_1 : 54;
1836 shubreg_t i_widget : 4;
1837 shubreg_t i_to_cnt : 5;
1838 shubreg_t i_vld : 1;
1843 /************************************************************************
1845 * There are 8 instances of this register. This register contains *
1846 * the information that the II has to remember once it has launched a *
1847 * PIO Read operation. The contents are used to form the correct *
1848 * Router Network packet and direct the Crosstalk reply to the *
1849 * appropriate processor. *
1851 ************************************************************************/
1853 typedef union ii_iprte4a_u {
1854 shubreg_t ii_iprte4a_regval;
1856 shubreg_t i_rsvd_1 : 54;
1857 shubreg_t i_widget : 4;
1858 shubreg_t i_to_cnt : 5;
1859 shubreg_t i_vld : 1;
1864 /************************************************************************
1866 * There are 8 instances of this register. This register contains *
1867 * the information that the II has to remember once it has launched a *
1868 * PIO Read operation. The contents are used to form the correct *
1869 * Router Network packet and direct the Crosstalk reply to the *
1870 * appropriate processor. *
1872 ************************************************************************/
1874 typedef union ii_iprte5a_u {
1875 shubreg_t ii_iprte5a_regval;
1877 shubreg_t i_rsvd_1 : 54;
1878 shubreg_t i_widget : 4;
1879 shubreg_t i_to_cnt : 5;
1880 shubreg_t i_vld : 1;
1885 /************************************************************************
1887 * There are 8 instances of this register. This register contains *
1888 * the information that the II has to remember once it has launched a *
1889 * PIO Read operation. The contents are used to form the correct *
1890 * Router Network packet and direct the Crosstalk reply to the *
1891 * appropriate processor. *
1893 ************************************************************************/
1895 typedef union ii_iprte6a_u {
1896 shubreg_t ii_iprte6a_regval;
1898 shubreg_t i_rsvd_1 : 54;
1899 shubreg_t i_widget : 4;
1900 shubreg_t i_to_cnt : 5;
1901 shubreg_t i_vld : 1;
1906 /************************************************************************
1908 * There are 8 instances of this register. This register contains *
1909 * the information that the II has to remember once it has launched a *
1910 * PIO Read operation. The contents are used to form the correct *
1911 * Router Network packet and direct the Crosstalk reply to the *
1912 * appropriate processor. *
1914 ************************************************************************/
1916 typedef union ii_iprte7a_u {
1917 shubreg_t ii_iprte7a_regval;
1919 shubreg_t i_rsvd_1 : 54;
1920 shubreg_t i_widget : 4;
1921 shubreg_t i_to_cnt : 5;
1922 shubreg_t i_vld : 1;
1928 /************************************************************************
1930 * There are 8 instances of this register. This register contains *
1931 * the information that the II has to remember once it has launched a *
1932 * PIO Read operation. The contents are used to form the correct *
1933 * Router Network packet and direct the Crosstalk reply to the *
1934 * appropriate processor. *
1936 ************************************************************************/
1939 typedef union ii_iprte0b_u {
1940 shubreg_t ii_iprte0b_regval;
1942 shubreg_t i_rsvd_1 : 3;
1943 shubreg_t i_address : 47;
1944 shubreg_t i_init : 3;
1945 shubreg_t i_source : 11;
1950 /************************************************************************
1952 * There are 8 instances of this register. This register contains *
1953 * the information that the II has to remember once it has launched a *
1954 * PIO Read operation. The contents are used to form the correct *
1955 * Router Network packet and direct the Crosstalk reply to the *
1956 * appropriate processor. *
1958 ************************************************************************/
1960 typedef union ii_iprte1b_u {
1961 shubreg_t ii_iprte1b_regval;
1963 shubreg_t i_rsvd_1 : 3;
1964 shubreg_t i_address : 47;
1965 shubreg_t i_init : 3;
1966 shubreg_t i_source : 11;
1971 /************************************************************************
1973 * There are 8 instances of this register. This register contains *
1974 * the information that the II has to remember once it has launched a *
1975 * PIO Read operation. The contents are used to form the correct *
1976 * Router Network packet and direct the Crosstalk reply to the *
1977 * appropriate processor. *
1979 ************************************************************************/
1981 typedef union ii_iprte2b_u {
1982 shubreg_t ii_iprte2b_regval;
1984 shubreg_t i_rsvd_1 : 3;
1985 shubreg_t i_address : 47;
1986 shubreg_t i_init : 3;
1987 shubreg_t i_source : 11;
1992 /************************************************************************
1994 * There are 8 instances of this register. This register contains *
1995 * the information that the II has to remember once it has launched a *
1996 * PIO Read operation. The contents are used to form the correct *
1997 * Router Network packet and direct the Crosstalk reply to the *
1998 * appropriate processor. *
2000 ************************************************************************/
2002 typedef union ii_iprte3b_u {
2003 shubreg_t ii_iprte3b_regval;
2005 shubreg_t i_rsvd_1 : 3;
2006 shubreg_t i_address : 47;
2007 shubreg_t i_init : 3;
2008 shubreg_t i_source : 11;
2013 /************************************************************************
2015 * There are 8 instances of this register. This register contains *
2016 * the information that the II has to remember once it has launched a *
2017 * PIO Read operation. The contents are used to form the correct *
2018 * Router Network packet and direct the Crosstalk reply to the *
2019 * appropriate processor. *
2021 ************************************************************************/
2023 typedef union ii_iprte4b_u {
2024 shubreg_t ii_iprte4b_regval;
2026 shubreg_t i_rsvd_1 : 3;
2027 shubreg_t i_address : 47;
2028 shubreg_t i_init : 3;
2029 shubreg_t i_source : 11;
2034 /************************************************************************
2036 * There are 8 instances of this register. This register contains *
2037 * the information that the II has to remember once it has launched a *
2038 * PIO Read operation. The contents are used to form the correct *
2039 * Router Network packet and direct the Crosstalk reply to the *
2040 * appropriate processor. *
2042 ************************************************************************/
2044 typedef union ii_iprte5b_u {
2045 shubreg_t ii_iprte5b_regval;
2047 shubreg_t i_rsvd_1 : 3;
2048 shubreg_t i_address : 47;
2049 shubreg_t i_init : 3;
2050 shubreg_t i_source : 11;
2055 /************************************************************************
2057 * There are 8 instances of this register. This register contains *
2058 * the information that the II has to remember once it has launched a *
2059 * PIO Read operation. The contents are used to form the correct *
2060 * Router Network packet and direct the Crosstalk reply to the *
2061 * appropriate processor. *
2063 ************************************************************************/
2065 typedef union ii_iprte6b_u {
2066 shubreg_t ii_iprte6b_regval;
2068 shubreg_t i_rsvd_1 : 3;
2069 shubreg_t i_address : 47;
2070 shubreg_t i_init : 3;
2071 shubreg_t i_source : 11;
2077 /************************************************************************
2079 * There are 8 instances of this register. This register contains *
2080 * the information that the II has to remember once it has launched a *
2081 * PIO Read operation. The contents are used to form the correct *
2082 * Router Network packet and direct the Crosstalk reply to the *
2083 * appropriate processor. *
2085 ************************************************************************/
2087 typedef union ii_iprte7b_u {
2088 shubreg_t ii_iprte7b_regval;
2090 shubreg_t i_rsvd_1 : 3;
2091 shubreg_t i_address : 47;
2092 shubreg_t i_init : 3;
2093 shubreg_t i_source : 11;
2098 /************************************************************************
2100 * Description: SHub II contains a feature which did not exist in *
2101 * the Hub which automatically cleans up after a Read Response *
2102 * timeout, including deallocation of the IPRTE and recovery of IBuf *
2103 * space. The inclusion of this register in SHub is for backward *
2105 * A write to this register causes an entry from the table of *
2106 * outstanding PIO Read Requests to be freed and returned to the *
2107 * stack of free entries. This register is used in handling the *
2108 * timeout errors that result in a PIO Reply never returning from *
2110 * Note that this register does not affect the contents of the IPRTE *
2111 * registers. The Valid bits in those registers have to be *
2112 * specifically turned off by software. *
2114 ************************************************************************/
2116 typedef union ii_ipdr_u {
2117 shubreg_t ii_ipdr_regval;
2120 shubreg_t i_rsvd_1 : 1;
2121 shubreg_t i_pnd : 1;
2122 shubreg_t i_init_rpcnt : 1;
2123 shubreg_t i_rsvd : 58;
2128 /************************************************************************
2130 * A write to this register causes a CRB entry to be returned to the *
2131 * queue of free CRBs. The entry should have previously been cleared *
2132 * (mark bit) via backdoor access to the pertinent CRB entry. This *
2133 * register is used in the last step of handling the errors that are *
2134 * captured and marked in CRB entries. Briefly: 1) first error for *
2135 * DMA write from a particular device, and first error for a *
2136 * particular BTE stream, lead to a marked CRB entry, and processor *
2137 * interrupt, 2) software reads the error information captured in the *
2138 * CRB entry, and presumably takes some corrective action, 3) *
2139 * software clears the mark bit, and finally 4) software writes to *
2140 * the ICDR register to return the CRB entry to the list of free CRB *
2143 ************************************************************************/
2145 typedef union ii_icdr_u {
2146 shubreg_t ii_icdr_regval;
2148 shubreg_t i_crb_num : 4;
2149 shubreg_t i_pnd : 1;
2150 shubreg_t i_rsvd : 59;
2155 /************************************************************************
2157 * This register provides debug access to two FIFOs inside of II. *
2158 * Both IOQ_MAX* fields of this register contain the instantaneous *
2159 * depth (in units of the number of available entries) of the *
2160 * associated IOQ FIFO. A read of this register will return the *
2161 * number of free entries on each FIFO at the time of the read. So *
2162 * when a FIFO is idle, the associated field contains the maximum *
2163 * depth of the FIFO. This register is writable for debug reasons *
2164 * and is intended to be written with the maximum desired FIFO depth *
2165 * while the FIFO is idle. Software must assure that II is idle when *
2166 * this register is written. If there are any active entries in any *
2167 * of these FIFOs when this register is written, the results are *
2170 ************************************************************************/
2172 typedef union ii_ifdr_u {
2173 shubreg_t ii_ifdr_regval;
2175 shubreg_t i_ioq_max_rq : 7;
2176 shubreg_t i_set_ioq_rq : 1;
2177 shubreg_t i_ioq_max_rp : 7;
2178 shubreg_t i_set_ioq_rp : 1;
2179 shubreg_t i_rsvd : 48;
2184 /************************************************************************
2186 * This register allows the II to become sluggish in removing *
2187 * messages from its inbound queue (IIQ). This will cause messages to *
2188 * back up in either virtual channel. Disabling the "molasses" mode *
2189 * subsequently allows the II to be tested under stress. In the *
2190 * sluggish ("Molasses") mode, the localized effects of congestion *
2191 * can be observed. *
2193 ************************************************************************/
2195 typedef union ii_iiap_u {
2196 shubreg_t ii_iiap_regval;
2198 shubreg_t i_rq_mls : 6;
2199 shubreg_t i_rsvd_1 : 2;
2200 shubreg_t i_rp_mls : 6;
2201 shubreg_t i_rsvd : 50;
2206 /************************************************************************
2208 * This register allows several parameters of CRB operation to be *
2209 * set. Note that writing to this register can have catastrophic side *
2210 * effects, if the CRB is not quiescent, i.e. if the CRB is *
2211 * processing protocol messages when the write occurs. *
2213 ************************************************************************/
2215 typedef union ii_icmr_u {
2216 shubreg_t ii_icmr_regval;
2218 shubreg_t i_sp_msg : 1;
2219 shubreg_t i_rd_hdr : 1;
2220 shubreg_t i_rsvd_4 : 2;
2221 shubreg_t i_c_cnt : 4;
2222 shubreg_t i_rsvd_3 : 4;
2223 shubreg_t i_clr_rqpd : 1;
2224 shubreg_t i_clr_rppd : 1;
2225 shubreg_t i_rsvd_2 : 2;
2226 shubreg_t i_fc_cnt : 4;
2227 shubreg_t i_crb_vld : 15;
2228 shubreg_t i_crb_mark : 15;
2229 shubreg_t i_rsvd_1 : 2;
2230 shubreg_t i_precise : 1;
2231 shubreg_t i_rsvd : 11;
2236 /************************************************************************
2238 * This register allows control of the table portion of the CRB *
2239 * logic via software. Control operations from this register have *
2240 * priority over all incoming Crosstalk or BTE requests. *
2242 ************************************************************************/
2244 typedef union ii_iccr_u {
2245 shubreg_t ii_iccr_regval;
2247 shubreg_t i_crb_num : 4;
2248 shubreg_t i_rsvd_1 : 4;
2249 shubreg_t i_cmd : 8;
2250 shubreg_t i_pending : 1;
2251 shubreg_t i_rsvd : 47;
2256 /************************************************************************
2258 * This register allows the maximum timeout value to be programmed. *
2260 ************************************************************************/
2262 typedef union ii_icto_u {
2263 shubreg_t ii_icto_regval;
2265 shubreg_t i_timeout : 8;
2266 shubreg_t i_rsvd : 56;
2271 /************************************************************************
2273 * This register allows the timeout prescalar to be programmed. An *
2274 * internal counter is associated with this register. When the *
2275 * internal counter reaches the value of the PRESCALE field, the *
2276 * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] *
2277 * field). The internal counter resets to zero, and then continues *
2280 ************************************************************************/
2282 typedef union ii_ictp_u {
2283 shubreg_t ii_ictp_regval;
2285 shubreg_t i_prescale : 24;
2286 shubreg_t i_rsvd : 40;
2291 /************************************************************************
2293 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2294 * used for Crosstalk operations (both cacheline and partial *
2295 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2296 * registers (_A to _E) are required to read and write each entry. *
2297 * The CRB Entry registers can be conceptualized as rows and columns *
2298 * (illustrated in the table above). Each row contains the 4 *
2299 * registers required for a single CRB Entry. The first doubleword *
2300 * (column) for each entry is labeled A, and the second doubleword *
2301 * (higher address) is labeled B, the third doubleword is labeled C, *
2302 * the fourth doubleword is labeled D and the fifth doubleword is *
2303 * labeled E. All CRB entries have their addresses on a quarter *
2304 * cacheline aligned boundary. *
2305 * Upon reset, only the following fields are initialized: valid *
2306 * (VLD), priority count, timeout, timeout valid, and context valid. *
2307 * All other bits should be cleared by software before use (after *
2308 * recovering any potential error state from before the reset). *
2309 * The following four tables summarize the format for the four *
2310 * registers that are used for each ICRB# Entry. *
2312 ************************************************************************/
2314 typedef union ii_icrb0_a_u {
2315 shubreg_t ii_icrb0_a_regval;
2317 shubreg_t ia_iow : 1;
2318 shubreg_t ia_vld : 1;
2319 shubreg_t ia_addr : 47;
2320 shubreg_t ia_tnum : 5;
2321 shubreg_t ia_sidn : 4;
2322 shubreg_t ia_rsvd : 6;
2327 /************************************************************************
2329 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2330 * used for Crosstalk operations (both cacheline and partial *
2331 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2332 * registers (_A to _E) are required to read and write each entry. *
2334 ************************************************************************/
2336 typedef union ii_icrb0_b_u {
2337 shubreg_t ii_icrb0_b_regval;
2339 shubreg_t ib_xt_err : 1;
2340 shubreg_t ib_mark : 1;
2341 shubreg_t ib_ln_uce : 1;
2342 shubreg_t ib_errcode : 3;
2343 shubreg_t ib_error : 1;
2344 shubreg_t ib_stall__bte_1 : 1;
2345 shubreg_t ib_stall__bte_0 : 1;
2346 shubreg_t ib_stall__intr : 1;
2347 shubreg_t ib_stall_ib : 1;
2348 shubreg_t ib_intvn : 1;
2349 shubreg_t ib_wb : 1;
2350 shubreg_t ib_hold : 1;
2351 shubreg_t ib_ack : 1;
2352 shubreg_t ib_resp : 1;
2353 shubreg_t ib_ack_cnt : 11;
2354 shubreg_t ib_rsvd : 7;
2355 shubreg_t ib_exc : 5;
2356 shubreg_t ib_init : 3;
2357 shubreg_t ib_imsg : 8;
2358 shubreg_t ib_imsgtype : 2;
2359 shubreg_t ib_use_old : 1;
2360 shubreg_t ib_rsvd_1 : 11;
2365 /************************************************************************
2367 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2368 * used for Crosstalk operations (both cacheline and partial *
2369 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2370 * registers (_A to _E) are required to read and write each entry. *
2372 ************************************************************************/
2374 typedef union ii_icrb0_c_u {
2375 shubreg_t ii_icrb0_c_regval;
2377 shubreg_t ic_source : 15;
2378 shubreg_t ic_size : 2;
2379 shubreg_t ic_ct : 1;
2380 shubreg_t ic_bte_num : 1;
2381 shubreg_t ic_gbr : 1;
2382 shubreg_t ic_resprqd : 1;
2383 shubreg_t ic_bo : 1;
2384 shubreg_t ic_suppl : 15;
2385 shubreg_t ic_rsvd : 27;
2390 /************************************************************************
2392 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2393 * used for Crosstalk operations (both cacheline and partial *
2394 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2395 * registers (_A to _E) are required to read and write each entry. *
2397 ************************************************************************/
2399 typedef union ii_icrb0_d_u {
2400 shubreg_t ii_icrb0_d_regval;
2402 shubreg_t id_pa_be : 43;
2403 shubreg_t id_bte_op : 1;
2404 shubreg_t id_pr_psc : 4;
2405 shubreg_t id_pr_cnt : 4;
2406 shubreg_t id_sleep : 1;
2407 shubreg_t id_rsvd : 11;
2412 /************************************************************************
2414 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2415 * used for Crosstalk operations (both cacheline and partial *
2416 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2417 * registers (_A to _E) are required to read and write each entry. *
2419 ************************************************************************/
2421 typedef union ii_icrb0_e_u {
2422 shubreg_t ii_icrb0_e_regval;
2424 shubreg_t ie_timeout : 8;
2425 shubreg_t ie_context : 15;
2426 shubreg_t ie_rsvd : 1;
2427 shubreg_t ie_tvld : 1;
2428 shubreg_t ie_cvld : 1;
2429 shubreg_t ie_rsvd_0 : 38;
2434 /************************************************************************
2436 * This register contains the lower 64 bits of the header of the *
2437 * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
2438 * register is set. *
2440 ************************************************************************/
2442 typedef union ii_icsml_u {
2443 shubreg_t ii_icsml_regval;
2445 shubreg_t i_tt_addr : 47;
2446 shubreg_t i_newsuppl_ex : 14;
2447 shubreg_t i_reserved : 2;
2448 shubreg_t i_overflow : 1;
2453 /************************************************************************
2455 * This register contains the middle 64 bits of the header of the *
2456 * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
2457 * register is set. *
2459 ************************************************************************/
2461 typedef union ii_icsmm_u {
2462 shubreg_t ii_icsmm_regval;
2464 shubreg_t i_tt_ack_cnt : 11;
2465 shubreg_t i_reserved : 53;
2470 /************************************************************************
2472 * This register contains the microscopic state, all the inputs to *
2473 * the protocol table, captured with the spurious message. Valid when *
2474 * the SP_MSG bit in the ICMR register is set. *
2476 ************************************************************************/
2478 typedef union ii_icsmh_u {
2479 shubreg_t ii_icsmh_regval;
2481 shubreg_t i_tt_vld : 1;
2482 shubreg_t i_xerr : 1;
2483 shubreg_t i_ft_cwact_o : 1;
2484 shubreg_t i_ft_wact_o : 1;
2485 shubreg_t i_ft_active_o : 1;
2486 shubreg_t i_sync : 1;
2487 shubreg_t i_mnusg : 1;
2488 shubreg_t i_mnusz : 1;
2489 shubreg_t i_plusz : 1;
2490 shubreg_t i_plusg : 1;
2491 shubreg_t i_tt_exc : 5;
2492 shubreg_t i_tt_wb : 1;
2493 shubreg_t i_tt_hold : 1;
2494 shubreg_t i_tt_ack : 1;
2495 shubreg_t i_tt_resp : 1;
2496 shubreg_t i_tt_intvn : 1;
2497 shubreg_t i_g_stall_bte1 : 1;
2498 shubreg_t i_g_stall_bte0 : 1;
2499 shubreg_t i_g_stall_il : 1;
2500 shubreg_t i_g_stall_ib : 1;
2501 shubreg_t i_tt_imsg : 8;
2502 shubreg_t i_tt_imsgtype : 2;
2503 shubreg_t i_tt_use_old : 1;
2504 shubreg_t i_tt_respreqd : 1;
2505 shubreg_t i_tt_bte_num : 1;
2506 shubreg_t i_cbn : 1;
2507 shubreg_t i_match : 1;
2508 shubreg_t i_rpcnt_lt_34 : 1;
2509 shubreg_t i_rpcnt_ge_34 : 1;
2510 shubreg_t i_rpcnt_lt_18 : 1;
2511 shubreg_t i_rpcnt_ge_18 : 1;
2512 shubreg_t i_rpcnt_lt_2 : 1;
2513 shubreg_t i_rpcnt_ge_2 : 1;
2514 shubreg_t i_rqcnt_lt_18 : 1;
2515 shubreg_t i_rqcnt_ge_18 : 1;
2516 shubreg_t i_rqcnt_lt_2 : 1;
2517 shubreg_t i_rqcnt_ge_2 : 1;
2518 shubreg_t i_tt_device : 7;
2519 shubreg_t i_tt_init : 3;
2520 shubreg_t i_reserved : 5;
2525 /************************************************************************
2527 * The Shub DEBUG unit provides a 3-bit selection signal to the *
2528 * II core and a 3-bit selection signal to the fsbclk domain in the II *
2531 ************************************************************************/
2533 typedef union ii_idbss_u {
2534 shubreg_t ii_idbss_regval;
2536 shubreg_t i_iioclk_core_submenu : 3;
2537 shubreg_t i_rsvd : 5;
2538 shubreg_t i_fsbclk_wrapper_submenu : 3;
2539 shubreg_t i_rsvd_1 : 5;
2540 shubreg_t i_iioclk_menu : 5;
2541 shubreg_t i_rsvd_2 : 43;
2546 /************************************************************************
2548 * Description: This register is used to set up the length for a *
2549 * transfer and then to monitor the progress of that transfer. This *
2550 * register needs to be initialized before a transfer is started. A *
2551 * legitimate write to this register will set the Busy bit, clear the *
2552 * Error bit, and initialize the length to the value desired. *
2553 * While the transfer is in progress, hardware will decrement the *
2554 * length field with each successful block that is copied. Once the *
2555 * transfer completes, hardware will clear the Busy bit. The length *
2556 * field will also contain the number of cache lines left to be *
2559 ************************************************************************/
2561 typedef union ii_ibls0_u {
2562 shubreg_t ii_ibls0_regval;
2564 shubreg_t i_length : 16;
2565 shubreg_t i_error : 1;
2566 shubreg_t i_rsvd_1 : 3;
2567 shubreg_t i_busy : 1;
2568 shubreg_t i_rsvd : 43;
2573 /************************************************************************
2575 * This register should be loaded before a transfer is started. The *
2576 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2577 * address as described in Section 1.3, Figure2 and Figure3. Since *
2578 * the bottom 7 bits of the address are always taken to be zero, BTE *
2579 * transfers are always cacheline-aligned. *
2581 ************************************************************************/
2583 typedef union ii_ibsa0_u {
2584 shubreg_t ii_ibsa0_regval;
2586 shubreg_t i_rsvd_1 : 7;
2587 shubreg_t i_addr : 42;
2588 shubreg_t i_rsvd : 15;
2593 /************************************************************************
2595 * This register should be loaded before a transfer is started. The *
2596 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2597 * address as described in Section 1.3, Figure2 and Figure3. Since *
2598 * the bottom 7 bits of the address are always taken to be zero, BTE *
2599 * transfers are always cacheline-aligned. *
2601 ************************************************************************/
2603 typedef union ii_ibda0_u {
2604 shubreg_t ii_ibda0_regval;
2606 shubreg_t i_rsvd_1 : 7;
2607 shubreg_t i_addr : 42;
2608 shubreg_t i_rsvd : 15;
2613 /************************************************************************
2615 * Writing to this register sets up the attributes of the transfer *
2616 * and initiates the transfer operation. Reading this register has *
2617 * the side effect of terminating any transfer in progress. Note: *
2618 * stopping a transfer midstream could have an adverse impact on the *
2619 * other BTE. If a BTE stream has to be stopped (due to error *
2620 * handling for example), both BTE streams should be stopped and *
2621 * their transfers discarded. *
2623 ************************************************************************/
2625 typedef union ii_ibct0_u {
2626 shubreg_t ii_ibct0_regval;
2628 shubreg_t i_zerofill : 1;
2629 shubreg_t i_rsvd_2 : 3;
2630 shubreg_t i_notify : 1;
2631 shubreg_t i_rsvd_1 : 3;
2632 shubreg_t i_poison : 1;
2633 shubreg_t i_rsvd : 55;
2638 /************************************************************************
2640 * This register contains the address to which the WINV is sent. *
2641 * This address has to be cache line aligned. *
2643 ************************************************************************/
2645 typedef union ii_ibna0_u {
2646 shubreg_t ii_ibna0_regval;
2648 shubreg_t i_rsvd_1 : 7;
2649 shubreg_t i_addr : 42;
2650 shubreg_t i_rsvd : 15;
2655 /************************************************************************
2657 * This register contains the programmable level as well as the node *
2658 * ID and PI unit of the processor to which the interrupt will be *
2661 ************************************************************************/
2663 typedef union ii_ibia0_u {
2664 shubreg_t ii_ibia0_regval;
2666 shubreg_t i_rsvd_2 : 1;
2667 shubreg_t i_node_id : 11;
2668 shubreg_t i_rsvd_1 : 4;
2669 shubreg_t i_level : 7;
2670 shubreg_t i_rsvd : 41;
2675 /************************************************************************
2677 * Description: This register is used to set up the length for a *
2678 * transfer and then to monitor the progress of that transfer. This *
2679 * register needs to be initialized before a transfer is started. A *
2680 * legitimate write to this register will set the Busy bit, clear the *
2681 * Error bit, and initialize the length to the value desired. *
2682 * While the transfer is in progress, hardware will decrement the *
2683 * length field with each successful block that is copied. Once the *
2684 * transfer completes, hardware will clear the Busy bit. The length *
2685 * field will also contain the number of cache lines left to be *
2688 ************************************************************************/
2690 typedef union ii_ibls1_u {
2691 shubreg_t ii_ibls1_regval;
2693 shubreg_t i_length : 16;
2694 shubreg_t i_error : 1;
2695 shubreg_t i_rsvd_1 : 3;
2696 shubreg_t i_busy : 1;
2697 shubreg_t i_rsvd : 43;
2702 /************************************************************************
2704 * This register should be loaded before a transfer is started. The *
2705 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2706 * address as described in Section 1.3, Figure2 and Figure3. Since *
2707 * the bottom 7 bits of the address are always taken to be zero, BTE *
2708 * transfers are always cacheline-aligned. *
2710 ************************************************************************/
2712 typedef union ii_ibsa1_u {
2713 shubreg_t ii_ibsa1_regval;
2715 shubreg_t i_rsvd_1 : 7;
2716 shubreg_t i_addr : 33;
2717 shubreg_t i_rsvd : 24;
2722 /************************************************************************
2724 * This register should be loaded before a transfer is started. The *
2725 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2726 * address as described in Section 1.3, Figure2 and Figure3. Since *
2727 * the bottom 7 bits of the address are always taken to be zero, BTE *
2728 * transfers are always cacheline-aligned. *
2730 ************************************************************************/
2732 typedef union ii_ibda1_u {
2733 shubreg_t ii_ibda1_regval;
2735 shubreg_t i_rsvd_1 : 7;
2736 shubreg_t i_addr : 33;
2737 shubreg_t i_rsvd : 24;
2742 /************************************************************************
2744 * Writing to this register sets up the attributes of the transfer *
2745 * and initiates the transfer operation. Reading this register has *
2746 * the side effect of terminating any transfer in progress. Note: *
2747 * stopping a transfer midstream could have an adverse impact on the *
2748 * other BTE. If a BTE stream has to be stopped (due to error *
2749 * handling for example), both BTE streams should be stopped and *
2750 * their transfers discarded. *
2752 ************************************************************************/
2754 typedef union ii_ibct1_u {
2755 shubreg_t ii_ibct1_regval;
2757 shubreg_t i_zerofill : 1;
2758 shubreg_t i_rsvd_2 : 3;
2759 shubreg_t i_notify : 1;
2760 shubreg_t i_rsvd_1 : 3;
2761 shubreg_t i_poison : 1;
2762 shubreg_t i_rsvd : 55;
2767 /************************************************************************
2769 * This register contains the address to which the WINV is sent. *
2770 * This address has to be cache line aligned. *
2772 ************************************************************************/
2774 typedef union ii_ibna1_u {
2775 shubreg_t ii_ibna1_regval;
2777 shubreg_t i_rsvd_1 : 7;
2778 shubreg_t i_addr : 33;
2779 shubreg_t i_rsvd : 24;
2784 /************************************************************************
2786 * This register contains the programmable level as well as the node *
2787 * ID and PI unit of the processor to which the interrupt will be *
2790 ************************************************************************/
2792 typedef union ii_ibia1_u {
2793 shubreg_t ii_ibia1_regval;
2795 shubreg_t i_pi_id : 1;
2796 shubreg_t i_node_id : 8;
2797 shubreg_t i_rsvd_1 : 7;
2798 shubreg_t i_level : 7;
2799 shubreg_t i_rsvd : 41;
2804 /************************************************************************
2806 * This register defines the resources that feed information into *
2807 * the two performance counters located in the IO Performance *
2808 * Profiling Register. There are 17 different quantities that can be *
2809 * measured. Given these 17 different options, the two performance *
2810 * counters have 15 of them in common; menu selections 0 through 0xE *
2811 * are identical for each performance counter. As for the other two *
2812 * options, one is available from one performance counter and the *
2813 * other is available from the other performance counter. Hence, the *
2814 * II supports all 17*16=272 possible combinations of quantities to *
2817 ************************************************************************/
2819 typedef union ii_ipcr_u {
2820 shubreg_t ii_ipcr_regval;
2822 shubreg_t i_ippr0_c : 4;
2823 shubreg_t i_ippr1_c : 4;
2824 shubreg_t i_icct : 8;
2825 shubreg_t i_rsvd : 48;
2830 /************************************************************************
2834 ************************************************************************/
2836 typedef union ii_ippr_u {
2837 shubreg_t ii_ippr_regval;
2839 shubreg_t i_ippr0 : 32;
2840 shubreg_t i_ippr1 : 32;
2845 /**************************************************************************
2847 * The following defines which were not formed into structures are *
2848 * probably indentical to another register, and the name of the *
2849 * register is provided against each of these registers. This *
2850 * information needs to be checked carefully *
2852 * IIO_ICRB1_A IIO_ICRB0_A *
2853 * IIO_ICRB1_B IIO_ICRB0_B *
2854 * IIO_ICRB1_C IIO_ICRB0_C *
2855 * IIO_ICRB1_D IIO_ICRB0_D *
2856 * IIO_ICRB1_E IIO_ICRB0_E *
2857 * IIO_ICRB2_A IIO_ICRB0_A *
2858 * IIO_ICRB2_B IIO_ICRB0_B *
2859 * IIO_ICRB2_C IIO_ICRB0_C *
2860 * IIO_ICRB2_D IIO_ICRB0_D *
2861 * IIO_ICRB2_E IIO_ICRB0_E *
2862 * IIO_ICRB3_A IIO_ICRB0_A *
2863 * IIO_ICRB3_B IIO_ICRB0_B *
2864 * IIO_ICRB3_C IIO_ICRB0_C *
2865 * IIO_ICRB3_D IIO_ICRB0_D *
2866 * IIO_ICRB3_E IIO_ICRB0_E *
2867 * IIO_ICRB4_A IIO_ICRB0_A *
2868 * IIO_ICRB4_B IIO_ICRB0_B *
2869 * IIO_ICRB4_C IIO_ICRB0_C *
2870 * IIO_ICRB4_D IIO_ICRB0_D *
2871 * IIO_ICRB4_E IIO_ICRB0_E *
2872 * IIO_ICRB5_A IIO_ICRB0_A *
2873 * IIO_ICRB5_B IIO_ICRB0_B *
2874 * IIO_ICRB5_C IIO_ICRB0_C *
2875 * IIO_ICRB5_D IIO_ICRB0_D *
2876 * IIO_ICRB5_E IIO_ICRB0_E *
2877 * IIO_ICRB6_A IIO_ICRB0_A *
2878 * IIO_ICRB6_B IIO_ICRB0_B *
2879 * IIO_ICRB6_C IIO_ICRB0_C *
2880 * IIO_ICRB6_D IIO_ICRB0_D *
2881 * IIO_ICRB6_E IIO_ICRB0_E *
2882 * IIO_ICRB7_A IIO_ICRB0_A *
2883 * IIO_ICRB7_B IIO_ICRB0_B *
2884 * IIO_ICRB7_C IIO_ICRB0_C *
2885 * IIO_ICRB7_D IIO_ICRB0_D *
2886 * IIO_ICRB7_E IIO_ICRB0_E *
2887 * IIO_ICRB8_A IIO_ICRB0_A *
2888 * IIO_ICRB8_B IIO_ICRB0_B *
2889 * IIO_ICRB8_C IIO_ICRB0_C *
2890 * IIO_ICRB8_D IIO_ICRB0_D *
2891 * IIO_ICRB8_E IIO_ICRB0_E *
2892 * IIO_ICRB9_A IIO_ICRB0_A *
2893 * IIO_ICRB9_B IIO_ICRB0_B *
2894 * IIO_ICRB9_C IIO_ICRB0_C *
2895 * IIO_ICRB9_D IIO_ICRB0_D *
2896 * IIO_ICRB9_E IIO_ICRB0_E *
2897 * IIO_ICRBA_A IIO_ICRB0_A *
2898 * IIO_ICRBA_B IIO_ICRB0_B *
2899 * IIO_ICRBA_C IIO_ICRB0_C *
2900 * IIO_ICRBA_D IIO_ICRB0_D *
2901 * IIO_ICRBA_E IIO_ICRB0_E *
2902 * IIO_ICRBB_A IIO_ICRB0_A *
2903 * IIO_ICRBB_B IIO_ICRB0_B *
2904 * IIO_ICRBB_C IIO_ICRB0_C *
2905 * IIO_ICRBB_D IIO_ICRB0_D *
2906 * IIO_ICRBB_E IIO_ICRB0_E *
2907 * IIO_ICRBC_A IIO_ICRB0_A *
2908 * IIO_ICRBC_B IIO_ICRB0_B *
2909 * IIO_ICRBC_C IIO_ICRB0_C *
2910 * IIO_ICRBC_D IIO_ICRB0_D *
2911 * IIO_ICRBC_E IIO_ICRB0_E *
2912 * IIO_ICRBD_A IIO_ICRB0_A *
2913 * IIO_ICRBD_B IIO_ICRB0_B *
2914 * IIO_ICRBD_C IIO_ICRB0_C *
2915 * IIO_ICRBD_D IIO_ICRB0_D *
2916 * IIO_ICRBD_E IIO_ICRB0_E *
2917 * IIO_ICRBE_A IIO_ICRB0_A *
2918 * IIO_ICRBE_B IIO_ICRB0_B *
2919 * IIO_ICRBE_C IIO_ICRB0_C *
2920 * IIO_ICRBE_D IIO_ICRB0_D *
2921 * IIO_ICRBE_E IIO_ICRB0_E *
2923 **************************************************************************/
2927 * Slightly friendlier names for some common registers.
2929 #define IIO_WIDGET IIO_WID /* Widget identification */
2930 #define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
2931 #define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
2932 #define IIO_PROTECT IIO_ILAPR /* IO interface protection */
2933 #define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
2934 #define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
2935 #define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
2936 #define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
2937 #define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
2938 #define IIO_LLP_LOG IIO_ILLR /* LLP log */
2939 #define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/
2940 #define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
2941 #define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
2942 #define IIO_IGFX_0 IIO_IGFX0
2943 #define IIO_IGFX_1 IIO_IGFX1
2944 #define IIO_IBCT_0 IIO_IBCT0
2945 #define IIO_IBCT_1 IIO_IBCT1
2946 #define IIO_IBLS_0 IIO_IBLS0
2947 #define IIO_IBLS_1 IIO_IBLS1
2948 #define IIO_IBSA_0 IIO_IBSA0
2949 #define IIO_IBSA_1 IIO_IBSA1
2950 #define IIO_IBDA_0 IIO_IBDA0
2951 #define IIO_IBDA_1 IIO_IBDA1
2952 #define IIO_IBNA_0 IIO_IBNA0
2953 #define IIO_IBNA_1 IIO_IBNA1
2954 #define IIO_IBIA_0 IIO_IBIA0
2955 #define IIO_IBIA_1 IIO_IBIA1
2956 #define IIO_IOPRB_0 IIO_IPRB0
2958 #define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x)))
2959 #define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x)))
2960 #define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
2961 #define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
2962 #define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
2964 #define IIO_NUM_IPRBS (9)
2966 #define IIO_LLP_CSR_IS_UP 0x00002000
2967 #define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
2968 #define IIO_LLP_CSR_LLP_STAT_SHFT 12
2970 #define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */
2971 #define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */
2973 /* key to IIO_PROTECT_OVRRD */
2974 #define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
2976 /* BTE register names */
2977 #define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
2978 #define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
2979 #define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
2980 #define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
2981 #define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
2982 #define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
2983 #define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
2984 #define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
2986 /* BTE register offsets from base */
2987 #define BTEOFF_STAT 0
2988 #define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
2989 #define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
2990 #define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
2991 #define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
2992 #define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
2995 /* names used in shub diags */
2996 #define IIO_BASE_BTE0 IIO_IBLS_0
2997 #define IIO_BASE_BTE1 IIO_IBLS_1
3000 * Macro which takes the widget number, and returns the
3001 * IO PRB address of that widget.
3002 * value _x is expected to be a widget number in the range
3005 #define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
3007 (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
3010 /* GFX Flow Control Node/Widget Register */
3011 #define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
3012 #define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
3013 #define IIO_IGFX_W_NUM_SHIFT 0
3014 #define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */
3015 #define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1)
3016 #define IIO_IGFX_PI_NUM_SHIFT 4
3017 #define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */
3018 #define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
3019 #define IIO_IGFX_N_NUM_SHIFT 5
3020 #define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
3021 #define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
3022 #define IIO_IGFX_P_NUM_SHIFT 16
3023 #define IIO_IGFX_INIT(widget, pi, node, cpu) (\
3024 (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
3025 (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \
3026 (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
3027 (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
3030 /* Scratch registers (all bits available) */
3031 #define IIO_SCRATCH_REG0 IIO_ISCR0
3032 #define IIO_SCRATCH_REG1 IIO_ISCR1
3033 #define IIO_SCRATCH_MASK 0xffffffffffffffffUL
3035 #define IIO_SCRATCH_BIT0_0 0x0000000000000001UL
3036 #define IIO_SCRATCH_BIT0_1 0x0000000000000002UL
3037 #define IIO_SCRATCH_BIT0_2 0x0000000000000004UL
3038 #define IIO_SCRATCH_BIT0_3 0x0000000000000008UL
3039 #define IIO_SCRATCH_BIT0_4 0x0000000000000010UL
3040 #define IIO_SCRATCH_BIT0_5 0x0000000000000020UL
3041 #define IIO_SCRATCH_BIT0_6 0x0000000000000040UL
3042 #define IIO_SCRATCH_BIT0_7 0x0000000000000080UL
3043 #define IIO_SCRATCH_BIT0_8 0x0000000000000100UL
3044 #define IIO_SCRATCH_BIT0_9 0x0000000000000200UL
3045 #define IIO_SCRATCH_BIT0_A 0x0000000000000400UL
3047 #define IIO_SCRATCH_BIT1_0 0x0000000000000001UL
3048 #define IIO_SCRATCH_BIT1_1 0x0000000000000002UL
3049 /* IO Translation Table Entries */
3050 #define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
3051 /* Hw manuals number them 1..7! */
3053 * IIO_IMEM Register fields.
3055 #define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */
3056 #define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */
3057 #define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */
3060 * As a permanent workaround for a bug in the PI side of the shub, we've
3061 * redefined big window 7 as small window 0.
3062 XXX does this still apply for SN1??
3064 #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
3067 * Use the top big window as a surrogate for the first small window
3069 #define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
3071 #define ILCSR_WARM_RESET 0x100
3074 * CRB manipulation macros
3075 * The CRB macros are slightly complicated, since there are up to
3076 * four registers associated with each CRB entry.
3078 #define IIO_NUM_CRBS 15 /* Number of CRBs */
3079 #define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
3080 #define IIO_ICRB_OFFSET 8
3081 #define IIO_ICRB_0 IIO_ICRB0_A
3082 #define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
3083 /* XXX - This is now tuneable:
3084 #define IIO_FIRST_PC_ENTRY 12
3087 #define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
3088 #define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
3089 #define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
3090 #define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
3091 #define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
3093 #define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7)
3096 * values for "ecode" field
3098 #define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
3099 #define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
3100 #define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
3101 * e.g. WINV to a Read only line. */
3102 #define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
3103 #define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
3104 #define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
3105 #define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
3106 #define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
3109 * Values for field imsgtype
3111 #define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
3112 #define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
3113 #define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */
3114 #define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
3117 * values for field initiator.
3119 #define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
3120 #define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
3121 #define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */
3122 #define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
3123 #define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
3126 * Number of credits Hub widget has while sending req/response to
3128 * Value of 3 is required by Xbow 1.1
3129 * We may be able to increase this to 4 with Xbow 1.2.
3131 #define HUBII_XBOW_CREDIT 3
3132 #define HUBII_XBOW_REV2_CREDIT 4
3135 * Number of credits that xtalk devices should use when communicating
3136 * with a SHub (depth of SHub's queue).
3138 #define HUB_CREDIT 4
3141 * Some IIO_PRB fields
3143 #define IIO_PRB_MULTI_ERR (1LL << 63)
3144 #define IIO_PRB_SPUR_RD (1LL << 51)
3145 #define IIO_PRB_SPUR_WR (1LL << 50)
3146 #define IIO_PRB_RD_TO (1LL << 49)
3147 #define IIO_PRB_ERROR (1LL << 48)
3149 /*************************************************************************
3151 Some of the IIO field masks and shifts are defined here.
3152 This is in order to maintain compatibility in SN0 and SN1 code
3154 **************************************************************************/
3157 * ICMR register fields
3158 * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
3162 #define IIO_ICMR_CRB_VLD_SHFT 20
3163 #define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
3165 #define IIO_ICMR_FC_CNT_SHFT 16
3166 #define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
3168 #define IIO_ICMR_C_CNT_SHFT 4
3169 #define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
3171 #define IIO_ICMR_PRECISE (1UL << 52)
3172 #define IIO_ICMR_CLR_RPPD (1UL << 13)
3173 #define IIO_ICMR_CLR_RQPD (1UL << 12)
3176 * IIO PIO Deallocation register field masks : (IIO_IPDR)
3177 XXX present but not needed in bedrock? See the manual.
3179 #define IIO_IPDR_PND (1 << 4)
3182 * IIO CRB deallocation register field masks: (IIO_ICDR)
3184 #define IIO_ICDR_PND (1 << 4)
3187 * IO BTE Length/Status (IIO_IBLS) register bit field definitions
3189 #define IBLS_BUSY (0x1UL << 20)
3190 #define IBLS_ERROR_SHFT 16
3191 #define IBLS_ERROR (0x1UL << IBLS_ERROR_SHFT)
3192 #define IBLS_LENGTH_MASK 0xffff
3195 * IO BTE Control/Terminate register (IBCT) register bit field definitions
3197 #define IBCT_POISON (0x1UL << 8)
3198 #define IBCT_NOTIFY (0x1UL << 4)
3199 #define IBCT_ZFIL_MODE (0x1UL << 0)
3202 * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
3204 #define IIEPH1_VALID (1UL << 44)
3205 #define IIEPH1_OVERRUN (1UL << 40)
3206 #define IIEPH1_ERR_TYPE_SHFT 32
3207 #define IIEPH1_ERR_TYPE_MASK 0xf
3208 #define IIEPH1_SOURCE_SHFT 20
3209 #define IIEPH1_SOURCE_MASK 11
3210 #define IIEPH1_SUPPL_SHFT 8
3211 #define IIEPH1_SUPPL_MASK 11
3212 #define IIEPH1_CMD_SHFT 0
3213 #define IIEPH1_CMD_MASK 7
3215 #define IIEPH2_TAIL (1UL << 40)
3216 #define IIEPH2_ADDRESS_SHFT 0
3217 #define IIEPH2_ADDRESS_MASK 38
3219 #define IIEPH1_ERR_SHORT_REQ 2
3220 #define IIEPH1_ERR_SHORT_REPLY 3
3221 #define IIEPH1_ERR_LONG_REQ 4
3222 #define IIEPH1_ERR_LONG_REPLY 5
3225 * IO Error Clear register bit field definitions
3227 #define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */
3228 #define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */
3229 #define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */
3230 #define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */
3231 #define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */
3232 #define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */
3233 #define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */
3234 #define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */
3235 #define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */
3236 #define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */
3237 #define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */
3238 #define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */
3239 #define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */
3240 #define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */
3241 #define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */
3244 * IIO CRB control register Fields: IIO_ICCR
3246 #define IIO_ICCR_PENDING (0x10000)
3247 #define IIO_ICCR_CMD_MASK (0xFF)
3248 #define IIO_ICCR_CMD_SHFT (7)
3249 #define IIO_ICCR_CMD_NOP (0x0) /* No Op */
3250 #define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */
3251 #define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */
3252 #define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory
3255 #define IIO_ICCR_CMD_FLUSH (0x800)
3259 * CRB Register description.
3261 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3262 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3263 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3264 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3265 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3267 * Many of the fields in CRB are status bits used by hardware
3268 * for implementation of the protocol. It's very dangerous to
3269 * mess around with the CRB registers.
3271 * It's OK to read the CRB registers and try to make sense out of the
3274 * Updating CRB requires all activities in Hub IIO to be quiesced.
3275 * otherwise, a write to CRB could corrupt other CRB entries.
3276 * CRBs are here only as a back door peek to shub IIO's status.
3277 * Quiescing implies no dmas no PIOs
3278 * either directly from the cpu or from sn0net.
3279 * this is not something that can be done easily. So, AVOID updating
3283 #ifndef __ASSEMBLY__
3286 * Easy access macros for CRBs, all 5 registers (A-E)
3288 typedef ii_icrb0_a_u_t icrba_t;
3289 #define a_sidn ii_icrb0_a_fld_s.ia_sidn
3290 #define a_tnum ii_icrb0_a_fld_s.ia_tnum
3291 #define a_addr ii_icrb0_a_fld_s.ia_addr
3292 #define a_valid ii_icrb0_a_fld_s.ia_vld
3293 #define a_iow ii_icrb0_a_fld_s.ia_iow
3294 #define a_regvalue ii_icrb0_a_regval
3296 typedef ii_icrb0_b_u_t icrbb_t;
3297 #define b_use_old ii_icrb0_b_fld_s.ib_use_old
3298 #define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype
3299 #define b_imsg ii_icrb0_b_fld_s.ib_imsg
3300 #define b_initiator ii_icrb0_b_fld_s.ib_init
3301 #define b_exc ii_icrb0_b_fld_s.ib_exc
3302 #define b_ackcnt ii_icrb0_b_fld_s.ib_ack_cnt
3303 #define b_resp ii_icrb0_b_fld_s.ib_resp
3304 #define b_ack ii_icrb0_b_fld_s.ib_ack
3305 #define b_hold ii_icrb0_b_fld_s.ib_hold
3306 #define b_wb ii_icrb0_b_fld_s.ib_wb
3307 #define b_intvn ii_icrb0_b_fld_s.ib_intvn
3308 #define b_stall_ib ii_icrb0_b_fld_s.ib_stall_ib
3309 #define b_stall_int ii_icrb0_b_fld_s.ib_stall__intr
3310 #define b_stall_bte_0 ii_icrb0_b_fld_s.ib_stall__bte_0
3311 #define b_stall_bte_1 ii_icrb0_b_fld_s.ib_stall__bte_1
3312 #define b_error ii_icrb0_b_fld_s.ib_error
3313 #define b_ecode ii_icrb0_b_fld_s.ib_errcode
3314 #define b_lnetuce ii_icrb0_b_fld_s.ib_ln_uce
3315 #define b_mark ii_icrb0_b_fld_s.ib_mark
3316 #define b_xerr ii_icrb0_b_fld_s.ib_xt_err
3317 #define b_regvalue ii_icrb0_b_regval
3319 typedef ii_icrb0_c_u_t icrbc_t;
3320 #define c_suppl ii_icrb0_c_fld_s.ic_suppl
3321 #define c_barrop ii_icrb0_c_fld_s.ic_bo
3322 #define c_doresp ii_icrb0_c_fld_s.ic_resprqd
3323 #define c_gbr ii_icrb0_c_fld_s.ic_gbr
3324 #define c_btenum ii_icrb0_c_fld_s.ic_bte_num
3325 #define c_cohtrans ii_icrb0_c_fld_s.ic_ct
3326 #define c_xtsize ii_icrb0_c_fld_s.ic_size
3327 #define c_source ii_icrb0_c_fld_s.ic_source
3328 #define c_regvalue ii_icrb0_c_regval
3331 typedef ii_icrb0_d_u_t icrbd_t;
3332 #define d_sleep ii_icrb0_d_fld_s.id_sleep
3333 #define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt
3334 #define d_pripsc ii_icrb0_d_fld_s.id_pr_psc
3335 #define d_bteop ii_icrb0_d_fld_s.id_bte_op
3336 #define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
3337 #define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
3338 #define d_regvalue ii_icrb0_d_regval
3340 typedef ii_icrb0_e_u_t icrbe_t;
3341 #define icrbe_ctxtvld ii_icrb0_e_fld_s.ie_cvld
3342 #define icrbe_toutvld ii_icrb0_e_fld_s.ie_tvld
3343 #define icrbe_context ii_icrb0_e_fld_s.ie_context
3344 #define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout
3345 #define e_regvalue ii_icrb0_e_regval
3347 #endif /* __ASSEMBLY__ */
3349 /* Number of widgets supported by shub */
3350 #define HUB_NUM_WIDGET 9
3351 #define HUB_WIDGET_ID_MIN 0x8
3352 #define HUB_WIDGET_ID_MAX 0xf
3354 #define HUB_WIDGET_PART_NUM 0xc120
3355 #define MAX_HUBS_PER_XBOW 2
3357 #ifndef __ASSEMBLY__
3358 /* A few more #defines for backwards compatibility */
3359 #define iprb_t ii_iprb0_u_t
3360 #define iprb_regval ii_iprb0_regval
3361 #define iprb_mult_err ii_iprb0_fld_s.i_mult_err
3362 #define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd
3363 #define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr
3364 #define iprb_rd_to ii_iprb0_fld_s.i_rd_to
3365 #define iprb_ovflow ii_iprb0_fld_s.i_of_cnt
3366 #define iprb_error ii_iprb0_fld_s.i_error
3367 #define iprb_ff ii_iprb0_fld_s.i_f
3368 #define iprb_mode ii_iprb0_fld_s.i_m
3369 #define iprb_bnakctr ii_iprb0_fld_s.i_nb
3370 #define iprb_anakctr ii_iprb0_fld_s.i_na
3371 #define iprb_xtalkctr ii_iprb0_fld_s.i_c
3374 #define LNK_STAT_WORKING 0x2 /* LLP is working */
3376 #define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
3377 #define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
3378 #define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */
3379 #define IIO_WSTAT_TXRETRY_SHFT (16)
3380 #define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
3381 IIO_WSTAT_TXRETRY_MASK)
3383 /* Number of II perf. counters we can multiplex at once */
3385 #define IO_PERF_SETS 32
3388 #include <asm/sn/dmamap.h>
3389 #include <asm/sn/driver.h>
3390 #include <asm/sn/xtalk/xtalk.h>
3392 /* Bit for the widget in inbound access register */
3393 #define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w))
3394 /* Bit for the widget in outbound access register */
3395 #define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w))
3397 /* NOTE: The following define assumes that we are going to get
3398 * widget numbers from 8 thru F and the device numbers within
3399 * widget from 0 thru 7.
3401 #define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))
3403 /* IO Interrupt Destination Register */
3404 #define IIO_IIDSR_SENT_SHIFT 28
3405 #define IIO_IIDSR_SENT_MASK 0x30000000
3406 #define IIO_IIDSR_ENB_SHIFT 24
3407 #define IIO_IIDSR_ENB_MASK 0x01000000
3408 #define IIO_IIDSR_NODE_SHIFT 9
3409 #define IIO_IIDSR_NODE_MASK 0x000ff700
3410 #define IIO_IIDSR_PI_ID_SHIFT 8
3411 #define IIO_IIDSR_PI_ID_MASK 0x00000100
3412 #define IIO_IIDSR_LVL_SHIFT 0
3413 #define IIO_IIDSR_LVL_MASK 0x000000ff
3415 /* Xtalk timeout threshhold register (IIO_IXTT) */
3416 #define IXTT_RRSP_TO_SHFT 55 /* read response timeout */
3417 #define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT)
3418 #define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */
3419 #define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
3420 #define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */
3421 #define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
3424 * The IO LLP control status register and widget control register
3427 typedef union hubii_wcr_u {
3428 uint64_t wcr_reg_value;
3430 uint64_t wcr_widget_id: 4, /* LLP crossbar credit */
3431 wcr_tag_mode: 1, /* Tag mode */
3432 wcr_rsvd1: 8, /* Reserved */
3433 wcr_xbar_crd: 3, /* LLP crossbar credit */
3434 wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */
3435 wcr_dir_con: 1, /* widget direct connect */
3436 wcr_e_thresh: 5, /* elasticity threshold */
3437 wcr_rsvd: 41; /* unused */
3441 #define iwcr_dir_con wcr_fields_s.wcr_dir_con
3443 /* The structures below are defined to extract and modify the ii
3444 performance registers */
3446 /* io_perf_sel allows the caller to specify what tests will be
3449 typedef union io_perf_sel {
3450 uint64_t perf_sel_reg;
3452 uint64_t perf_ippr0 : 4,
3459 /* io_perf_cnt is to extract the count from the shub registers. Due to
3460 hardware problems there is only one counter, not two. */
3462 typedef union io_perf_cnt {
3465 uint64_t perf_cnt : 20,
3472 typedef union iprte_a {
3475 shubreg_t i_rsvd_1 : 3;
3476 shubreg_t i_addr : 38;
3477 shubreg_t i_init : 3;
3478 shubreg_t i_source : 8;
3479 shubreg_t i_rsvd : 2;
3480 shubreg_t i_widget : 4;
3481 shubreg_t i_to_cnt : 5;
3482 shubreg_t i_vld : 1;
3487 /* PIO MANAGEMENT */
3488 typedef struct hub_piomap_s *hub_piomap_t;
3491 hub_piomap_alloc(vertex_hdl_t dev, /* set up mapping for this device */
3492 device_desc_t dev_desc, /* device descriptor */
3493 iopaddr_t xtalk_addr, /* map for this xtalk_addr range */
3495 size_t byte_count_max, /* maximum size of a mapping */
3496 unsigned flags); /* defined in sys/pio.h */
3498 extern void hub_piomap_free(hub_piomap_t hub_piomap);
3501 hub_piomap_addr(hub_piomap_t hub_piomap, /* mapping resources */
3502 iopaddr_t xtalk_addr, /* map for this xtalk addr */
3503 size_t byte_count); /* map this many bytes */
3506 hub_piomap_done(hub_piomap_t hub_piomap);
3509 hub_piotrans_addr( vertex_hdl_t dev, /* translate to this device */
3510 device_desc_t dev_desc, /* device descriptor */
3511 iopaddr_t xtalk_addr, /* Crosstalk address */
3512 size_t byte_count, /* map this many bytes */
3513 unsigned flags); /* (currently unused) */
3515 /* DMA MANAGEMENT */
3516 typedef struct hub_dmamap_s *hub_dmamap_t;
3519 hub_dmamap_alloc( vertex_hdl_t dev, /* set up mappings for dev */
3520 device_desc_t dev_desc, /* device descriptor */
3521 size_t byte_count_max, /* max size of a mapping */
3522 unsigned flags); /* defined in dma.h */
3525 hub_dmamap_free(hub_dmamap_t dmamap);
3528 hub_dmamap_addr( hub_dmamap_t dmamap, /* use mapping resources */
3529 paddr_t paddr, /* map for this address */
3530 size_t byte_count); /* map this many bytes */
3533 hub_dmamap_done( hub_dmamap_t dmamap); /* done w/ mapping resources */
3536 hub_dmatrans_addr( vertex_hdl_t dev, /* translate for this device */
3537 device_desc_t dev_desc, /* device descriptor */
3538 paddr_t paddr, /* system physical address */
3539 size_t byte_count, /* length */
3540 unsigned flags); /* defined in dma.h */
3543 hub_dmamap_drain( hub_dmamap_t map);
3546 hub_dmaaddr_drain( vertex_hdl_t vhdl,
3551 /* INTERRUPT MANAGEMENT */
3552 typedef struct hub_intr_s *hub_intr_t;
3555 hub_intr_alloc( vertex_hdl_t dev, /* which device */
3556 device_desc_t dev_desc, /* device descriptor */
3557 vertex_hdl_t owner_dev); /* owner of this interrupt */
3560 hub_intr_alloc_nothd(vertex_hdl_t dev, /* which device */
3561 device_desc_t dev_desc, /* device descriptor */
3562 vertex_hdl_t owner_dev); /* owner of this interrupt */
3565 hub_intr_free(hub_intr_t intr_hdl);
3568 hub_intr_connect( hub_intr_t intr_hdl, /* xtalk intr resource hndl */
3569 intr_func_t intr_func, /* xtalk intr handler */
3570 void *intr_arg, /* arg to intr handler */
3571 xtalk_intr_setfunc_t setfunc, /* func to set intr hw */
3572 void *setfunc_arg); /* arg to setfunc */
3575 hub_intr_disconnect(hub_intr_t intr_hdl);
3578 /* CONFIGURATION MANAGEMENT */
3581 hub_provider_startup(vertex_hdl_t hub);
3584 hub_provider_shutdown(vertex_hdl_t hub);
3586 #define HUB_PIO_CONVEYOR 0x1 /* PIO in conveyor belt mode */
3587 #define HUB_PIO_FIRE_N_FORGET 0x2 /* PIO in fire-and-forget mode */
3589 /* Flags that make sense to hub_widget_flags_set */
3590 #define HUB_WIDGET_FLAGS ( \
3591 HUB_PIO_CONVEYOR | \
3592 HUB_PIO_FIRE_N_FORGET \
3596 typedef int hub_widget_flags_t;
3598 /* Set the PIO mode for a widget. */
3599 extern int hub_widget_flags_set(nasid_t nasid,
3600 xwidgetnum_t widget_num,
3601 hub_widget_flags_t flags);
3603 /* Error Handling. */
3604 extern int hub_ioerror_handler(vertex_hdl_t, int, int, struct io_error_s *);
3605 extern int kl_ioerror_handler(cnodeid_t, cnodeid_t, cpuid_t,
3606 int, paddr_t, caddr_t, ioerror_mode_t);
3607 #endif /* _KERNEL */
3608 #endif /* _ASM_IA64_SN_SN2_SHUBIO_H */