1 #ifndef _ASM_IA64_SPINLOCK_H
2 #define _ASM_IA64_SPINLOCK_H
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
9 * This file is used for SMP configurations only.
12 #include <linux/compiler.h>
13 #include <linux/kernel.h>
15 #include <asm/atomic.h>
16 #include <asm/bitops.h>
17 #include <asm/intrinsics.h>
18 #include <asm/system.h>
21 volatile unsigned int lock;
24 #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
25 #define spin_lock_init(x) ((x)->lock = 0)
29 * Try to get the lock. If we fail to get the lock, make a non-standard call to
30 * ia64_spinlock_contention(). We do not use a normal call because that would force all
31 * callers of spin_lock() to be non-leaf routines. Instead, ia64_spinlock_contention() is
32 * carefully coded to touch only those registers that spin_lock() marks "clobbered".
35 #define IA64_SPINLOCK_CLOBBERS "ar.ccv", "ar.pfs", "p14", "p15", "r27", "r28", "r29", "r30", "b6", "memory"
38 _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags)
40 register volatile unsigned int *ptr asm ("r31") = &lock->lock;
42 #if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
43 # ifdef CONFIG_ITANIUM
44 /* don't use brl on Itanium... */
46 " mov ar.ccv = r0\n\t"
50 "cmpxchg4.acq r30 = [%1], r30, ar.ccv\n\t"
51 "movl r29 = ia64_spinlock_contention_pre3_4;;\n\t"
52 "cmp4.ne p14, p0 = r30, r0\n\t"
55 "(p14) br.cond.spnt.many b6"
56 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
59 " mov ar.ccv = r0\n\t"
63 "cmpxchg4.acq r30 = [%1], r30, ar.ccv;;\n\t"
64 "cmp4.ne p14, p0 = r30, r0\n\t"
66 "(p14) brl.cond.spnt.many ia64_spinlock_contention_pre3_4;;"
67 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
68 # endif /* CONFIG_MCKINLEY */
70 # ifdef CONFIG_ITANIUM
71 /* don't use brl on Itanium... */
72 /* mis-declare, so we get the entry-point, not it's function descriptor: */
73 asm volatile ("mov r30 = 1\n\t"
75 "mov ar.ccv = r0;;\n\t"
76 "cmpxchg4.acq r30 = [%0], r30, ar.ccv\n\t"
77 "movl r29 = ia64_spinlock_contention;;\n\t"
78 "cmp4.ne p14, p0 = r30, r0\n\t"
80 "(p14) br.call.spnt.many b6 = b6"
81 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
83 asm volatile ("mov r30 = 1\n\t"
85 "mov ar.ccv = r0;;\n\t"
86 "cmpxchg4.acq r30 = [%0], r30, ar.ccv;;\n\t"
87 "cmp4.ne p14, p0 = r30, r0\n\t"
88 "(p14) brl.call.spnt.many b6=ia64_spinlock_contention;;"
89 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
90 # endif /* CONFIG_MCKINLEY */
93 #define _raw_spin_lock(lock) _raw_spin_lock_flags(lock, 0)
94 #else /* !ASM_SUPPORTED */
95 #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
96 # define _raw_spin_lock(x) \
98 __u32 *ia64_spinlock_ptr = (__u32 *) (x); \
99 __u64 ia64_spinlock_val; \
100 ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
101 if (unlikely(ia64_spinlock_val)) { \
103 while (*ia64_spinlock_ptr) \
105 ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
106 } while (ia64_spinlock_val); \
109 #endif /* !ASM_SUPPORTED */
111 #define spin_is_locked(x) ((x)->lock != 0)
112 #define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
113 #define _raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
114 #define spin_unlock_wait(x) do { barrier(); } while ((x)->lock)
117 volatile unsigned int read_counter : 31;
118 volatile unsigned int write_lock : 1;
120 #define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 }
122 #define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
123 #define rwlock_is_locked(x) (*(volatile int *) (x) != 0)
125 #define _raw_read_lock(rw) \
127 rwlock_t *__read_lock_ptr = (rw); \
129 while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \
130 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
131 while (*(volatile int *)__read_lock_ptr < 0) \
136 #define _raw_read_unlock(rw) \
138 rwlock_t *__read_lock_ptr = (rw); \
139 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
143 #define _raw_write_lock(rw) \
145 __asm__ __volatile__ ( \
146 "mov ar.ccv = r0\n" \
147 "dep r29 = -1, r0, 31, 1;;\n" \
149 "ld4 r2 = [%0];;\n" \
150 "cmp4.eq p0,p7 = r0,r2\n" \
151 "(p7) br.cond.spnt.few 1b \n" \
152 "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n" \
153 "cmp4.eq p0,p7 = r0, r2\n" \
154 "(p7) br.cond.spnt.few 1b;;\n" \
155 :: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory"); \
158 #define _raw_write_trylock(rw) \
160 register long result; \
162 __asm__ __volatile__ ( \
163 "mov ar.ccv = r0\n" \
164 "dep r29 = -1, r0, 31, 1;;\n" \
165 "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \
166 : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \
170 #else /* !ASM_SUPPORTED */
172 #define _raw_write_lock(l) \
174 __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \
175 __u32 *ia64_write_lock_ptr = (__u32 *) (l); \
177 while (*ia64_write_lock_ptr) \
179 ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \
180 } while (ia64_val); \
183 #define _raw_write_trylock(rw) \
186 __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \
187 ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \
191 #endif /* !ASM_SUPPORTED */
193 #define _raw_write_unlock(x) \
195 smp_mb__before_clear_bit(); /* need barrier before releasing lock... */ \
196 clear_bit(31, (x)); \
199 #endif /* _ASM_IA64_SPINLOCK_H */