2 /* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
5 #ifndef _M68K_SHGLCORE_H
6 #define _M68K_SHGLCORE_H
8 #include <linux/config.h>
10 #ifdef CONFIG_SHGLCORE
12 #include <asm/MC68332.h>
14 #ifdef CONFIG_SHGLCORE_2MEG
16 #define SHGLCORE_ROM_BANK_0_ADDR 0x000000
17 #define SHGLCORE_ROM_BANK_1_ADDR 0x100000
18 #define SHGLCORE_RAM_BANK_0_ADDR 0x200000
19 #define SHGLCORE_RAM_BANK_1_ADDR 0x300000
20 #define SHGLCORE_FLASH_BANK_0_ADDR 0x400000
22 #define SHGLCORE_ROM_BANK_0_LENGTH 0x100000
23 #define SHGLCORE_ROM_BANK_1_LENGTH 0x100000
24 #define SHGLCORE_RAM_BANK_0_LENGTH 0x100000
25 #define SHGLCORE_RAM_BANK_1_LENGTH 0x100000
26 #define SHGLCORE_FLASH_BANK_0_LENGTH 0x80000
28 #define SHGLCORE_ACC_ADDR 0x600000
29 #define SHGLCORE_LANCE_ADDR 0x700000
33 #define SHGLCORE_ROM_BANK_0_ADDR 0x000000
34 #define SHGLCORE_RAM_BANK_0_ADDR 0x100000
35 #define SHGLCORE_FLASH_BANK_0_ADDR 0x300000
37 #define SHGLCORE_ROM_BANK_0_LENGTH 0x100000
38 #define SHGLCORE_RAM_BANK_0_LENGTH 0x100000
39 #define SHGLCORE_FLASH_BANK_0_LENGTH 0x80000
41 #define SHGLCORE_ACC_ADDR 0x400000
42 #define SHGLCORE_LANCE_ADDR 0x500000
46 #define MAX_DMA_ADDRESS SHGLCORE_RAM_BANK_0_ADDR + SHGLCORE_RAM_BANK_0_LENGTH
48 #define SHGLCORE_LATCH_ADDR (SHGLCORE_ACC_ADDR+0x100)
49 #define SHGLCORE_1865_0_ADDR (SHGLCORE_ACC_ADDR+0x600)
50 #define SHGLCORE_1865_1_ADDR (SHGLCORE_ACC_ADDR+0x700)
52 #define SHGLCORE_LATCH_BIT(x) BYTE_REF(SHGLCORE_LATCH_ADDR+x)
54 #define SHGLCORE_LATCH_STATUS_LED 0
55 #define SHGLCORE_LATCH_ERROR_LED 1
56 #define SHGLCORE_LATCH_ALARM_LED 2
58 #define SHGLCORE_LATCH_1865 4
60 #define SHGLCORE_LATCH_RELAY_1 6
61 #define SHGLCORE_LATCH_RELAY_2 7
65 #endif /* _M68K_SHGLCORE_H */