2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 2004 Ralf Baechle
11 #include <linux/config.h>
20 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
21 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
22 * for data translations should not occur for 3 cpu cycles.
24 #ifdef CONFIG_CPU_RM9000
26 #define mtc0_tlbw_hazard \
29 _ssnop; _ssnop; _ssnop; _ssnop; \
32 #define tlbw_eret_hazard \
35 _ssnop; _ssnop; _ssnop; _ssnop; \
41 * The taken branch will result in a two cycle penalty for the two killed
42 * instructions on R4000 / R4400. Other processors only have a single cycle
43 * hazard so this is nice trick to have an optimal code for a range of
46 #define mtc0_tlbw_hazard \
48 #define tlbw_eret_hazard
53 * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
54 * It is a MIPS32R2 processor so ehb will clear the hazard.
57 #ifdef CONFIG_CPU_MIPSR2
59 * Use a macro for ehb unless explicit support for MIPSR2 is enabled
65 #define irq_enable_hazard \
66 ehb # irq_enable_hazard
68 #define irq_disable_hazard \
69 ehb # irq_disable_hazard
73 #define irq_enable_hazard
74 #define irq_disable_hazard
78 #else /* __ASSEMBLY__ */
81 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
82 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
83 * for data translations should not occur for 3 cpu cycles.
85 #ifdef CONFIG_CPU_RM9000
87 #define mtc0_tlbw_hazard() \
88 __asm__ __volatile__( \
90 "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
93 #define tlbw_use_hazard() \
94 __asm__ __volatile__( \
96 "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
101 * Overkill warning ...
103 #define mtc0_tlbw_hazard() \
104 __asm__ __volatile__( \
105 ".set noreorder\n\t" \
106 "nop; nop; nop; nop; nop; nop;\n\t" \
109 #define tlbw_use_hazard() \
110 __asm__ __volatile__( \
111 ".set noreorder\n\t" \
112 "nop; nop; nop; nop; nop; nop;\n\t" \
119 * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
120 * It is a MIPS32R2 processor so ehb will clear the hazard.
123 #ifdef CONFIG_CPU_MIPSR2
125 * Use a macro for ehb unless explicit support for MIPSR2 is enabled
129 " sll $0, $0, 3 \n\t"
132 " .macro\tirq_enable_hazard \n\t"
136 " .macro\tirq_disable_hazard \n\t"
140 #define irq_enable_hazard() \
141 __asm__ __volatile__( \
142 "ehb\t\t\t\t# irq_enable_hazard")
144 #define irq_disable_hazard() \
145 __asm__ __volatile__( \
146 "ehb\t\t\t\t# irq_disable_hazard")
148 #elif defined(CONFIG_CPU_R10000)
151 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
155 " .macro\tirq_enable_hazard \n\t"
158 " .macro\tirq_disable_hazard \n\t"
161 #define irq_enable_hazard() do { } while (0)
162 #define irq_disable_hazard() do { } while (0)
167 * Default for classic MIPS processors. Assume worst case hazards but don't
168 * care about the irq_enable_hazard - sooner or later the hardware will
169 * enable it and we don't care when exactly.
173 " .macro _ssnop \n\t"
174 " sll $0, $2, 1 \n\t"
178 " # There is a hazard but we do not care \n\t"
180 " .macro\tirq_enable_hazard \n\t"
183 " .macro\tirq_disable_hazard \n\t"
184 " _ssnop; _ssnop; _ssnop \n\t"
187 #define irq_enable_hazard() do { } while (0)
188 #define irq_disable_hazard() \
189 __asm__ __volatile__( \
190 "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
194 #endif /* __ASSEMBLY__ */
196 #endif /* _ASM_HAZARDS_H */