2 * Definitions for the SGI O2 Crime chip.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2000 Harald Koerfgen
11 #ifndef __ASM_CRIME_H__
12 #define __ASM_CRIME_H__
14 #include <asm/addrspace.h>
20 #define CRIME_BASE 0x14000000 /* physical */
22 extern void *sgi_crime;
24 static inline uint64_t crime_read(unsigned long offset)
26 return readq(sgi_crime + offset);
28 static inline void crime_write(uint64_t val, unsigned long offset)
30 writeq(val, sgi_crime + offset);
34 #define BIT(x) (1UL << (x))
36 /* All CRIME registers are 64 bits */
37 #define CRIME_ID 0x000
39 #define CRIME_ID_MASK 0xff
40 #define CRIME_ID_IDBITS 0xf0
41 #define CRIME_ID_IDVALUE 0xa0
42 #define CRIME_ID_REV 0x0f
44 #define CRIME_REV_PETTY 0x00
45 #define CRIME_REV_11 0x11
46 #define CRIME_REV_13 0x13
47 #define CRIME_REV_14 0x14
49 #define CRIME_CONTROL 0x008
50 #define CRIME_CONTROL_MASK 0x3fff
52 /* CRIME_CONTROL register bits */
53 #define CRIME_CONTROL_TRITON_SYSADC 0x2000
54 #define CRIME_CONTROL_CRIME_SYSADC 0x1000
55 #define CRIME_CONTROL_HARD_RESET 0x0800
56 #define CRIME_CONTROL_SOFT_RESET 0x0400
57 #define CRIME_CONTROL_DOG_ENA 0x0200
58 #define CRIME_CONTROL_ENDIANESS 0x0100
60 #define CRIME_CONTROL_ENDIAN_BIG 0x0100
61 #define CRIME_CONTROL_ENDIAN_LITTLE 0x0000
63 #define CRIME_CONTROL_CQUEUE_HWM 0x000f
64 #define CRIME_CONTROL_CQUEUE_SHFT 0
65 #define CRIME_CONTROL_WBUF_HWM 0x00f0
66 #define CRIME_CONTROL_WBUF_SHFT 8
68 #define CRIME_INT_STAT 0x010
69 #define CRIME_INT_MASK 0x018
70 #define CRIME_SOFT_INT 0x020
71 #define CRIME_HARD_INT 0x028
73 /* Bits in CRIME_INT_XXX and CRIME_HARD_INT */
74 #define MACE_VID_IN1_INT BIT (0)
75 #define MACE_VID_IN2_INT BIT (1)
76 #define MACE_VID_OUT_INT BIT (2)
77 #define MACE_ETHERNET_INT BIT (3)
78 #define MACE_SUPERIO_INT BIT (4)
79 #define MACE_MISC_INT BIT (5)
80 #define MACE_AUDIO_INT BIT (6)
81 #define MACE_PCI_BRIDGE_INT BIT (7)
82 #define MACEPCI_SCSI0_INT BIT (8)
83 #define MACEPCI_SCSI1_INT BIT (9)
84 #define MACEPCI_SLOT0_INT BIT (10)
85 #define MACEPCI_SLOT1_INT BIT (11)
86 #define MACEPCI_SLOT2_INT BIT (12)
87 #define MACEPCI_SHARED0_INT BIT (13)
88 #define MACEPCI_SHARED1_INT BIT (14)
89 #define MACEPCI_SHARED2_INT BIT (15)
90 #define CRIME_GBE0_INT BIT (16)
91 #define CRIME_GBE1_INT BIT (17)
92 #define CRIME_GBE2_INT BIT (18)
93 #define CRIME_GBE3_INT BIT (19)
94 #define CRIME_CPUERR_INT BIT (20)
95 #define CRIME_MEMERR_INT BIT (21)
96 #define CRIME_RE_EMPTY_E_INT BIT (22)
97 #define CRIME_RE_FULL_E_INT BIT (23)
98 #define CRIME_RE_IDLE_E_INT BIT (24)
99 #define CRIME_RE_EMPTY_L_INT BIT (25)
100 #define CRIME_RE_FULL_L_INT BIT (26)
101 #define CRIME_RE_IDLE_L_INT BIT (27)
102 #define CRIME_SOFT0_INT BIT (28)
103 #define CRIME_SOFT1_INT BIT (29)
104 #define CRIME_SOFT2_INT BIT (30)
105 #define CRIME_SYSCORERR_INT CRIME_SOFT2_INT
106 #define CRIME_VICE_INT BIT (31)
108 /* Masks for deciding who handles the interrupt */
109 #define CRIME_MACE_INT_MASK 0x8f
110 #define CRIME_MACEISA_INT_MASK 0x70
111 #define CRIME_MACEPCI_INT_MASK 0xff00
112 #define CRIME_CRIME_INT_MASK 0xffff0000
114 #define CRIME_DOG 0x030
115 #define CRIME_DOG_MASK 0x001fffff
117 /* CRIME_DOG register bits */
118 #define CRIME_DOG_POWER_ON_RESET 0x00010000
119 #define CRIME_DOG_WARM_RESET 0x00080000
120 #define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
121 #define CRIME_DOG_VALUE 0x00007fff
123 #define CRIME_TIMER 0x038
124 #define CRIME_TIMER_MASK 0x0000ffffffffffff
126 #define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */
127 #define CRIME_NS_PER_TICK 15 /* for delay_calibrate */
129 #define CRIME_CPU_ERROR_ADDR 0x040
130 #define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff
132 #define CRIME_CPU_ERROR_STAT 0x048
133 /* REV_PETTY only! */
134 #define CRIME_CPU_ERROR_ENA 0x050
137 * bit definitions for CRIME/VICE error status and enable registers
139 #define CRIME_CPU_ERROR_MASK 0x7 /* cpu error stat is 3 bits */
140 #define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4
141 #define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2
142 #define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1
145 * these are the definitions for the error status/enable register in
146 * petty crime. Note that the enable register does not exist in crime
149 #define CRIME_CPU_ERROR_MASK_REV0 0x3ff /* cpu error stat is 9 bits */
150 #define CRIME_CPU_ERROR_CPU_INV_ADDR_RD 0x200
151 #define CRIME_CPU_ERROR_VICE_II 0x100
152 #define CRIME_CPU_ERROR_VICE_SYSAD 0x80
153 #define CRIME_CPU_ERROR_VICE_SYSCMD 0x40
154 #define CRIME_CPU_ERROR_VICE_INV_ADDR 0x20
155 #define CRIME_CPU_ERROR_CPU_II 0x10
156 #define CRIME_CPU_ERROR_CPU_SYSAD 0x8
157 #define CRIME_CPU_ERROR_CPU_SYSCMD 0x4
158 #define CRIME_CPU_ERROR_CPU_INV_ADDR_WR 0x2
159 #define CRIME_CPU_ERROR_CPU_INV_REG_ADDR 0x1
161 #define CRIME_VICE_ERROR_ADDR 0x058
162 #define CRIME_VICE_ERROR_ADDR_MASK 0x3fffffff
164 #define CRIME_MEM_CONTROL 0x200
165 #define CRIME_MEM_CONTROL_MASK 0x3 /* 25 cent register */
166 #define CRIME_MEM_CONTROL_ECC_ENA 0x1
167 #define CRIME_MEM_CONTROL_USE_ECC_REPL 0x2
170 * macros for CRIME memory bank control registers.
172 #define CRIME_MEM_BANK_CONTROL(__bank) (0x208 + ((__bank) << 3))
173 #define CRIME_MEM_BANK_CONTROL_MASK 0x11f /* 9 bits 7:5 reserved */
174 #define CRIME_MEM_BANK_CONTROL_ADDR 0x01f
175 #define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100
176 #define CRIME_MAXBANKS 8
178 #define CRIME_MEM_REFRESH_COUNTER 0x248
179 #define CRIME_MEM_REFRESH_COUNTER_MASK 0x7ff
182 * CRIME Memory error status register bit definitions
184 #define CRIME_MEM_ERROR_STAT 0x250
185 #define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */
186 #define CRIME_MEM_ERROR_MACE_ID 0x0000007f
187 #define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080
188 #define CRIME_MEM_ERROR_RE_ID 0x00007f00
189 #define CRIME_MEM_ERROR_RE_ACCESS 0x00008000
190 #define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000
191 #define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000
192 #define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000
193 #define CRIME_MEM_ERROR_RESERVED 0x00080000
194 #define CRIME_MEM_ERROR_SOFT_ERR 0x00100000
195 #define CRIME_MEM_ERROR_HARD_ERR 0x00200000
196 #define CRIME_MEM_ERROR_MULTIPLE 0x00400000
197 #define CRIME_MEM_ERROR_ECC 0x01800000
198 #define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000
199 #define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000
200 #define CRIME_MEM_ERROR_INV 0x0e000000
201 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
202 #define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
203 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
205 #define CRIME_MEM_ERROR_ADDR 0x258
206 #define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff
208 #define CRIME_MEM_ERROR_ECC_SYN 0x260
209 #define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff
211 #define CRIME_MEM_ERROR_ECC_CHK 0x268
212 #define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff
214 #define CRIME_MEM_ERROR_ECC_REPL 0x270
215 #define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff
217 #endif /* __ASM_CRIME_H__ */