2 * AMD Alchemy DB1x00 Reference Boards
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc.
6 * ppopov@mvista.com or source@mvista.com
8 * ########################################################################
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * ########################################################################
27 #ifndef __ASM_DB1X00_H
28 #define __ASM_DB1X00_H
30 #ifdef CONFIG_MIPS_DB1550
31 #define BCSR_KSEG1_ADDR 0xAF000000
32 #define NAND_PHYS_ADDR 0x20000000
34 #define BCSR_KSEG1_ADDR 0xAE000000
38 * Overlay data structure of the Db1x00 board registers.
39 * Registers located at physical 0E0000xx, KSEG1 0xAE0000xx
41 typedef volatile struct
43 /*00*/ unsigned short whoami;
44 unsigned short reserved0;
45 /*04*/ unsigned short status;
46 unsigned short reserved1;
47 /*08*/ unsigned short switches;
48 unsigned short reserved2;
49 /*0C*/ unsigned short resets;
50 unsigned short reserved3;
51 /*10*/ unsigned short pcmcia;
52 unsigned short reserved4;
53 /*14*/ unsigned short specific;
54 unsigned short reserved5;
55 /*18*/ unsigned short leds;
56 unsigned short reserved6;
57 /*1C*/ unsigned short swreset;
58 unsigned short reserved7;
64 * Register/mask bit definitions for the BCSRs
66 #define BCSR_WHOAMI_DCID 0x000F
67 #define BCSR_WHOAMI_CPLD 0x00F0
68 #define BCSR_WHOAMI_BOARD 0x0F00
70 #define BCSR_STATUS_PC0VS 0x0003
71 #define BCSR_STATUS_PC1VS 0x000C
72 #define BCSR_STATUS_PC0FI 0x0010
73 #define BCSR_STATUS_PC1FI 0x0020
74 #define BCSR_STATUS_FLASHBUSY 0x0100
75 #define BCSR_STATUS_ROMBUSY 0x0400
76 #define BCSR_STATUS_SWAPBOOT 0x2000
77 #define BCSR_STATUS_FLASHDEN 0xC000
79 #define BCSR_SWITCHES_DIP 0x00FF
80 #define BCSR_SWITCHES_DIP_1 0x0080
81 #define BCSR_SWITCHES_DIP_2 0x0040
82 #define BCSR_SWITCHES_DIP_3 0x0020
83 #define BCSR_SWITCHES_DIP_4 0x0010
84 #define BCSR_SWITCHES_DIP_5 0x0008
85 #define BCSR_SWITCHES_DIP_6 0x0004
86 #define BCSR_SWITCHES_DIP_7 0x0002
87 #define BCSR_SWITCHES_DIP_8 0x0001
88 #define BCSR_SWITCHES_ROTARY 0x0F00
90 #define BCSR_RESETS_PHY0 0x0001
91 #define BCSR_RESETS_PHY1 0x0002
92 #define BCSR_RESETS_DC 0x0004
93 #define BCSR_RESETS_FIR_SEL 0x2000
94 #define BCSR_RESETS_IRDA_MODE_MASK 0xC000
95 #define BCSR_RESETS_IRDA_MODE_FULL 0x0000
96 #define BCSR_RESETS_IRDA_MODE_OFF 0x4000
97 #define BCSR_RESETS_IRDA_MODE_2_3 0x8000
98 #define BCSR_RESETS_IRDA_MODE_1_3 0xC000
100 #define BCSR_PCMCIA_PC0VPP 0x0003
101 #define BCSR_PCMCIA_PC0VCC 0x000C
102 #define BCSR_PCMCIA_PC0DRVEN 0x0010
103 #define BCSR_PCMCIA_PC0RST 0x0080
104 #define BCSR_PCMCIA_PC1VPP 0x0300
105 #define BCSR_PCMCIA_PC1VCC 0x0C00
106 #define BCSR_PCMCIA_PC1DRVEN 0x1000
107 #define BCSR_PCMCIA_PC1RST 0x8000
109 #define BCSR_BOARD_PCIM66EN 0x0001
110 #define BCSR_BOARD_SD0_PWR 0x0040
111 #define BCSR_BOARD_SD1_PWR 0x0080
112 #define BCSR_BOARD_PCIM33 0x0100
113 #define BCSR_BOARD_GPIO200RST 0x0400
114 #define BCSR_BOARD_PCICFG 0x1000
115 #define BCSR_BOARD_SD0_WP 0x4000
116 #define BCSR_BOARD_SD1_WP 0x8000
118 #define BCSR_LEDS_DECIMALS 0x0003
119 #define BCSR_LEDS_LED0 0x0100
120 #define BCSR_LEDS_LED1 0x0200
121 #define BCSR_LEDS_LED2 0x0400
122 #define BCSR_LEDS_LED3 0x0800
124 #define BCSR_SWRESET_RESET 0x0080
126 /* PCMCIA Db1x00 specific defines */
127 #define PCMCIA_MAX_SOCK 1
128 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
131 #define SET_VCC_VPP(VCC, VPP, SLOT)\
132 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
134 /* SD controller macros */
138 #define mmc_card_inserted(_n_, _res_) \
140 BCSR * const bcsr = (BCSR *)0xAE000000; \
141 unsigned long mmc_wp, board_specific; \
143 mmc_wp = BCSR_BOARD_SD1_WP; \
145 mmc_wp = BCSR_BOARD_SD0_WP; \
147 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
148 if (!(board_specific & mmc_wp)) {/* low means card present */ \
149 *(int *)(_res_) = 1; \
151 *(int *)(_res_) = 0; \
156 * Apply power to card slot(s).
158 #define mmc_power_on(_n_) \
160 BCSR * const bcsr = (BCSR *)0xAE000000; \
161 unsigned long mmc_pwr, mmc_wp, board_specific; \
163 mmc_pwr = BCSR_BOARD_SD1_PWR; \
164 mmc_wp = BCSR_BOARD_SD1_WP; \
166 mmc_pwr = BCSR_BOARD_SD0_PWR; \
167 mmc_wp = BCSR_BOARD_SD0_WP; \
169 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
170 if (!(board_specific & mmc_wp)) {/* low means card present */ \
171 board_specific |= mmc_pwr; \
172 au_writel(board_specific, (int)(&bcsr->specific)); \
179 /* Timing values as described in databook, * ns value stripped of
181 * These defines are here rather than an SOC1550 generic file because
182 * the parts chosen on another board may be different and may require
185 #define NAND_T_H (18 >> 2)
186 #define NAND_T_PUL (30 >> 2)
187 #define NAND_T_SU (30 >> 2)
188 #define NAND_T_WH (30 >> 2)
190 /* Bitfield shift amounts */
191 #define NAND_T_H_SHIFT 0
192 #define NAND_T_PUL_SHIFT 4
193 #define NAND_T_SU_SHIFT 8
194 #define NAND_T_WH_SHIFT 12
196 #define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
197 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
198 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
199 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
201 #endif /* __ASM_DB1X00_H */